JP2008244299A - Manufacturing method of non-volatile memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a non-volatile memory, capable of easily manufacturing a non-volatile memory, having a charge storing film below a silicon layer. <P>SOLUTION: The manufacturing method of a non-volatile memory is used to form a non-volatile memory, having a plurality of memory cells 10 that forms at least one-dimensional cell arrangement on an SOI wafer consisting of a supporting substrate 11, an embedded oxide film 12 and a silicon layer. The manufacturing method has a step of applying anisotropic etching processing to the silicon layer and the embedded oxide film in accordance with a hole arrangement pattern of a plurality of holes, to form a plurality of through holes that extend to the inside of the embedded oxide film via the silicon layer; a step of applying isotropic etching processing the embedded oxide film, exposed via the through holes to form a plurality cylindrical cavities each spread in the radius direction of the through holes; and a step of filling the cylindrical cavity with a charge storing film 15. Furthermore, a charge-storing film, left after replacing the charge storing film in a predetermined region of the cylindrical cavity with an element isolation film being formed into an island shape, and an active region is formed on a silicon layer above the charge-storing film formed into an island shape. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a nonvolatile memory manufacturing method, and more particularly to a nonvolatile memory manufacturing method for manufacturing a nonvolatile memory on an SOI (Silicon on Insulator) SOI wafer.

  As a technique for manufacturing a nonvolatile memory, Patent Document 1 discloses a technique for forming a MOSFET as a memory element on a single crystal silicon substrate using an SOI structure. Further, Patent Document 2 includes a first insulating layer and a second insulating layer formed on both sides of a channel region, respectively, and at least one of the insulating layers has an ONO (oxide accumulation function). A non-volatile semiconductor memory device including a -nitride-oxide) film is disclosed. Patent Document 3 discloses an operation method in a nonvolatile semiconductor memory device in which a charge storage layer having a charge storage function is formed. Further, Patent Document 4 discloses a field effect semiconductor device in which a MOSFET is formed on an SOI wafer and a silicon nitride film is used as a charge storage layer.

  Non-Patent Document 1 discloses a SONOS (Silicon-Oxide-Nitride-) that is double-layered, that is, includes an ONO layer as a charge storage layer on a silicon layer and also has an ONO layer below the silicon layer. A nonvolatile memory having an Oxide-Silicon structure is disclosed. Further, Non-Patent Document 1 discloses a manufacturing method for performing a process of growing a SiGe / Si layer as a method for creating such a nonvolatile memory.

The outline of the manufacturing method using the SiGe / Si layer will be described with reference to FIG. 1. First, the SiGe layer 8 is formed on the Si wafer 1, and then the silicon layer 9 is further formed on the formed SIGe layer 8. Is formed (FIG. 1A). Later, the SIGe layer 8 is replaced with an ONO layer composed of the oxide film 2, the nitride film 3, and the oxide film 4. In the silicon layer 9, the drain region D and the source region S are formed so as to sandwich the channel region 5 and the channel region 5 by a normal method, and the ONO layer of the oxide film 6 including the nitride film 7 is formed on the channel region 5. Is formed. Next, a gate region G on the oxide film 6 is formed. As a result, a nonvolatile memory including an ONO layer above the silicon layer and an ONO layer below the silicon layer is manufactured (FIG. 1B).
Japanese Patent Laid-Open No. 3-253072 JP-A-9-97851 JP 2002-353342 A JP 2003-152192 A `A 4-Bit Double SONOS Memory (DSM) with 4 Storage Nodes per Cell for Ultimate Multi-Bit Operation ', 2006 Symposium on VLSI Technology Digest of Technical Papers.

  However, depending on conventional techniques such as the technique of Non-Patent Document 1, there is a problem that a dedicated apparatus is required to grow the SiGe / Si film and the manufacturing process becomes complicated. Further, even if the SiGe layer is removed during the manufacturing process, there is a problem that the contamination by Ge cannot be completely removed in the subsequent process.

  An object of the present invention is to provide a nonvolatile memory manufacturing method for easily manufacturing a nonvolatile memory having a charge storage film under a silicon layer.

  A non-volatile memory manufacturing method according to the present invention includes a non-volatile memory manufacturing method in which a non-volatile memory having a plurality of memory cells formed of at least a one-dimensional cell array is formed on an SOI wafer including a support substrate, a buried oxide film, and a silicon layer. The silicon layer and the buried oxide film are subjected to anisotropic etching according to a hole arrangement pattern of a plurality of holes, thereby penetrating the silicon layer and extending into the buried oxide film. A plurality of cylinders each extending in the radial direction of the through-hole by forming a through-hole forming step for forming a hole and applying an isotropic etching process to the buried oxide film exposed through the formed through-hole A cylindrical cavity forming step for forming a cavity, a cylindrical cavity filling step for filling the cylindrical cavity with a charge storage film, and a charge storage film in a predetermined region of the cylindrical cavity are replaced by an element isolation film. A charge storage film forming step of forming a charge storage layer in an island shape, characterized in that it comprises a channel region forming a channel region in the silicon layer of the charge storage film above formed in the island shape, a.

  According to the nonvolatile memory manufacturing method of the present invention, a nonvolatile memory having a charge storage film under the silicon layer can be easily manufactured.

  Embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 2 shows a cross section of one memory cell 10 included in the nonvolatile memory obtained by executing the nonvolatile memory manufacturing method according to the present invention. The nonvolatile memory is manufactured on the basis of an SOI wafer in which a support substrate, a buried oxide film, and a silicon layer are stacked, has a structure similar to a MOSFET, and includes a charge storage film particularly under the channel region thereof. A plurality of memory cells 10 form a two-dimensional cell array.

  The memory cell 10 includes a support substrate 11 such as a silicon substrate, an impurity region 13, a buried oxide film 12 including a charge storage film 15, a channel region 37 having a drain region 35 and a source region 39 on both sides, The oxide film 27, the nitride film 18, the oxide film 29, and the gate electrode 31 are sequentially stacked substantially along the central axis of the memory cell 10. Element isolation films 33 are formed on both sides of the four layers composed of the oxide film 27, the nitride film 18, the oxide film 29, and the gate electrode 31. The channel region 37 is formed in the silicon layer of the SOI wafer, that is, the SOI layer, and the drain region 35 and the source region 39 are formed in the SOI layer in a self-aligned manner with respect to the gate electrode 31. The oxide film 27, the nitride film 18, and the oxide film 29 form a single ONO layer as a second charge storage film, and have a function of storing charges for information storage together with the charge storage film 15. The gate electrode 31, the drain region 35, and the source region 39 are connected to a control line (not shown) for writing or reading information recording via an appropriate contact member.

  In this specification, unless otherwise specified, the name of an oxide film means a silicon oxide film, and the name of a nitride film means a silicon nitride film.

  The charge storage film 15 is made of a material such as polysilicon, and a portion of the buried oxide film 12 is interposed between the upper portion of the charge storage film 15 and the channel region 37, and the buried oxide is interposed between the lower portion and the impurity region 13. Part of the membrane 12 is interposed. The charge storage film 15 may be an ONO layer made of an oxide film-nitride film-oxide film. In this case, the charge storage film 15 may be directly bonded to the channel region 37 and the impurity region 13. The impurity region 13 is a region for supplying charges to the charge storage film 15 and is connected to a control line (not shown) for writing or reading information recording via an appropriate contact member.

  The memory cell 10 has a structure similar to a normal MOSFET, and may be either a pMOS type or an nMOS type. For example, if the memory cell 10 is an nMOS type, the drain region 35 and the source region 39 have n-type conductivity, the channel region has P-type conductivity, and the impurity region 13 has high-concentration n-type conductivity. And

  As described above, the memory cell 10 includes the charge storage layer 15 having a charge storage function under the channel region 37 that can be formed in the silicon layer (SOI layer) in the SOI structure, and also on the channel region 37. 2 includes an ONO layer having a charge storage function. Thereby, the memory cell 10 can store multi-value information.

  3 to 10 show a manufacturing method for manufacturing a nonvolatile memory according to the present invention, and show a structure in which a top surface and a cross section of the nonvolatile memory in each step are viewed. As a premise, a plurality of memory cells are formed at each of a plurality of cell positions P1 to P4 in the cell array. In addition, the cell interval in the vertical direction of the drawing is Y, and the cell interval in the horizontal direction of the drawing is X.

  In the first step (see FIG. 3), ion implantation is performed on the support substrate 11 below the buried oxide film 12 using photolithography to form an impurity region 13, and then an oxide film 19 is deposited on the SOI layer 17. A nitride film 21 is further deposited on the oxide film 19. Thereby, the impurity region 13 is formed in an island shape at the cell positions P1 to P4.

  In the second step (see FIG. 4), photolithography and etching are performed according to the hole arrangement pattern of a plurality of holes, and penetrates the nitride film 21, the oxide film 10 and the SOI layer 17 into the buried oxide film 12. A plurality of through holes C <b> 1 to C <b> 4 that extend and reach the support substrate 11 are formed. As shown in the figure, the hole arrangement pattern is such that, for example, the through-hole C1 is at an intermediate position between the cell position P1 and the adjacent cell position P2, and the through-hole C4 is between the cell position P3 and the adjacent cell position P4. Be in the middle position. That is, the hole array pattern has a shape shifted by approximately half of the cell interval Y only in the one-dimensional direction (vertical direction in the drawing) of the cell array that is a two-dimensional array. This step constitutes a through hole forming process according to the present invention.

  In the third step (see FIG. 5), the buried oxide film 12 is removed by performing isotropic etching using an etchant such as a hydrofluoric acid solution. At this time, the etching amount, that is, the oxide film removal amount is adjusted according to the cell intervals X and Y so that a part of the buried oxide film 12 remains. That is, the buried oxide film 12 is eroded by an etching agent in the radial direction around each of the through holes C1 to C4 to form a plurality of cylindrical cavities V1 to V4 respectively corresponding to the through holes C1 to C4. The remaining buried oxide film 12 is left. Further, the cylindrical cavities V1 to V4 communicate with each other according to the distance of the cell interval Y. In the example of this figure, the cylindrical cavity V1 and the cylindrical cavity V2 communicate with each other with a width L at the cell position P2 in the cross section A, and the cylindrical cavity V3 and the cylindrical cavity V4 similarly in the cell position P3 in the cross section A. Communicate. This step constitutes the cylindrical cavity forming process according to the present invention.

  In the fourth step (see FIG. 6), the inside of the cylindrical cavities V1 to V4 is covered with an oxide film by performing an oxidation treatment. That is, the oxide film 19 is formed around the SOI layer 17 and the oxide film 19 is also formed on the impurity region 13.

  In the fifth step (see FIG. 7), the charge storage films 15 and 15 'are embedded by filling the cylindrical cavities V1 to V4 with a material such as polysilicon using a method such as CVD (Chemical Vapor Deposition). An ONO layer may be formed in combination with the oxide film 19 by using a nitride film instead of polysilicon. This step constitutes the cylindrical cavity filling process according to the present invention.

  In the sixth step (see FIG. 8), the charge storage film 15 '(see FIG. 7) on the nitride film 21 is removed by performing an etching process or a CMP (Chemical-Mechanical Polishing) process. Next, photolithography and etching processes are performed to pattern a predetermined area determined from the arrangement shape of a desired active (AC) area up to the support substrate 11, and the charges in the portions where the through holes C1 to C4 exist between the memory cells. The accumulation film 15 is removed. Further, processing such as HDP (High Density Plasma) is performed, and the element isolation film 23 for element isolation is replaced. As a result, the charge storage film left in each of the cell positions P1 to P4 is formed in an island shape. This step constitutes the charge storage film forming process according to the present invention.

In the seventh step (see FIG. 9), the element isolation film 23, the nitride film 21, and the oxide film 19 are removed along the surface of the SOI layer 17 by performing an etching process or a CMP process. Thus, in the eighth step (see FIG. 10) in which the SOI layer 17 is exposed, a normal CMOS process, a process of depositing an ONO film, or a flash memory manufacturing process is applied. As a result, a channel region 37 having a drain region and a source region (not shown) on both sides is formed in an island shape at each of the cell positions P1 to P4, and from the oxide film 27, the nitride film 18 and the oxide film 29. The ONO layer, the gate electrode 31, and the element isolation film 33 are formed in an island shape on both sides thereof, and an active (AC) region corresponding to each memory cell is formed. This step constitutes an active region forming process according to the present invention.

  In this embodiment, the hole arrangement pattern is assumed to have a shape shifted by half the cell interval Y in only one arrangement direction of the two-dimensional cell arrangement, and the cylindrical cavities V1 to V4 communicate with each other. Yes. However, the present invention is not limited to this, and as long as the charge storage layer is effectively filled in a predetermined cell position, the deviation between the cell arrangement and the hole arrangement and the presence / absence and degree of communication can be appropriately selected.

  As apparent from the above embodiments, by applying the nonvolatile memory manufacturing method according to the present invention, a charge storage film is provided below the SOI layer using an SOI wafer, unlike the conventional configuration using a Si wafer. A nonvolatile memory can be easily manufactured. In addition, a nonvolatile memory including a charge storage film below the SOI layer can be manufactured without requiring a dedicated device for growing a SiGe / Si film using a Ge element. Further, according to the present invention, ions are implanted into the support substrate below the position where the charge storage film is formed. The obtained impurity region can be used as a lower electrode for injecting charges into the lower charge storage film. For example, a charge difference can be selectively injected into or released from the charge storage film by providing a potential difference between the SOI layer and the impurity region. By selectively injecting or releasing charge, the entire nonvolatile memory and peripheral circuits are not affected.

  Further, according to the present invention, when the buried oxide film is removed, a part of the buried oxide film is left. As a result, the charge storage films at each of the cell positions P1 to P4 can be separated, and the outflow of stored charges can be prevented even when polysilicon is used as the charge storage film. The present invention also has a high affinity with the subsequent manufacturing process because the lower charge storage film is formed before the formation of the active (AC) region including the formation of the gate electrode.

It is sectional drawing of the non-volatile memory manufactured by the non-volatile memory manufacturing method by a prior art. 1 is a cross-sectional view of a nonvolatile memory manufactured by a nonvolatile memory manufacturing method according to the present invention. It is the upper surface and sectional drawing of a non-volatile memory in the 1st step of the non-volatile memory manufacturing method by this invention. It is the upper surface and sectional drawing of the non-volatile memory in a 2nd step. It is the upper surface and sectional drawing of the non-volatile memory in a 3rd step. It is the upper surface and sectional drawing of the non-volatile memory in a 4th step. It is the upper surface and sectional drawing of the non-volatile memory in a 5th step. It is the upper surface and sectional drawing of the non-volatile memory in a 6th step. It is the upper surface and sectional drawing of the non-volatile memory in a 7th step. It is the upper surface and sectional drawing of the non-volatile memory in an 8th step.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Memory cell 11 Support substrate 12 Embedded oxide film 13 Impurity region 15, 15 'Charge storage film 17 SOI layer 18, 21 Nitride film 19, 27, 29 Oxide film 21 Nitride film 23, 33 Element isolation film 31 Gate electrode 35 Drain Region 37 Channel region 39 Source region

Claims (8)

A non-volatile memory manufacturing method for forming a non-volatile memory in which a plurality of memory cells form at least a one-dimensional cell array on an SOI wafer comprising a support substrate, a buried oxide film, and a silicon layer,
By subjecting the silicon layer and the buried oxide film to anisotropic etching according to a hole arrangement pattern of a plurality of holes, a plurality of through holes extending through the silicon layer and extending into the buried oxide film are formed. A through-hole forming step,
A columnar cavity forming step in which a plurality of cylindrical cavities each extending in the radial direction of the through-hole are formed by performing an isotropic etching process on the buried oxide film exposed through the formed through-hole,
A cylindrical cavity filling step of filling the cylindrical cavity with a charge storage film;
A charge storage film forming step of forming the remaining charge storage film in an island shape by replacing the charge storage film in a predetermined region of the cylindrical cavity with an element isolation film;
An active region forming step of forming an active region in the silicon layer above the charge storage film formed in the island shape;
A method for manufacturing a non-volatile memory, comprising:   2. The method of manufacturing a nonvolatile memory according to claim 1, wherein the through hole forming step performs an etching process in accordance with a hole arrangement pattern in which the hole arrangement of the plurality of holes is shifted from the cell arrangement by approximately half of the cell interval. .   2. The method of manufacturing a nonvolatile memory according to claim 1, wherein the cylindrical cavity forming step forms a plurality of cylindrical cavities communicating in the arrangement direction of the cell array.   The cylindrical cavity forming step leaves an embedded oxide film between the cylindrical cavity, the support substrate and the silicon layer by adjusting the etching amount in the isotropic etching process, and the cylindrical cavity filling step 2. The method of manufacturing a nonvolatile memory according to claim 1, wherein the cylindrical cavity in which the embedded oxide film is left is filled with polysilicon as the charge storage film.   The cylindrical cavity filling step further includes a step of coating the cylindrical cavity with an oxide film prior to the cylindrical cavity filling process, wherein the cylindrical cavity filling process fills the cylindrical cavity with polysilicon as the charge storage film. Item 12. A method for manufacturing a nonvolatile memory according to Item 1.   2. The non-volatile memory manufacturing method according to claim 1, wherein the cylindrical cavity filling step forms an ONO film as the charge storage film in the cylindrical cavity.   Prior to the through-hole forming step, an ion implantation process is performed on the support substrate, so that the charge storage film forming step is formed in a portion of the support substrate adjacent to the buried oxide film. 2. The method of manufacturing a nonvolatile memory according to claim 1, further comprising the step of forming an impurity region for supplying a charge to the charge storage film in an island shape.   2. The method of manufacturing a nonvolatile memory according to claim 1, wherein the active region forming step includes a step of forming a second charge storage film above the silicon layer.

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