JP2008135580A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology to suppress leakage current generated between leads in an address driver to be used in a semiconductor device, in particular, a plasma display device. <P>SOLUTION: A trench isolation region 13 is formed along the outer periphery of a semiconductor chip 10, and an element-forming region 22 and an outer edge region 23 are separated from each other by the trench isolation region 13. In the element-forming region 22, bump electrodes 11a-11d are formed, and leads 14a-14d are connected to the bump electrodes 11a-11d, respectively; whereas, in the outer edge region 23 a guard ring 19 is formed and a trench isolation region 20 is formed outside the guard ring 19. A plurality of trench isolation regions 21 are formed in a direction of intersecting the trench isolation region 20. The outer edge region 23 are divided into a plurality of small regions which are insulated from each other by the trench isolation region 20 and the trench isolation regions 21. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a technique effective when applied to a semiconductor device such as an address driver.

  Japanese Unexamined Patent Application Publication No. 2006-19427 (Patent Document 1) describes a highly reliable semiconductor chip, a method for manufacturing the semiconductor chip, and a technique for providing a semiconductor device. Specifically, the semiconductor chip includes a semiconductor substrate. The semiconductor substrate is an SOI (Silicon On Insulator) substrate, and includes a support substrate, an insulating layer stacked on the support substrate, and a silicon layer stacked on the insulating layer. This semiconductor substrate has a circuit formation region provided in a silicon layer. Further, an insulating region is provided in the semiconductor substrate. This insulating region is provided so as to surround the entire side surface of the circuit forming region.

  Japanese Patent Application Laid-Open No. 2003-289076 (Patent Document 2) describes a technique for providing a small SOI semiconductor device. Specifically, the SOI semiconductor device includes at least an SOI substrate including a semiconductor layer formed over an insulating film and an active semiconductor element formed in the semiconductor layer. An active semiconductor element in an SOI type semiconductor device is formed in an element formation region surrounded by an isolation region for isolating a semiconductor layer into an island shape, and an element formation in which the active semiconductor element is formed A gettering layer containing a high concentration impurity is formed in a part of the semiconductor layer other than the region. The gettering layer is not formed in the element formation region where the active semiconductor element is formed.

  Japanese Patent Laid-Open No. 2002-33382 (Patent Document 3) describes a technique for preventing leakage current from being generated due to crystal defects generated around a trench of an SOI substrate. Specifically, a crystal defect can be formed in the non-device formation region by forming an ion implantation region in the non-device formation region and oxidizing the surface of the ion implantation region with LOCOS (Local Oxidation of Silicon). Thus, crystal defects can be prevented from being formed in the device formation region. For this reason, it is said that leakage current can be prevented from being generated by forming crystal defects around the trench of the SOI substrate in the vicinity of the device.

Japanese Laid-Open Patent Publication No. 06-268054 (Patent Document 4) describes a technique for providing a semiconductor device capable of making contact with a conductive material for preventing capacitive coupling very easily. Specifically, an N ^- silicon substrate is disposed on the silicon oxide film. A plurality of circuit elements are formed on the N ^- silicon substrate. A trench reaching the silicon oxide film is formed in the N ^- silicon substrate, and islands for circuit element formation are defined by the trench. A silicon oxide film is formed on the outer periphery of the circuit element formation island. Further, a capacitive coupling preventing island is formed on the N ^- silicon substrate between the circuit element forming islands, and a potential is applied to the capacitive coupling preventing island so as to be a constant potential.
JP 2006-19427 A JP 2003-289076 A JP 2002-33382 A Japanese Patent Laid-Open No. 06-268054

  A plasma display device is a type of thin display device that emits light by applying a high voltage to a high-pressure rare gas sealed between glass substrates. The principle was discovered at the University of Illinois in the United States in 1966, and after that it was put into practical use as a computer display device in the 1980s, but it was not very popular. However, with the recent release of plasma televisions, plasma display devices have become widespread as thin large screen televisions.

  The display principle of the plasma display device is the same as that of a fluorescent lamp. A high-pressure gas composed of a rare gas element such as helium or neon is sealed between two glass substrates with electrodes formed on the surface, and a voltage is applied to the gas. To generate ultraviolet rays. The generated ultraviolet light is converted into visible light by the phosphor. In this way, display is performed. A plasma display device that emits light according to such a display principle has characteristics that a response speed is high and contrast is high compared to other display devices such as a liquid crystal display device. Furthermore, since it has an advantage that the viewing angle is wide and the screen can be easily enlarged, it is widely used as a large-screen thin TV.

  An electrode is formed on the plasma display panel of the plasma display device. One of the electrodes is an address electrode having a function of applying an electric field that generates a discharge and a function of positioning which region emits light. Is formed. A voltage is applied to the address electrode in order to cause discharge. A semiconductor device called an address driver exists as a circuit for controlling the voltage applied to the address electrode.

  The address driver is composed of a semiconductor chip having a control circuit formed from transistors, circuit elements (resistances and capacitors), and the like. In this semiconductor chip, an input terminal and an output terminal are formed. After serial data is input from the input terminal and converted to parallel data, the parallel data is output from the output terminal. Yes. The output parallel data (voltage) is applied to the address electrodes connected to the output terminals. The address driver is composed of a semiconductor chip, and the output terminal of the semiconductor chip is connected to the flexible substrate via a lead. That is, a semiconductor chip constituting an address driver is mounted on a flexible substrate (TCP: Tape Carrier Package), and the semiconductor chip is sealed with a resin (resin). The leads are connected to address electrodes formed on the plasma display panel.

  FIG. 32 shows a partial cross section of a semiconductor chip (address driver) having such a TCP configuration. FIG. 32 is a cross-sectional view showing the vicinity of the end portion where the output terminal of the semiconductor chip is formed. As shown in FIG. 32, the semiconductor chip constituting the address driver has an SOI structure. Specifically, in the semiconductor chip, a buried insulating layer (BOX layer) 101 is formed on a support substrate 100 made of a semiconductor substrate such as silicon, and an active layer made of a semiconductor region is formed on the buried insulating layer 101. . A groove isolation region 102 reaching the buried insulating layer 101 is formed in the active layer, and the element formation region 103 and the outer edge region (scribe region, frame region) 104 are electrically isolated by the groove isolation region 102. . An interlayer insulating film 105 is formed on the element formation region 103 and the outer edge region 104. Although not shown, a MISFET (Metal Insulator Semiconductor Field Effect Transistor) and a circuit element are formed in the element formation region 103, and wiring is formed through an interlayer insulating film 105. That is, a control circuit constituting an address driver is formed in the element formation region 103. On the other hand, a guard ring is formed in the outer edge region 104 so that foreign substances such as moisture do not enter the element forming region 103. This guard ring is made of, for example, an aluminum film and is formed so as to surround the periphery of the semiconductor chip.

  As shown in FIG. 32, a passivation film (surface protective film) 108 is formed on the interlayer insulating film 105. At the end of the element formation region 103, an opening is formed in the passivation film 108, and a pad 107 made of an aluminum film is formed in the opening. A bump electrode 109 a is formed on the pad 107. The bump electrode 109a constitutes an output terminal of the address driver.

  The semiconductor chip thus configured is mounted on a flexible substrate (not shown) (TCP mounting). In this mounting process, the bump electrode 109a formed on the semiconductor chip and the lead 110a formed on the flexible substrate are connected. Thereafter, the semiconductor chip mounted on the flexible substrate is sealed with the resin 111. In this way, a semiconductor device which is an address driver is manufactured.

  Here, the resin used for sealing the semiconductor chip contains a resin and a solvent. Examples of the solvent contained in the resin include xylene, toluene, and methyl ethyl ketone. Since these solvents have conductivity, the resin is sealed with the resin, and then the solvent is removed by heat treatment such as baking. That is, after resin sealing with a resin, heat treatment is performed to cure the resin. The solvent is volatilized from the resin by the heat treatment at this time. Resin increases insulation by volatilizing the solvent.

  However, although the heat treatment described above is performed, it is difficult to completely remove the solvent by this heat treatment. In particular, the solvent tends to remain in the gap between the semiconductor chip and the lead 110a shown in FIG. The remaining solvent volatilizes over time, so that the problem disappears after a long time, but becomes a problem in the initial stage of manufacturing the address driver. That is, in the initial stage of manufacturing the address driver, the resin remains in the resin and insulation is not sufficiently ensured. Therefore, as shown in FIG. 32, when the address driver is operated, the lead 110a and the outer edge region 104 which is a semiconductor region are in the resin. The present inventors have found that there is a problem of conducting through 111. That is, a leak path 112 is formed between the lead 110a and the outer edge region 104, and a leak current flows. In particular, in the address driver used in the plasma display device, a high voltage is applied to the address electrode (lead 110a), so that a leak current tends to flow when the lead 110a and the outer edge region 104 approach each other.

  Thus, when a leak current flows through the lead 110a and the outer edge region 104, the leak current flows between a plurality of leads formed in the semiconductor chip. The reason for this will be described. FIG. 33 is a plan view showing the vicinity of the outer periphery of a semiconductor chip mounted with TCP. As shown in FIG. 33, a groove separation region 102 is formed in the semiconductor chip, and the element formation region 103 and the outer edge region 104 are electrically separated by the groove separation region 102. In the element formation region 103, bump electrodes 109a to 109d are arranged along the groove separation region 102, and leads 110a to 110d are connected to the bump electrodes 109a to 109d, respectively. The semiconductor chip is actually covered with a resin, but the resin is not shown in FIG.

  For example, FIG. 32 shows a cross section of the bump electrode 109a of FIG. 33. As shown in FIG. 32, since the solvent remains in the resin 111 in the initial stage of manufacturing the address driver, the lead 110a and the outer edge region are shown. A leakage path 112 exists between the terminal 104 and the leakage current. Next, as can be seen from FIG. 33, since the outer edge region 104 is a semiconductor region and a current flows, a leak path 113 is formed. Then, when the solvent contained in the resin again remains, for example, a leak path is formed from the outer edge region 104 to the lead 110b through the resin. Therefore, a leakage current flows from the lead 110a to the outer edge region 104 through the resin 111, and this leakage current is transmitted to the outer edge region 104 made of the semiconductor region. After that, it flows again to the lead 110b through the resin. In this way, for example, a leak current flows between the lead 110a and the lead 110b. As described above, when a leak current flows between a plurality of leads, the address driver cannot operate normally.

  As an example, a case has been described in which a leak current occurs between adjacent leads 110a and 110b. However, the present invention is not limited to this, and for example, a leak current may flow between the lead 110a and the lead 110d. That is, if a high voltage is applied to the lead 110a and the lead 110d and a ground potential is applied to the lead 110b and the lead 110c, the lead 110a and the lead 110d to which the high voltage is applied are connected via a resin. Since a leak path is easily formed, it is conceivable that the lead 110 a and the lead 110 d are short-circuited through the outer edge region 104. Further, a guard ring is formed in the outer edge region 104, and this guard ring is formed of an aluminum film having a small resistance value. Therefore, the impedance of the outer edge region 104 is small, and the outer edge region 104 tends to be a leak path.

  As described above, in particular, in the plasma display device using a high voltage, it can be seen that there is a problem that a plurality of leads are conducted through the resin and the outer edge region in the initial stage where the solvent remains in the resin. .

  Here, in FIG. 32, it is conceivable that the height of the bump electrode 109a is increased to increase the distance between the lead 110a and the outer edge region 104 so that a leak path is not formed. However, the bump electrode 109a is usually formed by using an expensive gold film. If the height of the bump electrode 109a is increased, the amount of the gold film to be used increases, and the manufacturing cost of the address driver increases. Will occur. Although it is conceivable to increase the distance from the lead 110a by making the outer edge region 104 longer, if the outer edge region 104 is made larger, the area of the semiconductor chip becomes larger and the semiconductor chip can be obtained from one semiconductor wafer. The number of For this reason, there is still a problem that the manufacturing cost of the address driver increases.

  An object of the present invention is to provide a technique capable of suppressing a leakage current generated between leads in an address driver used in a semiconductor device, particularly, a plasma display device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows. An embodiment of the present invention includes (a) a semiconductor substrate, (b) a buried insulating layer embedded in the semiconductor substrate, and (c) an active layer made of a semiconductor region formed on the buried insulating layer, (D) The present invention relates to a semiconductor device including a first trench isolation region that extends from the active layer to the buried insulating layer and is formed along the outer periphery of the semiconductor chip. In the semiconductor device configured as described above, the first groove isolation region forms an element formation region inside the first groove isolation region, and an outer edge region outside the first groove isolation region. At this time, a plurality of second groove separation regions are formed in the outer edge region in a direction intersecting with the first groove separation region.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows. According to the embodiment, the leakage current between the leads can be reduced. For example, even when a conductive solvent remains in the resin used for sealing the semiconductor chip, it is possible to prevent a short circuit between the leads through the resin and the outer edge region of the semiconductor chip.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say.

  Similarly, in the following embodiments, when referring to the shape, positional relationship, etc., of components, etc., unless otherwise specified, and in principle, it is considered that this is not clearly the case, it is substantially the same. Including those that are approximate or similar to the shape. The same applies to the above numerical values and ranges.

  In all the drawings for explaining the embodiments, the same members are denoted by the same reference symbols in principle, and the repeated explanation thereof is omitted. In order to make the drawings easy to understand, even a plan view may be hatched.

(Embodiment 1)
The semiconductor device according to the first embodiment will be described with reference to the drawings. The semiconductor device according to the first embodiment is an address driver used for a plasma display device, for example. First, a circuit constituting this address driver will be described. FIG. 1 is a circuit block constituting an address driver.

  In FIG. 1, a circuit 1 constituting an address driver includes a shift register 2, a latch circuit 3, a control circuit 4, a pre-buffer 5, a level shift circuit (Level Shift). ) 6 and driver 7. The circuit 1 includes data input terminals A1 to A3 for inputting serial data. Further, the circuit 1 is provided with a logic power supply VDD1, a logic GND, a high voltage power supply VDD2, a high voltage power supply GND, a clock CLK, a latch control signal LAT, a data input terminal STB, and a data input terminal SUS. The circuit 1 having such an input has a function of inputting serial data from the data input terminals A1 to A3 and outputting parallel data from the output terminals OUT1 to 192. Parallel data (signal voltage) output from the output terminals OUT1 to 192 is applied to each address electrode formed on the plasma display panel. The circuit 1 will be described below.

  The circuit 1 has, for example, three 64-bit shift registers 2 and a 192-bit output terminal. The shift register 2 sequentially inputs serial data from the data input terminals A1 to A3 based on the clock CLK. The serial data input to the shift register 2 is rearranged into an arbitrary pattern and converted into parallel data. Then, the parallel data is held in the latch circuit 3 by the latch control signal LAT. The held parallel data is input to the control circuit 4. In the control circuit 4, parallel data held in the latch circuit 3, data input from the data input terminal STB, and data input from the data input terminal SUS are input. Data input from the data input terminal STB is data whose all bits are “Hi”, and data input from the data input terminal SUS is data whose all bits are “Lo”. The control circuit 4 prioritizes the parallel data input from the latch circuit 3, the data input from the data input terminal STB, and the data input from the data input terminal SUS. The priority in the control circuit 4 is data input from the data input terminal SUS> data input from the data input terminal STB> parallel data input from the latch circuit 3. That is, in the control circuit 4, when the parallel data input from the data input terminal SUS, the data input terminal STB, and the latch circuit 3 is input, the data input from the data input terminal SUS is output preferentially. When data input from the data input terminal SUS is not active, data input from the data input terminal STB is output, and data input from the data input terminal SUS and data input from the data input terminal STB are output. When is not active, the parallel data input from the latch circuit 3 is output.

  In the control circuit 4, when the output signal is switched, the output unit 8 outputs a signal to the output unit 8 at an appropriate timing so that the high-side driver and the low-side driver constituting the driver 7 of the output unit 8 are not turned on at the same time. To do. The signal output from the control circuit 4 is converted from the logic power supply VDD1 level to the high voltage power supply VDD2 level by the prebuffer 5 and the level shift circuit 6 constituting the output unit 8. Then, it is output from the driver 7 to the output terminals OUT1 to 192. In this way, the circuit 1 constituting the address driver operates.

  Next, the configuration of the output unit 8 will be described with reference to FIG. As shown in FIG. 2, the output unit 8 includes a prebuffer 5, a level shift circuit 6, and a driver 7. The level shift circuit 6 includes n-channel transistors M1 and M2 and p-channel transistors M3 and M4. It has an input IN1 connected to the gate electrode of the n-channel transistor M1 and an input IN2 connected to the gate electrode of the n-channel transistor M2. A signal obtained by inverting the input IN1 at the same timing as the input IN1 is input to the input IN2 with respect to the input IN1. The n-channel transistors M1 and M2 are formed so that the on-resistance when turned on is smaller than that of the p-channel transistors M3 and M4. The n-channel transistor M1 and the p-channel transistor M3 are connected in series between the high-voltage power supply VDD2 and GND. Similarly, the n-channel transistor M2 and the p-channel transistor M4 are connected in series between the high-voltage power supply VDD2 and GND. The gate electrode of the p-channel transistor M4 is connected between the n-channel transistor M1 and the p-channel transistor M3, and the gate electrode of the p-channel transistor M3 is connected between the n-channel transistor M2 and the p-channel transistor M4. For example, a voltage of 20 V to 100 V is applied to the high voltage power supply VDD2.

  The prebuffer 5 includes a p-channel transistor M5 and an n-channel transistor M6, and the p-channel transistor M5 and the n-channel transistor M6 are connected in series between the logic power supply VDD1 and GND. The input IN3 is connected to the gate electrode of the p-channel transistor M5 and the gate electrode of the n-channel transistor M6. For example, a voltage of 5 V is applied to the logic power supply VDD1.

  These inputs IN1 to IN3 are connected to the control circuit 4 shown in FIG. 1, and the prebuffer 5 and the level shift circuit 6 are controlled by the control circuit 4.

  The driver 7 has a Pch driver (high side driver) composed of a p-channel transistor M7 and an Nch driver (low side driver) composed of an n-channel transistor M8. The gate electrode of the p-channel transistor M7 is connected to the level shift circuit 6, and the gate electrode of the n-channel transistor M8 is connected to the prebuffer 5. That is, the p-channel transistor M7 that is a high-side driver is driven by the level shift circuit 6, and the n-channel transistor M8 that is a low-side driver is driven by the prebuffer 5. Specifically, the gate electrode of the p-channel transistor M7 constituting the high-side driver of the driver 7 is connected between the p-channel transistor M4 and the n-channel transistor M2 of the level shift circuit 6. On the other hand, a gate electrode of an n-channel transistor M8 constituting a low-side driver of the driver 7 is connected between the p-channel transistor M5 and the n-channel transistor M6 of the prebuffer 5.

  The operation of the output unit 8 configured as described above will be described. First, since the p-channel transistor M7 constituting the high-side driver of the driver 7 is driven by the level shift circuit 6, the on / off operation of the p-channel transistor M7 by the level shift circuit 6 will be described.

  First, it is assumed that “Lo (0 V)” is input to the input IN 1 of the level shift circuit 6. At this time, “Hi (5 V)” is input to the input IN2. Therefore, the p-channel transistor M3 is turned on and the p-channel transistor M4 is turned off.

  In this state, when “Hi (5 V)” is input to the input IN1 of the level shift circuit 6, the n-channel transistor M1 whose gate electrode is connected to the input IN1 is turned on. On the other hand, when “Hi” is input to the input IN1, since the inverted signal of the input IN1 is input to the input IN2, the input IN2 becomes “Lo (0 V)”. Since the input IN2 is connected to the gate electrode of the n-channel transistor M2, the n-channel transistor M2 is turned off. When the n-channel transistor M2 is turned off, the potential between the n-channel transistor M2 and the p-channel transistor M4 remains GND as in the previous state.

  Here, since the n-channel transistor M1 is turned on, the gate electrode of the p-channel transistor M4 is finally connected to GND through the turned-on n-channel transistor M1. In this case, the n-channel transistor M1 and the p-channel transistor M3 are simultaneously turned on at an intermediate stage, but the on-resistance of the n-channel transistor M1 is designed to be lower than that of the p-channel transistor M3, so that the p-channel The gate voltage of the p-channel transistor M4 decreases until the transistor M4 is turned on. As a result, the p-channel transistor M4 is turned on. Thereafter, when the p-channel transistor M4 is turned on, the high-voltage power supply VDD2 is applied to the gate electrode of the p-channel transistor M3, so that the p-channel transistor M3 is turned off. As a result, the gate electrode of the p-channel transistor M4 is completely connected to the GND, and the ON state is maintained.

  On the other hand, when the p-channel transistor M4 is turned on, the potential of the high-voltage power supply VDD2 is applied to the gate electrode of the p-channel transistor M3, so that the p-channel transistor M3 is turned off. At this time, the potential between the p-channel transistor M4 that is turned on and the n-channel transistor M2 that is turned off is the potential of the high-voltage power supply VDD2. Since this potential is applied to the gate electrode of the p-channel transistor M7 constituting the high-side driver of the driver 7, the p-channel transistor M7 is turned off.

  Next, it is assumed that “Hi (5 V)” is input to the input IN1 of the level shift circuit 6. At this time, “Lo (0 V)” is input to the input IN2. Therefore, the p-channel transistor M3 is turned off and the p-channel transistor M4 is turned on.

  In this state, when “Lo” is input to the input IN1 of the level shift circuit 6, the n-channel transistor M1 whose gate electrode is connected to the input IN1 is turned off. When the n-channel transistor M1 is turned off, the potential between the n-channel transistor M1 and the p-channel transistor M3 remains GND as in the previous state. On the other hand, when “Lo” is input to the input IN1, since the inverted signal of the input IN1 is input to the input IN2, the input IN2 becomes “Hi”. Since the input IN2 is connected to the gate electrode of the n-channel transistor M2, the n-channel transistor M2 is turned on.

  Here, since the n-channel transistor M2 is turned on, the gate electrode of the p-channel transistor M3 is connected to GND via the turned-on n-channel transistor M2. In this case, the n-channel transistor M2 and the p-channel transistor M4 are simultaneously turned on, but the on-resistance of the n-channel transistor M2 is designed to be lower than that of the p-channel transistor M4, so that the p-channel transistor M3 is turned on. Until the gate voltage of the p-channel transistor M3 decreases. As a result, the p-channel transistor M3 is turned on. Thereafter, when the p-channel transistor M3 is turned on, the high-voltage power supply VDD2 is applied to the gate electrode of the p-channel transistor M4, so that the p-channel transistor M4 is turned off. As a result, the gate electrode of the p-channel transistor M3 is completely connected to the GND, and the ON state is maintained.

  On the other hand, when the p-channel transistor M3 is turned on, the potential of the high-voltage power supply VDD2 is applied to the gate electrode of the p-channel transistor M4, so that the p-channel transistor M4 is turned off. At this time, the potential between the p-channel transistor M4 that is turned off and the n-channel transistor M2 that is turned on is the potential of GND. Since this potential is applied to the gate electrode of the p-channel transistor M7 constituting the high-side driver of the driver 7, the p-channel transistor M7 is turned on. In this way, the p-channel transistor M7 constituting the high-side driver of the driver 7 can be controlled by the level shift circuit 6.

  Next, since the n-channel transistor M8 constituting the low-side driver of the driver 7 is driven by the prebuffer 5, the on / off operation of the n-channel transistor M8 by the prebuffer 5 will be described.

  When “Hi (5 V)” is input to the input IN3 of the pre-buffer 5, “Hi” is applied to the gate electrode of the n-channel transistor M6 connected to the input IN3. For this reason, the n-channel transistor M6 is turned on. On the other hand, since the input IN3 is also connected to the gate electrode of the p-channel transistor M5, “Hi” is also applied to the gate electrode of the p-channel transistor M5. Therefore, the p-channel transistor M5 is turned off. In this way, since the p-channel transistor M5 is turned off and the n-channel transistor M6 is turned on, the potential between the n-channel transistor M6 and the p-channel transistor M5 is grounded to GND via the turned-on n-channel transistor M6. The For this reason, since “Lo” is applied to the gate electrode of the n-channel transistor M8 constituting the low-side driver of the driver 7, the n-channel transistor M8 is turned off.

  On the other hand, when “Lo (0 V)” is input to the input IN3 of the prebuffer 5, “Lo” is applied to the gate electrode of the n-channel transistor M6 connected to the input IN3. For this reason, the n-channel transistor M6 is turned off. On the other hand, since the input IN3 is also connected to the gate electrode of the p-channel transistor M5, “Lo” is also applied to the gate electrode of the p-channel transistor M5. Therefore, the p-channel transistor M5 is turned on. Thus, since the p-channel transistor M5 is turned on and the n-channel transistor M6 is turned off, the potential between the n-channel transistor M6 and the p-channel transistor M5 becomes 5V through the turned-on p-channel transistor M5. For this reason, since “Hi” is applied to the gate electrode of the n-channel transistor M8 constituting the low-side driver of the driver 7, the n-channel transistor M8 is turned on. In this way, the n-channel transistor M8 constituting the low-side driver of the driver 7 can be controlled by the prebuffer 5.

  As described above, since the high-side driver of the driver 7 is driven by the level shift circuit 6 and the low-side driver of the driver 7 is driven by the prebuffer 5, the switching timing of the on / off operation in the high-side driver and the low-side driver The on / off operation switching timing can be shifted. Therefore, the high-side driver and the low-side driver are turned on at the same time, and it is possible to prevent a through current from flowing between the high-voltage power supply VDD2 and GND. This timing control is appropriately performed by the control circuit 4 to which the inputs IN1 to IN3 are connected.

  FIG. 3 shows the relationship between the output state of the driver 7 and the inputs IN1 to IN3 by summarizing the above-described operations. As shown in FIG. 3, when “Lo” is input to the input IN, “Hi” is input to the input IN2, and “Hi” is input to the input IN3, the p-channel transistor (high side driver) M7 shown in FIG. The transistor (low side driver) M8 is turned off. Therefore, the output becomes “Hi” and the high voltage power supply VDD2 is output. On the other hand, when “Hi” is input to the input IN1, “Lo” is input to the input IN2, and “Lo” is input to the input IN3, the p-channel transistor (high-side driver) M7 shown in FIG. M8 turns on. Therefore, the output becomes “Lo” and the ground potential is output. From this, it is understood that the output unit 8 can convert the level of the signal from the level of the logic power supply VDD1 (5V) to the level of the high voltage power supply VDD2 (20V to 100V). Thus, the signal (voltage) output from the address driver is applied to the address electrode formed in the plasma display panel, and an appropriate cell can be discharged.

  Next, the semiconductor chip on which the circuit described in FIGS. 1 to 3 is formed will be described. FIG. 4 is a top view showing an appearance of the semiconductor chip 10 on which a circuit for realizing an address driver is formed. As shown in FIG. 4, the semiconductor chip 10 has a rectangular shape, and bump electrodes 11 are formed along a pair of long sides and a pair of short sides (periphery of the semiconductor chip). The bump electrode 11 includes types such as an input bump electrode for inputting serial data to the address driver and an output bump electrode for outputting parallel data from the address driver. Furthermore, bump electrodes for supplying logic (logic power supply) input bump electrodes, high voltage power supply VDD2 input bump electrodes, and GND are formed. FIG. 4 shows an example in which an output bump electrode is formed along one long side of the semiconductor chip 10 and an input bump electrode is formed on the other long side. Further, along the short side of the semiconductor chip 10, a bump electrode for high voltage power supply VDD2 and GND are formed. The arrangement of the bump electrodes shown in FIG. 4 is merely an example, and the semiconductor chip may be configured such that the output bump electrodes are formed not only in one long side direction but also in the short side direction. An output bump electrode may also be formed on the other long side.

  In the semiconductor chip 10 forming the address driver, among the bump electrodes 11 formed on the semiconductor chip 10, the output bump electrodes are larger than the input bump electrodes. This is because the signal input to the address driver is serial data, and the signal output from the address driver is parallel data. That is, since the output bump electrodes are provided in a number corresponding to the individual address electrodes, the number of output bump electrodes is increased.

  The semiconductor chip 10 forming the address driver is configured as described above. However, in an actual product, the semiconductor chip 10 is used in a state of being mounted on a flexible substrate (tape substrate) (TCP: Tape Carrier Package). . FIG. 5 is a diagram showing a state where the semiconductor chip 10 is mounted on the flexible substrate 12. As shown in FIG. 5, the semiconductor chip 10 is disposed on the flexible substrate 12, and an input signal (logic input, high-voltage power supply) is formed by wiring (rough wiring on the left side of the semiconductor chip 10) formed on the flexible substrate 12. , Logic power supply, GND, etc.) are input to the semiconductor chip 10. And it turns out that the output signal from a semiconductor chip is output through the wiring (The wiring with the right space | interval of the right side of the semiconductor chip 10) formed in the flexible substrate 12. FIG.

  6 is a plan view in which the vicinity of the semiconductor chip 10 of FIG. 5 is enlarged. As shown in FIG. 6, a hole is formed in the flexible substrate 12, and the semiconductor chip 10 is disposed in this hole. A groove isolation region 13 is formed along the outer periphery of the semiconductor chip 10, and a region inside the groove isolation region 13 is an element formation region of the semiconductor chip 10. On the other hand, a region outside the groove separation region 13 is an outer edge region (scribe region, frame region) of the semiconductor chip 10. A plurality of bump electrodes 11 are formed along the groove isolation region 13 in the element formation region formed inside the groove isolation region 13. A lead (inner lead, arm) 14 is connected to each of the bump electrodes 11. The lead 14 is a wiring formed on the flexible substrate 12.

  7 is a cross-sectional view showing a cross section taken along line AA of FIG. In FIG. 7, the semiconductor chip 10 is disposed in the hole formed in the flexible substrate 12, and the lead 14 is connected to the bump electrode 11 formed in the semiconductor chip 10. The lead 14 is formed on the flexible substrate 12 and is formed of, for example, copper wiring. The lead 14 is bonded to the flexible substrate 12 using an adhesive 16, and the surface of the lead 14 is covered with a solder resist 17. However, the portion connected to the bump electrode 11 near the tip of the lead 14 is not covered with the solder resist 17. In this way, the bump electrodes 11 formed on the semiconductor chip 10 and the leads 14 formed on the flexible substrate 12 are connected. Furthermore, the semiconductor chip 10 is sealed with a resin (resin). Resin is a substance containing a resin and a solvent. Examples of the solvent include xylene, toluene, and methyl ethyl ketone.

  Next, a more detailed configuration of the semiconductor chip 10 will be described. FIG. 8 is a plan view showing the vicinity of the outer end of the semiconductor chip 10 and corresponds to the region 15 in FIG. As shown in FIG. 8, the semiconductor chip 10 has a groove isolation region (first groove isolation region) 13 extending along the outer periphery. Due to the groove isolation region 13, a region inside the groove isolation region 13 becomes an element formation region 22, and a region outside the groove isolation region 13 becomes an outer edge region 23. A plurality of bump electrodes 11 a to 11 d are formed in the element isolation region 22, and the plurality of bump electrodes 11 a to 11 d are arranged side by side along the extending direction of the groove isolation region 13. Leads 14a to 14d are connected to the bump electrodes 11a to 11d, respectively. The leads 14 a to 14 d are connected to the bump electrodes 11 a to 11 d, respectively, extend in a direction intersecting with the groove isolation region 13, and reach the outside of the semiconductor chip 10 through the outer edge region 23.

  On the other hand, a guard ring 19 is formed in the outer edge region 23 so as to be parallel to the groove separation region 13. The guard ring 19 is provided to prevent moisture and foreign matter from entering the element forming region 22. A groove separation region (third groove separation region) 20 is formed outside the guard ring 19 so as to be parallel to the guard ring 19. A plurality of groove separation regions (second groove separation regions) 21 are formed outside the groove separation region 20 in a direction intersecting with the groove separation region 20. For example, the groove isolation region 21 is formed so as to be orthogonal to the groove isolation region 20 and is formed so as to reach the outer end portion of the semiconductor chip 10. With this configuration, the outer edge region 23 can be divided into cell regions that are divided and subdivided by the groove separation region 20 and the plurality of groove separation regions 21. At this time, the cells divided by the groove separation region 20 and the plurality of groove separation regions 21 are individually electrically insulated. One of the features of the first embodiment is that a groove separation region 20 and a groove separation region 21 are provided in the outer edge region 23. This feature point will be further described in detail.

  9 is a cross-sectional view showing a cross section taken along line AA of FIG. As shown in FIG. 9, the semiconductor chip 10 serving as an address driver has an SOI (silicon on insulator) structure. First, a buried insulating layer 26 is formed on a support substrate 25 made of a semiconductor substrate such as silicon. An active layer made of a semiconductor region is formed on the buried insulating layer 26. A trench isolation region 13 is formed in this active layer, and the trench isolation region 13 penetrates the active layer and reaches the buried insulating layer 26. The trench isolation region 13 is formed by embedding an insulating film such as a silicon oxide film in a trench formed in the active layer. Therefore, the inner region and the outer region of the groove separation region 13 are electrically insulated. An inner region of the groove isolation region 13 is an element formation region 22, and an outer region of the groove isolation region 13 is an outer edge region 23. In FIG. 9, MISFET (Metal Insulator Semiconductor Field Effect Transistor) and circuit elements are not shown in the element formation region 22, but in FIG. 9, the end of the element formation region that is near the boundary with the outer edge region 23 is shown. For this reason, in the vicinity of the center of the element formation region 22, MISFETs and circuit elements (resistances and capacitors) constituting the address driver are formed.

  A groove separation region 20 is further formed in the outer edge region separated by the groove separation region 13. Similar to the groove isolation region 13, the groove isolation region 20 is also formed by embedding an insulating film such as a silicon oxide film in a groove penetrating the active layer. That is, the trench isolation region 20 also penetrates the active layer and reaches the buried insulating layer 26. An interlayer insulating film 27 is formed on the active layer where the groove isolation region 13 and the groove isolation region 20 are formed, and a guard ring 19 and a pad 29 are formed on the interlayer insulating film 27. The guard ring 19 is formed in the outer edge region 23, and the pad 29 is formed in the element forming region 22. The guard ring 19 and the pad 29 are made of, for example, an aluminum film.

  A surface protective film (passivation film) 28 is formed on the interlayer insulating film 27 on which the guard ring 19 and the pad 29 are formed, and an opening is provided in the surface protective film 28 on the pad 29. A bump electrode 11a is formed in the opening, and a lead 14a is connected to the bump electrode 11a. The bump electrode 11a is made of, for example, a gold film, and the lead 14a is made of, for example, copper wiring. The region including the connection portion between the bump electrode 11 a and the lead 14 a is sealed with the resin 30. The resin 30 is formed not only on the upper surface of the semiconductor chip but also on the side surface.

  10 is a cross-sectional view showing a cross section taken along line BB of FIG. The configuration in FIG. 10 is almost the same as the configuration in FIG. 9, but the region without the groove separation region 21 formed in the outer edge region 23 is cut in the AA line in FIG. The groove separation region 21 is not clearly shown. On the other hand, in the BB line of FIG. 8, since the region where the groove isolation region 21 formed in the outer edge region 23 is formed, the groove isolation region 21 is clearly shown in FIG. . This is the difference between FIG. 9 and FIG. As shown in FIG. 10, it can be seen that the groove isolation region 21 also extends toward the outer side of the outer edge region 23 and reaches the outer end portion of the semiconductor chip. Further, it can be seen that the trench isolation region 21 also penetrates the active layer and reaches the buried insulating layer 26. Similarly to the groove isolation region 20 shown in FIG. 9, the groove isolation region 21 is also formed by embedding an insulating film such as a silicon oxide film in the groove. Thus, it can be seen that the groove separation regions 13, 20, and 21 have the same configuration. Therefore, as described in the address driver manufacturing method, the trench isolation regions 13, 20, and 21 are formed in the same process.

  FIG. 11 is a perspective view of the structure shown in FIGS. FIG. 11 clearly shows the arrangement of the groove separation region 20 and the groove separation region 21 formed in the outer edge region 23. As shown in FIG. 11, it can be seen that a guard ring 19 is formed in the outer edge region 23 separated by the groove separation region 13, and a groove separation region 20 is formed outside the guard ring 19. Providing the groove separation region 20 is one feature of the first embodiment, and is provided for forming a region that does not include the guard ring 19 in the outer edge region 23. That is, when the guard ring 19 made of a low-resistance aluminum film is formed in the active layer (semiconductor region) that forms the outer edge region 23, the impedance of the outer edge region 23 decreases. When the impedance of the outer edge region 23 is lowered, the problem described later occurs. Therefore, in order to form a high impedance region in the outer edge region 23, the groove separation region 20 is separated. That is, in the region outside the guard ring 19 separated by the groove separation region 20, the impedance can be increased because the guard ring 19 is electrically insulated.

  Further, one of the features of the first embodiment is that a plurality of groove separation regions 21 are provided in a region outside the groove separation region 20 separated by the groove separation region 20 in the outer edge region 23. The plurality of groove isolation regions 21 are formed in a direction intersecting with the groove isolation region 20 and have a function of subdividing the outer edge region 23 and isolating it into cell regions insulated from each other. The impedance of the outer edge region 23 can be increased by the groove separation region 21, and the cell regions obtained by dividing the outer edge region 23 can be electrically insulated from each other. By providing the groove separation region 21 in this way, the first embodiment has the following remarkable effects.

  Next, the remarkable effect realized by providing the groove separation region 20 and the groove separation region 21 will be described together with the problem solved in the first embodiment.

  First, problems that occur in the conventional structure in which the groove separation region 20 and the groove separation region 21 are not provided in the outer edge region 23 will be described.

  As shown in FIG. 32, the semiconductor chip is sealed with a resin 111. The resin used for sealing the semiconductor chip contains a resin and a solvent. Examples of the solvent contained in the resin include xylene, toluene, and methyl ethyl ketone. Since these solvents have conductivity, the resin is sealed with the resin, and then the solvent is removed by heat treatment such as baking. That is, since the resin increases the insulating properties by volatilizing the solvent, heat treatment is performed after the resin is sealed with the resin.

  However, although the heat treatment described above is performed, it is difficult to completely remove the solvent by this heat treatment. In particular, the solvent tends to remain in the gap between the semiconductor chip and the lead 110a shown in FIG. The remaining solvent volatilizes over time, so that the problem disappears after a long time, but becomes a problem in the initial stage of manufacturing the address driver. That is, in the initial stage of manufacturing the address driver, the resin remains in the resin and insulation is not sufficiently ensured. Therefore, as shown in FIG. 32, when the address driver is operated, the lead 110a and the outer edge region 104 which is a semiconductor region are in the resin. The present inventors have found that there is a problem of conducting through 111. That is, a leak path 112 is formed between the lead 110a and the outer edge region 104, and a leak current flows. In particular, in the address driver used in the plasma display device, a high voltage is applied to the address electrode (lead 110a), so that a leak current tends to flow when the lead 110a and the outer edge region 104 approach each other.

  Thus, when a leak current flows through the lead 110a and the outer edge region 104, the leak current flows between a plurality of leads formed in the semiconductor chip. The reason for this will be described. FIG. 33 is a plan view showing the vicinity of the outer periphery of a semiconductor chip mounted with TCP. As shown in FIG. 33, a groove separation region 102 is formed in the semiconductor chip, and the element formation region 103 and the outer edge region 104 are electrically separated by the groove separation region 102. In the element formation region 103, bump electrodes 109a to 109d are arranged along the groove separation region 102, and leads 110a to 110d are connected to the bump electrodes 109a to 109d, respectively. The semiconductor chip is actually covered with a resin, but the resin is not shown in FIG.

  For example, FIG. 32 shows a cross section of the bump electrode 109a of FIG. 33. As shown in FIG. 32, since the solvent remains in the resin 111 in the initial stage of manufacturing the address driver, the lead 110a and the outer edge region are shown. A leakage path 112 exists between the terminal 104 and the leakage current. Next, as can be seen from FIG. 33, since the outer edge region 104 is a semiconductor region and a current flows, a leak path 113 is formed. Then, when the solvent contained in the resin again remains, for example, a leak path is formed from the outer edge region 104 to the lead 110b through the resin. Therefore, a leakage current flows from the lead 110a to the outer edge region 104 through the resin 111, and this leakage current is transmitted to the outer edge region 104 made of the semiconductor region. After that, it flows again to the lead 110b through the resin. In this way, for example, a leak current flows between the lead 110a and the lead 110b. As described above, when a leak current flows between a plurality of leads, the address driver cannot operate normally. Thus, it can be seen that the conventional structure in which the groove separation region 20 and the groove separation region 21 are not provided has a problem that leakage current is generated between a plurality of leads via the resin 111 and the outer edge region 104.

  Therefore, in the first embodiment, a groove separation region 20 is provided as shown in FIG. Thereby, in the outer edge region 23, the region outside the guard ring 19 can be electrically insulated from the guard ring 19. Therefore, since the impedance of the outer edge region 20 can be increased equivalently, it is possible to make it difficult for the leakage current to flow in the outer edge region 23. That is, since the guard ring 19 is formed of a metal film and lowers the impedance of the outer edge region 23, leakage current easily flows through the outer edge region 23. However, by providing the groove isolation region 20, the guard ring 19 The outer region can be electrically isolated from the guard ring 19. For this reason, it is possible to make it difficult for leakage current to flow through the outer edge region 23. That is, even if a leak path is generated between the lead and the outer edge region 23 through a resin in which the solvent does not volatilize, the impedance of the outer edge region 23 is increased, so that the leakage current is not easily transmitted through the outer edge region 23 thereafter. be able to. In addition, although the point which provided this groove | channel isolation | separation area | region 20 is one characteristic of this Embodiment 1, it can be said that it is an additional element. In other words, the configuration is required when the guard ring 19 is provided in the outer edge region 23, but the guard ring 19 may not be provided. In this case, it is not necessary to provide the groove separation region 20.

  The essential feature of the first embodiment is that a plurality of groove separation regions 21 are provided. As shown in FIG. 12, the plurality of groove separation regions 21 are formed in a direction intersecting the groove separation region 20, and the outer edge region 23 is subdivided into a plurality of minute regions. The plurality of minute regions are electrically insulated by the groove separation region 21. Thereby, it is possible to prevent a leak path from being formed in the outer edge region 23. This point will be described with reference to FIG.

  For example, it is assumed that a leak path is formed between the lead 14c connected to the bump electrode 11c and the outer edge region 23 through a resin that does not volatilize the solvent. Similarly, it is assumed that a leak path is also formed between the lead 14d connected to the bump electrode 11d and the outer edge region 23 through a resin that does not volatilize the solvent. That is, in FIG. 12, the lead 14c and the region 31a are conducted through the resin, and the lead 14d and the region 31b are conducted through the resin.

  Here, the outer edge region 23 is subdivided into minute regions insulated from each other by the groove separation region 21. That is, there are a plurality of minute regions electrically insulated by the groove separation region 21 between the region 31a and the region 31b. Therefore, since the region 31a and the region 31b are electrically insulated, a leak path that connects the region 31a and the region 31b is not formed. That is, even if the lead 14c and the region 31a or the lead 14d and the region 31b are electrically connected via the resin, the region 31a and the region 31b are electrically insulated, so that the leak path connecting the lead 14c and the lead 14d is not connected. For this reason, a short circuit failure between the lead 14c and the lead 14d can be prevented. As described above, by providing a plurality of groove separation regions 21 and subdividing the outer edge region 23 into a plurality of electrically insulated minute regions, it is possible to prevent short-circuit defects between leads. In particular, an address driver used in a plasma display apparatus uses a high voltage for an output signal. That is, a high voltage is applied to the leads 14a to 14d connected to the bump electrodes 14a to 14d, respectively. For this reason, it becomes easy to conduct | electrically_connect the lead | read | reed 14a-14d and the outer edge area | region 23 through the resin which does not volatilize a solvent. However, even in this case, the outer edge region 23 can be subdivided into minute regions that are electrically insulated from each other by the groove separation region 21, so that the outer edge region 23 can be prevented from becoming a leak path. That is, a short circuit failure between the leads 14a to 14d through the resin and the outer edge region can be prevented.

  In the first embodiment, the outer edge region 23 is subdivided into a plurality of minute regions by the groove separation region 21, but the interval between the groove separation regions 21 is narrower than the interval between the plurality of leads 14a to 14d. Is desirable. This is because the shorter the interval between the groove separation regions 21, the shorter the short circuit between the leads 14 a to 14 d can be prevented. This is because, for example, in FIG. 12, the interval between the groove separation regions 21 is narrower than the interval between the leads 14a to 14d. In this case, the region 31a that is electrically connected to the lead 14c and the region that is electrically connected to the lead 14d. A plurality of minute regions intervene between 31b. For this reason, it can be seen that a leak path hardly occurs between the region 31a and the region 31b. That is, the narrower the interval between the groove separation regions 21, the more the leak path can be prevented from being formed in the outer edge region 23.

  On the other hand, when the interval between the groove separation regions 21 is made larger than the interval between the leads 14a to 14d, for example, the region 31a and the region 31b shown in FIG. 12 are included in the same minute region. Then, since a leak current flows between the same minute regions, a short defect occurs between the lead 14c and the lead 14d. Therefore, it is desirable that the interval between the groove separation regions 21 be narrower than the interval between the leads 14a to 14d.

  Although it is preferable that the interval between the groove isolation regions 21 is narrowed, in an extreme case, it is conceivable that all the outer edge regions 23 are insulating regions. However, in this case, a manufacturing process in which the outer edge region 23 is entirely an insulating region is required, and the process becomes complicated. On the other hand, in the first embodiment, the groove separation region 20 and the groove separation region 21 are formed. The trench isolation region 20 and the trench isolation region 21 have the same configuration as the trench isolation region 13 that separates the element formation region and the outer edge region. Therefore, since the groove separation region 20 and the groove separation region 21 can be formed in the conventional step of forming the groove separation region 13, it is possible to prevent the process from becoming complicated.

  The semiconductor device according to the first embodiment is configured as described above, and the manufacturing method thereof will be described below with reference to the drawings.

  First, as shown in FIG. 13, an SOI substrate (semiconductor wafer) is prepared. The SOI substrate is a substrate having a silicon single crystal formed on an insulator, and includes an SOI substrate called SIMOX (Silicon Implanted Oxide) and an SOI substrate called a bonded substrate. An SOI substrate called SIMOX is a substrate in which a buried oxide film is formed inside a semiconductor substrate by ion implantation of oxygen into a semiconductor substrate made of silicon at a high energy (up to 180 Kev) and a high concentration, followed by high-temperature heat treatment. . An SOI substrate called a bonded substrate is a semiconductor substrate made of silicon with a silicon oxide film formed on the surface and another silicon substrate made by thermocompression bonding through the silicon oxide film, and then the substrate on one side is halfway. This is a substrate having a silicon single crystal layer on a silicon oxide film produced by grinding and removing to the maximum. By forming the MISFET on the SOI substrate, it is possible to completely isolate the element, and the capacity of the source region or the drain region can be reduced, so that the integration density and the operation speed are improved, the withstand voltage is increased, and the latching is performed. There is an advantage that can be made up-free. As shown in FIG. 13, in the SOI substrate, a buried insulating layer 41 is formed on a support substrate 40 made of silicon, and an active layer 42 made of, for example, silicon is formed on the buried insulating layer 41. The buried insulating layer 41 is made of, for example, a silicon oxide film.

  Next, as shown in FIG. 14, an element isolation region 44 is formed on the active layer 42. The element isolation region is provided so that the elements do not interfere with each other. This element isolation region can be formed by using, for example, a LOCOS (local Oxidation of silicon) method. For example, in the LOCOS method, the element isolation region is formed as follows. That is, the silicon nitride film 43 is formed on the active layer 42. Then, the silicon nitride film 43 is patterned using a photolithography technique and an etching technique. The patterning is performed so that the silicon nitride film 43 does not remain in the region for forming the element isolation region. Thereafter, heat treatment is performed on the SOI substrate. Then, in the region where the silicon nitride film 43 is not formed, the active layer 42 is oxidized to form an element isolation region 44 made of a silicon oxide film. On the other hand, in the region where the silicon nitride film 43 is formed, the silicon oxide film is not formed due to the oxidation resistance of the silicon nitride film 43. In this manner, the element isolation region 44 is formed according to the patterning shape of the silicon nitride film 43.

  Subsequently, as shown in FIG. 15, a resist film 45 is formed on the active layer 42 in which the element isolation region 44 is formed. Then, the resist film 45 is patterned by using a photolithography technique. The patterning is performed so that the resist film 45 does not remain in the region where the groove 46 is formed. Thereafter, a groove 46 is formed by etching using the patterned resist film 45 as a mask. The groove 46 is formed so as to penetrate the active layer 42 and reach the buried insulating layer 41. There are various types of grooves 46. First, a groove for separating the element formation region and the outer edge region, a groove for separating each CMISFET formation region, and a groove formed in the outer edge region, which is a feature of the first embodiment, are formed. That is, these grooves are formed as the grooves 46.

  Next, as shown in FIG. 16, a silicon oxide film 47 is formed on the SOI substrate, and the silicon oxide film 47 is embedded in the trench 46. Thereafter, as shown in FIG. 17, the trench isolation regions 49 to 50 are formed by removing the resist film 45 and the silicon nitride film 43. The trench isolation region 48 is for separating the element formation region and the outer edge region, and the trench isolation region 49 is for separating each CMISFET formation region. The groove separation region 50 is a groove formed in the outer edge region, and is a groove characteristic of the first embodiment. The groove separation region 50 has a function of electrically separating a guard ring formed in a process described later. The groove separation region 50 is formed so as to be parallel to the groove separation region 48. In FIG. 17, the groove separation region 50 is illustrated, but the outer edge region includes a plurality of grooves in a direction intersecting the groove separation region 50, that is, in a direction from the groove separation region 50 to the outside of the outer edge region. An isolation region (not shown) is formed. Although this groove separation region (not shown) does not appear in the cross-sectional view shown in FIG. 17, it is a feature of the first embodiment. The groove separation region (not shown) and the groove separation region 50 form an outer edge. The region is subdivided into a plurality of minute regions that are electrically insulated from each other.

  Next, as shown in FIG. 18, a well is formed by introducing impurities into the CMISFET formation region. For example, the p-type well 51 is formed in the n-channel MISFET formation region in the CMISFET formation region, and the n-type well 52 is formed in the p-channel MISFET formation region. The p-type well 51 is formed by introducing a p-type impurity such as boron into the active layer 42 by ion implantation. Similarly, the n-type well 52 is formed by introducing an n-type impurity such as phosphorus (P) or arsenic (As) into the active layer 42 by ion implantation.

  Subsequently, a channel formation semiconductor region (not shown) is formed in the surface region of the p-type well 51 and the surface region of the n-type well 52. This channel forming semiconductor region is formed to adjust the threshold voltage for forming the channel.

Next, a gate insulating film 53 is formed on the active layer 42. The gate insulating film 53 is formed of, for example, a silicon oxide film, and can be formed using, for example, a thermal oxidation method. However, the gate insulating film 53 is not limited to the silicon oxide film and can be variously changed. For example, the gate insulating film 53 may be a silicon oxynitride film (SiON). That is, a structure in which nitrogen is segregated at the interface between the gate insulating film 53 and the active layer 42 may be employed. The silicon oxynitride film has a higher effect of suppressing generation of interface states in the film and reducing electron traps than the silicon oxide film. Therefore, the hot carrier resistance of the gate insulating film 53 can be improved, and the insulation resistance can be improved. In addition, the silicon oxynitride film is less likely to penetrate impurities than the silicon oxide film. For this reason, by using a silicon oxynitride film for the gate insulating film 53, it is possible to suppress a variation in threshold voltage caused by diffusion of impurities in the gate electrode toward the active layer 42 side. For example, the silicon oxynitride film may be formed by heat-treating the SOI substrate in an atmosphere containing nitrogen such as NO, NO _2, or NH ₃ . Further, after forming a gate insulating film 53 made of a silicon oxide film on the surface of the SOI substrate, the SOI substrate is heat-treated in an atmosphere containing nitrogen, and nitrogen is segregated at the interface between the gate insulating film 53 and the SOI substrate. The same effect can be obtained.

  The gate insulating film 53 may be formed of a high dielectric constant film having a dielectric constant higher than that of, for example, a silicon oxide film. Conventionally, a silicon oxide film has been used as the gate insulating film 53 from the viewpoint of high insulation resistance and excellent electrical and physical stability at the silicon-silicon oxide interface. However, with the miniaturization of elements, the thickness of the gate insulating film 53 is required to be extremely thin. When such a thin silicon oxide film is used as the gate insulating film 53, a so-called tunnel current is generated in which electrons flowing through the channel of the MISFET tunnel through the barrier formed by the silicon oxide film and flow to the gate electrode.

  Therefore, by using a material having a dielectric constant higher than that of the silicon oxide film, a high dielectric film capable of increasing the physical film thickness even with the same capacitance has been used. According to the high dielectric film, since the physical film thickness can be increased even if the capacitance is the same, the leakage current can be reduced.

For example, a hafnium oxide film (HfO ₂ film), which is one of hafnium oxides, is used as the high dielectric film. Instead of the hafnium oxide film, a hafnium aluminate film, an HfON film (hafnium oxynitride film) is used. ), HfSiO films (hafnium silicate films), HfSiON films (hafnium silicon oxynitride films), HfAlO films, and other hafnium-based insulating films can also be used. Further, a hafnium-based insulating film in which an oxide such as tantalum oxide, niobium oxide, titanium oxide, zirconium oxide, lanthanum oxide, or yttrium oxide is introduced into these hafnium-based insulating films can also be used. Since the hafnium-based insulating film has a dielectric constant higher than that of the silicon oxide film or the silicon oxynitride film, like the hafnium oxide film, the same effect as that obtained when the hafnium oxide film is used can be obtained.

  Subsequently, a polysilicon film is formed on the gate insulating film 53. The polysilicon film can be formed using, for example, a CVD method. Then, n-type impurities such as phosphorus and arsenic are introduced into the polysilicon film formed in the n-channel type MISFET formation region by using a photolithography technique and an ion implantation method. Similarly, a p-type impurity such as boron is introduced into the polysilicon film formed in the p-channel MISFET formation region.

  Next, the polysilicon film is processed by etching using the patterned resist film as a mask to form a gate electrode 54a in the n-channel MISFET formation region and a gate electrode 54b in the p-channel MISFET formation region.

  Here, an n-type impurity is introduced into the polysilicon film in the gate electrode 54a in the n-channel type MISFET formation region. Therefore, the work function value of the gate electrode can be set to a value in the vicinity of the conduction band of silicon (4.15 eV), so that the threshold voltage of the n-channel MISFET can be reduced. On the other hand, a p-type impurity is introduced into the polysilicon film in the gate electrode 54b in the p-channel MISFET formation region. Therefore, the work function value of the gate electrode can be set to a value in the vicinity of the valence band of silicon (5.15 eV), so that the threshold voltage of the p-channel MISFET can be reduced. Thus, in the first embodiment, the threshold voltage can be reduced in both the n-channel MISFET and the p-channel MISFET (dual gate structure).

  Subsequently, a shallow n-type impurity diffusion region 55 aligned with the gate electrode 54a of the n-channel MISFET is formed by using a photolithography technique and an ion implantation method. The shallow n-type impurity diffusion region 55 is a semiconductor region. Similarly, a shallow p-type impurity diffusion region 56 is formed in the p-channel MISFET formation region. The shallow p-type impurity diffusion region 56 is formed in alignment with the gate electrode 54b of the p-channel type MISFET. This shallow p-type impurity diffusion region 56 can be formed by using a photolithography technique and an ion implantation method.

  Next, a silicon oxide film is formed over the SOI substrate. The silicon oxide film can be formed using, for example, a CVD method. Then, the silicon oxide film is anisotropically etched to form side walls 57 on the side walls of the gate electrodes 54a and 54b. The side wall 57 is formed from a single layer film of a silicon oxide film. However, the present invention is not limited to this, and for example, a side wall formed of a laminated film of a silicon nitride film and a silicon oxide film may be formed.

  Subsequently, a deep n-type impurity diffusion region 58 aligned with the sidewall 57 is formed in the n-channel MISFET formation region by using a photolithography technique and an ion implantation method. The deep n-type impurity diffusion region 58 is a semiconductor region. The deep n-type impurity diffusion region 58 and the shallow n-type impurity diffusion region 55 form a source region. Similarly, a drain region is formed by the deep n-type impurity diffusion region 58 and the shallow n-type impurity diffusion region 55. Thus, by forming the source region and the drain region with the shallow n-type impurity diffusion region 55 and the deep n-type impurity diffusion region 58, the source region and the drain region can have an LDD (Lightly Doped Drain) structure.

  Similarly, deep p-type impurity diffusion regions 59 aligned with the sidewalls 57 are formed in the p-channel type MISFET formation region. The deep p-type impurity diffusion region 59 and the shallow p-type impurity diffusion region 56 form a source region and a drain region. Therefore, the source region and the drain region also have an LDD structure in the p-channel type MISFET.

  After forming the deep n-type impurity diffusion region 58 and the deep p-type impurity diffusion region 59 in this way, a heat treatment at about 1000 ° C. is performed. Thereby, the introduced impurities are activated.

  Thereafter, a cobalt film is formed on the semiconductor substrate. At this time, a cobalt film is formed so as to be in direct contact with the gate electrodes 54a and 54b. Similarly, the cobalt film is also in direct contact with the deep n-type impurity diffusion region 58 and the deep p-type impurity diffusion region 59.

  The cobalt film can be formed using, for example, a sputtering method. Then, after the cobalt film is formed, heat treatment is performed to cause the polysilicon film constituting the gate electrodes 54a and 54b to react with the cobalt film, thereby forming the cobalt silicide film 60. Thereby, the gate electrodes 54 a and 54 b have a laminated structure of the polysilicon film and the cobalt silicide film 60. The cobalt silicide film 60 is formed to reduce the resistance of the gate electrodes 54a and 54b. Similarly, by the heat treatment described above, the silicon silicide film 60 reacts with the surface of deep n-type impurity diffusion region 58 and deep p-type impurity diffusion region 59 to form cobalt silicide film 60. Therefore, the resistance can be reduced also in the deep n-type impurity diffusion region 58 and the deep p-type impurity diffusion region 59.

  Then, the unreacted cobalt film is removed from the SOI substrate. In the first embodiment, the cobalt silicide film 60 is formed. However, for example, a nickel silicide film or a titanium silicide film may be formed instead of the cobalt silicide film.

  Next, as shown in FIG. 20, a silicon oxide film to be the interlayer insulating film 61 is formed on the main surface of the SOI substrate. This silicon oxide film can be formed using, for example, a CVD method using TEOS (tetraethyl orthosilicate) as a raw material. Thereafter, the surface of the silicon oxide film is planarized using, for example, a CMP (Chemical Mechanical Polishing) method.

  Subsequently, contact holes are formed in the silicon oxide film by using a photolithography technique and an etching technique. Then, a titanium / titanium nitride film is formed on the silicon oxide film including the bottom surface and inner wall of the contact hole. The titanium / titanium nitride film is composed of a laminated film of a titanium film and a titanium nitride film, and can be formed by using, for example, a sputtering method. This titanium / titanium nitride film has a so-called barrier property that prevents, for example, tungsten, which is a material of a film to be embedded in a later process, from diffusing into silicon.

  Subsequently, a tungsten film is formed on the entire main surface of the SOI substrate so as to fill the contact hole. This tungsten film can be formed using, for example, a CVD method. Then, the plug 62 can be formed by removing the unnecessary titanium / titanium nitride film and tungsten film formed on the silicon oxide film by, for example, the CMP method.

  Next, a titanium / titanium nitride film, an aluminum film containing copper, and a titanium / titanium nitride film are sequentially formed on the silicon oxide film and the plug 62. These films can be formed by using, for example, a sputtering method. Subsequently, these films are patterned by using a photolithography technique and an etching technique, and the wiring 64 is formed. Thereafter, similarly, an interlayer insulating film 63 is formed on the wiring 64, and a second layer wiring is formed on the interlayer insulating layer 63. In this wiring step, wiring is formed, but a guard ring 65 is formed in the outer edge region. The guard ring 65 is formed between the groove separation region 48 and the groove separation region 50. Accordingly, the outer edge region is electrically insulated from the guard ring 65 by the groove separation region 50.

  Thereafter, a surface protective film 66 is formed on the SOI substrate. Then, an opening reaching the pad (wiring) is formed in the surface protective film 66, and a gold film is formed in the opening using, for example, a plating method. Thereby, the bump electrode 67 can be formed. In this manner, an SOI substrate (semiconductor wafer) on which the address driver (semiconductor device) in the first embodiment is formed can be obtained.

  FIG. 21 is a plan view showing a part of an SOI substrate on which an address driver is formed. As shown in FIG. 21, a plurality of chip regions 68 are formed on the SOI substrate, and an address driver serving as a semiconductor chip is formed in each chip region 68. In each chip region 68, a groove isolation region 48 is formed inside the outer periphery of the chip region 68, and an inner region from the groove isolation region 48 is an element formation region. Further, the outer region from the groove separation region 48 is an outer edge region. Bump electrodes 67 are formed along the trench isolation region 48 in the element formation region. On the other hand, in the outer edge region, a guard ring 65 is formed outside the groove separation region 48, and a groove separation region 50 is formed so as to surround the guard ring 65. A plurality of groove separation regions 69 are formed from the groove separation region 50 toward the outer region. That is, a plurality of groove separation regions 69 are formed in a direction intersecting with the groove separation region 50. Such an SOI substrate is diced along a dicing line 70 to be separated into individual semiconductor chips. Here, an enlarged view of the region 71 of FIG. 21 is shown in FIG.

  FIG. 22 shows the groove separation region 50 and the groove separation region 69. It can be seen that the groove separation region 69 does not reach the dicing line 70. That is, since an inspection pattern called TEG is usually formed on the dicing line 70, the groove separation region 69 is not formed on the dicing line 70 so that the inspection pattern can be formed on the dicing line 70. However, when the trench isolation region 69 is separated into semiconductor chips, it is necessary to reach the outer end of the semiconductor chip. That is, since the outer edge region needs to be subdivided into a plurality of minute regions insulated from each other by the groove separation region 69, the groove separation region 69 must reach the outer end portion of the semiconductor chip. Therefore, in the first embodiment, the groove separation region 69 does not reach the dicing line 70 but is formed to reach the cutting line 72. That is, dicing is performed using a blade called a blade, but there is a certain cutting width when cutting with the blade. If the groove separation region 69 is formed so as to reach the cutting line 72, the cutting width 72 represents the cut width, and when the SOI substrate is separated into semiconductor chips, it reaches the outer end. There is no problem because the groove isolation region 69 can be formed.

  Note that since the inspection pattern formed on the dicing line 70 is not formed on all the regions of the dicing line, in the region where the inspection pattern is not formed, as shown in FIG. 69 may be formed, that is, the groove isolation region 69 may be formed across the dicing line 70. As a result, the groove isolation region 69 can be reliably formed to reach the outer end portion of the semiconductor chip.

  In this way, the SOI substrate is divided into individual semiconductor chips by dicing. Next, a process of mounting the separated semiconductor chip on the flexible substrate (TCP mounting) will be described. FIG. 24 is a flowchart showing the flow of the mounting process.

  As shown in FIG. 25, the semiconductor chip 75 is disposed in the hole formed in the flexible substrate 76, and the lead 78 formed on the flexible substrate 76 is connected to a bump electrode (not shown) formed on the semiconductor chip 75. (S101 in FIG. 24). This connection is made by crimping the tip of the lead 78 and the bump electrode with the bonding tool 80. The lead 78 is connected to the flexible substrate 76 using an adhesive 77, and a solder resist 79 is formed on the surface of the lead 78.

  Subsequently, a bonding inspection is performed to check whether the lead 78 and the bump electrode are securely connected (S102 in FIG. 24). When the connection between the lead 78 and the bump electrode is confirmed, next, as shown in FIG. 26, potting is performed (S103 in FIG. 24). In FIG. 26, a state in which a resin (resin) 82 is dropped onto the semiconductor chip 75 using the nozzle 81 is shown. The resin 82 includes a resin and a solvent. Examples of the solvent include xylene, toluene, and methyl ethyl ketone. Since these solvents have electrical conductivity, the resin is sealed with a resin, and then the resin is cured by performing a heat treatment such as baking to remove the solvent. In other words, since the resin is hardened and hardened by volatilizing the solvent, heat treatment (temporary cure) is performed after resin sealing with the resin (S104 in FIG. 24).

  Thereafter, marking is performed (S105 in FIG. 24), and heat treatment (main cure) is performed (S106 in FIG. 24). As shown in FIG. 27, the heat treatment is performed by heating the flexible substrate 76 to which the semiconductor chip 75 is connected to cure the resin 82 and volatilize the solvent contained in the resin 82. In addition, heat processing (this cure) and marking may be performed by reversing the process order.

  In this way, the semiconductor chip 75 can be mounted on the flexible substrate 76, and the address driver in the first embodiment can be manufactured. Thereafter, an electrical characteristic test is performed (S107 in FIG. 24), and then an appearance inspection is performed (S108 in FIG. 24). If the product is determined to be a non-defective product through the electrical characteristic test and the appearance inspection, it is packaged and shipped (S109 in FIG. 24).

  As described above, the semiconductor chip is sealed with a resin. At this time, heat treatment is performed in order to remove the conductive solvent contained in the resin and cure it. However, even if heat treatment is performed, in the initial stage when the address driver is manufactured, the solvent may remain in the resin, and insulation may not be ensured. When the address driver is operated in this state, the lead and the outer edge region are electrically connected via the resin, and further, the outer edge region becomes a leak path, and another lead is again electrically connected to the outer edge region via the resin. Eventually, a leakage current flows between the leads via the resin and the outer edge region. This phenomenon occurs in the initial stage of production in which the solvent contained in the resin does not completely evaporate, and does not cause a problem after the solvent has sufficiently evaporated. However, there is a problem that the address driver does not operate normally even in the initial stage of manufacture. Therefore, in the first embodiment, a plurality of groove isolation regions are formed in the outer edge region that becomes a leak path, and the outer edge region is subdivided into a plurality of minute regions that are insulated from each other, thereby causing conduction through the resin. In addition, the leak path can be blocked in the outer edge region. Thereby, it is possible to prevent the leakage current between the leads.

  As described above, according to the first embodiment, it is possible to prevent the leakage current between the leads due to the solvent contained in the resin not being completely volatilized. In particular, the first embodiment works effectively in an electrical characteristic test performed after sealing a semiconductor chip with a resin. In the first embodiment, the effect of preventing the leakage current between the leads can be obtained in the initial stage immediately after the address driver is actually shipped as a product. However, it is during the electrical characteristic test that the address driver is first operated after sealing with the resin. In this electrical characteristic test, if a leak current occurs between the leads because the solvent contained in the resin does not completely evaporate, it is determined as a defective product. However, in practice, if the solvent contained in the resin volatilizes, there is no problem, and it is not appropriate to judge it as a defective product. In other words, short-circuit defects that occur between leads due to the solvent in the resin not completely evaporating and short-circuit defects due to inherent structural defects can no longer be distinguished in the electrical characteristic test, reducing the reliability of the electrical characteristic test. To do. Therefore, according to the address driver to which the countermeasure shown in the first embodiment is applied, it is possible to prevent the occurrence of a leakage current between the leads due to the solvent contained in the resin not being volatilized. For this reason, even in the electrical characteristic test performed in the initial stage of manufacture, the short circuit defect that occurs between the leads does not occur because the solvent contained in the resin does not completely evaporate. Only short-circuit defects can be detected. Thereby, the reliability of the test | inspection in an electrical property test can be improved.

  According to the first embodiment, since it is not necessary to increase the height of the bump electrode made of a gold film in order to prevent a leakage current between the leads, it is possible to increase the manufacturing cost without increasing the manufacturing cost. Generation of leakage current can be prevented. Further, since it is not necessary to increase the width of the outer edge region in order to prevent the leakage current between the leads, similarly, the generation of the leakage current between the leads can be prevented without increasing the manufacturing cost.

  It is clear that COF (Chip On Film) having a similar process has the same problem and can be handled by a similar method.

(Embodiment 2)
In the first embodiment, an example in which a plurality of groove separation regions are formed in a direction intersecting the guard ring has been described. In the second embodiment, a plurality of groove separation regions are formed in a direction parallel to the guard ring. An example will be described.

  FIG. 28 is a plan view showing the vicinity of the outer end portion of the semiconductor chip according to the first embodiment. 28 differs from the first embodiment in that a plurality of groove separation regions 85 are provided. That is, the point that the groove separation region 13 that separates the element formation region 22 and the outer edge region 23 is formed is the same as in the first embodiment. A guard ring 19 is formed in the outer edge region 23 so as to be parallel to the groove separation region 13, and a plurality of groove separation regions 85 are formed outside the guard ring 19. In the first embodiment, the groove separation region formed outside the guard ring 19 is formed in a direction intersecting the guard ring 19, but in the second embodiment, the groove separation region 85 formed outside the guard ring 19 is formed. Are formed in parallel with the guard ring 19. The outer edge region 23 can be subdivided into a plurality of minute regions also by forming the plurality of groove separation regions 85 in this way. That is, since the width of the active layer constituting the outer edge region 23 is narrowed by the groove isolation region 85, the resistance value can be increased. That is, by providing a plurality of groove separation regions 85 and narrowing the interval between the groove separation regions 85, the impedance of the outer edge region 23 exposed on the chip cross section can be increased. Further, the variation in the width of the active layer constituting the outer edge region 23 exposed in the cross section of the chip due to the variation in cutting due to dicing can be suppressed to be equal to or less than the interval between the plurality of groove isolation regions 85 provided. For this reason, the width of the active layer constituting the outer edge region 23 can be kept narrow, and the resistance value can be kept high. For this reason, as in the first embodiment, it is possible to prevent leakage current between leads.

  For example, in FIG. 28, it is assumed that a certain line-shaped region separated by the plurality of groove separation regions 85 is electrically connected to the lead through the resin. Further, it is assumed that a line-shaped region that is another lead is electrically connected to the lead through the resin. In this case, since the resistance value is high when the width of the active layer constituting the outer edge region 23 where the chip cross section is exposed is equal to or less than the interval between the groove isolation regions 85, a leak current is hardly generated between the leads.

  FIG. 29 is a cross-sectional view showing a cross section taken along line AA of FIG. FIG. 29 is substantially the same as that of the first embodiment, but it can be seen that a plurality of groove separation regions 85 are formed outside the guard ring 19 in the outer edge region 23. It can be seen that the groove separation region 85 subdivides the outer edge region 23 into a plurality of minute regions insulated from each other.

  As described above, according to the second embodiment, it can be understood that the short-circuit defect occurring between the leads can be prevented because the solvent contained in the resin does not volatilize.

(Embodiment 3)
The third embodiment is an example in which the first embodiment and the second embodiment are combined. FIG. 30 is a plan view showing the vicinity of the outer end portion of the semiconductor chip according to the third embodiment. In FIG. 30, the difference from the first embodiment and the second embodiment is that a plurality of groove separation regions 86 and a plurality of groove separation regions 87 are provided. That is, the point that the groove isolation region 13 that separates the element formation region 22 and the outer edge region 23 is formed is the same as in the first and second embodiments. A guard ring 19 is formed in the outer edge region 23 in parallel with the groove separation region 13, and a plurality of groove separation regions 86 and groove separation regions 87 are formed outside the guard ring 19. The third embodiment has a groove separation region 86 formed in a direction parallel to the guard ring 19 and a groove separation region 87 formed in a direction intersecting the guard ring 19. Thereby, since the outer edge area | region 23 can be subdivided into the vertical and horizontal directions, the impedance of the outer edge area | region 23 can be raised further.

  31 is a cross-sectional view showing a cross section taken along line AA of FIG. FIG. 31 is similar to the first embodiment, but it can be seen that a plurality of groove separation regions 86 and groove separation regions 87 are formed outside the guard ring 19 in the outer edge region 23. It can be seen that the groove separation region 86 and the groove separation region 87 subdivide the outer edge region 23 into a plurality of minute regions insulated from each other.

  As described above, according to the third embodiment, it can be seen that the short-circuit defect occurring between the leads can be prevented because the solvent contained in the resin does not volatilize.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention can be widely used in the manufacturing industry for manufacturing semiconductor devices.

1 is a circuit block diagram showing a circuit configuration of a semiconductor device (address driver) according to a first embodiment of the present invention. FIG. 2 is a circuit diagram illustrating an example of a circuit configuration of an output unit in FIG. 1. It is a table | surface which shows the relationship between the input in FIG. 2, and an output. 4 is a plan view showing the semiconductor chip in the first embodiment. FIG. It is a figure which shows the state which mounted the semiconductor chip on the mounting board | substrate. It is the enlarged view to which the semiconductor chip vicinity of FIG. 5 was expanded. It is sectional drawing cut | disconnected by the AA line of FIG. It is the enlarged view to which a part of FIG. 6 was expanded. It is sectional drawing cut | disconnected by the AA line of FIG. It is sectional drawing cut | disconnected by the BB line of FIG. It is a perspective view which shows the outer end part vicinity of the semiconductor chip which connected the lead | read | reed. It is a figure explaining that it can prevent that a leak current generate | occur | produces between leads. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device in the first embodiment. FIG. FIG. 14 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 13; FIG. 15 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 14; FIG. 16 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 15; FIG. 17 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 16; FIG. 18 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 17; FIG. 19 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 18; FIG. 20 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 19; It is a figure which shows the chip | tip area | region of a semiconductor wafer. It is the enlarged view to which a part of FIG. 21 was expanded. It is a figure which shows the modification of FIG. It is a flowchart which shows the flow of the process of mounting a semiconductor chip on a flexible substrate. It is sectional drawing which shows a mode that a lead is crimped | bonded to the bump electrode of a semiconductor chip. It is sectional drawing which shows a mode that resin is dripped at the semiconductor chip connected to the flexible substrate. It is sectional drawing which shows a mode that heat processing is performed to the flexible substrate carrying a semiconductor chip. FIG. 10 is a plan view showing the vicinity of an outer end portion of a semiconductor chip in a second embodiment. It is sectional drawing cut | disconnected by the AA line of FIG. FIG. 10 is a plan view showing the vicinity of the outer end portion of a semiconductor chip in a third embodiment. It is sectional drawing cut | disconnected by the AA line of FIG. It is the figure which the present inventors examined, Comprising: It is sectional drawing which shows the outer end part vicinity of a semiconductor chip. It is the figure which the present inventors examined, Comprising: It is a top view which shows the outer end part vicinity of a semiconductor chip.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Circuit 2 Shift register 3 Latch circuit 4 Control circuit 5 Prebuffer 6 Level shift circuit 7 Driver 8 Output part 10 Semiconductor chip 11 Bump electrode 11a-11d Bump electrode 12 Flexible substrate 13 Groove isolation area 14 Lead 14a-14d Lead 15 Area 16 Adhesive 17 Solder resist 18 Resin 19 Guard ring 20 Groove isolation region 21 Groove isolation region 22 Element formation region 23 Outer edge region 25 Support substrate 26 Embedded insulating layer 27 Interlayer insulating film 28 Surface protection film 29 Pad 30 Resin 31a region 31b region 40 Support Substrate 41 Embedded insulating layer 42 Active layer 43 Silicon nitride film 44 Element isolation region 45 Resist film 46 Groove 47 Silicon oxide film 48 Groove isolation region 49 Groove isolation region 50 Groove isolation region 51 p-type well 52 n-type well 53 gate insulating film 54a gate electrode 54b gate electrode 55 shallow n-type impurity diffusion region 56 shallow p-type impurity diffusion region 57 sidewall 58 deep n-type impurity diffusion region 59 deep p-type impurity diffusion region 60 cobalt silicide film 61 interlayer Insulating film 62 Plug 63 Interlayer insulating film 64 Wiring 65 Guard ring 66 Surface protective film 67 Bump electrode 68 Chip area 69 Groove isolation area 70 Dicing line 71 area 72 Cutting line 75 Semiconductor chip 76 Flexible substrate 77 Adhesive 78 Lead 79 Solder resist 80 Bonding tool 81 Nozzle 82 Resin 85 Groove separation region 86 Groove separation region 87 Groove separation region 100 Support substrate 101 Embedded insulating layer 102 Groove separation region 103 Element formation region 104 Outer edge region 105 Interlayer insulation 106 guard ring 107 pad 108 surface protective film 109a bump electrode 110a leads 111 Resin 112 leak path 113 leakage path A1~A3 data input terminal OUT1~192 output IN1~3 input (output unit input)
CLK clock LAT latch control signal SUS data input terminal STB data input terminal VDD1 logic power supply VDD2 high voltage power supply M1, M2, M6, M8 n-channel transistors M3, M4, M5, M7 p-channel transistors

Claims (11)

(A) a semiconductor substrate;
(B) a buried insulating layer buried in the semiconductor substrate;
(C) an active layer made of a semiconductor region formed on the buried insulating layer;
(D) a first trench isolation region that extends from the active layer to the buried insulating layer and is formed along the outer periphery of the semiconductor chip;
In the semiconductor device, an element formation region is formed inside the first groove isolation region and an outer edge region is formed outside the first groove isolation region by the first groove isolation region,
A plurality of second groove isolation regions are formed in the outer edge region in a direction intersecting with the first groove isolation region. The semiconductor device according to claim 1,
The semiconductor device, wherein the plurality of second groove isolation regions reach the outer end of the semiconductor chip. The semiconductor device according to claim 1,
The outer edge region is subdivided into regions insulated from each other by the plurality of second groove isolation regions. The semiconductor device according to claim 1,
The semiconductor device, wherein the plurality of second groove isolation regions reach the buried insulating layer. The semiconductor device according to claim 1, further comprising:
(E) a plurality of bump electrodes formed in the element formation region;
(F) a plurality of leads connected to each of the plurality of bump electrodes;
(G) A semiconductor device comprising: a resin formed on the semiconductor substrate including between the plurality of leads and the outer edge region. The semiconductor device according to claim 5,
An interval between the plurality of second groove isolation regions is narrower than an interval between the plurality of leads. The semiconductor device according to claim 1,
In the outer edge region, a guard ring is formed so as to surround the semiconductor chip,
3. A semiconductor device, wherein a third groove isolation region is formed outside the guard ring so as to be parallel to the first groove isolation region. The semiconductor device according to claim 7,
The semiconductor device according to claim 1, wherein the third trench isolation region reaches the buried insulating layer. The semiconductor device according to claim 1,
The semiconductor device is an address driver used in a plasma display device. (A) a semiconductor substrate;
(B) a buried insulating layer buried in the semiconductor substrate;
(C) an active layer made of a semiconductor region formed on the buried insulating layer;
(D) a first trench isolation region that extends from the active layer to the buried insulating layer and is formed along the outer periphery of the semiconductor chip;
In the semiconductor device, an element formation region is formed inside the first groove isolation region and an outer edge region is formed outside the first groove isolation region by the first groove isolation region,
A plurality of third groove isolation regions are formed in the outer edge region in a direction parallel to the first groove isolation region. (A) a semiconductor substrate;
(B) a buried insulating layer buried in the semiconductor substrate;
(C) an active layer made of a semiconductor region formed on the buried insulating layer;
(D) a first trench isolation region that extends from the active layer to the buried insulating layer and is formed along the outer periphery of the semiconductor chip;
In the semiconductor device, an element formation region is formed inside the first groove isolation region and an outer edge region is formed outside the first groove isolation region by the first groove isolation region,
In the outer edge region, a plurality of second groove separation regions are formed in a direction intersecting the first groove separation region, and a plurality of third groove separation regions are formed in a direction parallel to the first groove separation region. A semiconductor device characterized by comprising:

Images