JP2008131320A - Flip-flop circuit and display device - Google Patents

Abstract

A setup time and a data output time are shortened without increasing a gate load of a latch node of a sense amplifier unit.
In a sense amplifier type flip-flop circuit, when a differential sense amplifier circuit is configured, a switch element (between output nodes Fa and Fb of a differential input section 12 and latch nodes n11 and n12 of a sense latch section 11 is provided. In this example, N-channel transistors N15 and N16) are connected, and the latch nodes n11 and n12 are connected from the differential input unit 12 during the period (precharge period) when the clock signal CK is at “L” level by the action of the switch element. Try to separate.
[Selection] Figure 1

Description

  The present invention relates to a flip-flop circuit and a display device, and more particularly to a flip-flop circuit using a sense amplifier and a display device using the flip-flop circuit.

  In a clock synchronous system configured using a flip-flop circuit, it is important to shorten the setup time and data output time of the flip-flop circuit in order to realize high-speed circuit operation.

  As one of the flip-flop circuits capable of high-speed operation, “Sense-Amplifier-Based Flip-Flop” (hereinafter referred to as “sense-amplifier type flip-flop”) is improved by setting up a differential sense amplifier using an inverter loop. (For example, see Non-Patent Document 1).

  FIG. 6 shows a basic configuration of the sense amplifier type flip-flop circuit. The sense amplifier type flip-flop circuit includes a differential sense amplifier circuit 100 and an RS latch circuit 200.

  The differential sense amplifier circuit 100 receives a clock signal CK and a data signal D synchronized with the clock signal CK. The differential sense amplifier circuit 100 generates a one-shot pulse signal Sb or Rb synchronized with the clock signal CK according to the polarity of the data signal D. The one-shot pulse signals Sb and Rb are input to the RS latch circuit 200. The RS latch circuit 200 outputs output signals Q / Qb having opposite phases according to the states of the one-shot pulse signals Sb and Rb, and holds the data signal D.

  FIG. 7 is a circuit diagram showing a circuit configuration according to a conventional example of the differential sense amplifier circuit 100. As shown in FIG. 7, the differential sense amplifier circuit 100 according to the conventional example has a configuration including a sense latch unit 101 and a differential input unit 102.

  The sense latch unit 101 includes P-channel transistors P101 and P102 and N-channel transistors N101 and N102, and performs a latch operation in synchronization with the clock signal CK. The differential input unit 102 includes N-channel transistors N103 and N104 and an inverter INV101, and performs a differential operation according to the polarity of the data signal D synchronized with the clock signal CK.

  In the differential sense amplifier circuit 100, during a period when the clock signal CK is at a high level (hereinafter referred to as “H” level), the N-channel transistor N105 constituting the current source is turned on, and this differential sense amplifier circuit When 100 operates, the latch operation of the data signal D is executed.

  On the other hand, during a period when the clock signal CK is at a low level (hereinafter referred to as “L” level), the N-channel transistor N105 is cut off, thereby releasing the data latch and the data latch in the next cycle. In preparation, the potentials Sb and Rb of the latch nodes n101 and n102 are precharged to the VDD level (power supply level) by N channel transistors (latch node precharge transistors) P103 and P104.

  The N-channel transistor N106 is arranged so that the supply of the VSS level (ground level) to the sense latch unit 101 is not interrupted even when the polarity of the data signal D is inverted after data latching.

  FIG. 8 is a circuit diagram showing an example of the circuit configuration of the RS latch circuit 200. As shown in FIG. 8, the RS latch circuit 200 includes two inverters INV201 and INV202, P channel transistors P201 to P206, and N channel transistors N201 to N206.

  Next, the circuit operation of the conventional sense amplifier type flip-flop circuit composed of the differential sense amplifier circuit 100 and the RS latch circuit 200 configured as described above will be described with reference to the timing chart of FIG.

  First, during a period when the clock signal CK is at “L” level (precharge period in FIG. 9), the precharge charge transistors P103 and P104 are turned on, so that the potentials Sb and Rb of the latch nodes n101 and n102 are precharged to the VDD level. Has been. Further, since the P channel transistors P101 and P102 of the sense latch unit 101 are in the cut-off state and the N channel transistors N101 and N102 are in the on state, the output nodes Fa and Fb of the differential input unit 102 are at the VDD-Vth level. (Vth is a threshold voltage of the N-channel transistor) and is precharged.

  Here, when the data signal D is at “H” level, the N-channel transistor N103 of the differential input unit 102 is turned on, and the N-channel transistor N104 is cut off. Conversely, when the data signal D is at “L” level, the N-channel transistor N103 is cut off and the N-channel transistor N104 is turned on.

  Here, when the clock signal CK becomes “H” level (latch period in FIG. 9), the precharge transistors P103 and P104 are cut off, the N-channel transistor N105 is turned on, and the latch operation is started.

  This latch operation will be described by taking the case where the data signal D is at “H” level as an example. First, when the data signal D is at “H” level, the output node Fa is discharged from the VDD-Vth level to the VSS level by the N-channel transistors N105 and N103. On the other hand, since the N-channel transistor N104 is cut off, the output node Fb is discharged from the VDD-Vth level to the VSS level by the N-channel transistors N105, N103, and N106.

  Due to the difference in the number of gate stages, the output node Fa (indicated by the dotted line in the figure) first changes to the VSS level as indicated by the period t1 in FIG. As a result, the level of the potential Sb of the latch node n101 starts to drop via the N channel transistor N101.

  The sense latch unit 101 forms a feed forward loop. When the level of the potential Sb of the latch node n101 starts to decrease, the P channel transistor P102 starts to turn on, and conversely, the N channel transistor N102 starts to turn off. Finally, the potential Sb of the latch node n101 is fixed to the “L” level, and the potential Rb of the latch node n102 is fixed to the “H” level.

  Conversely, when the data signal D is at the “L” level, the output nodes Fa and Fb and the latch nodes n101 and n102 are connected to the case where the data signal D is at the “H” level as shown in the period t2 of FIG. Will do the opposite.

  As described above, in the sense amplifier type flip-flop circuit according to the conventional example, the potentials of the output nodes Fa and Fb of the differential input unit 102 are input to the source side of the sense latch unit 101, and the sense latch unit 101 outputs the output node. The potential difference between Fa and Fb is detected, amplified and latched, and the inverters 201 and INV202 and the P channel transistors P201 and P206 constituting the SR latch circuit are driven to output the output signal Q / Qb.

  That is, the P-channel transistors P101 and P102 and the N-channel transistors N101 and N102 function as a sense amplifier that detects a potential difference between the output nodes Fa and Fb of the differential input unit 102 and a driver that drives the latch nodes n101 and n102. It will also serve as. Therefore, in order to increase the access time, it is necessary to increase the drivability by increasing the dimensions of the P-channel transistors P101 and P102 and the N-channel transistors N101 and N102.

  However, when the dimensions of the transistors P101, P102 and N101, N102 are increased, the gate capacitance of the latch nodes n101, n102 increases and the coupling noise increases, causing malfunction in the sense amplifier operation, which is another role. There is a disadvantage that it becomes easier.

  For this reason, the dimensions of the transistors P101 and P102 and N101 and N102 cannot be made very large. As a result, when the operating frequency increases, the source side node of the sense latch unit 101 (the output node of the differential input unit 102) The precharge speeds of Fa and Fb are also suppressed, and another problem arises that precharge time becomes insufficient and causes malfunction.

  Therefore, conventionally, a means for separating the sense amplifier unit 101 and the differential input unit 102 is added to suppress the charge / discharge amount of the latch nodes n101 and n102, thereby shortening the setup time and the data output time. (For example, refer to Patent Document 1).

B. Nikolic, et al., “Improved Sense-Amplifier-Based Flip-Flop: Design and Measurements,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, pp.876-884, JUNE., 2000 JP 2004-214717 A

  However, the conventional technique described in Patent Document 1 employs a configuration in which the gate control of the N-channel transistor that performs source-side control of the differential input unit 102 is performed based on the potentials Sb and Rb of the latch nodes n101 and n102. In order to increase the speed, it is necessary to increase the size of the N-channel transistor. This means that the gate load of the latch nodes n101 and n102 increases. When the gate load of the latch nodes n101 and n102 increases, the latch speed decreases, so that the setup time and data output time cannot be sufficiently shortened.

  In view of the above, an object of the present invention is to provide a flip-flop circuit that can shorten the setup time and the data output time without increasing the gate load of the latch node of the sense amplifier unit, and a display device using the flip-flop circuit. And

  The flip-flop circuit according to the present invention includes a latch unit that performs a latch operation in synchronization with a clock signal, a differential input unit that performs a differential operation according to the polarity of a data signal synchronized with the clock signal, and the clock signal Switch means for disconnecting the two input / output nodes of the latch unit and the two output nodes of the differential input unit during the “L” level period; and the differential signal during the “H” level period of the clock signal. And a control means for controlling an enable period during which the input unit is in an operating state.

  In the flip-flop circuit configured as described above, the two input / output nodes of the latch unit are disconnected from the differential input unit during the period when the clock signal CK is at the “L” level by the action of the switching unit, so that The potentials of the two input / output nodes change sharply. As a result, the latch operation in the latch unit is performed at a higher speed, and the transmission of data to the next stage is also performed at a higher speed. In addition, by controlling the enable period of the differential input unit during the “H” level period of the clock signal, the signal change of the data signal input from the outside is not transmitted to the two input / output nodes after the enable period. Therefore, it is possible to secure a data hold time

  According to the present invention, the latch operation is performed at a higher speed without increasing the gate load of the latch node of the sense amplifier unit, and the transmission of data to the latch circuit at the next stage is also performed at a higher speed. The setup time and data output time can be shortened without impairing the hold time characteristics.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  The flip-flop circuit according to the present invention receives a clock signal CK and a data signal D synchronized with the clock signal CK, and generates a one-shot pulse signal Sb or Rb synchronized with the clock signal CK according to the polarity of the data signal D Based on a configuration comprising a differential sense amplifier circuit that performs an output signal Q / Qb having opposite phases according to the states of the one-shot pulse signals Sb and Rb, and an RS latch circuit that latches the data signal D Yes.

  According to the present invention, in this sense amplifier type flip-flop circuit, the setup time and the data output time can be shortened without increasing the size of the transistors constituting the sense latch portion of the differential sense amplifier circuit. Therefore, the configuration of the differential sense amplifier circuit is characterized.

[First Embodiment]
FIG. 1 is a circuit diagram showing a configuration example of a differential sense amplifier circuit according to the first embodiment of the present invention. As shown in FIG. 1, the differential sense amplifier circuit 10 according to the present embodiment has a configuration including a sense amplifier unit 11 and a differential input unit 12 as basic components.

  The sense amplifier unit 11 includes P-channel transistors P11 and P12 whose sources are connected to the VDD line (first power supply line), drains and drains of the transistors P11 and P12 are connected, and the sources are shared. The N channel transistors N11 and N12 are connected to each other.

  In the sense amplifier unit 11, the gates of the transistors P11 and N11 are commonly connected to the drain common connection node n12 of the transistors P12 and N12, and the gates of the transistors P12 and N12 are connected to the drain common connection node n11 of the transistors P11 and N11. Commonly connected. The drain common connection nodes n11 and n12 are latch nodes which are input / output nodes of the sense amplifier unit 11, and are connected to the input / output terminals 13 and 14, respectively.

  The differential input unit 12 includes N-channel transistors N13 and N14 whose sources are connected in common, and an inverter INV11 whose input terminal is connected to the gate of the transistor N13 and whose output terminal is connected to the gate of the transistor N14. A differential operation is performed according to the polarity of the data signal D input to the gate of the N-channel transistor N13 via the data terminal 15.

  The differential sense amplifier circuit 10 according to the present embodiment includes P-channel transistors P13 to P15, N-channel transistors N15 to N18, and an inverter INV12 in addition to the sense amplifier unit 11 and the differential input unit 12.

  P channel transistors P13 and P14 have their sources connected to the VDD line and their drains connected to latch nodes n11 and n12, respectively. A clock signal CK is commonly applied to the gates of the transistors P13 and P14 via the clock terminal 16. That is, the transistors P13 and P14 function as precharge transistors that precharge the potentials Sb and Rb of the latch nodes n11 and n12 to the VDD level during the period when the clock signal CK is at the “L” level.

  N-channel transistors N15 and N16 are connected between latch nodes n11 and n12 of sense amplifier unit 11 and drains of N-channel transistors N13 and N14 of differential input unit 12, respectively. A clock signal CK is commonly applied to the gates of the transistors N15 and N16 via the clock terminal 16.

  The P-channel transistor P15 is connected between the source side node (common connection node of the sources of the N-channel transistors N11 and N12) n13 of the sense amplifier unit 11 and the VDD line. The N-channel transistor N17 is connected between the source-side node n13 of the sense amplifier unit 11 and the VSS line (second power supply line, for example, a ground line). A clock signal CK is commonly applied to the gates of the transistors P15 and N17 via the clock terminal 16.

  The N-channel transistor N18 is a current source transistor of the differential input unit 12, and is between the source side node (common connection node of the sources of the N-channel transistors N13 and N14) n14 of the differential input unit 12 and the VSS line. It is connected to the. The inverter INV12 is connected between the clock terminal 16 and the gate of the N-channel transistor M18, and inverts the polarity of the clock signal CK and applies it to the gate of the transistor N18.

  The differential sense amplifier circuit 10 according to the first embodiment having the above-described configuration is characterized in that the latch nodes n11 and n12 of the sense latch unit 11 and the output nodes of the differential input unit 12 (N-channel transistors N13, N13, N-channel transistors N15 and N16 are connected between each drain of N14) Fa and Fb.

  Here, the N-channel transistors N15 and N16 have the latch nodes n11 and n12 of the sense latch unit 11 and the output nodes Fa and Fb of the differential input unit 102 during a period (precharge period) when the clock signal CK is at “L” level. It has a function as a switch means to disconnect.

  The differential sense amplifier circuit 10 according to the first embodiment is also characterized in that an N-channel transistor N17 and a P-channel transistor P15 are connected to the source side node n13 of the sense amplifier unit 11. The P-channel transistor P15 has a function as precharge means for turning on during a period when the clock signal CK is at "L" level and precharging the source side node n13 to VDD level.

  The differential sense amplifier circuit 10 according to the first embodiment is further characterized in that an inverter INV12 is connected between the clock terminal 16 and the gate of the N-channel transistor N18. The inverter INV12 has a function as control means for controlling an ON period of the N-channel transistor N18 during a period when the clock signal CK is at “H” level, that is, an enable period during which the differential input unit 12 is in an operating state.

  Next, the circuit operation of the differential sense amplifier circuit 10 according to the first embodiment will be described with reference to the timing chart of FIG.

  2, the clock signal CK, the inverted clock signal CKb that is the output of the inverter INV12, the data signal D, the inverted data signal Db that is the output of the inverter INV11, the potential SA of the source side node n13 of the sense latch unit 11, and the latch node Waveforms Sb and Rb of n11 and n12, and S (set), R (reset) input and Q output waveforms of the SR latch circuit of the next stage (see FIG. 6) are shown.

  First, during the period in which the clock signal CK is at the “L” level (precharge period in FIG. 2), the P channel transistors P13 and P14 are in the ON state, so that the potentials Sb and Rb of the latch nodes n11 and n12 are at the VDD level. Precharged. At this time, since the P-channel transistor P15 is also in the on state, the potential SA of the source side node n13 of the sense latch section 11 is also precharged to the VDD level.

  Here, when the data signal D is at “H” level, the N-channel transistor N13 of the differential input unit 12 is in the on state, the N-channel transistor N14 is in the cut-off state, and the N-channel transistor N18 is on. The output node Fa becomes conductive with the VSS line. On the other hand, when the data signal D is at the “L” level, the N-channel transistor N13 is in the cut-off state and the N-channel transistor N14 is in the on-state, so that the output node Fb becomes conductive with the VSS line.

  Next, when the clock signal CK becomes “H” level (latch period in FIG. 2), the precharge transistors P13 and P14 are cut off and the N channel transistors N15 and N16 are turned on.

  At this time, the N-channel transistor N18 is in the ON state for the delay time of the inverter INV12 within the “H” level period of the clock signal CK, so that the differential input unit 12 is in the enabled state (sense latch driving in FIG. 2). Therefore, if the data signal D is at the “H” level (the period t1 in FIG. 2), the potential Sb of the latch node n11 is steeply changed by the path of the transistor N15 → the transistor N13 → the transistor N18. It will change to L "level.

  On the other hand, if the data signal D is at the “L” level (portion t2 in FIG. 2), the potential Rb of the latch node n12 sharply goes to the “L” level through the path of the transistor N16 → the transistor N14 → the transistor N18. Will change.

  In response to the rising edge of the clock signal CK, the P-channel transistor P15 is turned off and the N-channel transistor N17 is turned on. Therefore, the potential SA of the node n13 is pulled to the VSS level, and the potentials Sb, The difference of Rb is sense latched.

  At this time, as described above, the action of the N channel transistors N15 and N16 causes the potential Sb of the latch node n11 or the potential Rb of the latch node n12 to change abruptly according to the polarity of the data signal D. This is faster than the technology, and at the same time, data transmission to the SR latch circuit of the next stage (see FIG. 6) is also faster.

  As described above, in the sense amplifier type flip-flop circuit, when the differential sense amplifier circuit is configured, the switch means is provided between the output nodes Fa and Fb of the differential input unit 12 and the latch nodes n11 and n12 of the sense latch unit 11. (In this example, N-channel transistors N15 and N16) are connected, and the action of the switch means causes the latch nodes n11 and n12 to be connected to the differential input section 12 during a period (precharge period) when the clock signal CK is at “L” level. As a result, the potential Sb / Rb of the latch nodes n11 / n12 changes sharply according to the polarity of the data signal D.

  As a result, the sense latch operation is performed at a higher speed, and the data is transmitted to the next stage SR latch circuit at a higher speed, so that the setup time and the data output time can be shortened. In this increase in speed, there is no increase in the size of the transistors constituting the sense latch unit 11 and an increase in the gate load of the latch nodes n11 and n12, so that a stable sensing operation is ensured.

  Further, the enable period (sense) of the differential input section 12 in the “H” level period of the clock signal CK according to the delay time of the inverter INV12 as control means connected between the clock terminal 16 and the gate of the N-channel transistor N18. By controlling the latch driving period), the N-channel transistor N18 is cut off after the sense latch driving period, and the signal change of the data signal D input from the outside is not transmitted to the latch nodes n11 and n12. It is possible to secure a data hold time while maintaining the above.

  That is, the latch operation can be performed at a higher speed without increasing the gate loads of the latch nodes n11 and n12 of the sense latch unit 11, and the data can be transmitted to the SR latch circuit at the next stage at a higher speed. Thus, the setup time and data output time can be shortened without impairing the data hold time characteristics.

  In addition, the sense latch unit 11 and the source side (VSS side) of the differential input unit 12 are separated by the N channel transistors N15 and N16, and the potential of the node n13 by the P channel transistor P15 connected to the source side node n13. By precharging SA to the VDD level, the precharge operation for the next cycle can be performed at a higher speed than the prior art, so that the precharge time is insufficient when the operating frequency is increased. Can be eliminated, and high frequency operation can be supported.

[Second Embodiment]
FIG. 3 is a circuit diagram showing a configuration example of a differential sense amplifier circuit according to the second embodiment of the present invention. In FIG. 3, the same parts as those in FIG.

  The control of the sense latch driving period described above, that is, the control of the N-channel transistor N18 is performed by the delay time of the inverter INV12 in the differential sense amplifier circuit 10 according to the first embodiment. In the differential sense amplifier circuit 20, the detection is performed based on the potential SA of the source side node n 13 of the sense latch unit 11. Other configurations are the same as those of the differential sense amplifier circuit 10 according to the first embodiment.

  If the sense latch driving period is longer than necessary, the data hold time margin decreases. Conversely, if the sense latch driving period is too short, the setup time and the data output time cannot be sufficiently shortened.

  Therefore, if the control of the sense latch driving period is performed based on the potential SA of the source side node n13 of the sense latch unit 11, the N-channel transistor N17 is turned on in response to the rising edge of the clock signal CK, and the sense latch unit 11 The N-channel transistor N18 can be cut off at the timing when the sense latch operation is completed when the potential SA of the source side node n13 becomes “L” level.

  Thus, in the control of the source side of the differential input unit 12, the gate level of the N-channel transistor N18 that controls the differential input unit 12 enable period (sense latch driving period) is controlled by the source side node of the sense latch unit 11. By performing based on the potential SA of n13, the sense latch driving period can be optimized, so that the balance between setup and hold time can be kept optimal.

[Third Embodiment]
FIG. 4 is a circuit diagram showing a configuration example of a differential sense amplifier circuit according to the third embodiment of the present invention. In FIG. 4, the same parts as those in FIG.

  The differential sense amplifier circuit 30 according to the present embodiment is connected between the latch nodes n11 and n12 of the sense latch unit 11 and the VDD line in addition to the components of the differential sense amplifier circuit 10 according to the first embodiment. The N-channel transistors N19 and N20 are used as first and second transistors.

  The reset signal R of the next stage SR latch circuit (see FIG. 6) is applied to the gate of the N-channel transistor N19 via the reset terminal 17. The reset signal R is a second signal based on the potential Rb of the latch node n12 output from the reset terminal 14 to the SR latch circuit at the next stage. The set signal S of the SR latch circuit at the next stage is applied to the gate of the N-channel transistor N20 via the set terminal 18. The set signal S is a first signal based on the potential Sb of the latch node n11 output from the set terminal 13 to the SR latch circuit at the next stage.

  Here, after the potentials Sb and Rb of the latch nodes n11 and n12 are determined by the sense latch unit 11 (after the sense latch driving period ends) and the clock signal CK is at the “H” level, the polarity of the data signal D Is changed, for example, the data signal D of “H” level is input to the data terminal 15, the potential Sb of the latch node n11 is determined to be “L” level, and the potential Rb of the latch node n12 is determined to be “H” level. Consider the case where the signal D changes to the “L” level.

  In this case, the N-channel transistor N13 is cut off, the N-channel transistor N14 is turned on, and the N-channel transistor N16 is also in the on-state because the clock signal CK is at “H” level. Therefore, although it is a floating node, the VSS level of the node n14 can be seen as the potential Rb of the latch node n12 via the N-channel transistors N16 and N14, and a level drop occurs instantaneously.

  Therefore, it is conceivable that the latch data will be destroyed when the hold time is driven. In other words, the hold time of the flip-flop circuit is determined by the drop in the level of the node n14.

  Therefore, N-channel transistors N19 and N20 are connected between the latch nodes n11 and n12 and the VDD line, and the gate level of these transistors N19 and N20 is controlled by the reset signal R of the SR latch circuit in the next stage (see FIG. 6). The determination is made based on the set signal S.

  Thus, in the case described above, if the Sb of the latch node n11 is fixed at the “L” level and the potential Rb of the latch node n12 is fixed at the “H” level, the set signal S is set at the “H” level. Since the reset signal R is at the “L” level, the N-channel transistor N20 is turned on, and the drop in the potential Rb of the latch node n12 can be suppressed.

  That is, after the potentials Sb and Rb of the latch nodes n11 and n12 are determined (after the sense latch driving period ends), even when the polarity of the data signal D changes, fluctuations in the potentials Sb and Rb of the latch nodes n11 and n12 are suppressed. Therefore, it is possible to increase the hold time margin.

  In each of the above embodiments, the case where the first power supply level is the VDD level (positive power supply level) and the second power supply level is the VSS level (negative power supply level) has been described as an example. A configuration in which the conductivity types of the transistors constituting the amplifier circuits 10, 20, and 30 are reversed from those in the circuit examples of FIGS. 1, 3, and 4, the first power supply level is set to the VSS level, and the second power supply level is set to the VDD level. It is also possible to adopt.

[Application example]
The flip-flop circuits 10, 20, and 30 according to the first to third embodiments are, for example, a master in a flat type display device represented by a liquid crystal display device, an organic EL (electroluminescence) device, and the like. The present invention can be used in a data processing circuit that samples digital data in synchronization with the clock MCK.

  FIG. 5 is a system configuration diagram showing an outline of the configuration of the liquid crystal display device. The liquid crystal display device 50 according to this application example includes a pixel array unit 52 in which pixels 51 including liquid crystal cells are two-dimensionally arranged in a matrix, and a vertical (V) as a peripheral drive circuit of the pixel array unit 52. A driver 53, horizontal (H) drivers 54A and 54B, a VCOM generation circuit 55, a data processing circuit 56, a timing generator 57, and the like are included.

  The liquid crystal display device 50 includes signals from an external DSP (Digital Signal Processor) circuit 60 that serve as a reference for operation of the liquid crystal display device 50, specifically, a master clock MCK, a vertical synchronization signal Vsync, and a horizontal synchronization signal Hsync. And digital data are input.

  The vertical driver 53 selectively scans each pixel 51 of the pixel array unit 52 in units of rows. The horizontal drivers 54A and 54B are arranged on both the upper and lower sides with the pixel array unit 52 interposed therebetween, and the digital data supplied from the data processing circuit 56 is converted into analog signals for each pixel 51 in the row selectively scanned by the vertical driver 53. Convert to and write. The VCOM generation circuit 55 generates a common voltage VCOM that is commonly applied to all the pixels with respect to the counter electrode of the pixel 51 of the pixel array unit 52.

  The data processing circuit 56 performs processing for sampling digital data input from the DSP circuit 60 in synchronization with the master clock MCK input from the DSP circuit 60 outside the apparatus. As the data processing circuit 56, the flip-flop circuits 10, 20, and 30 according to the first to third embodiments described above are used. The timing generator 57 is based on the master clock MCK, the vertical synchronization signal Vsync, and the horizontal synchronization signal Hsync input from the DSP circuit 60, and various timing signals necessary for driving the vertical driver 53 and the horizontal drivers 54A and 54B, for example, A vertical start pulse signal, a vertical clock signal, a horizontal start signal, a horizontal clock signal, and the like are generated.

  As described above, in the flat display device such as the liquid crystal display device 50, the flip-flop circuit 10 according to the first to third embodiments described above is used as the data processing circuit circuit 56 that samples digital data in synchronization with the master clock MCK. , 20, and 30 have the effect of shortening the setup time and the data output time, so that the flip-flop circuits 10, 20, and 30 can greatly contribute to speeding up the display operation.

1 is a circuit diagram illustrating a configuration example of a differential sense amplifier circuit according to a first embodiment of the present invention. 3 is a timing chart for explaining the circuit operation of the differential sense amplifier circuit according to the first embodiment. It is a circuit diagram which shows the structural example of the differential sense amplifier circuit which concerns on 2nd Embodiment of this invention. It is a circuit diagram which shows the structural example of the differential sense amplifier circuit which concerns on 3rd Embodiment of this invention. It is a system block diagram which shows the outline of a structure of the liquid crystal display device which concerns on the application example of this invention. It is a block diagram which shows the basic composition of a sense amplifier type flip-flop circuit. It is a circuit diagram which shows the circuit structure based on the prior art example of a differential sense amplifier circuit. It is a circuit diagram which shows an example of a circuit structure of RS latch circuit. It is a timing chart with which it uses for description of the circuit operation | movement of the sense amplifier type flip-flop circuit which concerns on a prior art example.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10, 20, 30, 100 ... Differential sense amplifier circuit, 11 ... Sense amplifier part, 12 ... Differential input part, 50 ... Liquid crystal display device, 51 ... Pixel, 52 ... Pixel array part, 53 ... Vertical (V) driver 54A, 54B ... Horizontal (H) driver, 55 ... VCOM generation circuit, 56 ... Data processing circuit, 57 ... Timing generator, 200 ... RS latch circuit

Claims (6)

A latch unit that performs a latch operation in synchronization with a clock signal;
A differential input unit that performs a differential operation according to the polarity of the data signal synchronized with the clock signal;
Switch means for disconnecting between two input / output nodes of the latch unit and two output nodes of the differential input unit during a period when the clock signal is at a low level;
And a control means for controlling an enable period during which the differential input section is in an operating state during a high level period of the clock signal. The flip-flop circuit according to claim 1, further comprising precharge means for precharging the source side node of the latch unit to a power supply level during a period when the clock signal is at a low level. The control unit includes an inverter connected between a clock terminal to which the clock signal is input and a gate of a current source transistor of the differential input unit, and controls the enable period according to a delay time of the inverter. The flip-flop circuit according to claim 1. 2. The flip-flop according to claim 1, wherein the control unit controls the enable period by controlling a gate level of a current source transistor of the differential input unit with a potential of a source side node of the latch unit. circuit. A first transistor connected between one input / output node of the latch portion and a power supply line; and a second transistor connected between the other input / output node of the latch portion and a power supply line. Have
The gate level of the second transistor is controlled by a first signal based on the potential of the one input / output node, and the gate level of the first transistor is controlled by a second signal based on the potential of the other input / output node. The flip-flop circuit according to claim 1, wherein the flip-flop circuit is controlled. A display device having a data processing circuit that samples digital data in synchronization with a master clock,
As the data processing circuit,
A latch unit that performs a latch operation in synchronization with a clock signal;
A differential input unit that performs a differential operation according to the polarity of the data signal synchronized with the clock signal;
Switch means for disconnecting between two input / output nodes of the latch unit and two output nodes of the differential input unit during a period when the clock signal is at a low level;
A display device comprising: a flip-flop circuit including control means for controlling an enable period during which the differential input unit is in an operating state during a high level period of the clock signal.

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