JP2008130846A - Semiconductor wafer, and production method of semiconductor wafer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor wafer in which the diffusion of a metal component of a metal plating film formed on a barrier metal film from the metal plating film into an interlayer insulating film is prevented. <P>SOLUTION: In this semiconductor wafer, with respect to the film formation region of an interlayer insulating film 6, a barrier metal film 9, a Cu seed film 10, and a Cu plating film 11, when the barrier metal film 9, a Cu seed film 10, and a Cu plating film 11 are film-formed, the position of the terminal of the more upper layer in the circumferential region of the wafer is positioned at the more inner side of the wafer stepwise than the terminal position of the interlayer insulating film 6. By this film-formation method, under the Cu seed film 10 and the Cu plating film 11, always the barrier metal film 9 is present. As the result, during a heat treatment process after the formation of the Cu seed film 10 and the Cu plating film 11, it can be prevented that Cu is diffused anomalously from the Cu seed film 10 and the Cu plating film 11 into the interlayer insulating film 6 to change the device properties. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor wafer in which a wiring metal layer is formed on an interlayer insulating film by a so-called damascene method, and a manufacturing method thereof.

  As a method for forming a wiring metal layer on an interlayer insulating film by a damascene method, for example, one described in Patent Document 1 is known. In the manufacturing method described in Patent Document 1, first, the outer peripheral edge of the wafer is masked with a clamp ring, and a TiN barrier film is formed by sputtering. Next, a Cu seed film is formed by sputtering using a clamp ring having a larger inner diameter than the clamp ring used when the TiN barrier film is formed. As a result, the Cu seed film is formed over a wide area so as to cover the TiN barrier film.

This prevents the TiN barrier film from being exposed even when misalignment occurs during the film formation of the TiN barrier film and the Cu seed film. Therefore, Cu plating is formed on the Cu seed film. The film is prevented from being grown directly on the TiN barrier film. In this manner, peeling of the Cu plating film from the TiN barrier film, which can be a foreign matter in the manufacturing stage, caused by poor adhesion between TiN and Cu is prevented.
JP 11-297695 A

  For example, when forming a bonding pad on a device formation region of a semiconductor wafer, in order to prevent the plastic deformation of Al during bonding from propagating to the lower layer, a hard and relatively thick metal film (for example, 5um Cu film) is often formed. Since the Cu film is difficult to process by dry etching, it is generally processed by the damascene method described above.

  Here, a problem when a wiring metal layer is formed on an interlayer insulating film by a conventional damascene method will be described using an SOI wafer as an example. FIG. 5 shows an interlayer insulating film 6 made of a TEOS film and an insulating film 4 made of, for example, TiN on an SOI wafer made of a base layer 1, a buried oxide film 2, and an SOI layer 3 through an insulating film 4 made of a silicon oxide film or the like. It is sectional drawing which shows the cross-sectional shape in the outer peripheral area | region of an SOI wafer when the barrier metal film | membrane 9 and Cu seed film | membrane 10 which become this are formed in order. Although not shown, a Cu plating film is further formed on the Cu seed film 10 by electroplating.

  In FIG. 5, when forming a wiring groove (not shown) in which a Cu film is embedded in the interlayer insulating film 6, in the outer peripheral region of the SOI wafer, for the purpose of preventing the generation of foreign matters due to the resist film, etc. The resist film in the outer peripheral region is etched by the rinsing process. For this reason, when the interlayer insulating film 6 for forming the wiring trench is etched, the interlayer insulating film 6 in the outer peripheral region is also etched at the same time.

  As described above, the outer peripheral terrace portion 8 formed by etching away the interlayer insulating film 6 in the outer peripheral region has the buried oxide film 2 as a base. Since this buried oxide film 2 has undergone several etching processes, its surface is in a rough state. Due to the influence of the surface state of the buried oxide film 2 and the influence of the etching of the interlayer insulating film 6 described above, the surface of the outer peripheral terrace portion 8 is also very rough.

  When the barrier metal film 9, the Cu seed film 10 and the like are formed on the outer peripheral terrace 8, the Cu seed is formed at a place where the barrier metal film 9 is not normally formed due to the rough surface of the base. The film 10 may be formed. In this case, the Cu seed film 10 is in direct contact with the interlayer insulating film 6, and Cu may diffuse into the interlayer insulating film 6 by a heat treatment in a later process, resulting in a change in device characteristics.

  The present invention has been made in view of the above points, and a semiconductor wafer capable of preventing the metal component from diffusing into an interlayer insulating film from a metal plating film formed on the barrier metal film, and It aims at providing the manufacturing method.

In order to achieve the above object, a semiconductor wafer according to claim 1 is formed by sequentially forming an interlayer insulating film, a barrier metal film, and a metal plating film in which wiring grooves including contact holes are formed on the wafer. And
In the outer peripheral region of the wafer, the end of the barrier metal film terminates at a position inside the wafer from the end of the interlayer insulating film, and the end of the metal plating film is more than the end of the barrier metal film. It terminates at a position inside the wafer.

  By adopting the above-described configuration, a barrier metal film always exists as a base for the metal plating film. For this reason, it is possible to prevent the metal component of the metal plating film from abnormally diffusing into the interlayer insulating film and changing the device characteristics during the heat treatment.

  Even when the interlayer insulating film is removed by etching for the side rinse process in the outer peripheral region of the wafer, the barrier metal film and the metal plating film are formed on the outer peripheral terrace portion whose surface has been roughened by the etching or the like. Since no film is formed, the metal component can be prevented from diffusing into the interlayer insulating film from this point.

  As described in claim 2, the metal plating film includes a plating seed film formed on the barrier metal film and an electroplating film formed on the plating seed film. The end of the barrier metal film is preferably terminated at a position inside the wafer, and the end of the electroplated film is preferably terminated at a position inside the wafer from the end of the plating seed film. As described above, when the electroplating film is grown on the plating seed film, if the end of the electroplating film is terminated inside the wafer rather than the end of the plating seed film, the metal plating film is more reliably formed. Further, it can be formed within the range of the barrier metal film.

  As described in claim 3, the metal plating film may be made of Cu. This is because it is used as a base for aluminum bonding in a semiconductor wafer. This Cu has the property of easily diffusing into the interlayer insulating film. For this reason, when a metal plating film consists of Cu, it is preferable to employ | adopt especially the structure of this invention mentioned above and to prevent the spreading | diffusion to the interlayer insulation film of Cu.

  As the interlayer insulating film, as described in claim 4, any of a TEOS film, an SOG film, and a laminated film obtained by laminating them can be used. Further, as described in claim 5, the barrier metal film can be made of any one of TiN, TiW, Ta, and TaN.

  As described in claim 6, an SOI wafer may be used as the wafer. In the case of an SOI wafer, the surface of the outer peripheral region of the SOI wafer tends to be rough due to the influence of the buried oxide film. However, in the present invention, since the barrier metal film and the metal plating film are formed while avoiding the outer peripheral region having such a rough surface, it is possible to prevent the metal plating film from directly contacting the interlayer insulating film.

  The seventh and eighth aspects relate to a manufacturing method for manufacturing the semiconductor wafer according to the first and second aspects. That is, the method of manufacturing a semiconductor wafer according to claim 7 includes a step of forming an interlayer insulating film on the wafer, a step of forming a wiring groove including a contact hole in the interlayer insulating film, and an end portion of which is an interlayer insulating layer. A step of forming a barrier metal film on the interlayer insulating film so as to terminate at a position inside the wafer from the edge of the film, and the edge at a position inside the wafer from the edge of the barrier metal film. A step of forming a metal plating film on the barrier metal film so as to terminate, and the barrier metal film and the metal plating film remain in the wiring groove and the surface of the interlayer insulating film is exposed And a step of polishing the metal plating film.

  In the manufacturing method according to claim 8, the metal plating film forming step includes a step of forming a plating seed film on the barrier metal film, and a step of forming an electroplating film on the plating seed film. In the plating seed film deposition step, the plating seed film is deposited and electroplated so that the end of the plating seed film terminates at a position inside the wafer from the end of the barrier metal film. In the film formation step, the electroplating film is formed so that the end of the electroplating film terminates at a position inside the wafer from the end of the plating seed film.

  Hereinafter, a semiconductor wafer and a manufacturing method thereof according to an embodiment of the present invention will be described. FIGS. 1A to 1C and FIGS. 2A to 2D are views showing a manufacturing process of an SOI wafer as an example of a semiconductor wafer. First, the manufacturing method of the SOI wafer according to the present embodiment will be described with reference to these drawings. In order to facilitate understanding of the state of the SOI wafer, FIGS. 1A to 1C and FIGS. 2A to 2D show an outer peripheral region in the vicinity of the outer edge of the SOI wafer and a semiconductor device. And the internal area.

The cross-sectional view of FIG. 1A shows a state where the first wiring layer 5 is formed and patterned on the SOI wafer. The SOI wafer has a base layer 1, a buried oxide film 2, and an SOI layer 3. In the SOI layer 3, active elements such as transistors (not shown) are formed. Then, in order to provide an electrode that is electrically connected to the active element of the SOI layer 3, a first conductive material such as polycrystalline silicon is used on the insulating film 4 made of a BPSG film or a SiO ₂ film in which a contact hole is formed. One wiring layer 5 is formed. The first wiring layer is patterned into a desired electrode shape, and each electrode is separated and insulated.

  In the step shown in FIG. 1B, an interlayer insulating film 6 made of, for example, a TEOS film is formed on the first wiring layer 5. The surface of the interlayer insulating film 6 is planarized by a polishing method such as a CMP method. During the planarization process, the interlayer insulating film 6 is polished so that the interlayer insulating film 6 on the first wiring layer 5 remains, for example, about 2 μm. As the interlayer insulating film 6, in addition to the TEOS film, a porous film such as an SOG film may be used.

  In the step shown in FIG. 1C, a wiring trench 7 including a contact hole with the first wiring layer 5 is formed in the interlayer insulating film 6 by using a photolithography / dry etching technique. FIG. 1C shows a state where the resist used for forming the wiring trench 7 has already been removed. In the photolithography process, an opening is formed corresponding to a portion where the wiring trench 7 is to be formed, and at the same time, the resist is used for the purpose of preventing the generation of foreign matters due to resist chipping in the outer peripheral portion. A part of the resist in the outer peripheral region is removed by the rinsing process. For this reason, in the dry etching process of the interlayer insulating film 6 using the resist as a mask, the site where the wiring trench 7 is to be formed where the resist is open and the interlayer insulating film 6 in the outer peripheral region are removed by etching, and the outer peripheral region of the SOI wafer is removed. An outer peripheral terrace portion 8 is formed on the outer periphery.

  However, since the outermost peripheral portion of the SOI wafer on which the outer peripheral terrace portion 8 is formed is outside the semiconductor chip formation region, the interlayer insulating film 6 in the outer peripheral terrace portion 8 is not completely removed, and there are minute irregularities. It is said.

  Next, in the step shown in FIG. 2A, a barrier metal film 9 is formed to a thickness of, for example, 20 nm on the interlayer insulating film 6 including the formation site of the wiring trench 7 by a sputtering method or the like. The barrier metal film 9 is for preventing the diffusion of Cu from the Cu seed film 10 or the Cu plating film 11 described later into the interlayer insulating film 6 and is formed of TiN. In addition, TiW, Ta, You may form from TaN.

  When the barrier metal film 9 is formed, as shown in FIG. 2A, the outer peripheral region of the SOI wafer is shielded by using a shield plate 20 formed in a ring shape. Control the deposition area. Specifically, the shielding plate 20 is opened so that the end of the barrier metal film 9 terminates at a position inside the SOI wafer from the end of the interlayer insulating film 6 removed for the side rinse treatment. Set the aperture. For example, the shielding plate 20 provides a gap of about 0.5 mm between the end of the interlayer insulating film 6 and the end of the barrier metal film 9. This prevents the barrier metal film 9 from being formed on the outer peripheral terrace portion 8 whose surface is rough.

  In the step shown in FIG. 2B, a Cu seed film 10 is formed on the barrier metal film 9 to a thickness of, for example, 200 nm by sputtering or the like. The Cu seed film 10 serves as one electrode when the Cu plating film 11 is formed by the electroplating method, and the Cu plating film 11 grows on the Cu seed film 10.

  Also when the Cu seed film 10 is formed, the outer peripheral region of the SOI wafer is shielded by the ring-shaped shielding plate 21 and the film formation region of the Cu seed film 10 is controlled. The shielding plate 21 for defining the deposition region of the Cu seed film 10 has a smaller opening diameter than the shielding plate 20 for defining the deposition region of the barrier metal film 9. Moreover, both the shielding plates 20 and 21 are installed with respect to the SOI wafer so that the centers of the respective openings are at the same position. Therefore, due to the shielding plate 21, the film formation region of the Cu seed film 10 has a smaller diameter than the film formation region of the barrier metal film 9. As a result, the end portion of the Cu seed film 10 terminates at a position inside the SOI wafer with respect to the end portion of the barrier metal film 9. Also in this case, for example, the opening diameter of the shielding plate 21 is set so that an interval of about 0.5 mm is provided between the end of the barrier metal film 9 and the end of the Cu seed film 10.

  Therefore, the barrier metal film 9 always exists as the base of the Cu seed film 10. For this reason, even when the electroplating is performed using the Cu seed film 10 as one electrode and the Cu plating film 11 is grown, the Cu seed film 10 and the Cu plating film 11 do not pass through the barrier metal film 9. A portion that directly contacts the interlayer insulating film 6 does not occur.

  Further, in the present embodiment, in the electroplating process for growing the Cu plating film 11 on the Cu seed film 10, the formation of the Cu plating film 11 is performed so that the Cu plating film 11 is surely grown only on the Cu seed film 10. At this time, as shown in FIG. 2C, a shielding plate 22 that shields the outer peripheral region of the SOI wafer is used. That is, the inner diameter portion of the shielding plate 22 is in contact with the Cu seed film 10 so that the electroplating solution does not reach the outer peripheral region of the SOI wafer. In this state, the electroplating process is performed, and the Cu plating film 11 is formed to a thickness of about 5 μm, for example.

  The shielding plate 22 that shields the outer peripheral region of the SOI wafer has a smaller opening diameter than the shielding plate 21 used when the Cu seed film 10 is formed. For this reason, the deposition area of the Cu plating film 11 becomes a range further reduced in diameter than the deposition area of the Cu seed film 10, and the end of the Cu plating film 11 is more SOI than the end of the Cu seed film 10. It ends at a position inside the wafer. Also in this case, for example, the opening diameter of the shielding plate 22 is set so that an interval of about 0.5 mm is provided between the end of the Cu seed film 10 and the end of the Cu plating film 11.

  By using such a shielding plate 22, it is possible to prevent a situation in which the Cu plating film 11 is mistakenly formed directly on the barrier metal film 9 and the distance from the interlayer insulating film 6 is shortened. .

  Finally, in the step shown in FIG. 2D, the barrier metal film 9, the Cu seed film 10 and the Cu plating film 11 remain in the wiring groove 7 of the interlayer insulating film 6, and the surface of the interlayer insulating film 6 is exposed. Thus, the surface of the SOI wafer is polished by, for example, a CMP method. By this polishing, most of the barrier metal film 9, Cu seed film 10 and Cu plating film 11 on the interlayer insulating film 6 except for the inside of the wiring trench 7 are removed. However, as shown in FIG. 2D, a part of the barrier metal film 9, the Cu seed film 10, and the Cu plating film 11 remain in the outer peripheral region of the SOI wafer. Thus, even if a part of the barrier metal film 9, the Cu seed film 10 and the Cu plating film 11 remain in the outer peripheral region of the SOI wafer, the barrier metal is always under the Cu seed film 10 and the Cu plating film 11. A membrane 9 is present.

  When the wiring structure is formed by the damascene method, by adopting the above-described manufacturing method, as shown in FIG. 3, an interlayer formed simultaneously with a side rinse process when forming a wiring groove in the interlayer insulating film 6 is formed. The end of the insulating film 6 is formed at a position closest to the outer edge of the SOI wafer. The end portion of the barrier metal film 9 is located inside the SOI wafer from the end portion of the interlayer insulating film 6, and the end portion of the Cu seed film 10 is further inside than the end portion of the barrier metal film 9. The end of the uppermost Cu plating film 11 is located further inside than the end of the Cu seed film 10.

  That is, according to the present embodiment, the barrier metal film 9, the Cu seed film 10, and the Cu plating film 11 are formed with respect to the film formation regions of the interlayer insulating film 6, the barrier metal film 9, the Cu seed film 10, and the Cu plating film 11. Each thin film end in the wafer outer peripheral region when the film is formed is arranged so as to be inward of the wafer stepwise from the end position of the interlayer insulating film 6 as the upper layer is formed.

  Therefore, the barrier metal film 9 always exists under the Cu seed film 10 and the Cu plating film 11. As a result, during the heat treatment in the process after the formation of the Cu seed film 10 and the Cu plating film 11, Cu is abnormally diffused from the Cu seed film 10 and the Cu plating film 11 into the interlayer insulating film 6 to change the device characteristics. Can be prevented.

  In the outer peripheral area of the SOI wafer, the barrier metal film 9, the Cu seed film, and the Cu plating film 11 are formed on the outer peripheral terrace portion 8 formed by etching away the interlayer insulating film 6 for the side rinse treatment. Since no film is formed, abnormal diffusion of Cu into the interlayer insulating film 6 can be effectively prevented also from this point.

(Modification)
The preferred embodiments of the present invention have been described above. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention.

  For example, in the above-described embodiment, the end portions of the interlayer insulating film 6 are used such that the end positions of the barrier metal film 9, the Cu seed film 10, and the Cu plating film 11 are higher using the shielding plates 20, 21, and 22. It was arranged so as to be inside the wafer stepwise from the position of the part.

  However, the position of each end of these thin films may be controlled using a photolithography / dry etching technique. FIGS. 4A to 4C show an example in which the end position of the barrier metal film 9 is controlled using a photolithography / dry etching technique.

  First, in the step shown in FIG. 4A, the barrier metal film 9 is formed on the entire surface of the interlayer insulating film 6 without using the shielding plate 20. Then, in the step shown in FIG. 4B, the barrier metal film 9 in the outer peripheral region of the SOI wafer is removed, and the end of the barrier metal film 9 is positioned at a desired position inside the SOI wafer from the end of the interlayer insulating film 6. The side rinse width of the applied resist film 12 is adjusted so as to form a portion. At this time, the inside of the wafer is covered with the resist film 12.

  Using this resist film 12 as a mask, as shown in FIG. 4C, wet etching (for example, a mixed solution of ammonia water, hydrogen peroxide water, and water) is performed to remove the barrier metal film 9 in the wafer outer peripheral region. To do. Thereafter, the resist film 12 is removed.

  4A to 4C, the barrier metal film 9 has been described as an example, but the Cu seed film 10 can be similarly processed.

  In the above-described embodiment, the case where the second wiring layer is formed on the SOI wafer has been described as an example. However, if the process is a combination of an interlayer insulating film, a barrier metal film, a plating seed film, and an electroplating film, The present invention can also be applied to multilayer wiring.

  Furthermore, in the above-described embodiment, the example in which the SOI wafer is used as the semiconductor wafer has been described. However, the present invention can also be applied to a bulk wafer.

  Moreover, although the plating seed film and the electroplating film are formed of Cu, it is needless to say that other metals may be used.

(A)-(c) is sectional drawing which shows the one part manufacturing process of the manufacturing method of the semiconductor wafer by embodiment. (A)-(d) is sectional drawing which shows the remaining manufacturing processes of the manufacturing method of a semiconductor wafer following FIG.1 (a)-(c). It is sectional drawing which shows the state of the semiconductor wafer in the middle of manufacture obtained by the manufacturing method of the semiconductor wafer by this embodiment. (A)-(c) is sectional drawing for demonstrating the manufacturing process of the semiconductor wafer by a modification. It is explanatory drawing for demonstrating the problem at the time of forming a wiring metal layer in an interlayer insulation film by the conventional damascene method.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Base layer 2 Embedded oxide film 3 SOI layer 4 Insulating film 5 1st wiring layer 6 Interlayer insulating film 7 Wiring groove 8 Outer periphery terrace part 9 Barrier metal film 10 Cu seed film 11 Cu plating film

Claims (8)

A semiconductor wafer in which an interlayer insulating film in which a wiring groove including a contact hole is formed, a barrier metal film, and a metal plating film are sequentially formed on the wafer,
In the outer peripheral region of the wafer, the end of the barrier metal film is terminated at a position inside the wafer from the end of the interlayer insulating film, and the end of the metal plating film is the barrier metal film. The semiconductor wafer is terminated at a position inside the wafer with respect to the end of the wafer. The metal plating film is composed of a plating seed film formed on the barrier metal film and an electroplating film formed on the plating seed film,
The end of the plating seed film is terminated at a position inside the wafer from the end of the barrier metal film, and the end of the electroplating film is inside the wafer from the end of the plating seed film. The semiconductor wafer according to claim 1, wherein the semiconductor wafer ends at a position of   The semiconductor wafer according to claim 1, wherein the metal plating film is made of Cu.   4. The semiconductor wafer according to claim 1, wherein the interlayer insulating film is one of a TEOS film, an SOG film, and a laminated film obtained by laminating them.   5. The semiconductor wafer according to claim 1, wherein the barrier metal film is made of any one of TiN, TiW, Ta, and TaN.   The semiconductor wafer according to claim 1, wherein the wafer is an SOI wafer having a buried insulating film therein. Forming an interlayer insulating film on the wafer;
Forming a wiring groove including a contact hole in the interlayer insulating film;
Forming a barrier metal film on the interlayer insulating film such that the end ends at a position inside the wafer from the end of the interlayer insulating film;
Forming a metal plating film on the barrier metal film such that the end portion is terminated at a position inside the wafer from the end portion of the barrier metal film;
Polishing the barrier metal film and the metal plating film so that the barrier metal film and the metal plating film remain in the wiring trench and the surface of the interlayer insulating film is exposed. Wafer manufacturing method. The metal plating film forming step includes a step of forming a plating seed film on the barrier metal film and a step of forming an electroplating film on the plating seed film.
In the plating seed film forming step, the plating seed film is formed such that an end of the plating seed film terminates at a position inside the wafer from an end of the barrier metal film, In the electroplating film forming step, the electroplating film is formed such that an end portion of the electroplating film is terminated at a position inside the wafer from an end portion of the plating seed film. A method for producing a semiconductor wafer according to claim 7.

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