JP2008130711A - Semiconductor device - Google Patents

Abstract

MOS semiconductor for use in memories and logic such as SRAM and flash memory, which eliminates contacts and wirings as much as possible and simplifies the structure to increase the integration of semiconductor devices and improve productivity Providing equipment.
In a MOS type semiconductor device, a semiconductor substrate, a source electrode having a well region in the semiconductor substrate, a gate, a source and a drain are formed. 133 passes through the diffusion region 131 that forms the source 13 and penetrates the well region 12 or the body region 111, and the drain electrode that forms the upper portion of the drain 14 passes through the well region 12 or the body region 111. Not penetrated.
[Selection] Figure 2

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which the structure such as source / drain and the like, contact plugs connected thereto, and wiring are changed to be highly integrated and the productivity is improved.

  2. Description of the Related Art Conventionally, in a semiconductor device having a MOS structure, not only the degree of integration is improved by miniaturization, but also the circuit operation speed is increased and the power consumption is reduced. As one means, there is an SOI semiconductor substrate technology in which a single crystal silicon film is provided on an insulating film, this silicon film is formed with an insulator in a certain area, and an active element such as a MOS-FET is formed in this area. Proposed. According to this SOI semiconductor substrate technology, it is possible to increase the degree of integration and the circuit operation speed by miniaturizing the electric wiring, the gate structure of the MOS semiconductor device, and the active region of the source / drain. As described above, the semiconductor device can be miniaturized by the SOI technology without greatly changing the configuration of the semiconductor device. For example, Patent Document 1 discloses a semiconductor device having a source electrode formed by being embedded in a semiconductor layer formed on an insulating film so as to reach a body region between the source region and the buried insulating film. Yes. According to this semiconductor device, even if the thickness of the semiconductor layer is reduced without increasing the element area, it is possible to easily suppress variation in characteristics due to the substrate floating effect. However, the cited document 1 relates to a semiconductor device having an insulating film on a semiconductor substrate, and the semiconductor substrate having an insulating film has a problem that the manufacturing process of the substrate becomes complicated and the manufacturing cost increases.

  In addition, a miniaturization technique for increasing the degree of integration using a bulk type semiconductor substrate other than an SOI substrate is being developed. In recent miniaturization techniques for bulk semiconductor devices, the height of a gate electrode, the thickness of a gate insulating layer, and the like are also reduced as the size of the entire semiconductor device is reduced. However, the mere miniaturization technique is gradually limited in its application range, and there is a problem that further miniaturization is difficult.

JP 2003-332579 A

  Therefore, the present invention has been made in view of the above-described problems of the prior art, and the problem is that the contact and wiring are omitted as much as possible, and the structure is simplified, thereby achieving high integration of the semiconductor device and improving productivity. An object of the present invention is to provide a semiconductor device with improved resistance.

  In order to solve the above problems, a semiconductor device according to the present invention has a configuration in which a source formed in a semiconductor device is electrically connected to a well region or a body region. That is, the semiconductor device of the present invention has a structure that can collectively control what has been contacted separately to control the potential by utilizing that the source and well or body are at the same potential. Thus, the structure is simplified. In other words, unlike the semiconductor substrate having an insulating film, the device of the present invention employs a bulk type semiconductor substrate to make the source potential equal to that of the well region or the body region, so that the wiring on the source side Is omitted.

  According to the semiconductor device of the present invention, the wiring on the source side or the contact plug can be omitted, so that the structure is simplified, and the entire structure can be miniaturized. can do. Further, according to the semiconductor device of the present invention, since the structure is simple, multilayering at the time of manufacture can be facilitated, and productivity can be improved.

  Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. In the description of the embodiment, for convenience, the description will be made while comparing with the prior art as necessary. In addition, it is easy for a person skilled in the art to make other embodiments by changing or modifying the present invention within the scope of the claims, and these changes and modifications are included in the scope of the claims. The following description is an example of the best mode of the present invention, and does not limit the scope of the claims.

FIG. 1 is a schematic diagram showing a configuration of a general semiconductor device.
In FIG. 1, this semiconductor device has a basic structure of a MOS type structure, and has a configuration common to all semiconductor devices having a MOS type structure. In the semiconductor device 10 having the MOS type structure, an element isolation film 18 is formed on a silicon semiconductor substrate 11 so as to surround a region where an element is to be formed, and a well region is formed in the semiconductor substrate 11 in the region. 12 and body region 111 are formed. The well region 12 is formed when determining the polarity of the semiconductor device 10 regardless of the conductivity type of the semiconductor substrate 11. In particular, it is often used when the source 13 and the drain 14 having the opposite polarity to that of the semiconductor substrate 11 are formed. Depending on the conductivity polarity of the semiconductor substrate 11, the well region 12 may not be provided, and the source 13 and the drain 14 may be formed in the body region 111 as they are. Therefore, in the semiconductor device of the present invention, the source 13 and the source electrode 133 constituting a part of the source 13 are brought into electrical contact with either the well region 12 or the body region 111 to be conducted.
Above the well region 12 or the body region 111 of the semiconductor substrate 11, a gate stacked body including a gate insulating film 151, a gate electrode 152 and a gate silicide film 153 formed corresponding to the channel region 16 (hereinafter simply referred to as “gate”). 15) is provided, and gate sidewall insulating films 154 are provided on both sides of the gate 15 so as to sandwich the gate 15. The semiconductor substrate 11 below the gate 15 is formed with a source 13 including a source diffusion region 131, a source LDD region 132, and a source electrode 133 on one side so as to sandwich the gate 15, and on the other side. A drain 14 including a drain diffusion region 141, a drain LDD region 142, and a drain electrode 143 is formed. A protective oxide film 17 is provided so as to cover the entire element isolation film 18, source electrode 133, source diffusion region 131, gate stack 15, drain LDD region 142, drain diffusion region 141, and drain electrode 143. The protective oxide film 17 is further covered with an interlayer insulating film 19. A contact plug 20 is formed in the interlayer insulating film 19, and the contact plug 20 is connected to a wiring layer 21 on the interlayer insulating film 19. Hereinafter, the protective oxide film 17 is omitted.
Such a MOS semiconductor device 10 is used as a static random access memory (SRAM), a memory such as a flash memory, and other logic devices.

FIG. 2 is a schematic diagram showing the configuration of the semiconductor device according to the present invention. Hereinafter, as shown in FIG. 2, the semiconductor device 10 will be described using an n-channel MOS transistor (abbreviated as “n-MOS”; hereinafter the same). In the semiconductor device of the present invention, a pn junction is formed between the drain electrode 143 and the well region 12 or the body region 111 as in the conventional case, and current does not flow because it is not normally forward biased. On the other hand, unlike the conventional case, between the source electrode 133 and the well region 12 or the body region 111, the current is easily leaked so as to be made equipotential.
2A, the semiconductor device includes a well region 12 and a body region 111 formed in a semiconductor substrate 11, a gate stacked body 15 provided on the well region 12 and the body region 111, a source 13, and the like. The source electrode 133 of the source 13 extends through the source diffusion region 131 to the well region 12, and the source electrode 133 is in contact with the well region 12. At this time, the source electrode 133 may be extended to the body region 111 and brought into contact with the body region 111. On the other hand, since the drain electrode 143 of the drain 14 does not penetrate the drain diffusion region 141 and is not in contact with the well region 12 or the body region 111, current leakage is suppressed by the presence of the pn junction. ing.

Usually, a voltage having the same polarity is applied to the drain 14 and the gate 15, and the source 13 is grounded or the same potential as that of the well region 12 is applied. No current flows between the n-type source diffusion region 131 and the p-type well region 12. However, by increasing the voltage applied to the gate 15, current begins to flow between the source 13 and the drain 14 through the channel. At this time, since the source 13 is grounded, it is on the negative side with respect to the drain 14, and the source 13 has the same polarity as the potential of the p-type well region 12. Accordingly, in the semiconductor device 10, the source electrode 133 extends through the source diffusion region 131 to the inside of the p-type well region 12, and the source electrode 133 is brought into contact with the p-type well region 12, thereby , Electrically connected and conducted. In this way, the source electrode 133 can be made equipotential by being connected to the p-type well region 12. Therefore, the wiring or contact plug on the source side can be omitted, so that the structure is simplified and miniaturization can be achieved as a whole.
Further, in the case of a MOS type transistor in which the well region 12 is not formed, it is preferable that the source electrode 133 extends through the source diffusion region 131 to the body region 111 and is in contact with the body region 111. As a result, the same effects can be obtained.

In the semiconductor device of the present invention, when the source diffusion region 131 is formed, the source diffusion region 131 is thinned by reducing the impurity implantation acceleration energy and / or reducing the dose amount. And the well region 12 can be conducted.
FIG. 2B is a schematic diagram showing another configuration of the semiconductor device of the present invention. In FIG. 2B, the source diffusion region 131 is made thinner than the drain diffusion region 143 without extending the source electrode 133, that is, without penetrating the source electrode 133 into the source diffusion region 131. This is shown by comparing the depths with arrows in the figure. Usually, when forming the n-type source diffusion region 131, As, P, or the like is implanted as an impurity, but the source diffusion region 131 is formed by limiting the implantation depth by reducing the acceleration energy at the time of implantation. Can be thinned. By making the source diffusion region 131 thinner, the distance from the source electrode 133 to the p-well region 12 is shortened to facilitate the flow of leak current, whereby the source electrode 133 and the p-well region 12 can be made conductive. . Similarly, when forming the p-type source 13 in order to form the p-MOS transistor, the p-type source diffusion region 131 can be made thin by reducing the acceleration energy of impurities such as B and BF _2. it can. According to this embodiment, the source diffusion region 131 can be made thin, and the source electrode 133 and the well region 12 can be made conductive to achieve the same effect.

FIG. 3 is a schematic view for explaining another configuration of the semiconductor device of the present invention.
In FIG. 3, this semiconductor device is provided with a dummy gate 15a so as to be adjacent to the contact plug 20 on the source side. By providing the dummy gate 15a close to the contact plug 20 on the source side, leakage is likely to occur between the contact plug 20 and the well region 12, whereby the source electrode connected to the contact plug 20 is obtained. By making 133 and the well region 12 easily conduct, the potential is made equal. This is because a defect such as a point defect is likely to occur between the metal material forming the contact plug 20 and the metal material forming the source electrode 133 forming the upper layer of the source 13, and current leakage occurs. It becomes easy. Due to this leakage, the source electrode 133 and the well region 12 become conductive, whereby the source electrode 133 and the well region 12 can be equipotential.

In the present invention, the existing gate 15 can be arranged close to the contact plug 20 without providing the dummy gate 15a. That is, the existing gate 15 is arranged close to the source 13 side, not between the source 13 and the drain 14. However, in this case, it is necessary to place the gate 15 and the source 14 side contact plug 20 at a distance that does not cause a short circuit. With such a configuration, current leakage is likely to occur between the source 13 and the well region 12. Then, the source electrode 133 and the well region 12 are easily conducted, and can be made equipotential. Accordingly, even with such a configuration, since the wiring layer to the source 13 can be omitted, the structure is simplified, and positioning with high accuracy between the source 13 and the contact plug 20 is not necessary, and productivity can be improved. Furthermore, the area for forming the source 13 can be reduced, and the semiconductor device 10 can be highly integrated.
Further, in such a wiring structure in the semiconductor device 10, it is necessary to form a contact for connecting the source 13 and an external power source, regardless of the function / configuration of the semiconductor device 10. And can be omitted without providing the contact plug 20 or the metal wiring layer 21. As a result, the occupation area of the semiconductor device 10 as a whole can be reduced, and the manufacturing can be facilitated and the productivity can be increased.

FIG. 4 is a schematic diagram showing a configuration of an SRAM (hereinafter, simply referred to as “semiconductor device”) to which the semiconductor device is applied.
In the SRAM 30, a p-MOS transistor P1 and an n-MOS transistor N1 form a first inverter 31, and a p-MOS transistor P2 and an n-MOS transistor N2 form a second inverter 32.
The input of the first inverter 31 and the output of the second inverter 32 are connected to a data line BL (not shown) via an n-MOS transistor N3 functioning for transfer, and the output of the first inverter 31 The input of the second inverter 32 is connected to a data line BL (not shown) via an n-MOS transistor N4 that functions as a transfer. The gates of the n-MOS transistors N3 and N4 functioning for transfer are connected to word lines W1 and W2 (not shown).

The MOS transistors have their respective functions, and the two n-MOS transistors N1 and N2 serve as driver transistors (hereinafter referred to as “driver Tr”), and the remaining two n-MOS transistors N3 and N4. Functions as a transfer transistor (hereinafter referred to as “transfer Tr”). The two p-MOS transistors P1 and P2 function as load transistors (hereinafter referred to as “load Tr”).
The driver TrN1 and the transfer TrN3 are formed in the same p-well region 12 as the first inverter 31. The next n-well region 12 a is provided via the element isolation film 18 so as to be adjacent to the p-well region 12. In the n-well region 12a, p-MOS transistors P1 and P2 functioning as loads Tr in the first inverter 31 and the second inverter 32, respectively, are provided. A p-well region 12b is provided via an element isolation film 18 so as to be adjacent to the n-well region 12a. A driver TrN2 and a transfer TrN4 that form the second inverter 32 are arranged in the p-well region 12b.

  FIG. 5 is a schematic diagram showing a configuration in which the semiconductor device of the present invention is applied to an SRAM. In FIG. 5A, a dummy gate 15a is provided adjacent to the source 13 of the n-MOS transistor N1 that functions as the driver Tr of the first inverter 31. The dummy gate 15a is arranged not close to the source 13 and the drain 14 but close to the source 13 side. With such a configuration, current leakage is likely to occur between the source 13 and the well region 12. Then, the source electrode 133 and the well region 12 are easily conducted, and can be made equipotential. Therefore, according to the present embodiment, since the source electrode 131 and the well region 12 are made conductive, no wiring for conduction is required. In addition, highly accurate positioning is unnecessary, and productivity is significantly improved. In FIG. 5A, a contact plug 20 is provided adjacent to the dummy gate 15a. The contact plug 20 need not be used to connect the wiring layer 21 to the source electrode 131 and may be omitted.

  In the semiconductor device of the present invention, as shown in FIG. 5B, the gate electrode 15 extending from the load TrP1 to the driver TrN1 can be brought closer to the source 13 side, as shown by the white arrow. That is, in the semiconductor device 10 of FIG. 5B, the existing gate 15 is moved to a position adjacent to the source 13 instead of providing the dummy gate 15a. By bringing the existing gate 15 close to the source 13, current leakage is likely to occur between the source 13 and the well region 12, and the source 13 and the well region 12 can be equipotential. Compared with the semiconductor device 10 of FIG. 5A, productivity can be improved by not providing a dummy gate. In this semiconductor device 10, it is not necessary to use the contact plug 20 for connection with the wiring layer 21 to the source electrode 131, and therefore, it may be omitted.

FIG. 6 is an explanatory diagram showing a NOR type flash memory as a conventional semiconductor device. 6A is a diagram showing the layout, and FIG. 6B is a cross-sectional view in the direction of arrows AA in FIG. 6A. The flash memory is a recording device using MOS transistors, and has an advantage that the recorded information can be erased collectively.
In FIG. 6A, a plurality of, for example, four MOS transistors 10 are arranged in parallel in the flash memory 40. Therefore, the active regions 41 of the MOS transistors 10 are arranged in parallel to each other, and the gates 15 are formed so as to cross the active regions 41, respectively. At this time, when the source 13 and the drain 14 are formed, a deep SD region 42 deeper than a normal source / drain region and an SD extension region 43 which is a high-concentration shallow junction are formed. Note that a gate wiring connected to the gate 15 is omitted.

In FIG. 6B, a contact plug 20 connected to the source electrode 133 of the source 13 is disposed on one side surface of the interlayer insulating film 19 of the transistor 10. The contact plug 20 is connected to the source wiring 211 above the contact plug 20. It is connected to the. A contact plug 20 connected to the drain electrode 143 of the drain 14 is disposed on the other side surface of the interlayer insulating film 19, and the contact plug 20 is connected to the drain wiring 212 thereabove. In the figure, the metal wiring layer connected to the gate 15 is omitted.
The gate 15 has a floating gate 156 above the gate insulating film 151, and an interlayer insulating layer 158 and a control gate 157 are formed on the floating gate 156. A MOS transistor in which the floating gate 156 and the control gate 157 are stacked in this way is referred to as a stacked gate structure MOS transistor.

In such a flash memory, when information is written, the voltage applied to the drain 14 is substantially equal to the power supply voltage Vdd, the gate voltage applied to the control gate 157 is set to a positive high voltage, and the source voltage applied to the source 13 is Data is written by injecting electrons from the drain 14 to the floating gate 156 with the ground voltage Vss. Here, as the voltage applied to the drain 14, if the power supply voltage Vdd for writing exists, it can be used. The high voltage applied to the gate 15 may be a write voltage, or a voltage generated by boosting the power supply voltage Vdd.
Further, a well tap region 121 (see FIG. 6A) for applying a fixed potential to the well region 12 is provided. The well tap region 121 is normally connected to the wiring layer 214 via the contact plug 20 formed in the interlayer insulating film 19. The wiring layer 21 connected to the well tap region 121 and the wiring layer 21 connected to the source electrode 133 of the MOS transistor are arranged in the row direction in FIG. As the metal wiring layer 21 (211 and 212), Cu or Al is preferably used.

FIG. 7 is an explanatory diagram showing a layout of the semiconductor device of the present invention and a partial cross section thereof. FIG. 7A is a diagram showing the layout, and FIG. 7B is a partial sectional view thereof. 7A, the semiconductor device of this embodiment differs from the semiconductor device of FIG. 6 in that the source electrode 133 extends through the source diffusion region 131 to the well region 12, and the well region 12 It is a point in contact with. The drain electrode 143 does not extend to the well region 12 or the body region 111.
The contact plug 20 or the wiring layer 21 connected to the contact plug 20 is not connected to the source electrode 133, and the conduction between the source power supply 133 and the well region 12 is made directly through the source diffusion region 131 through the source electrode 133. Do this by connecting. As a result, the structure of the semiconductor device is simplified and the overall size can be reduced.

Here, it is preferable to reduce the depth of impurity implantation in the source diffusion region 131, whereby the source electrode 133 and the well region 12 are more likely to be equipotential. In the present embodiment, the contact plug 20 on the source 13 side may be provided, and the metal wiring layer 21 connected to the source 13 side contact plug 20 may be omitted. By leaving the contact plug 20 on the source 13 side, the conventional configuration can be improved without greatly changing, and there is no need to change the manufacturing process. Further, by leaving the source 13 side contact plug 20, current leakage is likely to occur between the gate electrode 133 and the well region 12.
Further, the same effect can be obtained even if the source electrode 133 is made thinner than the normal thickness, that is, the depth of the source diffusion region 131 instead of extending through the source diffusion region 131 to the well region 12. . Further, when the source diffusion region 131 is formed, the same effect can be obtained by reducing the electric resistance of the source diffusion region 131 by implanting the same type of impurity as the well region 12 or the body region 111.

FIG. 8 is a schematic diagram showing a layout of a conventional semiconductor device and a partial cross-sectional view thereof. 8A is a diagram showing the layout, and FIG. 8B is a cross-sectional view in the direction of arrows BB in FIG. 8A.
In this semiconductor device, a well tap region 121 into which an impurity of the same type as that of the well region 12 or the body region 111 is implanted is formed in or adjacent to the source diffusion region 131 of the source 13. Conventionally, in order to stably maintain the potential of the well region 12, a ground wiring 214 has been provided to apply a voltage to the entire well region 12, as shown in FIG. 8B. The ground wiring 214 is connected to the well tap region 121. The source 13 and the well region 12 are equipotential, and the ground wiring 214 is connected to the well tap 121 in which the electrical resistance is reduced by implanting impurities, so that the batting contact in which the wiring as the application means is only the ground wiring 214. In the semiconductor device of the system, the web region 12 and the source electrode 133 are efficiently conducted to be equipotential. In such a semiconductor device, an n-type source 13 and an n-type drain 14 are formed by photolithography and ion implantation, thermally oxidized in a wet atmosphere of, for example, 850 ° C. or lower, and then ion-implanted with p-type impurities over the entire surface. Region 16 is formed. Therefore, the positional relationship between the n-type source 13 and the channel region 16 is self-aligned. Since the n-type impurity implantation, the P-type impurity implantation, and the contact photolithography are actively matched, the size of the batting contact needs to be larger than the normal contact size in consideration of all these misalignments.

In the present invention, the source electrode 133 may extend so as to penetrate the source diffusion region 131 and come into contact with the well region 12.
FIG. 9 is a schematic diagram showing a layout of the semiconductor device of the present invention and a partial cross-sectional view thereof. 9A is a diagram showing a layout, and FIG. 9B is a cross-sectional view in the direction of arrows CC in FIG. 9A. In FIG. 9, the source electrode 133 extends through the source diffusion region 131 and is in contact with the well region 12 provided with the low resistance region 122.
Even with such a configuration, conduction between the source electrode 133 and the low-resistance region 122 is improved. For the low resistance region 122, an impurity of the same type as the impurity implanted into the well region 12 is used. Accordingly, there is no need to change the manufacturing process, and it is possible to easily adjust the electrical resistance to be low by the dose amount and the acceleration energy. Therefore, according to the present embodiment, the ground wiring 214 can be omitted and the structure can be further simplified. In addition, the entire semiconductor device 10 can be miniaturized to reduce the occupied area per unit.

In the present invention, a metal insertion region 123 in which a metal is embedded by making a hole in a part of the source diffusion region 131 or adjacent to the source diffusion region 131 can also be provided.
FIG. 10 is a schematic diagram showing a layout of the semiconductor device of the present invention and a partial cross-sectional view thereof.
In FIG. 10, the semiconductor device 10 has a metal insertion region 123 in which TiSi ₂ is inserted as a representative material of metal, for example, silicide, in a part of the well tap region 121. Ti, Ni, Co, etc. can be mentioned as a metal alloyed with Si as a silicide. In particular, the specific resistance of TiSi ₂ is about 15 μΩ · cm, which is an order of magnitude lower than that of polysilicon, which is about 500 μΩ · cm. For this reason, by providing the metal insertion region 123 in which metal is embedded in the source diffusion region 133 or in the well tap region 121 provided so as to be adjacent to the source diffusion region 133, an electric current is generated between the source electrode 133 and the well region 12. Lowering the resistance makes the current leak more smoothly. As a result, the electrical resistance between the source electrode 133 and the well region 12 can be further reduced to be equipotential.

In such a wiring structure in a semiconductor device, it is not necessary to form a contact for connecting a source and an external power source, and a contact plug and a metal wiring layer can be omitted. As a result, the occupation area of the semiconductor device as a whole can be reduced, and high integration can be achieved.
Although the present invention has been described in detail above, the illustrated flash memory is not particularly limited, and may be a memory element such as SRAM or DRAM, or a NOR type or the like as long as it uses a MOS transistor. It may be a NAND type logic element. That is, the present invention also includes a semiconductor device in which a logic element and SRAM are integrated on a semiconductor substrate, and a non-volatile memory element such as a flash memory is integrated on the substrate in addition to the logic element and SRAM. Therefore, the structure can be simplified as compared with the prior art, and the occupation area per semiconductor device can be reduced and miniaturization can be achieved. Moreover, multilayering at the time of manufacture becomes easy, and productivity improves.

It is the schematic which shows the structure of a general semiconductor device. It is the schematic which shows the structure of the semiconductor device in this invention. It is the schematic shown in order to demonstrate the other structure of the semiconductor device of this invention. 1 is a schematic diagram illustrating a configuration in which a semiconductor device is applied to an SRAM. It is the schematic which shows the structure of SRAM which applied the semiconductor device. It is explanatory drawing which shows the layout and partial cross section of the conventional semiconductor device. It is explanatory drawing which shows the layout of the semiconductor device of this invention, and its partial cross section. It is the schematic which shows the layout of the conventional semiconductor device, and its fragmentary sectional view. It is the schematic which shows the layout of the semiconductor device of this invention, and its fragmentary sectional view. It is the schematic which shows the layout of the semiconductor device of this invention, and its fragmentary sectional view.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Semiconductor device 11 Semiconductor substrate 111 Body region 112 Batting contact 113 Semiconductor element region 12 Well region 121 Well tap region 122 Low resistance region 123 Metal insertion region 13 Source 131 Source diffusion region 132 Source LDD (Lightly Doped)
Drain) region 133 Source electrode 14 Drain 141 Drain diffusion region 142 Drain LDD (Lightly Doped)
Drain) region 143 Drain electrode 15 Gate or gate stack 151 Gate insulating film 152 Gate electrode 153 Gate silicide film 154 Gate sidewall insulating film 156 Floating gate 157 Control gate 158 Interlayer insulating layer 159 Side wall insulating layer 15a Dummy gate
16 Channel region 17 Protective oxide film 18 Device isolation film (STI)
19 Interlayer insulating film 20 Contact plug 21 Wiring layer 211 Source wiring 212 Drain wiring 213 Gate wiring 214 Ground wiring 30 Static random access memory (SRAM)
31 First inverter 32 Second inverter 40 Flash memory 41 Active region 42 Deep SD region 43 Extension SD region Vdd Power supply potential Vss Ground potential

Claims (5)

A semiconductor substrate;
A gate, a source and a drain formed in the semiconductor substrate;
A well region or a body region in which the source and the drain are formed;
In a semiconductor device having a well tap region formed in the well region or the body region,
The semiconductor device, wherein the source and the well region or the body region are electrically connected. The semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein the source has a conductive region that penetrates the source and is electrically connected to the well region or the body region. The semiconductor device according to claim 2,
Conducting the source and the well region or the body region,
Making the thickness of the source diffusion region thinner than the thickness of the drain region,
Impurities of the same type as the well region are implanted into the source diffusion region,
Alternatively, the semiconductor device is characterized by either burying metal in the source region. The semiconductor device according to any one of claims 1 to 3,
The electrode constituting the source is formed of silicide. A semiconductor device, wherein: A semiconductor substrate;
A gate, a source and a drain formed in the semiconductor substrate;
A well region or a body region in which the source and the drain are formed;
The source and the well region or body region are electrically connected,
A contact plug is not formed in the source. A semiconductor device, wherein: