JP2008130665A - Semiconductor light emitting device, method for manufacturing the same, and light emitting device - Google Patents

Abstract

A semiconductor light-emitting element that can efficiently dissipate heat, relax thermal stress, and obtain high reliability, a method of manufacturing the same, and a light-emitting device are provided.
A stress relaxation layer 81 capable of plastic deformation is provided on both sides of a ridge 61. Thermal stress generated at the time of joining the semiconductor laser array 20 and the base is absorbed and relaxed by the stress relaxation layer 81 to improve reliability and efficiently dissipate heat. The stress relaxation layer 81 is formed by electron beam evaporation of an insulating material such as SiO ₂ , AlO _2, or Si ₃ N ₄ . The stress relaxation layer is made of a plastically deformable metal material such as indium (In) or an In—Ag alloy, and the upper and lower sides thereof are metals that do not form an alloy with indium (In), for example, aluminum (Al). You may pinch | interpose with the alloying prevention layer which consists of. The interval D1 between the stress relaxation layers 81 is wider than the width W of the ridge portion 61, and is preferably three times or more the width W.
[Selection] Figure 3

Description

  The present invention relates to a semiconductor light-emitting element suitable for so-called direct mounting, which is directly bonded to a support (base) without using a submount, a manufacturing method thereof, and a light-emitting device.

As a high-power semiconductor laser device, a semiconductor laser array in which a plurality of elements are arranged in a line so that the emission directions of laser beams are aligned is used. As shown in FIG. 9, the semiconductor laser array 220 may be joined to the base (heat sink) 210 by the solder layers 231 and 232 with the submount 240 therebetween, as shown in FIG. As described above, the solder layer 231 may be mounted directly on the base 210 (direct mounting).
“Mounting of HIgh Power Laser Diodes on Diamond Heatsinks”, “IEEE TRANSACTIONS ON COMPONENTS, PACKAGING, AND MANFACTURERING TECHNOLOGY-PART A”, 1996, Vol. 19, p. 46 Japanese Patent No. 2863678 JP 2003-258381 A (paragraph 0038)

  The direct mount can effectively dissipate the heat generated by the semiconductor laser array 220, while a large thermal stress is generated at the time of bonding due to a difference in linear expansion coefficient between the semiconductor laser array 220 and the base 210. There is a risk of cracks. In addition, the thermal stress generated at the time of joining gives stress to the active layer, causing a change in emission wavelength and a change in threshold current value. For example, in the case of a red semiconductor laser array, as shown in FIG. 11, the oscillation wavelength is shortened by 8 nm and the oscillation threshold current value is increased more than twice. In FIG. 11, the semiconductor laser array was directly mounted on a base made of copper (Cu) and laser oscillation when bonded to a base made of copper (Cu) with a submount made of silicon carbide (SiC) in between. The laser oscillation and LED (Light Emitting Diode) emission in this case are shown in comparison.

  In order to cope with such a problem, conventionally, it has been proposed to provide a thick gold (Au) layer having a thickness of 2 μm between the solder layer and the heat sink (see, for example, Non-Patent Document 1). However, a gold (Au) layer having a thickness of about 2 μm cannot relieve a large stress due to a difference in thermal expansion coefficient. In order to relieve stress, it may be possible to further increase the thickness of the gold (Au) layer, for example, to about 10 μm. It also increased and was not realistic.

In addition, the heat sink has a laminated structure in which insulating layers having high thermal conductivity (diamond) and insulating layers having low thermal conductivity (SiO ₂ ) are alternately stacked, and by adjusting the thickness of each insulating layer, the entire heat sink Has been proposed (see, for example, Patent Document 1) such that the thermal expansion coefficient of the semiconductor laser chip is substantially equal to the thermal expansion coefficient of the main constituent material of the semiconductor laser chip to be mounted. However, in such a heat sink, if the thickness of the heat sink is reduced to about 200 μm, the insulating layers easily peel off on the laminated surface. On the other hand, if it is thick, the thermal conductivity of the insulating layer is poor and the thermal diffusion in the lateral direction. Therefore, there is a problem that it becomes difficult to efficiently dissipate the heat generated by the laser.

  Patent Document 2 describes that a laser chip is directly connected to a package body using an indium (In) solder material as a heat dissipation measure for a laser chip formed on a sapphire substrate having low thermal conductivity. . However, indium-based solder has poor wettability and is difficult to spread uniformly. Since this void is inferior in thermal conductivity, it causes local temperature rise and deterioration, and it is difficult to obtain high reliability. Furthermore, indium easily reacts with the gold (Au) of the electrode of the laser chip and the gold (Au) plating layer on the surface of the base to form an alloy. In this case, since the diffusion rates of indium (In) and gold (Au) are greatly different, so-called Kirkendall voids are generated at the bonding interface, resulting in a decrease in strength and an increase in bonding resistance.

  The present invention has been made in view of such problems, and the object thereof is a semiconductor light-emitting element that can efficiently perform heat dissipation and can obtain high reliability by relaxing thermal stress, and a method for manufacturing the same, Another object is to provide a light emitting device.

  A semiconductor light emitting device according to the present invention includes a semiconductor layer including an active layer, and the upper portion of the semiconductor layer is a protrusion for defining a current injection region into the active layer. A stress relaxation layer capable of plastic deformation is provided on at least a part of the periphery of the protrusion.

  A method of manufacturing a semiconductor light emitting device according to the present invention is a method of manufacturing a semiconductor light emitting device having a semiconductor layer including an active layer, and a protrusion for defining a current injection region into the active layer above the semiconductor layer. And a step of providing a plastically deformable stress relaxation layer on at least a part of the periphery of the upper protrusion of the semiconductor layer.

  A light-emitting device according to the present invention is obtained by bonding a semiconductor light-emitting element including a semiconductor layer including an active layer to a support, and the semiconductor light-emitting element includes the semiconductor light-emitting element of the present invention. The side provided with the protrusion and the stress relaxation layer is bonded to the support.

  In the semiconductor light-emitting element of the present invention or the light-emitting device of the present invention, the thermal stress generated when the semiconductor light-emitting element and the support are joined is plastically deformed in the stress relaxation layer provided on at least a part around the protrusion. Is alleviated. Therefore, the stress applied to the semiconductor light emitting element is reduced, and heat generation is efficiently dissipated to the support.

  According to the semiconductor light emitting device of the present invention or the method for manufacturing the semiconductor light emitting device of the present invention, the stress relaxation layer that can be plastically deformed is provided on at least a part of the periphery of the protruding portion. Thermal stress generated at the time of joining with the body can be relaxed, and high reliability can be obtained. Therefore, it is possible to realize a light emitting device having excellent heat dissipation efficiency and reliability by joining the protruding portion of the semiconductor light emitting element and the side provided with the stress relaxation layer to the support to constitute the light emitting device. it can.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(First embodiment)
FIG. 1 shows an overall configuration of a light emitting device according to a first embodiment of the present invention. This light emitting device is used as a red light source of a laser projector, and has a configuration in which, for example, a semiconductor laser array 20 is joined to a support (base) 10 by a solder layer 30.

  The base 10 also has a function as a heat sink that dissipates heat generated by the semiconductor laser array 20, and is made of, for example, a material having electrical and thermal conductivity such as copper (Cu), and has a gold surface on the surface. A thin film made of (Au) or the like is applied. The thermal conductivity is a characteristic necessary for releasing a large amount of heat generated from the semiconductor laser array 20 and maintaining the semiconductor laser array 20 at an appropriate temperature, and the electrical conductivity is a current flowing to the semiconductor laser array 20. This characteristic is necessary for efficient conduction.

  On the base 10, for example, an electrode member 11 made of the same material as the base 10 is fixed by screws 11A and 11B, for example. An insulating plate 12 made of an insulating resin such as glass or epoxy is provided between the base 10 and the electrode member 11, and the base 10 and the electrode member 11 are electrically insulated. The electrode member 11 is provided with a step portion 11C at one corner on the semiconductor laser array 20 side. The step portion 11C is made of, for example, a gold (Au) wire or a gold (Au) foil having a thickness of 50 μm. One end of the wire 40 is joined. The other end of the wire 40 is joined to the semiconductor laser array 20, and the electrode member 11 and the semiconductor laser array 20 are electrically connected via the wire 40. A protective member 13 made of the same material as the base 10 is fixed to the step 11C of the electrode member 11 with screws 13A in order to protect the wires 40, the semiconductor laser array 20, and the like.

  FIG. 2 shows a schematic configuration of the semiconductor laser array 20 shown in FIG. The semiconductor laser array 20 is, for example, a red laser having an oscillation wavelength in a wavelength range of 630 nm or more and 690 nm or less, and a plurality of light emitting units 21 are arranged in a line. The dimensions are about 10 mm in length, resonator length of 200 μm to 1.5 mm, specifically about 700 μm, and thickness of about 100 μm. Here, the length is a dimension in the arrangement direction of the light emitting units 21, and the resonator length is an emission direction of the light LB from the light emitting unit 21, that is, a dimension in the resonator direction, and the thickness is both the length and the resonator length. It is a dimension in the orthogonal direction.

  FIG. 3 illustrates a cross-sectional configuration of one light emitting unit 21. Each light emitting unit 21 includes, for example, an n-type cladding layer 52, a first light guide layer 53, an active layer 54, a second light guide layer 55, a first p-type cladding layer 56, an etch stop layer 57, and a first layer on a substrate 51. The 2p-type cladding layer 58, the intermediate layer 59, and the p-side contact layer 60 have a double heterostructure (DH) junction laminated structure in which they are laminated in this order.

  The substrate 51 is composed of an n-type GaAs substrate to which an n-type impurity such as silicon (Si) or selenium (Se) is added, for example. In addition, the substrate 51 has a main surface that is off from the {100} plane in a <100> direction by a predetermined angle, for example, about 8 ° to 16 °. The n-type cladding layer 52 has, for example, a thickness in the stacking direction (hereinafter simply referred to as a thickness) of 1 μm, and an n-type AlInP mixed crystal or AlGaInP mixed crystal to which an n-type impurity such as silicon (Si) or selenium (Se) is added. It is composed of crystals. For example, the first light guide layer 53 has a thickness of 120 nm and is made of an AlGaInP mixed crystal. The first light guide layer 53 may not contain impurities, or may contain an n-type impurity such as silicon (Si) or selenium (Se).

  The active layer 54 is, for example, 10 nm thick and has a quantum well structure (tensile strain, −0.7%) made of a GaInP mixed crystal containing no impurities.

  The second light guide layer 55 has, for example, a thickness of 120 nm and is composed of an AlGaInP mixed crystal. The second light guide layer 55 may not contain impurities, or may be added with a p-type impurity such as magnesium (Mg) or zinc (Zn). The first p-type cladding layer 56 has, for example, a thickness of 0.15 μm to 0.5 μm and is composed of a p-type AlInP mixed crystal or an AlGaInP mixed crystal to which a p-type impurity such as zinc (Zn) or magnesium (Mg) is added. Has been. The etch stop layer 57 is for suppressing variations in the thickness of the first p-type cladding layer 56 in the manufacturing process described later. The etch stop layer 57 has a thickness of 10 nm to 50 nm, for example, and is composed of a p-type GaInP mixed crystal to which a p-type impurity such as zinc (Zn) or magnesium (Mg) is added. The second p-type cladding layer 58 has, for example, a thickness of 0.8 μm and is composed of a p-type AlGaInP mixed crystal to which a p-type impurity such as zinc (Zn) or magnesium (Mg) is added. The intermediate layer 59 has, for example, a thickness of 0.05 μm and is composed of a p-type GaInP mixed crystal to which a p-type impurity such as zinc (Zn) or magnesium (Mg) is added. The p-side contact layer 60 has, for example, a thickness of 0.3 μm and is made of p-type GaAs to which a p-type impurity such as zinc (Zn) or magnesium (Mg) is added.

  Of these, the second p-type cladding layer 58, the intermediate layer 59, and the p-side contact layer 60 are formed as thin strip-shaped protrusions (ridges) 61 extending in one direction. The projecting portion 61 is a projecting portion for defining a current injection region to the active layer 54, and current is injected into a portion corresponding to the projecting portion 61 of the active layer 54.

A current confinement layer 62 is formed on the surface of the etch stop layer 57 on both sides of the protrusion 61. The current confinement layer 62 has a thickness of 50 nm to 250 nm, for example, and is made of silicon dioxide (SiO ₂ ), aluminum oxide (Al ₂ O ₃ ), silicon nitride (Si ₃ N ₄ ), or the like.

  A first p-side electrode layer 71 and a second p-side electrode layer 72 are sequentially formed on the top surfaces of the protrusions 61 and the current confinement layer 62, for example, corresponding to the light emitting portions 21. The first p-side electrode layer 71 has a configuration in which, for example, a titanium (Ti) layer having a thickness of 50 nm and a platinum (Pt) layer having a thickness of 100 nm are sequentially stacked from the p-side contact layer 60 side. Electrically connected. The second p-side electrode layer 72 has a configuration in which, for example, a titanium (Ti) layer having a thickness of 50 nm, a platinum (Pt) layer having a thickness of 100 nm, and a gold (Au) layer having a thickness of 300 nm are sequentially stacked from the p-side contact layer 60 side. And electrically connected to the p-side contact layer 60 through the first p-side electrode layer 71.

  Between the first p-side electrode layer 71 and the second p-side electrode layer 72, stress relaxation layers 81 capable of plastic deformation are formed on both sides of the protrusion 61. The semiconductor laser array 20 is bonded to the base 10 on the side where the protrusion 61 and the stress relaxation layer 81 are provided. Thereby, in this light emitting device, the thermal stress generated at the time of joining the semiconductor laser array 20 and the base 10 is absorbed and relaxed by the stress relaxation layer 81 so that the reliability can be improved and the heat dissipation can be efficiently performed. It has become.

The stress relaxation layer 81 is formed of at least one of a group of insulating materials composed of SiO ₂ , AlO _2, and Si ₃ N ₄ , and is formed by electron beam evaporation as will be described later. The thickness of the stress relaxation layer 81 is preferably, for example, 250 nm or more and 2000 nm or less, and more preferably 500 nm or more and 1500 nm or less. This is because when the thickness is less than 250 nm, the stress relaxation effect is reduced, and when the thickness is more than 2000 nm, film peeling is likely to occur in the step of forming the stress relaxation layer 81.

  The distance D1 between the stress relaxation layers 81 is, for example, preferably wider than the width W1 of the protrusion 61, specifically, three times or more the width W1. The heat generated in the current injection region of the active layer 54 below the protrusion 61 can be dissipated to the base 10 without being disturbed by the stress relaxation layer 81 made of an insulating material having low thermal conductivity. This is because it is possible to improve the reliability by suppressing the temperature rise. Furthermore, it is desirable that the distance D2 between each of the stress relaxation layers 81 and the ridge 61 is equal to or greater than the width W1 of the ridge 61. For example, when the entire width of one light emitting portion 21 is 330 μm and the width W1 of the protruding portion 61 is 60 μm, the interval D1 is 180 μm or more, the interval D2 is 60 μm or more, and the width W2 of the stress relaxation layer 81 is 75 μm. . Note that the width W2 of the stress relaxation layer may be adjusted to be wide or narrow according to the overall width of the light emitting portion 21.

  On the other hand, an n-side electrode layer 90 is provided on the back surface of the substrate 51, for example, corresponding to each light emitting unit 21. The n-side electrode layer 90 has a configuration in which, for example, a gold (Au) -germanium (Ge) alloy layer, a nickel (Ni) layer, and a gold (Au) layer are stacked in this order from the substrate 51 side. Connected.

  Further, in the semiconductor laser array 20, a pair of side surfaces facing each other in the resonator direction are resonator end faces, and a pair of reflecting mirror films (not shown) are formed on the pair of resonator end faces. . The reflectance is adjusted so that one of the pair of reflecting mirror films has a low reflectance and the other has a high reflectance. Thereby, the light generated in the active layer 54 is amplified by reciprocating between the pair of reflecting mirror films, and is emitted as a laser beam from the reflecting mirror film on the low reflectance side.

  For example, the solder layer 30 has a thickness of 3 μm to 6 μm and is made of gold (Au) -tin (Sn) solder (eutectic).

  The semiconductor laser array 20 and the light emitting device can be manufactured as follows, for example.

  4 to 6 show the manufacturing method of the semiconductor laser array 20 in the order of steps. First, as shown in FIG. 4 (A), for example, the substrate 51 made of the above-described material is formed from the above-described thickness and material by, for example, MOCVD (Metal Organic Chemical Vapor Deposition) method. The n-type cladding layer 52, the first light guide layer 53, the active layer 54, the second light guide layer 55, the first p-type cladding layer 56, the etch stop layer 57, the second p-type cladding layer 58, the intermediate layer 59 and the p side. Contact layers 60 are sequentially stacked.

  Next, as shown in FIG. 4 (B), a resist 101 is applied to the entire surface of the p-side contact layer 60 and formed into a predetermined shape by a lithography technique, whereby a mask 101 for forming the protrusions 61 is formed. Form.

  Subsequently, as shown in FIG. 4C, etching using the mask 101 is performed to selectively remove a part of the p-side contact layer 60, the intermediate layer 59, and the second p-type cladding layer 58, and to make them thin. Let it be a strip-shaped protrusion 61. At that time, the etch stop layer 57 is used as an etching stopper. After that, the mask 101 is removed.

  After forming the protrusion 61, as shown in FIG. 5A, the surface of the protrusion 61 and the etch stop layer 57 on both sides thereof is formed by, for example, a CVD (Chemical Vapor Deposition) method. Then, the current confinement layer 62 made of the above-described material is formed. Subsequently, similarly as shown in FIG. 5A, a resist is applied on the current confinement layer 62 and formed into a predetermined shape by a lithography technique, thereby providing an opening corresponding to the protrusion 61. A mask 102 is formed.

  After the mask 102 is formed over the current confinement layer 62, as shown in FIG. 5B, etching using the mask 102 is performed to selectively remove a part of the current confinement layer 62, and the ridge portion. An opening is provided corresponding to 61.

  After providing openings in the current confinement layer 62 corresponding to the protrusions 61, as shown in FIG. 5C, the upper surfaces of the protrusions 61 and the current confinement layer 62 are formed by, for example, electron beam evaporation. A first p-side electrode layer 71 is formed by sequentially stacking a titanium (Ti) layer and a platinum (Pt) layer made of the above-described thickness and material.

  After the first p-side electrode layer 71 is formed, as shown in FIG. 6A, a resist is applied to the entire surface of the first p-side electrode layer 71 and formed into a predetermined shape by lithography technology, thereby reducing stress. A mask 103 for forming the layer 81 is formed.

  After forming the mask 103 on the first p-side electrode layer 71, as shown in FIG. 6B, the stress relaxation layer 81 made of the above-described thickness and material is formed. The film forming method is selected so that the density of the stress relaxation layer 81 is reduced and plastic deformation is likely to occur. For example, it is preferable that the temperature of the substrate 51 be kept near room temperature, for example, 15 ° C. or more and 50 ° C. or less and formed by electron beam evaporation. Although the temperature of the stress relaxation layer 81 may rise during electron beam evaporation, it does not exceed 100 ° C. It is also possible to keep at room temperature by cooling.

  After forming the stress relaxation layer 81, as shown in FIG. 6C, the mask 103 is removed, and the above-described thickness is formed on the first p-side electrode layer 71 and the stress relaxation layer 81 by, for example, electron beam evaporation. Then, a titanium (Ti) layer, a platinum (Pt) layer, and a gold (Au) layer made of materials are laminated in this order to form the second p-side electrode layer 72.

  After forming the second p-side electrode layer 72, for example, the back side of the substrate 51 is ground to a thickness of the substrate 51 of about 110 μm, and the n-side electrode layer 90 is formed on the back side of the substrate 51.

  After the n-side electrode layer 90 is formed, the substrate 51 is arranged into a bar having a predetermined size by cleavage. At that time, before the cleavage, for example, by using a laser scribing machine, a laser beam whose beam diameter is narrowed down in advance is irradiated, so that the first p-side electrode layer 71 and the second p-side electrode layer 72 in the thickness direction. It is preferable to cut a part or the whole. This is because the first p-side electrode layer 71 and the second p-side electrode layer 72 are easily separated, and the so-called peeling of the first p-side electrode layer 71 and the second p-side electrode layer 72 can be suppressed. In this case, after cutting part or all of the first p-side electrode layer 71 and the second p-side electrode layer 72 in the thickness direction, separation by cleavage can be performed subsequently.

  Instead of laser scribing, part or all of the first p-side electrode layer 71 and the second p-side electrode layer 72 in the thickness direction may be cut by mechanical processing. That is, the first p-side electrode layer 71 and the second p-side electrode layer 72 are scratched with a diamond needle so as to be easily separated. In this case, the first p-side electrode layer 71 and the second p-side electrode layer 72 are shallowly damaged, and the first p-side electrode layer 71 and the second p-side electrode layer 72 are deeply damaged so as to reach the laser wafer. Process.

  In addition, when the first p-side electrode layer 71 and the second p-side electrode layer 72 are formed for mechanical processing, element isolation grooves may be provided. In that case, resist formation and photolithography are performed before the first p-side electrode layer 71 or the second p-side electrode layer 72 is formed, and the first p-side electrode layer 71 or the second p-side electrode layer 72 is formed and then separated by lift-off. A general method of providing a groove can be employed.

  Finally, a reflecting mirror film (not shown) is formed on the pair of resonator end faces opposed to each other in the length direction of the protrusion 61. Thereby, the semiconductor laser array 20 shown in FIGS. 2 and 3 is formed.

  After forming the semiconductor laser array 20, a base 10 made of the above-described dimensions and materials is prepared, and a gold (Au) layer and a surface of the base 10 on which the semiconductor laser array 20 is provided, for example, by vacuum deposition or plating. The solder layer 30 is formed by sequentially laminating tin (Sn) layers.

  After the solder layer 30 is formed on the base 10, the second p-side electrode layer 72 of the semiconductor laser array 20 and the solder layer 30 of the base 10 are opposed to each other, and alignment is performed with high precision. Put on. Subsequently, the base 10 is heated to melt the solder layer 30, and the base 10 and the semiconductor laser array 20 are joined. Here, a plastically deformable stress relaxation layer 81 is provided on both sides of the ridge portion 61, and the side of the semiconductor laser array 20 on which the ridge portion 61 and the stress relaxation layer 81 are provided is joined to the base 10. Therefore, the thermal stress generated when the semiconductor laser array 20 and the base 10 are joined is absorbed and relaxed by plastic deformation of the stress relaxation layer 81. Therefore, the stress applied to the semiconductor laser array 20 is reduced, and the occurrence of cracks and the like is suppressed.

  After joining the base 10 and the semiconductor laser array 20, the electrode member 11 is fixed on the base 10 with the insulating plate 12 therebetween, and one end of the wire 40 is joined to the step portion 11 </ b> C of the electrode member 11. Is joined to the n-side electrode layer 80 of the semiconductor laser array 20. After that, the protection member 13 is fixed to the step portion 11 </ b> C of the electrode member 11. Thus, the light emitting device shown in FIG. 1 is completed.

  In this light emitting device, when a predetermined voltage is applied between the n-side electrode layer 90, the first p-side electrode layer 71, and the second p-side electrode layer 72 of each light emitting unit 21, current is injected into the active layer 54. Light emission occurs due to electron-hole recombination. This light is reflected by a pair of reflecting mirror films (not shown), reciprocates between them to generate laser oscillation, and is emitted to the outside as a laser beam. Here, a plastically deformable stress relaxation layer 81 made of an insulating material is provided on both sides of the protrusion 61, and the side on which the protrusion 61 and the stress relaxation layer 81 of the semiconductor laser array 20 are provided is the base. 10, the thermal stress generated when the semiconductor laser array 20 and the base 10 are bonded is alleviated, and the stress applied to the semiconductor laser array 20 is reduced. Therefore, the reliability of the semiconductor laser array 20 is improved. In addition, the stress applied to the active layer 54 is reduced, and the change in the emission wavelength and the change in the threshold current value can be suppressed. Furthermore, since the semiconductor laser array 20 is directly bonded to the base 10 without a submount, the heat generated by the semiconductor laser array 20 is efficiently dissipated to the base 10.

  As described above, in this embodiment, since the stress relaxation layers 81 that can be plastically deformed are provided on both sides of the protrusion 61, the thermal stress generated when the semiconductor laser array 20 and the base 10 are joined is reduced. High reliability can be obtained. Therefore, the light emitting device excellent in heat dissipation efficiency and reliability can be obtained by bonding the side of the semiconductor laser array 20 where the protrusions 61 and the stress relaxation layer 81 are provided to the base 10 to form the light emitting device. Can be realized. In particular, stable characteristics can be obtained in the red semiconductor laser array 20 having an oscillation wavelength in the wavelength range of 630 nm to 690 nm.

  Further, since the solder layer 30 can be composed of gold (Au) -tin (Sn) solder, the reliability is improved and the strength is improved as compared with the direct mount using the conventional indium solder. Resistance can be reduced.

(Modification)
FIG. 7 shows a cross-sectional configuration of one light emitting portion 21A constituting a semiconductor laser array according to a modification of the present invention. The light emitting unit 21A has the same configuration as the light emitting unit 21A according to the above-described embodiment except that the light emitting unit 21A is an infrared laser having an oscillation wavelength in a wavelength region of 780 nm to 850 nm, and has the same functions and effects. have. Accordingly, the corresponding components will be described with the same reference numerals.

  The light emitting unit 21A includes, for example, a first n-type buffer layer 112, a second n-type buffer layer 113, an n-type cladding layer 114, a first light guide layer 115, an active layer 116, a second light guide layer 117, and the like on a substrate 111. The first p-type cladding layer 118, the etch stop layer 119, the second p-type cladding layer 120, the intermediate layer 121, and the p-side contact layer 122 have a double hetero (DH) junction stacked structure in this order.

The substrate 111 is constituted by an n-type GaAs substrate to which an n-type impurity such as silicon (Si) or selenium (Se) is added, for example. For example, the first n-type buffer layer 112 has a thickness of 0.5 μm and is made of n-type GaAs to which an n-type impurity such as silicon (Si) or selenium (Se) is added. The second buffer layer 113 has, for example, a thickness of 0.5 μm and is composed of an n-type Al _0.3 Ga _0.7 As mixed crystal to which an n-type impurity such as silicon (Si) or selenium (Se) is added. The n-type cladding layer 114 has, for example, a thickness of 1.8 μm and is composed of an n-type Al _0.47 Ga _0.53 As mixed crystal to which an n-type impurity such as silicon (Si) or selenium (Se) is added.

The first light guide layer 115 has a thickness of, for example, 60 nm or more and 65 nm or less, and is composed of an Al _0.3 Ga _0.7 As mixed crystal. The active layer 116 has a thickness of 10 nm, for example, and is composed of Al _0.14 Ga _0.86 As mixed crystal. The second light guide layer 117 has, for example, a thickness of 60 nm or more and 65 nm or less, and is composed of Al _0.3 Ga _0.7 As mixed crystal.

The first p-type cladding layer 118 has a thickness of, for example, 0.15 μm to 0.5 μm and is composed of a p-type Al _0.47 Ga _0.53 As mixed crystal to which a p-type impurity such as zinc (Zn) or magnesium (Mg) is added. Has been. The etch stop layer 119 has a thickness of 10 nm to 50 nm, for example, and is made of a p-type GaInP mixed crystal to which a p-type impurity such as zinc (Zn) or magnesium (Mg) is added. The second p-type cladding layer 120 has, for example, a thickness of 1.5 μm and is composed of a p-type Al _0.47 Ga _0.53 As mixed crystal to which a p-type impurity such as zinc (Zn) or magnesium (Mg) is added. The intermediate layer 121 has, for example, a thickness of 0.3 μm and is composed of a p-type Al _0.3 Ga _0.7 As mixed crystal to which a p-type impurity such as zinc (Zn) or magnesium (Mg) is added. The p-side contact layer 122 has, for example, a thickness of 0.5 μm and is made of p-type GaAs to which a p-type impurity such as zinc (Zn) or magnesium (Mg) is added.

  Among these, the second p-type cladding layer 120, the intermediate layer 121, and the p-side contact layer 122 are formed as thin strip-like protrusions 61, as in the first embodiment, and the etch stop layers 119 on both sides thereof are formed. A current confinement layer 62 is formed on the surface. Similar to the first embodiment, the first p-side electrode layer 71 and the second p-side electrode layer 72 are formed on the upper surfaces of the protrusions 61 and the current confinement layer 62, and the first surface is provided on the back surface of the substrate 111. As in the embodiment, an n-side electrode layer 90 is provided.

  Between the first p-side electrode layer 71 and the second p-side electrode layer 72, stress relaxation layers 81 that can be plastically deformed are provided on both sides of the protrusion 61, as in the first embodiment. The specific configuration of the stress relaxation layer 81 is the same as that of the first embodiment.

  The semiconductor laser array having the light emitting portion 21A can be manufactured in the same manner as in the first embodiment except that the thickness and material of the first buffer layer 112 to the p-side contact layer 122 are different. Further, the semiconductor laser array having the light emitting portion 21A can be joined to the base 10 by the solder layer 30 in the same manner as in the first embodiment to constitute a light emitting device.

(Second Embodiment)
FIG. 8 shows a cross-sectional configuration of one light emitting portion 21B constituting the semiconductor laser array according to the second embodiment of the present invention. The light emitting unit 21B has the same configuration as the light emitting unit 21 according to the first embodiment except that the constituent material of the stress relaxation layer 131 is different. Accordingly, the corresponding components will be described with the same reference numerals.

  Examples of the constituent material of the stress relaxation layer 131 include a group of plastically deformable metal materials such as tin (Sn) -lead (Pb) alloy, indium (In), and indium (In) -silver (Ag) alloy. At least one of these is preferred. Moreover, a tin (Sn) -indium (In) alloy (In = 52%) may be used.

  The thickness of the stress relaxation layer 131 is preferably, for example, 0.5 μm or more and 5 μm or less, and more preferably about 2 μm. This is because when the thickness is less than 0.5 μm, the stress relaxation effect is almost lost, and when the thickness is more than 5 μm, indium (In) easily protrudes from the end portion when melted.

  In addition, an alloying prevention layer 132 that suppresses alloying of indium (In) contained in the stress relaxation layer 131 is preferably provided on the upper side and the lower side of the stress relaxation layer 131. This is because indium (In) can be suppressed from reacting with gold (Au) or platinum (Pt) contained in the first p-side electrode layer 71 or the second p-side electrode layer 72 to form an alloy. The alloying prevention layer 132 is preferably made of a metal that does not form any alloy with indium (In), such as aluminum (Al). Titanium (Ti) may also be used. The thickness of the alloying prevention layer 132 is preferably 100 nm or more and 150 nm or less, for example. This is because if the thickness is less than 100 nm, an island shape is formed when the alloying prevention layer 132 is formed, and indium (In) may not be sufficiently confined.

  The semiconductor laser array having the light emitting portion 21B can be manufactured in the same manner as in the first embodiment except that the stress relaxation layer 131 and the alloying prevention layer 132 are formed using a metal mask. it can. Further, the semiconductor laser array having the light emitting portion 21B can be joined to the base 10 by the solder layer 30 in the same manner as in the first embodiment to constitute a light emitting device.

  In this light-emitting device, when a predetermined voltage is applied between the n-side electrode layer 90, the first p-side electrode layer 71, and the second p-side electrode layer 72 of each light-emitting portion 21B, the same as in the first embodiment Laser oscillation occurs. Here, stress relief layers 131 made of a plastically deformable metal material are provided on both sides of the protrusion 61, and the side on which the protrusion 61 and the stress relaxation layer 131 of the semiconductor laser array are provided is the base 10. Therefore, in addition to the operation of the first embodiment, the heat generated by the semiconductor laser array 20 is dissipated to the base 10 more efficiently.

  Further, since the stress relaxation layer 131 is sandwiched between the alloying prevention layers 132 made of a metal that does not form an alloy with indium at all, for example, aluminum (Al), even if the indium contained in the stress relaxation layer 131 is melted. Reaction and alloying with gold (Au) or platinum (Pt) contained in the first p-side electrode layer 71 or the second p-side electrode layer 72 is suppressed. Therefore, by cooling after mounting, the indium of the stress relaxation layer 131 returns to its original state without reacting or changing.

  As described above, in the present embodiment, the stress relaxation layer 131 made of a plastically deformable metal material is provided on both sides of the protrusion 61, and the protrusion 61 and the stress relaxation layer 131 of the semiconductor laser array 20 are provided. Since the side which is present is joined to the base 10, in addition to the effects of the first embodiment, the heat dissipation efficiency can be further improved.

  Furthermore, since the stress relaxation layer 131 is sandwiched between the alloying prevention layers 132 made of a metal that does not form an alloy with indium at all, such as aluminum (Al), even if the indium contained in the stress relaxation layer 131 melts. It is possible to suppress alloying by reacting with gold (Au) or platinum (Pt) contained in the 1p-side electrode layer 71 or the second p-side electrode layer 72.

  While the present invention has been described with reference to the embodiment, the present invention is not limited to the above embodiment, and various modifications can be made. For example, in the above embodiment, the case where the light emitting device includes the bar-shaped semiconductor laser array 20 has been described. However, the present invention is a semiconductor laser device (semiconductor laser chip) having only one light emitting unit 21, 21A, 21B. ) Is also applicable.

  Further, for example, in the above embodiment, the semiconductor laser array 20 is disposed so that the second p-side electrode layer 72 faces the base 10, and the first p-side electrode layer 71 and the second p-side electrode layer 72 are disposed. In the above description, the stress relaxation layers 81 and 131 are provided between the first and second layers. However, the stress relaxation layer is provided on the n-side electrode layer side of the laser using the p-type substrate, and the semiconductor laser array is arranged on the n-side. The electrode layer may be disposed so as to face the base.

  Furthermore, for example, the material and thickness of each layer described in the above embodiment, the film formation method and the film formation conditions are not limited, and other materials and thicknesses may be used, or other film formation methods and Film forming conditions may be used. For example, the solder layer 30 may be silver (Ag) -tin (Sn) solder (eutectic) or tin (Sn) -silver (Ag) -copper (Cu) solder. In addition, although it is preferable that the solder layer 30 is comprised with the solder (lead free solder) which does not contain lead, you may be comprised with lead-type solders, such as a tin (Sn) -lead (Pb) solder.

  In addition, in the above embodiment, the configuration of the semiconductor laser array 20 and the light emitting units 21, 21A, and 21B has been specifically described. However, it is not necessary to include all layers, and further include other layers. It may be. For example, in the second embodiment, the alloying prevention layer 132 may be provided on at least one of the upper side or the lower side of the stress relaxation layer 131. Further, the width W1 of the ridge portion 61 does not necessarily have to be constant over the entire extending direction, and there may be a portion where the width W1 is partially different.

  Furthermore, for example, in the first and second embodiments, a red laser having a semiconductor layer made of an AlGaInP-based compound semiconductor on a substrate made of GaAs or an infrared laser having a semiconductor layer made of an AlGaAs-based compound semiconductor. However, the present invention can also be applied to other material systems such as a GaN system (oscillation wavelength of 400 nm to 500 nm). However, particularly in the case of a red laser, the effect is great because the difference in linear expansion coefficient between GaAs constituting the substrate and copper (Cu) constituting the base 10 is large.

  In addition, in the above embodiment, the light emitting device including the semiconductor laser array 20 has been described as an example. However, the present invention includes other semiconductor light emitting elements such as LEDs or superluminescent diodes in addition to the semiconductor laser. It is applicable also to the light-emitting device provided. In that case, the shape of the protrusion for defining the current injection region to the active layer is not limited to the protrusion extending in one direction as in the case of a laser. Moreover, the stress relaxation layer should just be provided in at least one part around the protrusion part.

It is a disassembled perspective view showing the whole structure of the light-emitting device concerning the 1st Embodiment of this invention. FIG. 2 is an enlarged perspective view showing the semiconductor laser array shown in FIG. 1. It is sectional drawing showing the structure of the light emission part shown in FIG. It is sectional drawing showing the manufacturing method of the light emission part shown in FIG. 3 in order of a process. FIG. 5 is a cross-sectional view illustrating a process following FIG. 4. FIG. 6 is a cross-sectional view illustrating a process following FIG. 5. It is sectional drawing showing the structure of the light emission part which concerns on the modification of this invention. It is sectional drawing showing the structure of the light emission part which concerns on the 2nd Embodiment of this invention. It is sectional drawing for demonstrating an example of the conventional mounting method. It is sectional drawing for demonstrating the other example of the conventional mounting method. It is a figure for demonstrating the problem of the conventional mounting method.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Base, 11 ... Electrode member, 12 ... Insulating plate, 13 ... Protection member, 20 ... Semiconductor laser array, 21, 21A, 21B ... Light emission part, 30 ... Solder layer, 40 ... Wire, 51, 111 ... Substrate, 52 , 114 ... n-type cladding layer, 53, 115 ... first light guide layer, 54, 116 ... active layer, 55, 117 ... second light guide layer, 56, 118 ... first p-type cladding layer, 57, 119 ... etch Stop layer, 58, 120 ... second p-type cladding layer, 59, 121 ... intermediate layer, 60, 122 ... p-side contact layer, 71 ... first p-side electrode layer, 72 ... second p-side electrode layer, 81, 131 ... stress Relaxation layer, 90 ... n-side electrode layer, 101, 102, 103 ... mask, 112 ... first n-type buffer layer, 113 ... second n-type buffer layer, 132 ... alloying prevention layer

Claims (11)

A semiconductor light emitting device including a semiconductor layer including an active layer,
The upper part of the semiconductor layer is a protrusion for defining a current injection region to the active layer,
A semiconductor light emitting element, wherein a plastically deformable stress relaxation layer is provided on at least a part of the periphery of the protruding portion above the semiconductor layer. The semiconductor light emitting element according to claim 1, wherein the stress relaxation layer is formed of at least one of a group of insulating materials made of SiO ₂ , Al ₂ O _3, and Si ₃ N ₄ . The semiconductor light emitting element according to claim 2, wherein the stress relaxation layer is formed by electron beam evaporation. The stress relaxation layer is made of at least one selected from the group consisting of tin (Sn) -lead (Pb) alloy, indium (In), and indium (In) -silver (Ag) alloy. The semiconductor light-emitting device according to claim 1. The protrusion is a ridge extending in one direction,
The semiconductor light emitting element according to claim 1, wherein the semiconductor light emitting element generates laser oscillation by reciprocating light generated in the active layer in an extending direction of the protrusion. The stress relaxation layer is provided on both sides of the protrusion,
The semiconductor light emitting element according to claim 5, wherein an interval between each of the stress relaxation layers is at least three times a width of the protruding portion. The semiconductor light emitting element according to claim 1, wherein the semiconductor light emitting element array includes a plurality of light emitting parts each having the protruding portion. A method for manufacturing a semiconductor light emitting device including a semiconductor layer including an active layer,
Forming a protrusion for defining a current injection region to the active layer on the semiconductor layer;
And a step of providing a plastically deformable stress relaxation layer on at least a part of the periphery of the protruding portion on the upper side of the semiconductor layer. The stress relieving layer, SiO _2, Al ₂ O ₃ and Si ₃ at least one of the group of N of _four insulating material, a semiconductor light emitting according to claim 8, wherein the forming by electron beam evaporation Device manufacturing method. The stress relaxation layer is composed of at least one member selected from the group consisting of tin (Sn) -lead (Pb) alloy, indium (In), and indium (In) -silver (Ag) alloy. A method for manufacturing a semiconductor light emitting device according to claim 8. A light-emitting device in which a semiconductor light-emitting element including a semiconductor layer including an active layer is bonded to a support,
The upper part of the semiconductor layer is a protrusion for defining a current injection region to the active layer,
A stress relaxation layer capable of plastic deformation is provided on at least a part of the periphery of the upper protrusion of the semiconductor layer,
The side of the semiconductor light emitting element on which the protruding portion and the stress relaxation layer are provided is joined to the support.

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