JP2008124640A - Encoding apparatus and encoding method - Google Patents

Abstract

A circuit scale is further reduced.
A state machine outputs encoded data in accordance with a conversion table for converting input data determined in each of states 0 to 5 into encoded data in accordance with input data I0 to I5 for each clock. At the same time, the state in the next clock is determined. Each conversion table defines encoded data O, a state transition destination to, and a termination process confirmation bit T corresponding to input data I0 to I5 including termination patterns. The present invention can be applied to, for example, a recording apparatus.
[Selection] Figure 4

Description

  The present invention relates to an encoding device and an encoding method, and more particularly to an encoding device and an encoding method that are more suitable when data is recorded on a recording medium.

  Usually, when a signal is recorded on a recording medium such as a magnetic disk or an optical disk, the signal is pre-modulated and coded so that amplitude control and clock reproduction of the signal read at the time of reproduction are normally performed. A modulation code is recorded.

  For modulation coding, a coding table of a predetermined modulation code for applying a predetermined restriction to the input signal is used. The input signal is encoded into a predetermined modulation code based on the encoding table, and is recorded as a modulation code signal obtained by adding a predetermined restriction to the signal. As a restriction, for example, a DC-free restriction that allows the number of codes 0 and 1 to be even in a sufficiently long range, and the minimum and maximum lengths of the number of consecutive zeros are d and k (d, k) Restrictions etc. are used.

  As one of such modulation codes, there is a 17PP (Parity Preserve / Prohibit Repeated Minimum Transition Runlength) code used for the modulation of Blu-ray disk (trademark). In the 17PP code, since parity is maintained before and after encoding, that is, when the sum of the numbers of 1 in the signal to be encoded is an even number, the sum of the numbers of 1 in the modulation code is an even number, When the sum of the numbers of 1 in the signal to be encoded is an odd number, the sum of the numbers of 1s of the modulation codes is an odd number. Therefore, DC control is performed before encoding, that is, the number of codes 0 and 1 is the same. Can only be controlled to appear. Further, in the 17PP code, the number of shortest mark lengths that appear consecutively is set to 6 times, and it is possible to improve the data detection capability in PRML (Partial Response Maximum Likelihood) reproduction.

  The 17PP code is composed of a frame sync pattern and a data part.

  The frame sync pattern of the 17PP code, that is, the pattern of the sync signal portion, follows, for example, the frame sync pattern determination table shown in FIG. 1 proposed by the present applicant in Japanese Patent Application No. 10-237044.

  As shown in FIG. 1, the frame sync pattern determination table represents a frame state, a frame number, and a frame sync pattern. Further, the frame sync pattern is composed of Sync-body and Sync-ID. The frame state is any one of seven types FS0 to FS6. There are 31 frame numbers from 0 to 30, and the frame number is classified into 7 frame states. Specifically, frame number 0 is classified into frame state FS0, frame numbers 1, 5, 7, 23, and 24 are classified into frame state FS1, and frame numbers 2, 18, 19, 26, and 30 are each frame. In the state FS2, the frame numbers 3, 4, 11, 15, and 17 are classified in the frame state FS3, and the frame numbers 6, 10, 12, 28, and 29 are classified in the frame state FS4. 9, 16, 20, and 22 are classified into the frame state FS5, and the frame numbers 13, 14, 21, 25, and 27 are classified into the frame state FS6. The Sync-body is the first 24 bits of the output 30-bit frame sync pattern, and is “# 01 010 000 000 010 000 000 010”.

  Note that the first 1 bit in the Sync-body represented by “#” in FIG. 1 is “1” when the previous frame ends with the termination process, and “0” otherwise. The Sync-ID is the remaining 6 bits of the output frame sync pattern, and is any one of the 7 types for each frame state for classifying the frame number. Specifically, the Sync-ID is “000 001” when the frame state is FS0, “010 010” when the frame state is FS1, and “101 000” when the frame state is FS2. When the frame state is FS3, it is “100 001”, when the frame state is FS4, it is “000 100”, when the frame state is FS5, it is “001 001”, and when the frame state is FS6. Is "010 000".

  Thus, according to the frame sync pattern determination table, the corresponding frame sync pattern is determined according to the frame number.

  The data portion of the 17PP code is encoded by, for example, the variable length encoding method according to the encoding table shown in FIG. 2 proposed by the present applicant in Japanese Patent Application No. 10-150280. That is, in the 17PP code encoding, output bits for input bits are determined according to the encoding table of FIG.

  According to the encoding table of FIG. 2, in the basic process which is a normal process, when the input bit is “00 00 00 00”, “010 100 100 100” is output as the output bit, and the input bit is When “00 00 10 00”, “000 100 100 100” is output as the output bit, and when the input bit is “00 00 00”, “010 100 000” is output as the input bit. When the bit is “00 00 01”, “010 100 100” is output as the output bit, and when the input bit is “00 00 10”, “000 100 000” is output as the input bit. When the bit is “00 00 11”, “000 100 100” is output as the output bit. It is a force.

  Further, when the input bit is “00 01”, “000 100” is output as the output bit, and when the input bit is “00 10”, “010 000” is output as the output bit. Is “00 11”, “010 100” is output as the output bit, and when the input bit is “01”, “010” is output as the output bit and the input bit is “10”. In this case, “001” is output as an output bit. When the input bit is “11” and the previous output bit is “xx1” (x may be 0 or 1), “000” is output as the output bit, Is “11” and the previous output bit is “xx0” (x may be 0 or 1), “101” is output as the output bit.

  Further, according to the encoding table of FIG. 2, as special processing, when the input bit is “11 01 11” and the output bit in the next clock (the next output bit) is “010”, “001 000 000” is output as an output bit.

  Furthermore, according to the encoding table of FIG. 2, as the termination process, when the last input bit of the frame is “00 00”, “010 100” is output as the output bit, and the last input bit of the frame is If it is “00”, “000” is output as an output bit.

  When encoding the 17PP code based on such an encoding table, priority is given to the conversion of the input bits arranged above the encoding table of FIG. 2 into output bits. That is, the input bit that is “00 00 00 00” is the input bit that is “00 00 00 00” at the top in the encoding table of FIG. 2 and the input bit that is “00 00 00” that is the third from the top. 2, but the upper input bit in the coding table of FIG. 2 is given priority, so that the input bit “00 00 00 00” is converted to the output bit “010 100 100 100”. . At this time, when the bit string in the input data corresponds to the input bit of the special process, the conversion of the special process has priority. Further, when the end of the frame of the input data corresponds to the termination process, the termination process is converted.

  Two methods are conceivable as a method of mounting the configuration for encoding the data portion by hardware. One is a method of convolutionally encoding input data until the input data corresponds to an input bit defined in the encoding table (until an output bit is specified), and one is using a state machine. In this method, encoded data is output every clock.

  In the former method, since encoded data is output intermittently, that is, the output bits are 3 bits for 1 clock or 12 bits for 4 clocks, the delay amount is reduced by a delay circuit. It needs to be adjusted.

  On the other hand, in the latter method, the input bits are encoded by the state machine, and the encoded output bits are output continuously (3 bits for each clock), so that a delay circuit after encoding is unnecessary. (For example, see Non-Patent Document 1).

A. Hayami et al., "Sliding Window Coding Technique for the Variable Length Modulations", Optical Memory and Optical Data Storage Topical Meeting, 2002.International Symposium on, 338-340, July 2002

  However, the method of Non-Patent Document 1 has a problem that the termination processing in FIG.

  At present, a state machine that considers termination processing has not been proposed, and a configuration for encoding a 17PP code using a state machine cannot be implemented by hardware.

  The present invention has been made in view of such a situation, and makes it possible to further reduce the circuit scale.

  An encoding apparatus according to an aspect of the present invention is an encoding apparatus that converts input data having a basic data length of 2 bits into a 17PP (Parity Preserve / Prohibit Repeated Minimum Transition Runlength) code having a basic code length of 3 bits. Generating means for generating an end signal indicating that the input data is the end of the frame, and input of the first three basic data lengths among the six basic data length input data input in order up to the previous one The first state to be transited when the data is “11 01 11” and the 17PP code for the input data next to the input data of the three basic data lengths is “010”, up to the previous one Transition is made when the input data of the first four basic data lengths among the input data of the six basic data lengths input in order is “00 00 00 00” or “00 00 10 00” In the second state, the transition is made when the first two basic data length input data among the six basic data length input data input in order up to the previous one is “00 00”. 3 state, 4th state, 1 to be transited when the input data of the first basic data length among the 6 basic data length input data input in order up to the previous one is “00” The fifth state that is shifted when the last bit of the 17PP code with the basic code length of the previous 3 bits is 0, and the last bit of the 17PP code with the basic code length of the previous 3 bits is 1 Sixth states to be transitioned in a certain case, the first state to the sixth state in which the correspondence relationship between the input data having six basic data lengths and the 17PP code having one basic code length is defined. Of the states, the fifth state and the previous The fourth state has priority over the sixth state, the third state has priority over the fourth state, the second state has priority over the third state, A state machine that makes a state transition so that the first state is prioritized over the second state, and input data having six basic data lengths in the fourth state to the sixth state When the input data of the first two basic data lengths is “00 00”, or the input data of the first basic data length of the six basic data length input data is “00”, When input data that is “00 00” or input data that is “00” is the end of the frame, input data that is “00 00” or input data that is “00” is not the end of the frame. Different from sign The 17PP code is configured as a state machine defined for 6 basic data length input data, and the input data is converted into 17PP based on the 6 basic data length input data and the termination signal input in order. Coding means for coding the code.

  The correspondence relationship between the input data and the 17PP code can be defined by a state table for each of the first to sixth states.

  In the state table, corresponding to the input data of six basic data lengths input in order, a 17PP code of one basic code length, a transition state from the first state to the sixth state, and 6 Information indicating whether the input data of the first two basic data lengths among the input data of the two basic data lengths is “00 00” or “00” and the end of the frame is specified. be able to.

  The fifth state and the sixth state are initial states in which encoding of the input data is started, and the initial state is a synchronization signal arranged before the code string in the frame The last bit of the pattern may determine whether the fifth state or the sixth state.

  Based on the information indicating whether the input data of the first two basic data lengths among the input data of the six basic data lengths is “00 00” or “00” and the end of the frame, The first bit of the sync signal pattern in the frame can be determined.

  An encoding method according to an aspect of the present invention is an encoding method for converting input data having a basic data length of 2 bits into a 17PP code having a basic code length of 3 bits, and the input data is a frame end. The first three basic data length input data among the six basic data length input data input in order up to the previous one is “11 01 11”, and The first state that is transitioned when the 17PP code for the next input data of the input data of three basic data lengths is “010”, the input data of the six basic data lengths input in order up to the previous one When the input data of the first four basic data lengths is “00 00 00 00” or “00 00 10 00”, the second state is changed, and the six basics input in order up to the previous one The third state to be transitioned when the input data of the first two basic data lengths among the input data of the data length is “00 00”, the six basic data lengths input in order up to the previous one The fourth state to be shifted when the input data of the first basic data length among the input data of “0” is “00”, the last bit of the 17PP code having the basic code length of the previous three bits is 0 A fifth state that is transitioned in some cases, and a sixth state that is transitioned in the case where the last bit of the 17PP code of the previous three-bit basic code length is 1, Of the first to sixth states in which the correspondence between the input data of the basic data length and the 17PP code of one basic code length is defined, the fifth state and the sixth state The fourth state has priority and the fourth state The third state has priority over the state, the second state has priority over the third state, and the first state has priority over the second state, The state machine is a state machine, and in the fourth state to the sixth state, the first two basic data length input data among the six basic data length input data is “00 00”. Or when the input data of the first basic data length among the six basic data length input data is “00”, the input data of “00 00” or the input data of “00” is When it is the end, 17PP code different from the 17PP code when the input data of “00 00” or the input data of “00” is not the end of the frame is specified for the input data of six basic data lengths Is configured as a state machine that is, based on the input data and the termination signal of the six basic data length entered sequentially, comprising the step of encoding the input data to the 17PP code.

  In one aspect of the present invention, a termination signal indicating that the input data is the end of the frame is generated, and the first three basic data among the six basic data length input data sequentially input up to the previous one The first state to be transited when the input data of the data length is “11 01 11” and the 17PP code for the input data next to the input data of the three basic data lengths is “010”, 1 Transition is made when the input data of the first four basic data lengths among the input data of the six basic data lengths input in order up to the previous one is “00 00 00 00” or “00 00 10 00”. Transition to the second state, when the input data of the first two basic data lengths among the six basic data length input data sequentially input up to the previous one is “00 00” A fourth state to be transited when the first basic data length input data among the six basic data length input data sequentially input up to the previous one is “00”, The fifth state that is shifted when the last bit of the previous 17-bit code of the 3-bit basic code length is 0, and the last bit of the previous 17-bit code of the 3-bit basic code length is In the sixth state to which the transition is made when the number is 1, the first state through the state in which the correspondence relationship between the input data having six basic data lengths and the 17PP code having one basic code length are defined Of the sixth states, the fourth state has priority over the fifth state and the sixth state, the third state has priority over the fourth state, and the third state has priority over the third state. State 2 has priority, and state 1 has priority over state 2 In the fourth to sixth states, the first two basic data length input data among the six basic data length input data are “00 00”. Or when the input data of the first basic data length among the six basic data length input data is “00”, the input data of “00 00” or the input data of “00” is the end of the frame , The 17PP code different from the 17PP code when the input data of “00 00” or the input data of “00” is not the end of the frame is defined for the input data of six basic data lengths. The input data is encoded into a 17PP code based on the six basic data length input data and the termination signal which are configured as a state machine and sequentially input.

  As described above, according to the aspect of the present invention, it is possible to encode the 17PP code. In particular, according to the aspect of the present invention, the circuit scale can be further reduced.

  Embodiments of the present invention will be described below. Correspondences between the constituent elements of the present invention and the embodiments described in the specification or the drawings are exemplified as follows. This description is intended to confirm that the embodiments supporting the present invention are described in the specification or the drawings. Therefore, even if there is an embodiment that is described in the specification or the drawings but is not described here as an embodiment that corresponds to the constituent elements of the present invention, that is not the case. It does not mean that the form does not correspond to the constituent requirements. Conversely, even if an embodiment is described here as corresponding to a configuration requirement, that means that the embodiment does not correspond to a configuration requirement other than the configuration requirement. It's not something to do.

  An encoding apparatus according to an aspect of the present invention is an encoding apparatus that converts input data having a basic data length of 2 bits into a 17PP (Parity Preserve / Prohibit Repeated Minimum Transition Runlength) code having a basic code length of 3 bits. Generation means (for example, the frame counter 11 in FIG. 3) for generating an end signal indicating that the input data is the end of the frame, and input data of six basic data lengths input in order up to the previous one The first three basic data lengths of the input data are “11 01 11” and the 17PP code for the input data next to the input data of the three basic data lengths is “010”. In the first state, the input data of the first four basic data lengths among the input data of the six basic data lengths input in order up to the previous one are “00 00 00 00” or “ The second state to be transitioned in the case of “0 00 10 00” is the first two input data of the basic data length among the input data of the six basic data lengths input in order up to the previous one. In the third state to be transitioned when it is “00”, when the input data of the first basic data length among the input data of the six basic data lengths input in order up to the previous one is “00” The fourth state to be transitioned, the fifth state to be transitioned when the last bit of the 17PP code having the basic code length of the previous 3 bits is 0, and the basic code length of the previous 3 bits This is the sixth state that is transitioned when the last bit of the 17PP code of 1 is 1, each of which defines the correspondence between the input data of 6 basic data lengths and the 17PP code of 1 basic code length The first state to the first Among the states, the fourth state has priority over the fifth state and the sixth state, the third state has priority over the fourth state, and the third state. A state machine that makes a state transition so that the second state has priority over the second state, and the first state has priority over the second state. In this state, when the input data of the first two basic data lengths among the input data of the six basic data lengths is “00 00”, or the first basic data of the input data of the six basic data lengths When the long input data is “00”, when the input data that is “00 00” or the input data that is “00” is the end of the frame, the input data that is “00 00” or “00” Some input data is before A 17PP code different from the 17PP code at the end of the frame is configured as a state machine defined for input data of six basic data lengths, and the input data of the six basic data lengths input in order and the end Coding means (for example, the data coding unit 18 in FIG. 3) for coding input data into a 17PP code based on the signal is provided.

  The correspondence relationship between the input data and the 17PP code can be defined by a state table for each of the first to sixth states (for example, the conversion tables of FIGS. 5 to 10).

  In the state table, corresponding to the input data of six basic data lengths input in order, a 17PP code of one basic code length, a transition state from the first state to the sixth state, and 6 Information indicating whether the input data of the first two basic data lengths among the input data of the two basic data lengths is “00 00” or “00” and the end of the frame is specified. be able to.

  The fifth state and the sixth state are initial states in which encoding of the input data is started, and the initial state is a synchronization signal arranged before the code string in the frame The last bit of the pattern may determine whether the fifth state or the sixth state.

  Based on the information indicating whether the input data of the first two basic data lengths among the input data of the six basic data lengths is “00 00” or “00” and the end of the frame, The first bit of the sync signal pattern in the frame can be determined.

  An encoding method according to an aspect of the present invention is an encoding method for converting input data having a basic data length of 2 bits into a 17PP code having a basic code length of 3 bits, and the input data is a frame end. (For example, step S13 in FIG. 11), the input data of the first three basic data lengths among the input data of the six basic data lengths input in order up to the previous one are “11”. 01 11 ”, and the first state to be transitioned to when the 17PP code for the input data next to the input data of the three basic data lengths is“ 010 ”. The second state that is shifted when the input data of the first four basic data lengths among the six basic data length input data is “00 00 00 00” or “00 00 10 00”, 1 The third state that is shifted when the first two basic data length input data among the six basic data length input data input in order before is “00 00”. The fourth state that is shifted when the input data of the first basic data length among the input data of the six basic data lengths input in order is “00”, the basic code length of the previous three bits The fifth state that is changed when the last bit of the 17PP code is 0, and the sixth state that is changed when the last bit of the 17PP code having the basic code length of 3 bits immediately before is 1 Each of the first to sixth states in which a correspondence relationship between input data having six basic data lengths and a 17PP code having one basic code length is defined. For the state and the sixth state The fourth state has priority, the third state has priority over the fourth state, the second state has priority over the third state, and the second state A state machine that makes a state transition so that the first state is prioritized, and in the fourth to sixth states, the first two basics among the six basic data length input data When the input data of the data length is “00 00”, or when the input data of the first basic data length of the six basic data length input data is “00”, the input data is “00 00” Alternatively, when the input data of “00” is the end of the frame, the input data of “00 00” or the 17PP code different from the 17PP code when the input data of “00” is not the end of the frame is 6 One group A step of encoding the input data into a 17PP code based on the six basic data length input data and the termination signal, which are configured in order as the state machine defined for the input data of the data length (for example, Step S19) of FIG. 11 is included.

  Hereinafter, as an embodiment of the present invention, a recording apparatus that performs 17PP encoding will be described.

  FIG. 3 is a block diagram showing an embodiment of the recording apparatus 1 to which the present invention is applied.

  As shown in FIG. 3, the recording apparatus 1 includes a frame counter 11, a frame sync pattern determination unit 12, a delay circuit 13, a delay circuit 14, a delay circuit 15, a delay circuit 16, a delay circuit 17, a data encoding unit 18, And a code string output unit 19.

  The recording apparatus 1 receives 2-bit data per clock. Since one frame of data is 644 clocks, the data input as one frame is 1288 bits.

  The frame counter 11 receives inputs of Frame Sync and RUB (Recording Unit Block) Sync. Frame Sync is a signal input at the same time as the data string at the head of the frame every 644 clocks, that is, every frame. RUB Sync is 1-bit data input from a port different from Frame Sync, and is input simultaneously with Frame Sync every 31 frames. In other words, RUB Sync is a signal that identifies a frame that has frame number 0. Also, RUB Sync may be input every 31 × n (n is a natural number) frames.

  The frame counter 11 counts the number of input frames. The frame counter 11 calculates the frame number of the current frame based on the number of frames counted from the frame having the frame number 0 identified by RUB Sync, and supplies the frame number to the frame sync pattern determination unit 12.

  Further, the frame counter 11 generates a state machine initialization signal that is a signal for initializing the state of a state machine constituting the data encoding unit 18 described later, based on Frame Sync supplied for each frame. To do. Further, the frame counter 11 generates initial state information, which is information for determining the first state in the state machine, according to the frame number. Further, the frame counter 11 receives the input bit at the end from the time five clocks later from the time when the input bit at the end of the frame in the data string is input based on Frame Sync supplied for each frame. Until this time, a termination flag which is a signal indicating the end of the frame is generated. The frame counter 11 supplies the generated state machine initialization signal, initial state information, and termination flag to the data encoding unit 18.

  The end flag indicating the end of the frame continues in the period in which the input bits for 5 clocks at the end of the frame of the data string are input to the data encoding unit 18. 18 is input.

  The frame sync pattern determination unit 12 has the frame sync pattern determination table shown in FIG. 1 and determines a frame sync pattern based on the frame number supplied from the frame counter 11. The frame sync pattern determination unit 12 supplies the 30-bit frame sync pattern determined according to the frame sync pattern determination table to the code string output unit 19 over 3 clocks per 10 clocks.

  The frame sync pattern determination unit 12 generates a selector signal after supplying the frame sync pattern to the code string output unit 19 and supplies the selector signal to the code string output unit 19. Here, the selector signal is a signal for setting the first 10 clocks out of 644 clocks for each frame as a frame sync pattern and the remaining 634 clocks as a data portion that is encoded data. is there. That is, the boundary between the frame sync pattern and the encoded data in one frame is determined in the code string output unit 19 by the selector signal.

  The delay circuit 13 delays a data string input by 2 bits from an external device (not shown) by 1 clock every 2 bits, and supplies the data to the delay circuit 14 and the data encoding unit 18.

  The delay circuit 14 further delays the input data string by one clock every two bits.

  That is, the delay circuit 14 further delays the 1-clock delayed 2-bit data supplied from the delay circuit 13 by one clock and supplies the delayed data to the delay circuit 15 and the data encoding unit 18.

  The delay circuit 15 further delays the input data string by one clock every two bits.

  That is, the delay circuit 15 further delays the 2-bit data delayed by two clocks supplied from the delay circuit 14 by one clock and supplies the delayed data to the delay circuit 16 and the data encoding unit 18.

  The delay circuit 16 further delays the input data string by one clock every two bits.

  That is, the delay circuit 16 further delays the 3-bit delayed 2-bit data supplied from the delay circuit 15 by one clock and supplies the delayed data to the delay circuit 17 and the data encoding unit 18.

  The delay circuit 17 further delays the input data string by one clock every two bits.

  That is, the delay circuit 17 further delays the 4-bit delayed 2-bit data supplied from the delay circuit 16 by one clock and supplies the delayed data to the data encoding unit 18.

  That is, with reference to a data string input from an external device (not shown), 2-bit input data I5 without delay, 2-bit input data I4 delayed by one clock output from the delay circuit 13, and the delay circuit 14 2 bits of input data I3 delayed by 2 clocks output by 2, 2 bits of input data I2 delayed by 3 clocks output by the delay circuit 15, 2 bits of 2 bits delayed by 4 clocks output by the delay circuit 16 12-bit data for 6 clocks consisting of input data I1 and 2-bit input data I0 delayed by 5 clocks output from the delay circuit 17 are supplied to the data encoding unit 18 simultaneously.

  The data encoding unit 18 is configured by a state machine to be described later. The state machine constituting the data encoding unit 18 is initialized by the state machine initialization signal supplied from the frame counter 11. Further, the initial state (initial state) of the state machine constituting the data encoding unit 18 is determined by the initial state information supplied from the frame counter 11.

  The data encoding unit 18 accepts simultaneous input of input data I0 to I5 for 6 clocks supplied from an external device and the delay circuits 13 to 17. The data encoding unit 18, which is a state machine, encodes the input data I0 to I5 and outputs 3-bit encoded data O for the input data I0 to I5 every clock. The data encoding unit 18 supplies encoded data O of 3 bits per clock to the code string output unit 19.

  Further, the data encoding unit 18 performs, based on the termination flag supplied from the frame counter 11, for any one of the input data I0 to I4 that is the last two bits of one frame of the data string. End information indicating the end of the frame is added. The termination information is added to any one of the input data I0 to I4, which is the last two bits of the frame, by a termination flag that is continuous for five clocks in the data encoding unit 18.

  In addition, the data encoding unit 18 supplies a termination process confirmation bit T to the code string output unit 19. The termination processing confirmation bit T is a signal indicating whether or not the frame to be encoded has been terminated by termination processing, and is “1” when the termination of the frame is a termination pattern for termination processing, and is not a termination pattern. “0”.

  The code string output unit 19 generates a 17PP code based on the frame sync pattern and selector signal supplied from the frame sync pattern determination unit 12 and the encoded data O and the termination processing confirmation bit T supplied from the data encoding unit 18. Output a column.

  More specifically, the code string output unit 19 generates a frame sync pattern at the first 10 clocks of the 644 clock frame period from the bit string formed of the supplied frame sync pattern and encoded data O by a selector signal. The encoded data O constituting the data portion is selected in the remaining 634 clocks. Further, the code string output unit 19 holds a termination processing confirmation bit T of the previous frame and, based on the termination processing confirmation bit T of the previous frame, the first Sync-body of the frame sync pattern output in the current frame 1 bit is determined.

  Since the output 17PP code string is 3 bits per clock, it is 1932 bits per frame.

  Next, a state machine constituting the data encoding unit 18 will be described.

  FIG. 4 is a diagram for explaining the state machine constituting the data encoding unit 18.

  As shown in FIG. 4, the state machine has six states, state 0 to state 5.

  State 0 is a state when the last bit of the 3 output bits one clock before is 0. For example, when the last bit of Sync-ID in the frame sync pattern determination table of FIG. 1 is 0, that is, when the frame state in the frame sync pattern determination table of FIG. 1 is FS1, FS2, FS4, or FS6, The initial state is state 0.

  A state machine that is in state 0 transitions to state 1, state 2, or state 5 in one clock, or remains in state 0.

  State 1 is a state in which the last bit of the 3 output bits one clock before is 1. For example, when the last bit of Sync-ID in the frame sync pattern determination table of FIG. 1 is 1, that is, when the frame state in the frame sync pattern determination table of FIG. 1 is FS0, FS3, or FS5, the initial state Becomes state 1.

  The state machine that is state 1 transitions to state 0, state 2, or state 5 in one clock, or remains in state 1.

  In the state machine constituting the data encoding unit 18, whether the initial state is the state 0 or the state 1 is determined by the initial state information supplied from the frame counter 11.

  State 2 is a state for processing input data “00...”. That is, as input data, “00 01” (that is, input data I0 that is “00” and input data I1 that is “01”) and “00 10” (that is, “00” shown in the encoding table of FIG. ”Input data I0 and“ 10 ”input data I1) and“ 00 11 ”(that is,“ 00 ”input data I0 and“ 11 ”input data I1) are input. The state transitions to state 2.

  The state machine in state 2 transitions to either state 0 or state 3 in one clock.

  State 3 is a state for processing input data “00 00...”. That is, as input data, “00 00 00” shown in the encoding table of FIG. 2 (that is, input data I0 that is “00”, input data I1 that is “00”, and input data I2 that is “00”). , “00 00 01” (that is, input data I0 that is “00”, input data I1 that is “00”, and input data I2 that is “01”), “00 00 10” (that is, “00”) Input data I0 and input data I1 being “00” and input data I2 being “10”), and “00 00 11” (that is, input data I0 being “00” and input data I1 being “00”) If any of the input data I2) that is “11” is input, the state transitions to state 3.

  The state machine in state 3 transitions to either state 0 or state 4 in one clock.

  State 4 is a state for processing input data of “00 00 00 00” or “00 00 10 00”. That is, as input data, “00 00 00 00” (that is, input data I0 that is “00”, input data I1 that is “00”, and input data I2 that is “00” are shown in the encoding table of FIG. And "00" input data I3), or "00 00 10 00" (that is, "00" input data I0, "00" input data I1 and "10" input data I2 and "00"). Is input data I3), the state transitions to state 4.

  The state machine in state 4 transitions to state 0 in one clock.

  State 5 is a state for special processing. That is, “11 01 11” (that is, input data I0 being “11”, input data I1 being “01”, and input data I2 being “11”) shown in the encoding table of FIG. 2 is input. If so, the state transitions to state 5.

  A state machine that is in state 5 transitions to state 0 in one clock or remains in state 5.

  With this configuration, the state machine outputs encoded data according to a conversion table that converts input data determined in each of states 0 to 5 into encoded data according to input data for each clock. The state at the next clock can be determined.

  5 to 10 are diagrams showing the configuration of the conversion table in the state 0 to the state 5 of the state machine.

  In the state conversion tables shown in FIGS. 5 to 10, I0 to I5 are input data I0 to I5 input from an external device and the delay circuit 13 to the delay circuit 17, respectively divided into two bits. Data I5 is shown. Among the input data I0 to I5, the input data I0 is input to the recording device 1 earliest in time, and in the data string, the input data I0, input data I1, input data I2, input data I3, input data I4, input data Arranged in the order of I5. 5 to 10, any one of the input data I0 to I4 to which “t” is attached is one in which termination information is added by the data encoding unit 18. Which of the input data I0 to the input data I4 is added with termination information is determined based on a termination flag generated from Frame-sync indicating the head of the frame supplied from the frame counter 11.

  5 to 10, O indicates 3-bit encoded data output for each clock. 5 to 10, T indicates a termination process confirmation bit. The termination process confirmation bit T is “1” when the end of the frame is a termination pattern, and “0” when the frame is not a termination pattern. Further, based on the termination process confirmation bit T, the first 1 bit in the sync-body of the frame sync pattern is determined.

  5 to 10, to indicates a state transition destination, that is, any one of the states 0 to 5 in the next clock.

  In the input data I0 to I5 in FIGS. 5 to 10, the blank indicates that any data may be used. In addition, in the input data I0 to I5, the data (bit) represented by “*” may be any value of 0 or 1. In the state transition destination to, the value represented by “X” is It indicates that any value of 0 to 5 is acceptable.

  Thus, in the conversion table in states 0 to 5 of the state machine, the encoded data O, the state transition destination to, and the termination process confirmation bit T corresponding to the input data I0 to I5 are defined.

  In the following description, for example, “ab” (a and b are 0 or 1 respectively) is input as input data I0 and “cd” (c and d are 0 respectively) as input data I1 at a predetermined clock. Or 1) is input, "ef" (e and f are each 0 or 1) is input as input data I2, and "gh" (g and h are 0 or 1 respectively) is input and input. It is assumed that “ij” (i and j are 0 or 1 respectively) is input as the data I4 and “km” (k and m are 0 or 1 respectively) is input as the input data I5 (I0, I1, I2 , I3, I4, I5) = (ab cd ef gh ij km).

  In the following description, “*” indicates that any value of 0 or 1 may be used. Furthermore, t indicates that termination information is added.

  First, details of the conversion in state 0 will be described.

  According to the state 0 conversion table shown in FIG. 5, (I0, I1, I2, I3, I4, I5) = (11t ** ** ** ** **) is a data encoding unit at a predetermined clock. 18, “101” is output as encoded data O from the data encoding unit 18. In addition, since the input data is only the data at the end of the frame, that is, the input of data for one frame is completed, the transition destination state is “X”. That is, in the next clock, the data of the next frame is input and the state is initialized, so that the state may be changed to any state. Further, since it is not a termination process, a termination process confirmation bit T of “0” is output.

  Actually, since there is no data after the end of the frame, “*” after “t” indicating the end of the data indicates that nothing is input.

  When the input data at a predetermined clock is (I0, I1, I2, I3, I4, I5) = (11 01t ** ** ** **), “101” is output as the encoded data O, and the state Transitions to state 1. Further, since it is not a termination process, “0” is output as the termination process confirmation bit T.

  When the input data in a predetermined clock is (I0, I1, I2, I3, I4, I5) = (11 01 11t ** ** **), “101” is output as the encoded data O, and the state is Transition to state 1. Further, since it is not a termination process, “0” is output as the termination process confirmation bit T.

  When input data at a predetermined clock is (I0, I1, I2, I3, I4, I5) = (11 01 11 00t **), “101” is output as encoded data O, and the state is the state Transition to 1. Further, since it is not a termination process, “0” is output as the termination process confirmation bit T.

  When the input data in a predetermined clock is (I0, I1, I2, I3, I4, I5) = (11 01 11t 00 00t **), “001” is output as the encoded data O, and the state is state 5 Transition to. Further, since it is not a termination process, “0” is output as the termination process confirmation bit T.

  When the input data in a predetermined clock is (I0, I1, I2, I3, I4, I5) = (11 01 11 00 00 0 *), “001” is output as the encoded data O, and the state is state 5 Transition to. Further, since it is not a termination process, “0” is output as the termination process confirmation bit T.

  When input data at a predetermined clock is (I0, I1, I2, I3, I4, I5) = (11 01 11 00 1 **), “001” is output as encoded data O, and the state is the state Transition to 5. Further, since it is not a termination process, “0” is output as the termination process confirmation bit T.

  When the input data in a predetermined clock is (I0, I1, I2, I3, I4, I5) = (11 01 11 01 ** **), “001” is output as the encoded data O, and the state is the state Transition to 5. Further, since it is not a termination process, “0” is output as the termination process confirmation bit T.

  When the input data at the predetermined clock is (I0, I1, I2, I3, I4, I5) = (11 ** ** ** ** **), “101” is output as the encoded data O, The state transitions to state 1. Further, since it is not a termination process, “0” is output as the termination process confirmation bit T.

  When the input data at a predetermined clock is (I0, I1, I2, I3, I4, I5) = (10 ** ** ** ** **), “001” is output as the encoded data O, The state transitions to state 1. Further, since it is not a termination process, “0” is output as the termination process confirmation bit T.

  When the input data at a predetermined clock is (I0, I1, I2, I3, I4, I5) = (01 ** ** ** ** **), “010” is output as encoded data O, The state transitions to state 0. Further, since it is not a termination process, “0” is output as the termination process confirmation bit T.

  When the input data at the predetermined clock is (I0, I1, I2, I3, I4, I5) = (00t ** ** ** ** **), “000” is output as the encoded data O. . Further, since the input data is only the data at the end of the frame, the transition destination state is “X”, and the transition may be made to any state. Further, “1” is output as a termination process confirmation bit T indicating termination process.

  When the input data at the predetermined clock is (I0, I1, I2, I3, I4, I5) = (00 00t ** ** ** **), “010” is output as the encoded data O, and the state Transitions to state 2. Further, since it is not a termination process, “0” is output as the termination process confirmation bit T.

  When the input data in a predetermined clock is (I0, I1, I2, I3, I4, I5) = (00 00 0 ** ** ** **), “010” is output as the encoded data O, and the state Transitions to state 2. Further, since it is not a termination process, “0” is output as the termination process confirmation bit T.

  When the input data at a predetermined clock is (I0, I1, I2, I3, I4, I5) = (00 00 1 * ** ** **), “000” is output as the encoded data O, and the state Transitions to state 2. Further, since it is not a termination process, “0” is output as the termination process confirmation bit T.

  When input data at a predetermined clock is (I0, I1, I2, I3, I4, I5) = (00 01 ** ** ** **), “000” is output as encoded data O, and the state Transitions to state 2. Further, since it is not a termination process, “0” is output as the termination process confirmation bit T.

  When input data at a predetermined clock is (I0, I1, I2, I3, I4, I5) = (00 1 * ** ** ** **), “010” is output as encoded data O, The state transitions to state 2. Further, since it is not a termination process, “0” is output as the termination process confirmation bit T.

  Next, details of the conversion in state 1 will be described.

  According to the state 1 conversion table shown in FIG. 6, the input data at a predetermined clock is (I0, I1, I2, I3, I4, I5) = (11t *** ** *** ** **). At this time, “000” is output as the encoded data O. Further, since the input data is only the data at the end of the frame, the transition destination state is “X”, and the transition may be made to any state. Further, since it is not a termination process, “0” is output as the termination process confirmation bit T.

  When input data at a predetermined clock is (I0, I1, I2, I3, I4, I5) = (11 01t ** ** ** **), “000” is output as encoded data O, and the state Transitions to state 0. Further, since it is not a termination process, “0” is output as the termination process confirmation bit T.

  When input data at a predetermined clock is (I0, I1, I2, I3, I4, I5) = (11 01 11t ** ** **), “000” is output as encoded data O, and the state is Transition to state 0. Further, since it is not a termination process, “0” is output as the termination process confirmation bit T.

  When input data at a predetermined clock is (I0, I1, I2, I3, I4, I5) = (11 01 11 00t **), “000” is output as the encoded data O, and the state is the state Transition to 0. Further, since it is not a termination process, “0” is output as the termination process confirmation bit T.

  When the input data at the predetermined clock is (I0, I1, I2, I3, I4, I5) = (11 01 11 00 00t **), “001” is output as the encoded data O, and the state is state 5 Transition to. Further, since it is not a termination process, “0” is output as the termination process confirmation bit T.

  When the input data in a predetermined clock is (I0, I1, I2, I3, I4, I5) = (11 01 11 00 00 0 *), “001” is output as the encoded data O, and the state is state 5 Transition to. Further, since it is not a termination process, “0” is output as the termination process confirmation bit T.

  When input data at a predetermined clock is (I0, I1, I2, I3, I4, I5) = (11 01 11 00 1 **), “001” is output as encoded data O, and the state is the state Transition to 5. Further, since it is not a termination process, “0” is output as the termination process confirmation bit T.

  When the input data in a predetermined clock is (I0, I1, I2, I3, I4, I5) = (11 01 11 01 ** **), “001” is output as the encoded data O, and the state is the state Transition to 5. Further, since it is not a termination process, “0” is output as the termination process confirmation bit T.

  When the input data in a predetermined clock is (I0, I1, I2, I3, I4, I5) = (11 ** ** ** ** **), “000” is output as the encoded data O, The state transitions to state 0. Further, since it is not a termination process, “0” is output as the termination process confirmation bit T.

  When the input data at a predetermined clock is (I0, I1, I2, I3, I4, I5) = (10 ** ** ** ** **), “001” is output as the encoded data O, The state transitions to state 1. Further, since it is not a termination process, “0” is output as the termination process confirmation bit T.

  When the input data at a predetermined clock is (I0, I1, I2, I3, I4, I5) = (01 ** ** ** ** **), “010” is output as encoded data O, The state transitions to state 0. Further, since it is not a termination process, “0” is output as the termination process confirmation bit T.

  When the input data at the predetermined clock is (I0, I1, I2, I3, I4, I5) = (00t ** ** ** ** **), “000” is output as the encoded data O. . Further, since the input data is only the data at the end of the frame, the transition destination state is “X”, and the transition may be made to any state. Further, “1” is output as a termination process confirmation bit T indicating termination process.

  When the input data at the predetermined clock is (I0, I1, I2, I3, I4, I5) = (00 00t ** ** ** **), “010” is output as the encoded data O, and the state Transitions to state 2. Further, since it is not a termination process, “0” is output as the termination process confirmation bit T.

  When the input data in a predetermined clock is (I0, I1, I2, I3, I4, I5) = (00 00 0 ** ** ** **), “010” is output as the encoded data O, and the state Transitions to state 2. Further, since it is not a termination process, “0” is output as the termination process confirmation bit T.

  When the input data at a predetermined clock is (I0, I1, I2, I3, I4, I5) = (00 00 1 * ** ** **), “000” is output as the encoded data O, and the state Transitions to state 2. Further, since it is not a termination process, “0” is output as the termination process confirmation bit T.

  When input data at a predetermined clock is (I0, I1, I2, I3, I4, I5) = (00 01 ** ** ** **), “000” is output as encoded data O, and the state Transitions to state 2. Further, since it is not a termination process, “0” is output as the termination process confirmation bit T.

  When input data at a predetermined clock is (I0, I1, I2, I3, I4, I5) = (00 1 * ** ** ** **), “010” is output as encoded data O, The state transitions to state 2. Further, since it is not a termination process, “0” is output as the termination process confirmation bit T.

  Next, details of the conversion in state 2 will be described.

  According to the state 2 conversion table shown in FIG. 7, the input data at a predetermined clock is (I0, I1, I2, I3, I4, I5) = (00t *** ** *** ** **). At this time, “100” is output as the encoded data O. Further, since the input data is only the data at the end of the frame, the transition destination state is “X”, and the transition may be made to any state. Further, “1” is output as a termination process confirmation bit T indicating termination process.

  When input data at a predetermined clock is (I0, I1, I2, I3, I4, I5) = (00 ** ** ** ** **), “100” is output as encoded data O, The state transitions to state 3. Further, since it is not a termination process, “0” is output as the termination process confirmation bit T.

  When input data at a predetermined clock is (I0, I1, I2, I3, I4, I5) = (01 ** ** ** ** **), “100” is output as encoded data O, The state transitions to state 0. Further, since it is not a termination process, “0” is output as the termination process confirmation bit T.

  When input data at a predetermined clock is (I0, I1, I2, I3, I4, I5) = (10 ** ** ** ** **), “000” is output as encoded data O, The state transitions to state 0. Further, since it is not a termination process, “0” is output as the termination process confirmation bit T.

  When input data at a predetermined clock is (I0, I1, I2, I3, I4, I5) = (11 ** ** ** ** **), “100” is output as encoded data O, The state transitions to state 0. Further, since it is not a termination process, “0” is output as the termination process confirmation bit T.

  Next, details of the conversion in state 3 will be described.

  According to the state 3 conversion table shown in FIG. 8, the input data at a predetermined clock is (I0, I1, I2, I3, I4, I5) = (00t *** ** *** ** **). At this time, “000” is output as the encoded data O. Further, since the input data is only the data at the end of the frame, the transition destination state is “X”, and the transition may be made to any state. Further, since it is not a termination process, “0” is output as the termination process confirmation bit T.

  When the input data at the predetermined clock is (I0, I1, I2, I3, I4, I5) = (00 00 ** ** ** **), “100” is output as the encoded data O, and the state Transitions to state 4. Further, since it is not a termination process, “0” is output as the termination process confirmation bit T.

  When input data at a predetermined clock is (I0, I1, I2, I3, I4, I5) = (00 ** ** ** ** **), “000” is output as encoded data O, The state transitions to state 0. Further, since it is not a termination process, “0” is output as the termination process confirmation bit T.

  When input data at a predetermined clock is (I0, I1, I2, I3, I4, I5) = (01 ** ** ** ** **), “100” is output as encoded data O, The state transitions to state 0. Further, since it is not a termination process, “0” is output as the termination process confirmation bit T.

  When input data at a predetermined clock is (I0, I1, I2, I3, I4, I5) = (10t ** ** ** ** **), “000” is output as encoded data O. . Further, since the input data is only the data at the end of the frame, the transition destination state is “X”, and the transition may be made to any state. Further, since it is not a termination process, “0” is output as the termination process confirmation bit T.

  When the input data at a predetermined clock is (I0, I1, I2, I3, I4, I5) = (1 00 ** ** ** ** **), “100” is output as encoded data O, and the state Transitions to state 4. Further, since it is not a termination process, “0” is output as the termination process confirmation bit T.

  When input data at a predetermined clock is (I0, I1, I2, I3, I4, I5) = (10 ** ** ** ** **), “000” is output as encoded data O, The state transitions to state 0. Further, since it is not a termination process, “0” is output as the termination process confirmation bit T.

  When input data at a predetermined clock is (I0, I1, I2, I3, I4, I5) = (11 ** ** ** ** **), “100” is output as encoded data O, The state transitions to state 0. Further, since it is not a termination process, “0” is output as the termination process confirmation bit T.

  Next, details of the conversion in state 4 will be described.

  According to the state 4 conversion table shown in FIG. 9, the input data at a predetermined clock is (I0, I1, I2, I3, I4, I5) = (00t *** ** *** ** **). At this time, “100” is output as the encoded data O. Further, since the input data is only the data at the end of the frame, the transition destination state is “X”, and the transition may be made to any state. Further, since it is not a termination process, “0” is output as the termination process confirmation bit T.

  When input data at a predetermined clock is (I0, I1, I2, I3, I4, I5) = (00 ** ** ** ** **), “100” is output as encoded data O, The state transitions to state 0. Further, since it is not a termination process, “0” is output as the termination process confirmation bit T.

  Next, details of the conversion in state 5 will be described.

  According to the conversion table of state 5 shown in FIG. 10, the input data at a predetermined clock is (I0, I1, I2, I3, I4, I5) = (01 *************) At this time, “000” is output as the encoded data O, and the state 5 is transited. Further, since it is not a termination process, “0” is output as the termination process confirmation bit T.

  When the input data in a predetermined clock is (I0, I1, I2, I3, I4, I5) = (11 ** ** ** ** **), “000” is output as the encoded data O, The state transitions to state 0. Further, since it is not a termination process, “0” is output as the termination process confirmation bit T.

  As described above, the state machine constituting the data encoding unit 18 changes the state for each clock and outputs the encoded data according to the conversion table defined for each state.

  FIG. 11 is a flowchart for explaining the 17PP code encoding process in the recording apparatus 1.

  The recording apparatus 1 starts encoding processing when the first bit in a predetermined frame is input from an external device.

  In step S11, the frame counter 11 receives input of Frame Sync and RUB Sync.

  In step S12, the frame counter 11 calculates a frame number. More specifically, the frame counter 11 calculates the frame number of the current frame based on the number of frames counted from the frame of frame number 0 specified by RUB Sync, and supplies the frame number to the frame sync pattern determination unit 12. .

  In step S13, the frame counter 11 generates a state machine initialization signal, initial state information, and a termination flag. The frame counter 11 supplies the generated state machine initialization signal, initial state information, and termination flag to the data encoding unit 18.

  In step S14, the frame sync pattern determination unit 12 determines a frame sync pattern based on the frame number supplied from the frame counter 11 according to the frame sync pattern determination table. The frame sync pattern determination unit 12 supplies the 30-bit frame sync pattern determined according to the frame sync pattern determination table to the code string output unit 19 over 3 clocks per 10 clocks.

  In step S15, the frame sync pattern determination unit 12 generates a selector signal. The frame sync pattern determination unit 12 supplies the generated selector signal to the code string output unit 19.

  In step S <b> 16, the data encoding unit 18 initializes the state machine (as itself) by the state machine initialization signal supplied from the frame counter 11.

  In step S <b> 17, the data encoding unit 18 determines an initial state based on the initial state information supplied from the frame counter 11. The initial state is determined according to the frame number according to the frame sync pattern determination table.

  In step S18, the data encoding unit 18 receives input of input data. More specifically, the data encoding unit 18 receives input of input data I0 to I5 for 6 clocks supplied from an external device and the delay circuit 13 to the delay circuit 17 by 2 bits per clock.

  In step S19, the data encoding unit 18 performs an encoding process. More specifically, the data encoding unit 18 as a state machine encodes the input data I0 to I5. The data encoding unit 18 supplies the encoded data O obtained by encoding and the termination process confirmation bit T to the code string output unit 19.

  Here, the details of the encoding process corresponding to step S19 will be described with reference to the flowchart of FIG.

  In step S31, the data encoding unit 18 changes the state of the state machine to the initial state according to the initial state information supplied from the frame counter 11.

  That is, the state of the data encoding unit 18 as a state machine transitions to the initial state.

  In step S32, the data encoding unit 18 outputs the encoded data O corresponding to the input data I0 to I5 and the termination process confirmation bit T which is “0” according to the conversion table in the state.

  In step S33, the data encoding unit 18 shifts the state of the state machine to the next state according to the transition destination of the conversion table in the state.

  That is, the state of the data encoding unit 18 as a state machine transitions to the next state according to the transition destination of the conversion table in that state.

  In step S34, the data encoding unit 18 determines whether or not termination information is added to the input data I0. That is, the data encoding unit 18 determines whether or not the input data I0 is data at the end of the frame in the transitioned state.

  In step S34, if the data encoding unit 18 determines that the termination information is not added to the input data I0, that is, if the input data I0 is not the data at the end of the frame in the transitioned state, the process proceeds to step S32. Returning to step S32, steps S32 and S33 are repeated until it is determined that termination information is added to the input data I0.

  On the other hand, if the data encoding unit 18 determines in step S34 that termination information is added to the input data I0, that is, if the input data I0 is the data at the end of the frame in the transitioned state, the process Advances to step S35.

  In step S35, the data encoding unit 18 outputs the encoded data O corresponding to the input data I0 and the termination process confirmation bit T according to the conversion table in the state, and the process ends. At this time, if the input data I0 is “00”, the termination process confirmation bit T that is “1” is output, and if the input data I0 is other than “00”, the termination process confirmation that is “0”. Bit T is output.

  In this way, the data encoding unit 18 outputs the encoded data O and the termination process confirmation bit T according to the conversion table in each state by changing the state of the state machine.

  Here, a specific example of state machine processing for input data corresponding to each of basic processing, special processing, and termination processing will be described below.

  First, a case where “00 00 10 00 10 11” is input as input data for basic processing will be described. Note that the initial state information at this time indicates state 1.

  “00 00 10 00 10 11” is data for 6 clocks, and input data in the first clock is (I0, I1, I2, I3, I4, I5) = (00 00 10 00 10 11). At this time, the state in the state machine is state 1. According to the state 1 conversion table shown in FIG. 6, “000” is output as encoded data O, and the state transitions to state 2. Further, since it is not a termination process, “0” is output as the termination process confirmation bit T.

  The input data in the next clock is (I0, I1, I2, I3, I4, I5) = (00 10 00 10 11 **). Since the state at this time is state 2, state 2 shown in FIG. According to this conversion table, “100” is output as the encoded data O, and the state transitions to state 3. Further, since it is not a termination process, “0” is output as the termination process confirmation bit T.

  The input data in the next clock is (I0, I1, I2, I3, I4, I5) = (10 00 10 11 ** **). Since the state at this time is state 3, the state shown in FIG. According to the conversion table 3, “100” is output as the encoded data O, and the state transitions to the state 4. Further, since it is not a termination process, “0” is output as the termination process confirmation bit T.

  The input data in the next clock is (I0, I1, I2, I3, I4, I5) = (00 10 11 ** ** **), and the state at this time is state 4, and is shown in FIG. According to the conversion table of state 4, “100” is output as encoded data O, and the state transitions to state 0. Further, since it is not a termination process, “0” is output as the termination process confirmation bit T.

  The input data at the next clock is (I0, I1, I2, I3, I4, I5) = (10 11 ** ** ** **), and the state at this time is state 0, so it is shown in FIG. According to the state 0 conversion table, “001” is output as the encoded data O, and the state transitions to state 1. Further, since it is not a termination process, “0” is output as the termination process confirmation bit T.

  The input data at the next clock is (I0, I1, I2, I3, I4, I5) = (11 ** ** ** ** **). Since the state at this time is state 1, FIG. According to the state 1 conversion table shown, “000” is output as encoded data O, and the state transitions to state 0. Also, since it is not a termination process, “0” is output as the termination process confirmation bit T, and the conversion for the input “00 00 10 00 10 11” is completed.

  In this way, when “00 00 10 00 10 11” is input as input data for basic processing, the output of the data encoding unit 18 is “000 100 100 100 001 000”. It is obvious that the encoded data output in this way follows the encoding table shown in FIG.

  Next, a case where “00 10 11 01 11 01” is input as input data including special processing will be described. As shown in the encoding table of FIG. 2, when the input data is “11 01 11” and the output bit of the next clock is “010”, the conversion is treated as a special process. Note that the initial state information at this time indicates state 0.

  “00 10 11 01 11 01” is data for 6 clocks, and the input data in the first clock is (I0, I1, I2, I3, I4, I5) = (00 10 11 01 11 01). At this time, the state in the state machine is state 0. According to the conversion table of state 0 shown in FIG. 5, “010” is output as encoded data O, and the state transitions to state 2. Further, since it is not a termination process, “0” is output as the termination process confirmation bit T.

  The input data in the next clock is (I0, I1, I2, I3, I4, I5) = (10 11 01 11 01 **). Since the state at this time is state 2, state 2 shown in FIG. , “000” is output as encoded data O, and the state transitions to state 0. Further, since it is not a termination process, “0” is output as the termination process confirmation bit T.

  The input data in the next clock is (I0, I1, I2, I3, I4, I5) = (11 01 11 01 ** **). Since the state at this time is state 0, the state shown in FIG. According to the conversion table of 0, “001” is output as the encoded data O, and the state transitions to state 5. Further, since it is not a termination process, “0” is output as the termination process confirmation bit T.

  The input data in the next clock is (I0, I1, I2, I3, I4, I5) = (01 11 01 ** ** **). Since the state at this time is state 5, it is shown in FIG. According to the conversion table of state 5, “000” is output as encoded data O, and the state transitions to state 5. Further, since it is not a termination process, “0” is output as the termination process confirmation bit T.

  The input data at the next clock is (I0, I1, I2, I3, I4, I5) = (11 01 ** ** ** **). Since the state at this time is state 5, it is shown in FIG. According to the state 5 conversion table, “000” is output as the encoded data O, and the state transitions to state 0. Further, since it is not a termination process, “0” is output as the termination process confirmation bit T.

  The input data at the next clock is (I0, I1, I2, I3, I4, I5) = (01 ** ** ** ** **). Since the state at this time is state 0, FIG. According to the state 0 conversion table shown, “010” is output as encoded data O, and the state transitions to state 0. Also, since it is not a termination process, “0” is output as the termination process confirmation bit T, and the conversion for the input “00 10 11 01 11 01” is completed.

  In this way, when “00 10 11 01 11 01” is input as input data including special processing, the output of the data encoding unit 18 becomes “010 000 001 000 000 010”. It is obvious that the encoded data output in this way follows the encoding table shown in FIG.

  Next, a case where “00 10 11 00 00t” is input as input data including termination processing will be described. As shown in the encoding table of FIG. 2, when the input data is “00 00” and the end of the frame, the conversion is treated as a termination process. Note that the initial state information at this time indicates state 0.

  “00 10 11 00 00t” is data for 5 clocks, and the input data in the first clock is (I0, I1, I2, I3, I4, I5) = (00 10 11 00 00t **). At this time, the state in the state machine is state 0. According to the conversion table of state 0 shown in FIG. 5, “010” is output as encoded data O, and the state transitions to state 2. Further, since it is not a termination process, “0” is output as the termination process confirmation bit T.

  Note that “*” after “t” indicating the end of the frame indicates that nothing is input as described above.

  The input data at the next clock is (I0, I1, I2, I3, I4, I5) = (10 11 00 00t ** **). Since the state at this time is state 2, the state shown in FIG. According to the conversion table 2, “000” is output as the encoded data O, and the state transitions to state 0. Further, since it is not a termination process, “0” is output as the termination process confirmation bit T.

  The input data in the next clock is (I0, I1, I2, I3, I4, I5) = (11 00 00t ** ** **), and the state at this time is the state 0, and is shown in FIG. According to the conversion table of state 0, “101” is output as encoded data O, and the state transitions to state 1. Further, since it is not a termination process, “0” is output as the termination process confirmation bit T.

  The input data at the next clock is (I0, I1, I2, I3, I4, I5) = (00 00t ** ** ** **). Since the state at this time is state 1, it is shown in FIG. According to the state 1 conversion table, “010” is output as the encoded data O, and the state transitions to state 2. Further, since it is not a termination process, “0” is output as the termination process confirmation bit T.

  The input data at the next clock is (I0, I1, I2, I3, I4, I5) = (00t ** ** ** ** **), and the state at this time is state 2, so FIG. According to the state 2 conversion table shown, “100” is output as the encoded data O. Further, since the input data is only the data at the end of the frame, the transition destination state is “X”, and the transition may be made to any state. Furthermore, “1” is output as the termination processing confirmation bit T, and the conversion for the input “00 10 11 00 00t” is completed.

  In this way, when “00 10 11 00 00t” is input as input data including termination processing, the output of the data encoding unit 18 is “010 000 101 010 100”. It is obvious that the encoded data output in this way follows the encoding table shown in FIG.

  In this way, the input data is encoded into encoded data according to the encoding table shown in FIG. 2 by the state machine constituting the data encoding unit 18.

  Returning to the description of the flowchart of FIG. 11, in step S <b> 20, the code string output unit 19 outputs the frame sync pattern and selector signal supplied from the frame sync pattern determination unit 12 and the encoded data supplied from the data encoding unit 18. Based on O and the termination process confirmation bit T, a 17PP code string is output, and the process ends.

  In this way, the recording apparatus 1 can encode the 17PP code in consideration of the termination process by the state machine.

As described above, when the encoding table is used, the 17PP code can be encoded. In addition, it generates a termination signal indicating that the input data is the end of the frame,
The input data of the first three basic data lengths among the input data of the six basic data lengths input in order up to the previous one is “11 01 11”, and the input data of the three basic data lengths The first four basic data of the six basic data length input data sequentially input in the first state that is shifted when the 17PP code for the next input data is “010” The second state to be transitioned when the long input data is “00 00 00 00” or “00 00 10 00”. Among the input data of the six basic data lengths input in order up to the previous one The third state to be transitioned when the input data of the first two basic data lengths are “00 00”, the first basic of the input data of the six basic data lengths input in order up to the previous one De The fourth state to be transitioned when the input data of the data length is “00”, and the fifth state to be transitioned when the last bit of the 17PP code having the basic code length of the previous 3 bits is 0. And a sixth state that is transitioned when the last bit of the 17PP code having a basic code length of 3 bits immediately before is 1, each of which has six basic data length input data, Of the first to sixth states in which the correspondence with one basic code length 17PP code is defined, the fourth state has priority over the fifth and sixth states, State transition is performed such that the third state has priority over the state 4, the second state has priority over the third state, and the first state has priority over the second state. A state machine having six basic data lengths in the fourth to sixth states When the input data of the first two basic data lengths of the input data is “00 00”, or the input data of the first basic data length of the input data of the six basic data lengths is “00” In this case, when the input data “00 00” or the input data “00” is the end of the frame, the input data “00 00” or the input data “00” is not the end of the frame. The 17PP code, which is different from the code, is configured as a state machine defined for 6 basic data length input data, and the input data is based on the 6 basic data length input data and the termination signal input in order. In the case of encoding to 17PP code, the circuit scale can be further reduced.

  In the above, an embodiment in which the present invention is applied to a recording apparatus has been described. However, the present invention can be applied to an encoding apparatus that performs encoding of a 17PP code.

  The embodiments of the present invention are not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention.

It is a figure which shows the structure of the frame sync pattern determination table of a 17PP code. It is a figure which shows the structure of the encoding table of a 17PP code. 1 is a block diagram showing an embodiment of a recording apparatus 1 to which the present invention is applied. It is a figure explaining the state machine which comprises a data encoding part. It is a figure which shows the structure of the conversion table in the state 0 of a state machine. It is a figure which shows the structure of the conversion table in the state 1 of a state machine. It is a figure which shows the structure of the conversion table in the state 2 of a state machine. It is a figure which shows the structure of the conversion table in the state 3 of a state machine. It is a figure which shows the structure of the conversion table in the state 4 of a state machine. It is a figure which shows the structure of the conversion table in the state 5 of a state machine. It is a flowchart explaining the encoding process of a 17PP code. It is a flowchart explaining the detail of an encoding process.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Recording device, 11 Frame counter, 12 Frame sync pattern determination part, 13 thru | or 17 delay circuit, 18 Data encoding part, 19 Code sequence output part

Claims (6)

In an encoding device that converts input data having a basic data length of 2 bits into a 17PP (Parity Preserve / Prohibit Repeated Minimum Transition Runlength) code having a basic code length of 3 bits,
Generating means for generating an end signal indicating that the input data is the end of the frame;
The input data of the first three basic data lengths among the input data of the six basic data lengths input in order up to the previous one is “11 01 11”, and the input data of the three basic data lengths The first four basic data of the six basic data length input data sequentially input in the first state that is shifted when the 17PP code for the next input data is “010” The second state to be transitioned when the long input data is “00 00 00 00” or “00 00 10 00”. Among the input data of the six basic data lengths input in order up to the previous one The third state to be transitioned when the input data of the first two basic data lengths are “00 00”, the first basic of the input data of the six basic data lengths input in order up to the previous one De The fourth state to be transitioned when the input data of the data length is “00”, and the fifth state to be transitioned when the last bit of the 17PP code having the basic code length of the previous 3 bits is 0. And a sixth state that is transitioned when the last bit of the 17PP code having a basic code length of 3 bits immediately before is 1, each of which has six basic data length input data, Of the first to sixth states in which the correspondence with one basic code length 17PP code is defined, the fourth state has priority over the fifth and sixth states. The third state has priority over the fourth state, the second state has priority over the third state, and the first state has priority over the second state. As a priority, a state machine that makes a state transition, the fourth state In the sixth state, when the input data of the first two basic data lengths among the input data of the six basic data lengths is “00 00”, or the first of the input data of the six basic data lengths When the input data of the basic data length of “00” is “00”, the input data of “00 00” or the input data of “00” is the end of the frame, the input data of “00 00” or “ The 17PP code different from the 17PP code when the input data of “00” is not the end of the frame is configured as a state machine defined for the input data of the six basic data lengths, and the six basics input in order An encoding apparatus comprising: encoding means for encoding input data into a 17PP code based on input data having a data length and the termination signal. The encoding apparatus according to claim 1, wherein the correspondence relationship between the input data and the 17PP code is defined by a state table for each of the first to sixth states. In the state table, corresponding to the input data of six basic data lengths input in order, a 17PP code of one basic code length, a transition state from the first state to the sixth state, and 6 Information indicating whether or not the first two basic data length input data of the two basic data length input data is “00 00” or “00” and is the end of the frame The encoding device according to claim 2, wherein: The fifth state and the sixth state are initial states in which encoding of the input data is started,
2. The initial state is determined as to whether the fifth state or the sixth state is determined by the last bit of a synchronization signal pattern arranged before the code string in the frame. The encoding device described in 1. Based on the information indicating whether the input data of the first two basic data lengths among the input data of the six basic data lengths is “00 00” or “00” and the end of the frame, The encoding apparatus according to claim 4, wherein the first bit of the synchronization signal pattern in a frame is determined. In an encoding method for converting input data having a basic data length of 2 bits into a 17PP (Parity Preserve / Prohibit Repeated Minimum Transition Runlength) code having a basic code length of 3 bits,
Generate a termination signal indicating that the input data is the end of the frame,
The input data of the first three basic data lengths among the input data of the six basic data lengths input in order up to the previous one is “11 01 11”, and the input data of the three basic data lengths The first four basic data of the six basic data length input data sequentially input in the first state that is shifted when the 17PP code for the next input data is “010” The second state to be transitioned when the long input data is “00 00 00 00” or “00 00 10 00”. Among the input data of the six basic data lengths input in order up to the previous one The third state to be transitioned when the input data of the first two basic data lengths are “00 00”, the first basic of the input data of the six basic data lengths input in order up to the previous one De The fourth state to be transitioned when the input data of the data length is “00”, and the fifth state to be transitioned when the last bit of the 17PP code having the basic code length of the previous 3 bits is 0. And a sixth state that is transitioned when the last bit of the 17PP code having a basic code length of 3 bits immediately before is 1, each of which has six basic data length input data, Of the first to sixth states in which the correspondence with one basic code length 17PP code is defined, the fourth state has priority over the fifth and sixth states. The third state has priority over the fourth state, the second state has priority over the third state, and the first state has priority over the second state. As a priority, a state machine that makes a state transition, the fourth state In the sixth state, when the input data of the first two basic data lengths among the input data of the six basic data lengths is “00 00”, or the first of the input data of the six basic data lengths When the input data of the basic data length of “00” is “00”, the input data of “00 00” or the input data of “00” is the end of the frame, the input data of “00 00” or “ The 17PP code different from the 17PP code when the input data of “00” is not the end of the frame is configured as a state machine defined for the input data of the six basic data lengths, and the six basics input in order An encoding method including a step of encoding input data into a 17PP code based on input data having a data length and the termination signal.

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