JP2008124392A - Semiconductor device, manufacturing method thereof, and display device - Google Patents

Abstract

A semiconductor device having excellent on characteristics, off characteristics, and reliability, a manufacturing method thereof, and a display device are provided.
A gate electrode, a gate insulating layer, and a semiconductor layer are stacked in this order on an insulating substrate, and a source / drain electrode is electrically connected to the semiconductor layer through a contact layer. In the semiconductor device, the semiconductor layer includes, in order from the contact layer side, a low crystalline semiconductor layer in which an amorphous phase and a crystalline phase are mixed, and a high crystal having a larger crystallization ratio than the low crystalline semiconductor layer. The semiconductor device has a structure in which a conductive semiconductor layer is stacked.
[Selection] Figure 1

Description

The present invention relates to a semiconductor device, a manufacturing method thereof, and a display device. More specifically, the present invention relates to a semiconductor device suitable for a thin film transistor formed over an insulating substrate of a display device such as a liquid crystal display device or an organic electroluminescence display device, a manufacturing method thereof, and a display device.

A semiconductor device is an electronic device that includes an active element that utilizes electrical characteristics of a semiconductor, and is widely applied to, for example, audio equipment, communication equipment, computers, and home appliances. In particular, a semiconductor device including a three-terminal active element such as a thin film transistor (hereinafter also referred to as “TFT”) is an active matrix liquid crystal display device or an organic electroluminescence display device (hereinafter also referred to as “organic EL display device”). Etc.) are used in a wide range of fields as switching elements, control circuits, etc. in display devices.

FIG. 14 is a schematic cross-sectional view showing a conventional semiconductor device (TFT) in which the channel layer is made of amorphous (amorphous) silicon (a-Si). As shown in FIG. 14, in the semiconductor device 111, a gate electrode 2, a gate insulating film 3 made of a silicon nitride film (SiNx film), and an a-Si layer 4d as a channel layer are stacked on an insulating substrate 1. Has a structured. A source / drain electrode 6 is formed on the a-Si layer 4 d and the gate insulating film 3 other than the region facing the gate electrode 2. Further, between the a-Si layer 4d and the source / drain electrode 6, a contact layer 5 made of silicon (n ⁺ -Si) doped with phosphorus (P) or the like at a high concentration is interposed. Since such a semiconductor device 111 has a silicon nitride film as the gate insulating film 3, good interface characteristics are obtained and the S value is excellent. Further, since the a-Si layer 4d has a wide band gap, the leakage current (off current) can be reduced as compared with a TFT using crystalline silicon for the channel layer. Furthermore, since the interface between the contact layer 5 and the channel layer is also a-Si, a low leakage current is obtained. However, since the mobility of the a-Si layer 4d is only about 0.2 to 0.5 cm ² / Vs, the semiconductor device 111 has room for improvement in terms of improving on-characteristics.

On the other hand, a technique using microcrystalline silicon (μc-Si) for the channel layer is disclosed. FIG. 15 shows a conventional semiconductor device in which the channel layer is made of microcrystalline silicon (μc-Si).
It is a cross-sectional schematic diagram which shows TFT. The semiconductor device 112 has the same constituent elements as the semiconductor device 111 shown in FIG. 14, but the constituent material of the channel layer is different. Specifically, the channel layer is formed from the μc-Si layer 4e. Since the μc-Si layer 4e has a crystalline phase and its mobility is more than double that of the a-Si layer, the on-characteristics can be improved. However, since the μc-Si layer 4e has a number of defect levels in the film, the bonding interface characteristics with the contact layer 5 are deteriorated as compared with the a-Si layer. Further, the μc-Si layer 4e has a lower resistance than the a-Si layer and a narrow band gap, so that the off-current is large.

FIG. 16 shows a conventional semiconductor device (Si layer / gate insulating film (GI) = a-Si / SiNx) and another conventional semiconductor device (Si layer / gate insulating film (GI) = μc-Si / SiOx and Si). It is a graph which shows the Vgd (gate / drain voltage) -Ids (drain / source current) characteristic of a layer / gate insulating film (GI) = (micro | micron | mu) c-Si / SiNx). From FIG. 16, as described above, the semiconductor device 111 in which the channel layer is an a-Si layer was excellent in off characteristics and rising characteristics, but the on characteristics were poor. On the other hand, the semiconductor device 112 in which the channel layer is a μc-Si layer exhibited excellent on characteristics regardless of the material of the gate insulating film, but the off characteristics and the rising characteristics deteriorated.

On the other hand, the technique which interposes an a-Si layer between a crystalline silicon layer and a contact layer is disclosed (for example, refer patent documents 1-3). FIG. 17 is a schematic cross-sectional view showing a conventional semiconductor device (TFT) in which a semiconductor layer has a laminated structure of a μc-Si layer and an a-Si layer. The semiconductor device 113 has the same components as those of the semiconductor device 111 shown in FIG. 14, but the constituent materials of the semiconductor layers are different. Specifically, the semiconductor layer 4 has a structure in which a μc-Si layer 4e and an a-Si layer 4d are stacked from the gate insulating film 3 side. Since the a-Si layer 4d has a higher resistance and a wider band gap (μc-Si = 1.1 eV, a-Si = 1.7 eV) than the μc-Si layer 4e, the junction with the contact layer is a- The off-current can be reduced by using the Si layer 4d. Moreover, since the μc-Si layer 4e having excellent mobility can be used as the channel layer, the on-characteristics can be improved. However, the semiconductor device 113 still has room for improvement in the following points. That is, first, since the structures of the μc-Si layer 4e and the a-Si layer 4d are greatly different, a structural defect occurs at the interface. For this reason, the number of traps at the interface increases so much that the on-characteristics deteriorate (electron trap), the off-characteristics deteriorate (increased leakage current through the trap), and the reliability deteriorates (the TFT characteristic due to trapped charges). Change). Secondly, since the film stress is greatly different between the μc-Si layer and the a-Si layer, it causes film peeling. Further, due to this, the chemical solution may permeate into the semiconductor layer in the manufacturing process, and the manufacturing process is unstable.

Under such circumstances, as a technique for reducing leakage current, a stacked body of a first semiconductor film containing impurities, a thin film containing a crystalline phase, and at least one amorphous thin film not containing a crystalline phase is used. A semiconductor device having a configured second semiconductor film and in which the first semiconductor film and an amorphous thin film are joined is disclosed (for example, see Patent Document 4). Furthermore, Patent Document 4 discloses a technique for forming an amorphous thin film that does not include a crystal phase after the crystal phase gradually decreases after a microcrystalline film including a crystal phase is formed. . According to this document, the electrode interval in the semiconductor film deposition chamber is controlled to continuously change from the crystalline phase to the amorphous phase. However, even if the electrode spacing is controlled in the processing chamber, only the electric field strength can be controlled as the film formation parameter, and the most effective parameter for determining the film structure is the pressure and the flow rate of SiH ₄ and H _2. Therefore, it was impossible to obtain optimum film formation conditions for the crystalline phase and the amorphous phase, respectively. More specifically, even if the electric field strength is simply lowered due to the film formation conditions of the crystal phase, the gas phase reaction is halfway, the number of particles (dust) increases, the yield of non-defective products decreases, and the gas dissociation deteriorates to form a film. Only the downside, such as the slowdown, came out, and it was impossible to control the core crystal structure. Moreover, even if an amorphous film can be formed by reducing the electric field strength, the film density decreases and the structural defects in the film increase, and the film quality cannot be optimized. As a result, the defect density has increased, and all of the on-characteristics, off-characteristics, and reliability have deteriorated.
JP-A 62-295465 Japanese Patent Application Laid-Open No. 11-121761 JP 2001-217424 A JP 2005-322845 A

The present invention has been made in view of the above-described present situation, and an object of the present invention is to provide a semiconductor device having excellent on characteristics, off characteristics, and reliability, a manufacturing method thereof, and a display device.

The inventors of the present invention have studied various semiconductor devices having excellent on characteristics, off characteristics, and reliability, and have focused on the form of the semiconductor layer. Then, while suppressing a sudden structural change in the semiconductor layer, a low-crystallinity semiconductor layer having a high resistance is disposed on the contact layer side, and a crystallinity having a low resistance on the side away from the contact layer By disposing a semiconductor layer having a high resistance, the ON characteristics, the OFF characteristics, and the reliability are improved by reducing the structural change, the OFF characteristics are improved by the semiconductor layer having a high resistance, and the ON characteristics by the semiconductor layer having a low resistance are improved. The present inventors have found that the improvement can be achieved and have conceived that the above problems can be solved brilliantly, and have reached the present invention.

That is, the present invention includes a structure in which a gate electrode, a gate insulating layer, and a semiconductor layer are stacked in this order on an insulating substrate, and a structure in which a source / drain electrode is electrically connected to a semiconductor layer through a contact layer. The semiconductor layer has a low crystalline semiconductor layer in which an amorphous phase and a crystalline phase are mixed in order from the contact layer side, and a larger crystallization ratio than the low crystalline semiconductor layer. A semiconductor device having a structure in which a highly crystalline semiconductor layer is stacked (hereinafter also referred to as “first semiconductor device of the present invention”).

As described above, since the low crystalline semiconductor layer having a relatively high resistance value and a wide band gap is disposed at a position in contact with the contact layer, leakage current (off current) can be reduced, that is, off characteristics can be improved. It becomes. In addition, since the highly crystalline semiconductor layer contains a crystalline phase and has a higher mobility than the amorphous semiconductor layer, it can exhibit excellent on characteristics. In addition, since a low crystalline semiconductor has a lower resistance than an amorphous semiconductor, parasitic resistance can be reduced, and as a result, excellent on characteristics can be maintained. Furthermore, since the structural change between the low crystalline semiconductor and the highly crystalline semiconductor is smaller than the structural change between the amorphous semiconductor and the highly crystalline semiconductor, the low crystalline semiconductor layer and the highly crystalline semiconductor layer Generation of structural defects in the vicinity of the interface can be suppressed. Therefore, it is possible to suppress a decrease in on-characteristics, off-characteristics, and reliability due to traps at the interface, and it is possible to improve device characteristics.

In this specification, a contact layer is a layer that performs ohmic connection between a source / drain electrode and a semiconductor layer. The contact layer is usually configured to include a semiconductor layer doped with impurities.

In the first semiconductor device of the present invention, the difference in crystallization ratio between the high crystalline semiconductor layer and the low crystalline semiconductor layer is not particularly limited, but the high crystalline semiconductor layer is higher than the low crystalline semiconductor layer. Is preferably 15% or more, and more preferably 30% or more.

The present invention also includes a structure in which a gate electrode, a gate insulating layer, and a semiconductor layer are stacked in this order on an insulating substrate, and a structure in which a source / drain electrode is electrically connected to the semiconductor layer through a contact layer. The semiconductor layer includes a crystalline change semiconductor layer in which a crystallization rate changes in a thickness direction in order from a contact layer side, and a highly crystalline semiconductor having a crystallization rate higher than that of the crystalline change semiconductor layer The crystalline change semiconductor layer is a semiconductor device in which the crystallization rate continuously decreases from the highly crystalline semiconductor layer side to the contact layer side (hereinafter referred to as “second embodiment of the present invention”). It is also referred to as a “semiconductor device”.

As described above, since the crystalline change semiconductor layer having a relatively high resistance value and a wide band gap is disposed on the contact layer side at a position in contact with the contact layer, leakage current (off current) is reduced, that is, off characteristics. Can be improved. In addition, since the highly crystalline semiconductor layer contains a crystalline phase and has a higher mobility than the amorphous semiconductor layer, it can exhibit excellent on characteristics. Furthermore, since the crystalline semiconductor layer has a relatively large crystallization rate on the high crystalline semiconductor layer side, the occurrence of structural defects near the interface between the crystalline crystalline semiconductor layer and the highly crystalline semiconductor layer is suppressed. can do. Therefore, it is possible to suppress a decrease in on-characteristics, off-characteristics, and reliability due to traps at the interface, and it is possible to improve device characteristics.

Note that in this specification, a highly crystalline semiconductor layer having a crystallization rate equal to or higher than that of the crystalline change semiconductor layer means a highly crystalline semiconductor layer having a crystallization rate higher than that of the crystalline change semiconductor layer. More specifically, it means a highly crystalline semiconductor layer having a crystallization rate equal to or higher than the crystallization rate of the crystalline change semiconductor layer in the vicinity of the interface with the highly crystalline semiconductor layer.

The present invention also includes a structure in which a gate electrode, a gate insulating layer, and a semiconductor layer are stacked in this order on an insulating substrate, and a structure in which a source / drain electrode is electrically connected to the semiconductor layer through a contact layer. The semiconductor layer has an amorphous semiconductor layer, a low crystalline semiconductor layer in which an amorphous phase and a crystalline phase are mixed, and a low crystalline semiconductor layer in order from the contact layer side. It is also a semiconductor device having a structure in which a highly crystalline semiconductor layer having a high crystallization rate is stacked (hereinafter also referred to as “third semiconductor device of the present invention”).

As described above, since the amorphous semiconductor layer having a high resistance value and a wide band gap is disposed at a position in contact with the contact layer, more effective leakage current (off-state current) can be reduced, that is, more effective. The off characteristics can be improved. In addition, since the highly crystalline semiconductor layer contains a crystalline phase and has a higher mobility than the amorphous semiconductor layer, it can exhibit excellent on characteristics. Furthermore, the structural change between the low crystalline semiconductor and the high crystalline semiconductor and the structural change between the low crystalline semiconductor and the amorphous semiconductor are more than the structural change between the amorphous semiconductor and the high crystalline semiconductor. Therefore, the occurrence of structural defects near the interface in the semiconductor layer can be suppressed. Therefore, it is possible to suppress a decrease in on-characteristics, off-characteristics, and reliability due to traps at the interface, and it is possible to improve device characteristics. In addition, since the stress difference between the amorphous semiconductor layer and the crystalline semiconductor layer is relieved by the low crystalline semiconductor layer, the adhesion of the film is improved and the occurrence of film peeling can be suppressed. it can. Thus, the low crystalline semiconductor layer can function as a buffer layer.

Note that since the low crystalline semiconductor layer has low crystallinity, there is a concern that the defect density increases in manufacturing. Therefore, it is preferable that the layer be formed as thin as possible within the range having a function as a buffer layer. From such a viewpoint, the thickness of the low crystalline semiconductor layer is preferably 5 to 25 nm, and more preferably 5 to 10 nm. On the other hand, when the film thickness exceeds 25 nm, the defect density may increase remarkably, and when the film thickness is less than 5 nm, it may not function as a buffer layer.

In the third semiconductor device of the present invention, the difference in crystallization rate between the high crystalline semiconductor layer and the low crystalline semiconductor layer is not particularly limited, but the high crystalline semiconductor layer has a low crystallization rate. It is preferably 15% or more larger than the crystallization rate of the crystalline semiconductor layer, more preferably 30% or more.

The present invention also includes a structure in which a gate electrode, a gate insulating layer, and a semiconductor layer are stacked in this order on an insulating substrate, and a structure in which a source / drain electrode is electrically connected to the semiconductor layer through a contact layer. The semiconductor layer includes an amorphous semiconductor layer, a crystalline change semiconductor layer in which a crystallization rate changes in a thickness direction, and a crystallization higher than the crystalline change semiconductor layer in order from the contact layer side The crystalline change semiconductor layer is a semiconductor in which the crystallization rate continuously decreases from the high crystalline semiconductor layer side to the amorphous semiconductor layer side. It is also a device (hereinafter also referred to as “fourth semiconductor device of the present invention”).

As described above, since the amorphous semiconductor layer having a high resistance value and a wide band gap is disposed at a position in contact with the contact layer, more effective leakage current (off-state current) can be reduced, that is, more effective. The off characteristics can be improved. In addition, since the highly crystalline semiconductor layer contains a crystalline phase and has a higher mobility than the amorphous semiconductor layer, it can exhibit excellent on characteristics. Furthermore, since the crystalline change semiconductor layer has a relatively small crystallization rate on the amorphous semiconductor layer side and a relatively large crystallization rate on the high crystalline semiconductor layer side, it is near the interface in the semiconductor layer. The occurrence of structural defects can be suppressed. Therefore, it is possible to suppress a decrease in on-characteristics, off-characteristics, and reliability due to traps at the interface, and it is possible to improve device characteristics. In addition, since the stress difference between the amorphous semiconductor layer and the crystalline semiconductor layer is relieved by the crystalline change semiconductor layer, the adhesion of the film is improved and the occurrence of film peeling can be suppressed. it can. Thus, the crystalline change semiconductor layer can function as a buffer layer.

In addition, since a crystalline change semiconductor layer has a low crystallinity region, there is a concern that the defect density increases in manufacturing. Therefore, it is preferable that the layer be formed as thin as possible within the range having a function as a buffer layer. From such a viewpoint, the film thickness of the crystalline change semiconductor layer is preferably 5 to 25 nm, and more preferably 5 to 10 nm. On the other hand, when the film thickness exceeds 25 nm, the defect density may increase remarkably, and when the film thickness is less than 5 nm, it may not function as a buffer layer.

As described above, according to the third and fourth semiconductor devices of the present invention, since the low crystalline semiconductor layer and the crystalline change semiconductor layer can function as a buffer layer, defects such as structural defects and film peeling occur. It is possible to suppress the occurrence of occurrence more effectively. Therefore, a semiconductor device having a buffer semiconductor layer between an amorphous semiconductor layer and a highly crystalline semiconductor layer is also one aspect of the present invention.

That is, the present invention also includes a structure in which a gate electrode, a gate insulating layer, and a semiconductor layer are stacked in this order on an insulating substrate, and a structure in which a source / drain electrode is electrically connected to the semiconductor layer through a contact layer. The semiconductor layer includes, in order from the contact layer side, an amorphous semiconductor layer, a buffer semiconductor layer containing a crystalline phase, and a high crystal having a crystallization rate higher than that of the buffer semiconductor layer. The semiconductor device has a structure in which a conductive semiconductor layer is stacked (hereinafter also referred to as “fifth semiconductor device of the present invention”).

As described above, since the amorphous semiconductor layer having a high resistance value and a wide band gap is disposed at a position in contact with the contact layer, more effective leakage current (off-state current) can be reduced, that is, more effective. The off characteristics can be improved. In addition, since the highly crystalline semiconductor layer contains a crystalline phase and has a higher mobility than the amorphous semiconductor layer, it can exhibit excellent on characteristics. Furthermore, since the buffer semiconductor layer compensates for the structural difference between the amorphous semiconductor layer and the highly crystalline semiconductor layer, the occurrence of structural defects in the vicinity of the interface in the semiconductor layer can be suppressed. Therefore, it is possible to suppress a decrease in on-characteristics, off-characteristics, and reliability due to traps at the interface, and it is possible to improve device characteristics. Since the buffer semiconductor layer relieves a stress difference generated between the amorphous semiconductor layer and the highly crystalline semiconductor layer, the adhesion of the film can be improved and the occurrence of film peeling can be suppressed. Thus, the buffer semiconductor layer is a semiconductor layer containing a crystalline phase that functions as a buffer layer, and the buffer layer has a function of compensating for structural differences between the amorphous semiconductor layer and the highly crystalline semiconductor layer. And a function of relieving stress generated in the semiconductor layer. Therefore, as the buffer semiconductor layer, a structure compensation layer that compensates for the structural difference between the amorphous semiconductor layer and the highly crystalline semiconductor layer, and / or a stress relaxation layer that relieves stress generated in the semiconductor layer. It is preferable to be included.

The structure compensation layer that compensates for the structural difference between the amorphous semiconductor layer and the highly crystalline semiconductor layer is more specifically a semiconductor in which the structures of the amorphous semiconductor layer and the highly crystalline semiconductor layer are mixed. A layer is preferred.

In this specification, a highly crystalline semiconductor layer having a crystallization rate equal to or higher than that of the buffer semiconductor layer means a highly crystalline semiconductor layer having a crystallization rate equal to or higher than that of the buffer semiconductor layer. Specifically, it means a highly crystalline semiconductor layer having a crystallization rate equal to or higher than the maximum crystallization rate in the buffer semiconductor layer.

The configuration of the semiconductor device of the present invention is not particularly limited as long as such a component is formed as an essential component, and may or may not include other components. .
A preferred embodiment of the semiconductor device of the present invention will be described in detail below.

In the semiconductor device of the present invention, the material of the semiconductor is not particularly limited, but it is preferable to contain silicon (Si) from the viewpoint of versatility and ease of manufacture.

The form of the buffer semiconductor layer is not particularly limited, and the crystallinity is discontinuously decreased in the thickness direction from the high crystalline semiconductor layer side to the amorphous semiconductor layer side, for example, a form in which the crystallinity decreases stepwise Examples include a form having a certain value after the crystallization rate continuously decreases in the thickness direction from the crystalline semiconductor layer side to the amorphous semiconductor layer side. Among them, the above-described low crystalline semiconductor layer and crystal A property-changing semiconductor layer is preferred. That is, the buffer semiconductor layer includes a low crystalline semiconductor layer in which an amorphous phase and a crystalline phase are mixed, and the low crystalline semiconductor layer has a crystallization rate smaller than that of the high crystalline semiconductor layer. It is preferable. The buffer semiconductor layer includes a crystalline change semiconductor layer in which a crystallization rate changes in a thickness direction, and the crystalline change semiconductor layer extends from the high crystalline semiconductor layer side to the amorphous semiconductor layer side. It is preferable that the crystallization rate decreases continuously, and the highly crystalline semiconductor layer has a crystallization rate higher than that of the crystalline change semiconductor layer.

Note that the buffer semiconductor layer may include a low crystalline semiconductor layer and a crystalline change semiconductor layer. Further, when the buffer semiconductor layer includes a low crystalline semiconductor layer and / or a crystalline change semiconductor layer, there is a concern that the defect density in the buffer semiconductor layer increases. Therefore, the buffer semiconductor layer is preferably formed as thin as possible within a range in which the function as the buffer semiconductor layer is exhibited. From such a viewpoint, in the fifth semiconductor device of the present invention, the buffer semiconductor layer preferably has a film thickness of 5 to 25 nm or less, and more preferably 5 to 10 nm. On the other hand, when the film thickness exceeds 25 nm, the defect density may increase remarkably, and when the film thickness is less than 5 nm, it may not function as a buffer layer.

The crystallinity changing semiconductor layer preferably has a crystallization rate in the vicinity of the interface with the highly crystalline semiconductor layer substantially equal to the crystallization rate of the highly crystalline semiconductor layer. Thereby, since the structural change between the crystalline semiconductor layer and the highly crystalline semiconductor layer can be substantially eliminated, the occurrence of structural defects can be more effectively suppressed. Accordingly, it is possible to more effectively suppress a decrease in on-characteristics, off-characteristics, and reliability due to traps at the interface, and it is possible to further improve device characteristics. Moreover, generation | occurrence | production of film | membrane peeling can be suppressed more effectively. Note that the crystallization rate is substantially equal here, specifically, the crystallization rate in the vicinity of the interface between the crystalline change semiconductor layer and the high crystalline semiconductor layer and the crystallization rate of the high crystalline semiconductor layer. Is preferably 10% or less, more preferably 5% or less, and the crystallinity ratio in the vicinity of the interface between the crystalline semiconductor layer and the highly crystalline semiconductor layer is different from that of the highly crystalline semiconductor layer. It is more preferable that the crystallization rate completely coincides.

In the semiconductor device of the present invention, the semiconductor layer may or may not have a clear interface between the constituent layers, but from the viewpoint of more effectively suppressing the occurrence of film peeling, The semiconductor layer preferably does not have a clear interface between the constituent layers. That is, the semiconductor device preferably does not have a clear interface between any adjacent layers of the semiconductor layer constituting layers, and does not have a clear interface between each layer of the semiconductor layer constituting layers. It is more preferable. In addition, the following method is mentioned as a method of distinguishing each structural layer in the case of not having an interface. In other words, cross-sectional observation of a semiconductor layer with a TEM (transmission electron microscope), etching back the semiconductor layer (Si film), and performing Raman spectroscopic measurement or interface UV reflectance measurement to correlate the film thickness and crystallinity of each layer. The method of confirming is mentioned.

It is preferable that the crystalline change semiconductor layer is substantially amorphous on the contact layer side. Thereby, in the 2nd semiconductor device of this invention, generation | occurrence | production of leak current can be suppressed more effectively. Further, in the fourth and fifth semiconductor devices of the present invention, the structural change between the crystalline change semiconductor layer and the amorphous semiconductor layer can be substantially eliminated, so that the generation of structural defects is more effective. Can be suppressed. Accordingly, it is possible to more effectively suppress a decrease in on-characteristics, off-characteristics, and reliability due to traps at the interface, and it is possible to further improve device characteristics. Moreover, generation | occurrence | production of film | membrane peeling can be suppressed more effectively. Note that the term “substantially amorphous” specifically means that the crystallization rate is preferably 10% or less, more preferably 5% or less, and substantially 0%. Is more preferable. As a method for confirming that the crystallization rate is approximately 0%, when silicon is used as the semiconductor material, a method of observing the peak component (520 cm ⁻¹ ) of crystalline silicon by Raman spectroscopy described later can be given. If the crystallization rate is approximately 0%, the peak component (520 cm ⁻¹ ) of crystalline silicon is substantially absent.

The third to fifth semiconductor devices of the present invention have an amorphous semiconductor layer, and since the amorphous semiconductor has a high resistance, there is a concern about an increase in parasitic capacitance. However, an increase in parasitic capacitance can be suppressed by setting the amorphous semiconductor layer to the minimum necessary thickness within a range where leakage current can be suppressed. From such a viewpoint, the amorphous semiconductor layer preferably has a thickness of 5 to 30 nm, and more preferably 10 to 20 nm. On the other hand, if the film thickness exceeds 30 nm, the on-state characteristics may be significantly decreased and the parasitic capacitance may be significantly increased. If the film thickness is less than 5 nm, the leakage current may not be sufficiently suppressed.

The semiconductor device preferably has a structure in which a gate electrode, a gate insulating layer, and a semiconductor layer are stacked in this order from the insulating substrate side. As a result, a bottom-gate TFT can be realized, so that the semiconductor device of the present invention can be manufactured by diverting the a-Si TFT process that is currently practically used as it is. Note that the semiconductor device of the present invention may have a structure in which a semiconductor layer, a gate insulating layer, and a gate electrode are stacked in this order from the insulating substrate side, whereby a top-gate TFT can be realized. .

In the semiconductor layer, the crystalline phase preferably contains microcrystals. As a result, a crystalline semiconductor layer can be formed directly without adding a special crystallization step, and thus the semiconductor device of the present invention can be manufactured by a process similar to the current a-Si TFT process. It becomes.

Note that a semiconductor layer containing microcrystals (hereinafter also referred to as a “microcrystalline semiconductor layer”) normally exists in a state where a crystalline phase and an amorphous phase are mixed. Therefore, when the high crystalline semiconductor layer, the low crystalline semiconductor layer, and the crystalline change semiconductor layer contain microcrystals, it can be said that each is a microcrystalline semiconductor layer. In this case, each layer has a crystallization rate. It will be distinguished by the difference.

In addition, when the semiconductor material is silicon, microcrystalline silicon containing microcrystals as a crystalline phase, crystalline silicon containing only a crystalline phase, and amorphous silicon containing only an amorphous phase Can be distinguished by Raman spectroscopy. That is, crystalline silicon has a sharp peak at 520 cm ⁻¹ , and amorphous silicon has a broad peak at 480 cm ⁻¹ . Further, since microcrystalline silicon is a mixture of both, the spectrum has a shoulder on the low-end side of the peak at 520 cm ⁻¹ . It may compare the crystallinity of the microcrystalline silicon by the peak intensity ratio between the 520 cm ^-1 and 480 cm ^-1. Note that when microcrystalline silicon is formed by a high-density plasma CVD apparatus described later, the peak intensity ratio (520 cm ⁻¹ / 480 cm ⁻¹ ) is about 2 to 20. Thus, although the ratio of crystalline silicon can be increased by a high-density plasma CVD apparatus, complete crystalline silicon cannot be formed, and microcrystalline silicon that is a mixture of a crystalline phase and an amorphous phase is formed. Is done. On the other hand, in the case of polycrystalline silicon by solid phase growth (SPC), laser crystallization, etc., this ratio can be about 15 to 80, and the amorphous component should be formed so as not to be substantially present in the film. However, the manufacturing process becomes complicated and the manufacturing cost increases.

Thus, the microcrystalline semiconductor layer, in the Raman spectroscopy, (in the case of ^{silicon, 520cm -1} / ^480cm -1) Pure ratio of the peak intensity of the crystalline phase and the amorphous phase is approximately 2 to 20 Preferably there is.

Further, the crystallization rate in the present invention is calculated from the ratio of the pure peak intensity of the crystalline phase and the amorphous phase by Raman spectroscopy (for ^{silicon, 520cm -1} / ^480cm -1). That is, when the semiconductor material is silicon, the crystallization rate is determined by Raman spectroscopic measurement: (peak intensity of crystalline silicon) / {(peak intensity of crystalline silicon) + (peak intensity of amorphous silicon)} × 100 More specifically, it is calculated from (peak intensity at 520 cm ⁻¹ ) / {(peak intensity at 520 cm ⁻¹ ) + (peak intensity at 480 cm ⁻¹ )} × 100. Incidentally, each of the peaks of 520 cm ^-1 and 480 cm ^-1, means a peak of crystalline silicon and amorphous silicon, respectively the position of the peak of 520 cm ^-1 and 480 cm ^-1, strictly 520 cm ^-1 and 480 cm ^- there is no need to be in the ^1. The Raman spectroscopic measurement can be performed at room temperature with an Ar + laser (514 nm) using, for example, LabRAM HR-800 manufactured by HORIBA Joban Yvon as a Raman spectroscopic measurement apparatus. Furthermore, peak separation can be performed by LabSpec of LabRAM HR-800 attached software.

The microcrystal is preferably made of a columnar crystal substantially perpendicular to the plane direction of the semiconductor layer. The microcrystal having such a crystal shape can be directly formed by the current a-Si TFT process without adding a special crystallization process.

The columnar crystal preferably has a maximum diameter of 10 to 40 nm in the highly crystalline semiconductor layer. Thereby, a semiconductor device having uniform device characteristics can be manufactured over the entire insulating substrate. If the maximum diameter exceeds 40 nm, the density of the film may decrease, causing problems in the manufacturing process such as film peeling and chemical resistance deterioration. On the other hand, if the maximum diameter is less than 10 nm, structural defects at the crystal grain boundaries increase, and the on and off characteristics may be significantly degraded.

The highly crystalline semiconductor layer has a crystallization rate of preferably 60% or more, and more preferably 70% or more. Accordingly, the highly crystalline semiconductor layer can have a mobility higher than that of an amorphous semiconductor layer (for example, about 0.3 to 0.5 cm ² / Vs in the case of amorphous silicon). As a result, it is possible to increase the brightness of the organic EL display device, to make the gate driver in the liquid crystal display device monolithic, to drive at a higher frequency (usually 60 Hz to 120 Hz and 150 Hz). Note that the specific mobility of the highly crystalline semiconductor layer depends on other process factors, but when using microcrystalline silicon having a crystallization rate of 60% or more, 0.8 cm ² / Vs or more is realized. can do. Note that when the crystallization rate is less than 60%, a mobility that is substantially larger than that of the amorphous semiconductor layer may not be realized.

The low crystalline semiconductor layer preferably has a crystallization rate of 30 to 60%. Accordingly, a low crystalline semiconductor layer with better adhesion to the amorphous semiconductor layer and the high crystalline semiconductor layer can be formed, so that an interface with fewer structural defects can be formed. Note that when the crystallization rate exceeds 60%, the adhesion between the low crystalline semiconductor layer and the amorphous semiconductor layer may be deteriorated, and film peeling may occur. On the other hand, the crystallization rate is less than 30%. In addition, structural defects may increase between the low crystalline semiconductor layer and the high crystalline semiconductor layer, and on-state characteristics, off-state characteristics, and reliability may deteriorate, and device characteristics may deteriorate.

The crystalline change semiconductor layer is not particularly limited as long as its crystallization rate changes continuously within the range of the crystallization rate of the high crystalline semiconductor layer or less. It is preferable to continuously change between the crystallization rate and the crystallization rate of the amorphous semiconductor layer, and the crystallization rate changes from the crystallization rate of the highly crystalline semiconductor layer to the crystallization rate of the amorphous semiconductor layer. More preferably, it changes continuously. More specifically, the crystallinity changing semiconductor layer preferably has a crystallization rate that continuously changes between 80% and 0%, and the crystallization rate continuously changes from 80% to 0%. More preferably. Thus, a crystalline change semiconductor layer having better adhesion to the amorphous semiconductor layer and the highly crystalline semiconductor layer can be obtained. Therefore, the occurrence of film peeling can be more effectively suppressed and the occurrence of structural defects can be further suppressed. Note that when the crystallization rate exceeds 80%, structural defects increase between the crystalline change semiconductor layer and the highly crystalline semiconductor layer, resulting in deterioration of on-characteristics, off-characteristics and reliability, and deterioration of device characteristics. May occur.

The highly crystalline semiconductor layer preferably contains microcrystals as a crystalline phase and substantially does not contain an incubation layer. Since the incubation layer contains a large amount of voids in the film, a good interface with the gate insulating film cannot be obtained, and its mobility is very low. Therefore, since the highly crystalline semiconductor layer does not substantially contain the incubation layer, it is possible to realize good interface characteristics with the gate insulating film and high mobility. In addition, here, it is preferable that the thickness of an incubation layer is 5 nm or less that it does not contain an incubation layer substantially.

Note that the incubation layer is a precursor until the microcrystalline semiconductor grows, and has a different structure from the amorphous semiconductor layer used on the bonding side with the contact layer in the present invention. It can be clearly identified by a spectrophotometer (FT-IR). Measuring the silicon film containing an incubation layer and the amorphous silicon by FT-IR, there are peaks at 2000 cm ^-1 and 2100cm ^-1, _{Si-H 2} and in the vicinity of 2100 cm ^-1 when a voided large amount ( A peak due to Si—H ₂ ) _n is observed, and when there are few voids, a peak due to Si—H is observed in the vicinity of 2000 cm ⁻¹ . Thus, in the present specification, the incubation layer, the area of the peak due to Si-H in the vicinity of 2000 cm ^-1 to the peak attributable to the _{Si-H 2} and _{(Si-H 2) n} in the vicinity of 2100 cm ^-1 ratio is a layer at least 75%, while the amorphous silicon layer used for bonding the side of the contact layer in the present invention, 2100 cm around ^-1 to the peak attributable to the Si-H in the vicinity of 2000 cm ^-1 This is a layer in which the area ratio of peaks due to Si—H ₂ and (Si—H ₂ ) _n is 75% or more. Moreover, as a Fourier-transform infrared spectrophotometer, JASCO Corporation FT / IR600 is mentioned, for example, and a measurement is performed at room temperature. Moreover, subjected to peak separation by attached software of FT / IR600, it is possible to calculate the area between 2000 cm ^-1 component and 2100 cm ^-1 component.

The semiconductor layer preferably contains substantially no particles (particulate mass). In the case where a semiconductor layer is formed by a chemical vapor deposition method, if the vapor phase reaction is insufficient, film formation may be poor. That is, the semiconductor layer is not uniformly formed on the insulating substrate, and particles (about 0.1 to 20 μm in diameter) may be generated. The particles become dust for the semiconductor device. When the particles are generated, normal device characteristics cannot be obtained, and the yield rate of the semiconductor device is reduced. Therefore, when the semiconductor layer does not substantially contain particles, a semiconductor film with a more uniform film quality can be realized, and the yield rate of semiconductor devices can be improved. Here, “substantially not containing particles” is more specifically preferably 10 particles / m ² or less of particles having a diameter of 1 μm or less. The number of particles can be measured by an optical method, and as a particle number measuring apparatus, a standard apparatus is used as a process management apparatus such as an LCD (Liquid Crystal Display) or an IC (Semiconductor Integrated Circuit). If it is.

The contact layer has a structure in which an amorphous semiconductor layer containing impurities and a crystalline semiconductor layer containing impurities are stacked in order from the semiconductor layer side, and low-concentration impurities in order from the semiconductor layer side And a sheet resistance value in the order from the semiconductor layer side. A high resistance semiconductor layer having a sheet resistance value of 5 × 10 ⁴ to 1 × 10 ⁶ Ω / cm ² and a low resistance semiconductor layer having a sheet resistance value of 5 × 10 ^{7 to} 5 × 10 ⁸ Ω / cm ² were laminated. Any of the forms having a structure is preferable, and a form in which these forms are appropriately combined is more preferable. Thereby, since the electric field in the vicinity of the drain can be relaxed, the leakage current can be further reduced.

Examples of the impurities include group 15 elements such as phosphorus and group 13 elements such as boron. The impurity concentration of the low-concentration impurity semiconductor layer is preferably 1 × 10 ¹⁷ to 1 × 10 ¹⁹ atoms / cm ³ , and more preferably 5 × 10 ¹⁷ to 1 × 50 ¹⁸ atoms / cm ^3. preferable. On the other hand, if the impurity concentration of the low-concentration impurity semiconductor layer exceeds 1 × 10 ¹⁹ atoms / cm ³ , the resistance becomes too low and the role of LDD (Lightly Doped Drain) becomes insufficient, and the off-current increases remarkably. If it is less than 1 × 10 ¹⁷ atoms / cm ³ , the resistance becomes too high and the resistance becomes parasitic resistance, and the on-current may be significantly reduced. The impurity concentration of the high-concentration impurity semiconductor layer is preferably 1 × 10 ¹⁹ to 1 × 10 ²¹ atoms / cm ³ , more preferably 5 × 10 ^{19 to} 5 × 10 ²⁰ atoms / cm ^3. preferable. On the other hand, if the impurity concentration of the high-concentration impurity semiconductor layer exceeds 1 × 10 ²¹ atoms / cm ³ , impurities may precipitate, and if it is less than 1 × 10 ¹⁹ atoms / cm ³ , the resistance becomes too high. On-state current may be too low. The difference in impurity concentration between the high-concentration impurity semiconductor layer and the low-concentration impurity semiconductor layer is preferably 5 times or more, and more preferably 10 times or more. On the other hand, if the difference in impurity concentration between the high-concentration impurity semiconductor layer and the low-concentration impurity semiconductor layer is less than five times, the intended off-current reduction effect may not be obtained. Furthermore, if the sheet resistance value of the high-resistance semiconductor layer exceeds 5 × 10 ⁸ Ω / cm ² , the parasitic resistance may increase and the on-current may be excessively reduced, and may be less than 5 × 10 ⁷ Ω / cm ^2. In some cases, the resistance is too low to obtain an off-current reduction effect. If the sheet resistance value of the low-resistance semiconductor layer exceeds 1 × 10 ⁶ Ω / cm ² , the parasitic resistance may increase and the on-current may decrease excessively. The lower limit value of the sheet resistance value of the low-resistance semiconductor layer is preferably as low as possible, but is preferably 5 × 10 ⁴ Ω / cm ² or more in the current technical level. Can be easily manufactured.

The present invention also includes a structure in which a gate electrode, a gate insulating layer, and a semiconductor layer are stacked in this order on an insulating substrate, and a structure in which a source / drain electrode is electrically connected to the semiconductor layer through a contact layer. A method for manufacturing a semiconductor device comprising: a step of forming a low crystalline semiconductor layer in which an amorphous phase and a crystalline phase are mixed; and a crystallization larger than that of the low crystalline semiconductor layer. And a step of forming a highly crystalline semiconductor layer having a rate (hereinafter, also referred to as “first method of manufacturing a semiconductor device of the present invention”). Thereby, the first semiconductor device of the present invention can be easily manufactured.

Note that the low crystalline semiconductor layer and the high crystalline semiconductor layer may be continuously formed (film formation), whereby a substantially interface between the low crystalline semiconductor layer and the high crystalline semiconductor layer is formed. It is possible to realize a semiconductor device that does not include On the other hand, when an interface is formed between the low crystalline semiconductor layer and the high crystalline semiconductor layer, the film formation of both may be interrupted once.

The present invention also includes a structure in which a gate electrode, a gate insulating layer, and a semiconductor layer are stacked in this order on an insulating substrate, and a structure in which a source / drain electrode is electrically connected to the semiconductor layer through a contact layer. A method for manufacturing a semiconductor device, comprising: a step of forming a crystalline change semiconductor layer so that a crystallization rate continuously changes in a thickness direction; And a step of forming a highly crystalline semiconductor layer having a crystallization rate (hereinafter, also referred to as “second method for manufacturing a semiconductor device of the present invention”). Thereby, the second semiconductor device of the present invention can be easily manufactured.

Note that the crystalline change semiconductor layer and the highly crystalline semiconductor layer may be formed (deposited) continuously, whereby a substantially interface between the crystalline change semiconductor layer and the highly crystalline semiconductor layer is formed. It is possible to realize a semiconductor device that does not include On the other hand, when an interface is formed between the crystalline change semiconductor layer and the highly crystalline semiconductor layer, the film formation of both may be interrupted once.

In the present specification, more specifically, as an aspect of forming the crystalline change semiconductor layer so that the crystallization rate continuously changes in the thickness direction, more specifically, the highly crystalline semiconductor has a crystallization rate in the thickness direction. A mode in which the crystalline change semiconductor layer is formed so as to continuously decrease from the layer side toward the contact layer side is preferable.

The present invention also includes a structure in which a gate electrode, a gate insulating layer, and a semiconductor layer are stacked in this order on an insulating substrate, and a structure in which a source / drain electrode is electrically connected to the semiconductor layer through a contact layer. A method for manufacturing a semiconductor device, comprising: a step of forming an amorphous semiconductor layer; and a step of forming a low crystalline semiconductor layer in which an amorphous phase and a crystalline phase are mixed. And a step of forming a highly crystalline semiconductor layer having a larger crystallization rate than the low crystalline semiconductor layer (hereinafter also referred to as “third method for fabricating a semiconductor device of the present invention”). .) Thereby, the third semiconductor device of the present invention can be easily manufactured.

Note that at least one of the high crystalline semiconductor layer and the low crystalline semiconductor layer, and the low crystalline semiconductor layer and the amorphous semiconductor layer may be continuously formed (film formation). A semiconductor device having substantially no interface between the high crystalline semiconductor layer and the low crystalline semiconductor layer and / or the low crystalline semiconductor layer and the amorphous semiconductor layer can be realized. On the other hand, in the case of forming an interface between the layers, the three film formations may be interrupted as appropriate.

The present invention also includes a structure in which a gate electrode, a gate insulating layer, and a semiconductor layer are stacked in this order on an insulating substrate, and a structure in which a source / drain electrode is electrically connected to the semiconductor layer through a contact layer. A method for manufacturing a semiconductor device, comprising: a step of forming an amorphous semiconductor layer; and a step of forming a crystalline change semiconductor layer so that a crystallization rate continuously changes. And a method of manufacturing a semiconductor device including a step of forming a highly crystalline semiconductor layer having a crystallization rate equal to or higher than that of the crystalline change semiconductor layer (hereinafter also referred to as “fourth method of manufacturing a semiconductor device of the present invention”). It is also. Thereby, the fourth semiconductor device of the present invention can be easily manufactured.

Note that at least one of the highly crystalline semiconductor layer and the crystalline change semiconductor layer, and the crystalline change semiconductor layer and the amorphous semiconductor layer may be continuously formed (film formation). A highly crystalline semiconductor layer and a crystalline change semiconductor layer and / or a semiconductor device having substantially no interface between the crystalline change semiconductor layer and the amorphous semiconductor layer can be realized. On the other hand, when forming an interface between the layers, the three-layer film formation may be interrupted as appropriate. Moreover, that the crystallization rate continuously changes means more specifically an aspect in which the crystallization rate continuously increases or decreases.

The present invention also includes a structure in which a gate electrode, a gate insulating layer, and a semiconductor layer are stacked in this order on an insulating substrate, and a structure in which a source / drain electrode is electrically connected to the semiconductor layer through a contact layer. A method for manufacturing a semiconductor device comprising: a step of forming an amorphous semiconductor layer; a step of forming a buffer semiconductor layer containing a crystalline phase; and a crystal above the buffer semiconductor layer And a step of forming a highly crystalline semiconductor layer having a conversion rate (hereinafter also referred to as “fifth method of manufacturing a semiconductor device of the present invention”). Thereby, the fifth semiconductor device of the present invention can be easily manufactured.

Note that at least one of the high crystalline semiconductor layer and the buffer semiconductor layer, and the buffer semiconductor layer and the amorphous semiconductor layer may be continuously formed (film formation), whereby the high crystalline semiconductor A semiconductor device having substantially no interface between the layer and the buffer semiconductor layer and / or the buffer semiconductor layer and the amorphous semiconductor layer can be realized. On the other hand, in the case of forming an interface between the layers, the three film formations may be interrupted as appropriate.

The method for manufacturing a semiconductor device of the present invention is not particularly limited by other steps as long as these steps are included.
A preferred embodiment of the method for manufacturing a semiconductor device of the present invention will be described in detail below.

As a form of the buffer semiconductor layer in the method for manufacturing a semiconductor device of the present invention, the low crystalline semiconductor layer and the crystalline change semiconductor layer as described above are suitable. That is, the buffer semiconductor layer includes a low crystalline semiconductor layer in which an amorphous phase and a crystalline phase are mixed, and the high crystalline semiconductor layer has a higher crystallization rate than the low crystalline semiconductor layer. It is preferable. The buffer semiconductor layer includes a crystalline change semiconductor layer in which a crystallization rate changes in a thickness direction, and the crystalline change semiconductor layer extends from the high crystalline semiconductor layer side to the amorphous semiconductor layer side. It is preferable that the crystallization rate decreases continuously, and the highly crystalline semiconductor layer has a crystallization rate higher than that of the crystalline change semiconductor layer.

The method for manufacturing a semiconductor device includes an aspect including a step of forming a gate electrode, a step of forming a gate insulating layer on the gate electrode, and a step of forming a semiconductor layer on the gate insulating layer (hereinafter referred to as “first” Also referred to as “embodiment”). As a result, the semiconductor device of the present invention can be manufactured as a TFT having a bottom gate structure with almost no change in a general a-Si TFT process (only by changing only the semiconductor layer deposition step). Therefore, the manufacturing cost of the semiconductor device of the present invention can be suppressed.

In the first aspect, the method of manufacturing the semiconductor device includes an aspect including a step of forming a contact layer on the semiconductor layer and a step of removing a region of the contact layer facing the gate electrode, or etching on the semiconductor layer. An embodiment including a step of forming a stopper layer is preferable. Thus, the semiconductor device of the present invention can be manufactured as a TFT having a channel etch type or etching stopper type bottom gate structure by using a channel etch process or an etching stopper process which is a general process of the a-Si TFT process. it can. Therefore, the manufacturing cost of the semiconductor device of the present invention can be suppressed. The method for removing the contact layer is not particularly limited, but an etching method is preferable, and a dry etching method is particularly preferable.

The semiconductor device manufacturing method preferably includes a step of forming a semiconductor layer, a step of forming a gate insulating layer on the semiconductor layer, and a step of forming a gate electrode on the gate insulating layer. Thus, the semiconductor device of the present invention can be manufactured as a TFT having a top gate structure. In addition, since the crystallization ratio of the highly crystalline semiconductor layer on the gate insulating film side can be increased, higher mobility, that is, superior on-characteristics can be realized compared to the bottom gate structure. Become.

The semiconductor layer forming step uses a capacitively coupled (parallel plate type) plasma chemical vapor deposition (CVD) apparatus or a high density plasma chemical vapor deposition (CVD) apparatus, and the film forming pressure and / or It is preferable to form each semiconductor layer constituting layer by controlling the reaction gas flow rate ratio. By using a capacitively coupled CVD apparatus or a high-density plasma CVD apparatus, a semiconductor layer can be manufactured at a low temperature (eg, 350 ° C. or lower, more preferably 200 ° C. or lower), and an inexpensive glass is used as an insulating substrate. A substrate, a plastic substrate, or the like can be used. When a plastic substrate is used, it is preferable to form a film at 250 ° C. or lower. In addition, by appropriately controlling the deposition pressure and / or the reaction gas flow rate ratio (for example, SiH ₄ / H ₂ ratio in the case of forming a silicon layer), each semiconductor layer constituting layer having a desired crystallization ratio is controlled. It can be formed easily. Moreover, since generation | occurrence | production of a particle can be suppressed effectively from this, the non-defective rate of a semiconductor device can be improved. The high-density plasma CVD apparatus preferably has a plasma density that is about two orders of magnitude higher than the plasma density (about 10 ¹⁶ / m ² ) of a general parallel plate (CCP) type plasma CVD apparatus. .

The high crystalline semiconductor layer forming step is an aspect using a capacitively coupled (parallel plate type) plasma chemical vapor deposition (CVD) apparatus or an aspect using a high density plasma chemical vapor deposition (CVD) apparatus (hereinafter, It is also referred to as “second aspect”), and an aspect using a high-density plasma CVD apparatus is more preferable. Accordingly, a highly crystalline semiconductor layer can be manufactured at a low temperature (for example, 350 ° C. or lower), and an inexpensive glass substrate, plastic substrate, or the like can be used as an insulating substrate. In addition, the high-density plasma CVD apparatus exhibits superior performance in terms of crystallization (particularly in the initial stage of film formation) and film formation speed, as compared with a capacitively coupled plasma CVD apparatus. Furthermore, the high-density plasma CVD apparatus has a high degree of plasma dissociation and high reactivity compared with the capacitively coupled plasma CVD apparatus, so that even when the substrate temperature is low, film formation with high quality and high crystallization rate is possible. Is possible. On the other hand, it is difficult for a capacitively coupled CVD apparatus to obtain a crystalline phase from the beginning of film formation, and the first 50 nm becomes an amorphous layer (incubation layer). In addition, in the capacitively coupled CVD apparatus, in order to obtain microcrystals, the SiH ₄ / H ₂ ratio needs to be about 1/100. Therefore, the SiH ₄ supply rate is extremely limited, and the film formation rate is extremely high. Has the disadvantage of being slow.

The high-density plasma chemical vapor deposition (CVD) apparatus is preferably an inductively coupled plasma (ICP) method, a surface wave plasma method, or an electron cyclotron resonance (ECR) method. Any of these methods can relatively increase the size of a typical high-density plasma CVD apparatus. Therefore, it is possible to process a large substrate such as a glass substrate for a liquid crystal display device. In addition, each method can realize a plasma density that is one to two orders of magnitude higher than that of a capacitively coupled CVD apparatus, which enables a high-quality microcrystalline silicon film to be formed from the film-forming interface even under low temperature and low hydrogen dilution conditions. Can be formed.

In the second aspect, the high crystalline semiconductor layer forming step preferably has a film forming pressure of 1.33 × 10 ^{−1 to} 4.00 × 10 Pa ( ^{1 to} 300 mTorr), and 4.00 × 10 ^−1. More preferably, it is ˜1.33 × 10 Pa (3 to 100 mTorr). Accordingly, a microcrystalline silicon film having a high crystallization rate and a high density can be formed from the initial stage of the film formation due to a reaction on the surface of the film formation substrate. Note that when the film forming pressure exceeds 4.00 × 10 Pa, the crystallinity may be lowered, and the on-characteristic and off-characteristic may be degraded. On the other hand, if the film forming pressure is less than 1.33 × 10 ⁻¹ Pa, the plasma damage may increase and the film may become amorphous.

In the second aspect, the highly crystalline semiconductor layer forming step preferably uses SiH ₄ and H ₂ as source gases, and the SiH ₄ / H ₂ ratio is preferably 1/50 to 1/1, and SiH ₄ / The H ₂ ratio is more preferably 1/30 to 1/5. Accordingly, a microcrystalline silicon film having a high crystallization rate and a high density can be formed from the initial stage of the film formation due to a reaction on the surface of the film formation substrate. Incidentally, when the _SiH 4 / _{H 2} ratio exceeds 1/1, the crystallinity is lowered by shortage of hydrogen, it may be dangling bonds increases. On the other hand, if the SiH ₄ / H ₂ ratio is less than 1/50, hydrogen may be excessive, the film surface may be etched, and the surface irregularities may become too large.

In the method for manufacturing the semiconductor device, it is preferable to perform surface treatment with H ₂ plasma before forming the highly crystalline semiconductor layer. Thereby, the crystallinity of the highly crystalline semiconductor layer from the initial film formation can be improved.

In the low crystalline semiconductor layer forming step, an aspect using a capacitively coupled plasma chemical vapor deposition apparatus (hereinafter also referred to as “third aspect”) or an aspect using a high density plasma chemical vapor deposition apparatus (hereinafter referred to as “third aspect”). , Also referred to as “fourth embodiment”). Accordingly, a low crystalline semiconductor layer can be manufactured at a low temperature (eg, 350 ° C. or lower), and an inexpensive glass substrate, plastic substrate, or the like can be used as an insulating substrate.

In the third aspect, the low crystalline semiconductor layer forming step preferably uses SiH ₄ and H ₂ as a source gas, and the SiH ₄ / H ₂ ratio is preferably 1/30 to 1/150, and SiH ₄ / more preferably H ₂ ratio is 1 / 40-1 / 100. Thus, a silicon layer having a low crystallization rate can be easily formed using a capacitively coupled plasma CVD apparatus. Incidentally, when the _SiH 4 / _{H 2} ratio exceeds 1/30, which may result in amorphization. On the other hand, if the SiH ₄ / H ₂ ratio is less than 1/150, the crystallinity becomes too large, and the function as a low crystalline semiconductor layer (buffer layer) may not be sufficiently exhibited.

In the fourth aspect, the low crystalline semiconductor layer forming step preferably has a film forming pressure of 6.66 to 6.66 × 10 Pa (50 to 500 mTorr), and 9.33 to 2.66 × 10 Pa (70 More preferably, it is -200 mTorr). (Thus, a high-density plasma CVD apparatus can be used to easily form a silicon layer having a low crystallization rate. Note that when the film forming pressure exceeds 4.00 × 10 Pa, the gas phase reaction becomes severe. When the film forming pressure is less than 6.66 Pa, the crystallinity becomes too high, resulting in low crystallinity. The function as a conductive semiconductor layer (buffer layer) may not be sufficiently exhibited.

In the crystallinity-change semiconductor layer forming step, an aspect using a capacitively coupled plasma chemical vapor deposition apparatus (hereinafter also referred to as “fifth aspect”) or an aspect using a high density plasma chemical vapor deposition apparatus (hereinafter referred to as “fifth aspect”). , Also referred to as “sixth aspect”). Accordingly, the crystalline change semiconductor layer can be manufactured at a low temperature (for example, 350 ° C. or lower), and an inexpensive glass substrate, plastic substrate, or the like can be used as the insulating substrate.

In the fifth aspect, the crystalline change semiconductor layer forming step uses SiH ₄ and H ₂ as source gases and continuously changes the SiH ₄ / H ₂ ratio within a range of 1/400 to 1/5. It is preferable. Accordingly, a silicon layer whose crystallinity continuously changes can be easily formed using a capacitively coupled plasma CVD apparatus. Note that when the SiH ₄ / H ₂ ratio exceeds 1/5, the film quality of the amorphous phase is deteriorated. More specifically, the termination of dangling bonds by hydrogen may be insufficient. On the other hand, when the SiH ₄ / H ₂ ratio is less than 1/400, hydrogen becomes excessive, the film surface is etched, and the surface irregularities may become too large.

In the sixth aspect, the crystalline change semiconductor layer forming step preferably has a film forming pressure of 1.33 × 10 ^{−1 to} 6.66 × 10 Pa ( ^{1 to} 500 mTorr). Accordingly, a silicon layer whose crystallinity continuously changes can be easily formed using a high-density plasma CVD apparatus. Note that when the film forming pressure exceeds 6.66 × 10 Pa, the gas phase reaction becomes too intense and becomes amorphous, the number of particles increases, and the device characteristics may remarkably deteriorate. On the other hand, when the film forming pressure is less than 1.33 × 10 ⁻¹ Pa, the film quality of the amorphous phase deteriorates, more specifically, dangling bonds due to hydrogen may be insufficiently terminated. .

The present invention is also a display device including the semiconductor device of the present invention, or a display device including the semiconductor device manufactured by the semiconductor device manufacturing method of the present invention. According to the present invention, the on characteristic, the off characteristic, and the reliability can be improved, so that the display quality and reliability of the display device can be improved. As the display device of the present invention, a liquid crystal display device and an organic EL display device are suitable.

According to the semiconductor device of the present invention, a semiconductor device having excellent on characteristics, off characteristics, and reliability can be realized.

EXAMPLES Although an Example is hung up below and this invention is demonstrated still in detail with reference to drawings, this invention is not limited only to these Examples.

(Embodiment 1)
FIG. 1 is a schematic cross-sectional view of the semiconductor device of the first embodiment. Hereinafter, one NMOS transistor (N-type TFT) will be described. However, the semiconductor device of the present invention usually has a structure in which a plurality of NMOS transistors and / or a plurality of PMOS transistors (P-type TFTs) are formed on the same insulating substrate. Each embodiment is described as an NMOS transistor for a pixel switching element in a liquid crystal display device, but a gate driver of a liquid crystal display device, a switching element of an organic EL display device, and the like can be manufactured by a similar manufacturing method.

As shown in FIG. 1, the semiconductor device 101 includes a gate electrode 2, a gate insulating film 3, an island-shaped semiconductor layer 4 in plan view, and a semiconductor layer 4 other than a region facing the gate electrode 2 on an insulating substrate 1. A structure in which the contact layer 5 disposed above is laminated, and the semiconductor layer 4 disposed on the semiconductor layer 4 and the gate insulating film 3 other than the region facing the gate electrode 2 and electrically connected to the semiconductor layer 4 via the contact layer 5 And source / drain electrodes 6 connected to each other. As described above, the semiconductor device 101 has a bottom gate structure. In addition, the semiconductor device 101 includes a passivation film 7 and a planarizing film 8 that are formed so as to cover the insulating substrate 1, and a transparent electrode 9 that is formed on the planarizing film 8 and functions as a pixel electrode.

The semiconductor layer 4 includes, in order from the contact layer 5 side, a low crystalline silicon layer (low crystalline μc-Si layer) 4b in which an amorphous phase and microcrystals are mixed, a microcrystal, and a low crystalline μc. A high crystalline silicon layer (high crystalline μc-Si layer) 4a having a larger crystallization rate than the -Si layer 4b is laminated. The contact layer 5 is made of a silicon (n ⁺ -Si) layer doped with phosphorus (P) at a high concentration.

Below, the manufacturing method of the semiconductor device of Embodiment 1 is demonstrated. 2A to 2F are schematic cross-sectional views of the semiconductor device of Embodiment 1 in each manufacturing process.

First, as shown in FIG. 2A, a tantalum nitride (TaN) / tantalum (Ta) / tantalum nitride (TaN) laminated film is formed on a glass substrate which is an insulating substrate 1 by a sputtering method. The gate electrode 2 is formed by patterning by the method. The film thicknesses are TaN = 50 nm, Ta = 200 nm, and TaN = 50 nm, respectively. A dry etching method is used for etching the laminated film. Oxygen is introduced into the etching gas so that the photoresist can be etched back, and the cross-sectional shape of the gate electrode 2 is set to a taper shape of about 45 ° with respect to the substrate.

Next, as shown in FIG. 2B, a silicon nitride film (SiNx film) having a film thickness of 400 nm is formed as the gate insulating film 3 by plasma CVD. Subsequently, a high crystalline μc-Si layer 4a, a low crystalline μc-Si layer 4b, and a silicon film (n ⁺ -Si layer) doped with phosphorus (P) at a high concentration are formed as the contact layer 5. . Here, the silicon nitride film is formed by a parallel plate type plasma CVD apparatus, and the high crystalline μc-Si layer 4a and the low crystalline μc-Si layer 4b having microcrystals are formed by a high density plasma CVD apparatus (ICP method, Surface wave plasma method or ECR method). These films are formed by a multi-chamber apparatus and sequentially formed in a vacuum. The silicon nitride film and the n ⁺ -Si layer may have the same film formation conditions as in a general a-Si TFT process.

The film formation conditions of the highly crystalline μc-Si layer 4a include film formation pressure = ^{1 to} 300 mTorr (1.33 × 10 ^{−1 to} 4.00 × 10 Pa), SiH ₄ / H ₂ ratio = 1/50 to 1 However, in this embodiment, the deposition pressure is set to 10 mTorr (1.33 Pa), the SiH ₄ / H ₂ ratio is set to 1/20, and the substrate temperature is set to 300 ° C. In this way, by controlling the film forming pressure and the SiH ₄ / H ₂ ratio, the highly crystalline μc-Si layer 4a is effectively suppressed from generating particles in the highly crystalline μc-Si layer 4a. The crystallization rate of can be easily controlled. In the present embodiment, the crystallization rate of the high crystalline μc-Si layer 4a is about 70%, and the maximum diameter of the microcrystals (columnar crystals) in the high crystalline μc-Si layer 4a is about 30 nm. Become.

In addition, about the formation process of the semiconductor layer 4, you may flow argon (Ar) which is carrier gas simultaneously as a reactive gas. Thereby, the plasma can be stabilized. In addition, as a pretreatment for forming the highly crystalline μc-Si layer 4a, a surface treatment with H ₂ plasma may be performed for about 30 seconds on the gate insulating film 3. Thereby, the crystallinity of the highly crystalline μc-Si layer 4a can be improved from the initial stage of film formation. As specific conditions for the surface treatment with H ₂ plasma, for example, the conditions similar to the film formation conditions for the highly crystalline μc-Si layer 4a may be set, and only H ₂ gas may be introduced as a gas.

The film formation condition of the low crystalline μc-Si layer 4b is preferably set within the range of film formation pressure = 50 to 500 mTorr (6.66 to 6.66 × 10 Pa). The film pressure is 100 mTorr (1.33 × 10 Pa), the SiH ₄ / H ₂ ratio is 1/1, and the substrate temperature is 300 ° C. Thus, by controlling the deposition pressure and the SiH ₄ / H ₂ ratio, the low crystalline μc-Si layer 4b can be effectively suppressed while generating particles in the low crystalline μc-Si layer 4b. The crystallization rate of can be easily controlled. In the present embodiment, the crystallization rate of the low crystalline μc-Si layer 4b is about 40%.

The highly crystalline μc-Si layer 4a may be formed using a capacitively coupled CVD apparatus, but from the viewpoint of obtaining a higher quality μc-Si layer, a high-density plasma CVD apparatus is used as described above. Is preferred. FIG. 3 is an enlarged schematic cross-sectional view of a semiconductor layer when a μc-Si layer is formed using a high-density plasma CVD apparatus. As shown in FIG. 3, when a high-density plasma CVD apparatus is used, film formation with high quality and high crystallization rate is possible from the initial stage of film formation, and the incubation layer has a thickness of 5 nm or less, Virtually nonexistent. FIG. 4 is an enlarged schematic cross-sectional view of a semiconductor layer when a μc-Si layer is formed using a capacitively coupled CVD apparatus. As shown in FIG. 4, when a capacitively coupled CVD apparatus is used, the first about 50 nm becomes an incubation layer, and a semiconductor layer having a high crystallization rate is formed at an early stage of film formation. I can't.

On the other hand, the low crystalline μc-Si layer 4b may be formed by using a capacitively coupled CVD apparatus. In this case, the SiH ₄ / H ₂ ratio is set within a range of 1/150 to 1/30. Is preferred. In that case, the deposition pressure may be 1.50 Torr (200 Pa) and the substrate temperature may be 300 ° C.

The film thickness of the high crystalline μc-Si layer 4a is preferably 20 to 70 nm (40 nm in this embodiment), and the film thickness of the low crystallinity μc-Si layer 4b is preferably 10 to 40 nm (in this embodiment). 20 nm). Note that when the film thickness of the highly crystalline μc-Si layer 4a exceeds 70 nm, the off-current may increase remarkably, and when it is less than 20 nm, the on-current may remarkably decrease. Further, when the film thickness of the low crystalline μc-Si layer 4b exceeds 40 nm, the parasitic resistance increases and the on-current may be remarkably reduced. When the film thickness is less than 10 nm, the off-current increases remarkably. The effect may not be obtained.

The semiconductor layer 4 may or may not have an interface between the constituent layers, but it does not have an interface from the viewpoint of more effectively suppressing film peeling. Is preferred. In this case, in the present embodiment, the high crystalline μc-Si layer 4a and the low crystalline μc-Si layer 4b may be continuously formed, more specifically, without interrupting the film formation. By changing the deposition pressure of the high crystalline μc-Si layer 4a to the deposition conditions of the low crystalline μc-Si layer 4b, as shown in FIG. 3, the high crystalline μc-Si layer (microcrystalline Both layers can be formed without forming an interface between the layer I) and the low crystalline μc-Si layer (microcrystalline layer II). On the other hand, in the case of forming an interface between the constituent layers, after forming a constituent layer (in this embodiment, the highly crystalline μc-Si layer 4a), the deposition is temporarily interrupted, and then A constituent layer (low crystalline μc-Si layer 4b in this embodiment) may be formed.

The film thickness of the n ⁺ -Si layer is 60 nm. The n ⁺ -Si layer may have a single-layer structure including an a-si layer or a μc-Si layer, but in order from the semiconductor layer 4 side, n having high resistance (low impurity concentration) including an amorphous phase. The electric field at the drain end is reduced by forming a structure in which a ⁺ -Si layer (film thickness 20 nm) and a low resistance (high impurity concentration) n ⁺ -Si layer (film thickness 40 nm) having microcrystals are stacked. Thus, the off current can be reduced and the on current can be improved. Here, the sheet resistance of the high resistance n ⁺ -Si layer made of an amorphous phase is about 5 × 10 ^{7 to} 5 × 10 ⁸ Ω / cm ² , and the resistance of the low resistance n ⁺ -Si layer having microcrystals. This effect can be obtained by setting the sheet resistance to about 5 × 10 ⁴ to 1 × 10 ⁶ Ω / cm ² .

Next, as shown in FIG. 2 (c), the high crystalline μc-Si layer 4a, the low crystalline μc-Si layer 4b and the contact layer 5 are patterned by photolithography to form an active layer (I island). To do. For the etching in patterning, a dry etching method is used. Thereby, it becomes possible to pattern even a fine shape. As an etching gas, a chlorine (Cl ₂ ) gas that can easily be selected with a silicon nitride film is used. Etching is monitored by an endpoint detector (EPD), and etching is performed until the silicon nitride film (SiNx film) is reached.

Next, as shown in FIG. 2D, an aluminum (Al) / molybdenum (Mo) laminated film is formed by sputtering. The film thicknesses of the laminated films are Al = 100 nm and Mo = 100 nm, respectively. Then, after patterning the photoresist 20, the stacked film is etched to form the source / drain electrodes 6. Etching of the laminated film is performed by a wet etching method, whereby only the Al / Mo laminated film can be selectively etched. As the etchant, an SLA etchant (composition: H ₃ PO ₄ : H ₂ O: HNO ₃ : CH ₃ COOH = 16: 2: 1: 1), which is a general metal etchant, is used.

After wet etching the Al / Mo laminated film, as shown in FIG. 2E, the n ⁺ -Si layer as the contact layer 5 is etched by dry etching with the photoresist 20 left as it is. Then, the source / drain regions are separated. As a result, the source / drain regions can be separated without additional patterning (channel etch process).

Next, as shown in FIG. 2E, a passivation film 7 such as a silicon nitride film is formed by a plasma CVD method, and a planarizing film 8 such as a silicon oxide film is further formed. After opening the planarization film 8 and the passivation film 7, a transparent electrode 9 such as ITO (Indium Thin Oxide) is formed by sputtering. Finally, by patterning the transparent electrode 9, the semiconductor device 101 of the first embodiment which is a pixel switching element in the liquid crystal display device can be manufactured.

According to the semiconductor device 101, the low crystalline μc-Si layer 4 b having a relatively high resistance value and a wide band gap is disposed at a position in contact with the contact layer 5. Improvement is possible. Moreover, since the highly crystalline μc-Si layer 4a contains microcrystals and has a higher mobility than the a-Si layer, it can exhibit excellent on characteristics. Further, since the low crystalline μc-Si layer 4b has a lower resistance than a-Si, the parasitic resistance can be reduced, and as a result, excellent on-characteristics can be maintained. Further, since the structural change between the low crystalline μc-Si and the high crystalline μc-Si is smaller than the structural change between the a-Si and the high crystalline μc-Si, the low crystalline μc-Si layer It is possible to suppress the occurrence of structural defects in the vicinity of the interface between 4b and the highly crystalline μc-Si layer 4a. Therefore, it is possible to suppress a decrease in on-characteristics, off-characteristics, and reliability due to traps at the interface, and it is possible to improve device characteristics.

(Embodiment 2)
A semiconductor device according to the second embodiment will be described. In addition, while omitting the description of the contents overlapping between the present embodiment and the first embodiment, the same reference numerals are given to the constituent members that exhibit the same function. FIG. 5 is a schematic cross-sectional view of the semiconductor device of the second embodiment.

As shown in FIG. 5, the semiconductor device 102 differs from the semiconductor device 102 of the first embodiment in the configuration of the semiconductor layer 4 and includes an etching stopper layer 10. That is, the semiconductor layer 4 contains, in order from the contact layer 5 side, a crystallinity-change silicon layer (crystallinity change μc-Si layer) 4c in which the crystallization rate changes in the thickness direction, and a crystallinity change. A highly crystalline μc-Si layer 4a having a crystallization rate equal to or higher than the μc-Si layer is laminated. The semiconductor device 102 also has an etching stopper layer 10 disposed on the semiconductor layer 4 in a region facing the gate electrode 2.

In the crystalline change μc-Si layer 4c, the crystallization rate decreases continuously, for example, linearly or trigonometrically, from the highly crystalline μc-Si layer 4a side to the contact layer side.

Below, the manufacturing method of the semiconductor device of Embodiment 2 is demonstrated. In addition, description is abbreviate | omitted about the content which overlaps with the manufacturing method of this embodiment, and the manufacturing method of Embodiment 1. FIG. 6A to 6F are schematic cross-sectional views of the semiconductor device of Embodiment 2 in each manufacturing process.

First, as shown in FIG. 6A, the gate electrode 2 is formed on the insulating substrate 1 in the same manner as in the first embodiment.

Next, as shown in FIG. 6B, a silicon nitride film (SiNx film) is formed as the gate insulating film 3 as in the first embodiment. Subsequently, a silicon nitride film (SiNx film) is formed as the high crystalline μc-Si layer 4a, the crystalline change μc-Si layer 4c, and the etching stopper layer 10. Here, the highly crystalline μc-Si layer 4a having microcrystals and the crystalline change μc-Si layer 4c are formed by a high-density plasma CVD apparatus (ICP method, surface wave plasma method or ECR method). These films are formed by a multi-chamber apparatus and sequentially formed in a vacuum.

The highly crystalline μc-Si layer 4a is formed under the same film forming conditions as in the first embodiment. On the other hand, the film formation condition of the crystalline change μc-Si layer 4c is preferably set within the range of film formation pressure = ^{1 to} 500 mTorr (1.33 × 10 ^{−1 to} 6.66 × 10 Pa), In this embodiment, the deposition pressure is continuously increased from 5 mTorr (6.66 × 10 ⁻¹ Pa) to 60 mTorr (8.00 Pa), for example, linearly or trigonometrically, and the SiH ₄ / H ₂ ratio is increased. = 1/1, substrate temperature = 300 ° C. In this way, by controlling the film formation pressure and the SiH ₄ / H ₂ ratio, it is possible to effectively suppress the generation of particles in the crystallinity change μc-Si layer 4c, and the crystallinity change μc-Si layer 4c. The crystallization rate of can be easily controlled. Further, by continuously increasing the deposition pressure, the crystallization rate of the crystalline change μc-Si layer 4c can be controlled in the film, and the crystalline change μc-Si layer 4c is gradually crystallized in the thickness direction. The rate will decrease. More specifically, in the present embodiment, the crystallization rate of the crystallinity change μc-Si layer 4c decreases from about 70% to about 10%.

The crystalline change μc-Si layer 4c may be formed by using a capacitively coupled CVD apparatus, and in this case, the SiH ₄ / H ₂ ratio is set within a range of 1/400 to 1/5. Is preferred. In that case, the deposition pressure may be 2.25 Torr (300 Pa), and the substrate temperature may be 300 ° C.

The film thickness of the highly crystalline μc-Si layer 4a is preferably 20 to 70 nm (30 nm in the present embodiment), and the film thickness of the crystalline change μc-Si layer 4c is preferably 10 to 40 nm (in the present embodiment). 20 nm). Note that when the film thickness of the highly crystalline μc-Si layer 4a exceeds 70 nm, the off-current may increase remarkably, and when it is less than 20 nm, the on-current may remarkably decrease. On the other hand, if the film thickness of the crystalline change μc-Si layer 4c exceeds 40 nm, the on-current may be significantly reduced, and if it is less than 10 nm, the off-current may be significantly increased.

The semiconductor layer 4 may or may not have an interface between the constituent layers as in the first embodiment, but from the viewpoint of more effectively suppressing film peeling, It is preferable not to have an interface. In this case, in this embodiment, the high crystalline μc-Si layer 4a and the crystalline change μc-Si layer 4c may be continuously formed, more specifically, without interrupting the film formation. The deposition pressure of the highly crystalline μc-Si layer 4a may be changed to the deposition condition of the crystalline change μc-Si layer 4c. On the other hand, in the case of forming an interface between the constituent layers, after forming a constituent layer (in this embodiment, the highly crystalline μc-Si layer 4a), the deposition is temporarily interrupted, and then A constituent layer (in this embodiment, the crystalline change μc-Si layer 4c) may be formed.

The film thickness of the etching stopper layer 10 is 150 nm. Thereby, in the source / drain separation step by etching the n ⁺ -Si layer later, only the n ⁺ -Si layer can be selectively etched, so that the thickness of the active layer (I layer) can be reduced by the channel etch process. It can be made thinner than when it is formed. The off current can be further reduced by the effect of thinning the semiconductor layer.

Next, as shown in FIG. 6C, the etching stopper layer 10 is patterned by self-alignment with respect to the gate line (wiring including the gate electrode 2) by backside exposure.

Next, as in the first embodiment, after forming the n ⁺ -Si layer as the contact layer 5, the high crystalline μc-Si layer 4a, the crystalline change μc-Si layer 4c and the contact layer 5 are formed by photolithography. Patterning is performed to form an active layer (I island) as shown in FIG.

Next, as shown in FIG. 6E, a molybdenum (Mo) film is formed by a sputtering method. The film thickness of the Mo film is 200 nm. Then, after patterning the photoresist, the Mo film is etched to form the source / drain electrodes 6. Etching of the Mo film can be performed by selectively etching only the Mo film by wet etching. An SLA etchant is used as the etchant.

After wet etching the Mo film, the n ⁺ -Si layer as the contact layer 5 is etched by a dry etching method with the photoresist remaining as it is, so that the source / drain as shown in FIG. Perform region separation. As a result, the source / drain regions can be separated without additional patterning. At this time, since there is the etching stopper layer 10, there is no damage to the channel region of the semiconductor 4 due to this dry etching, and improvement in on-characteristics and reliability can be expected.

Next, as shown in FIG. 6F, an embodiment which is a pixel switching element in a liquid crystal display device by forming a passivation film 7, a planarizing film 8 and a transparent electrode 9 as in the first embodiment. Two semiconductor devices 102 can be manufactured.

According to the semiconductor device 102, since the crystalline change μc-Si layer 4c having a relatively high resistance value and a wide band gap is disposed on the contact layer 5 side at a position in contact with the contact layer 5, the leakage current is reduced. In other words, off characteristics can be improved. Moreover, since the highly crystalline μc-Si layer 4a contains microcrystals and has a higher mobility than the a-Si layer, it can exhibit excellent on characteristics. Furthermore, since the crystalline change μc-Si layer 4c has a relatively large crystallization rate on the high crystalline μc-Si layer 4a side, the crystalline change μc-Si layer 4c and the highly crystalline μc-Si layer 4a It is possible to suppress the occurrence of structural defects in the vicinity of the interface. Therefore, it is possible to suppress a decrease in on-characteristics, off-characteristics, and reliability due to traps at the interface, and it is possible to improve device characteristics.

(Embodiment 3)
A semiconductor device according to the third embodiment will be described. In addition, while omitting description about the content which overlaps with this embodiment and Embodiment 1 and 2, the same code | symbol was attached | subjected about the structural member which exhibits the same function. FIG. 7 is a schematic cross-sectional view of the semiconductor device of the third embodiment.

As shown in FIG. 7, the semiconductor device 103 differs from the semiconductor device 101 of the first embodiment in the configuration of the semiconductor layer 4. That is, the semiconductor layer 4 contains, in order from the contact layer 5 side, an amorphous (amorphous) silicon layer (a-Si layer) 4d, a low crystalline μc-Si layer 4b, and a microcrystal. A highly crystalline μc-Si layer 4a having a larger crystallization rate than the crystalline μc-Si layer 4b is laminated. Thus, the semiconductor device 103 has the low crystalline μc-Si layer 4b as a buffer semiconductor layer.

Below, the manufacturing method of the semiconductor device of Embodiment 3 is demonstrated. In addition, description is abbreviate | omitted about the content which overlaps with the manufacturing method of this embodiment, and the manufacturing method of Embodiment 1 and 2. FIG. 8A to 8F are schematic cross-sectional views of the semiconductor device of Embodiment 3 in each manufacturing process.

First, as shown in FIG. 8A, the gate electrode 2 is formed on the insulating substrate 1 in the same manner as in the first embodiment.

Next, as shown in FIG. 8B, as in the first embodiment, a silicon nitride film (SiNx film) is formed as the gate insulating film 3. Subsequently, an n ⁺ -Si layer is formed as the high crystalline μc-Si layer 4 a, the low crystalline μc-Si layer 4 b, the a-Si layer 4 d, and the contact layer 5. Here, the silicon nitride film and the a-Si layer 4d are formed by a parallel plate type plasma CVD apparatus, and the high crystalline μc-Si layer 4a and the low crystalline μc-Si layer 4b having microcrystals are high-density plasma. It is formed by a CVD apparatus (ICP method, surface wave plasma method or ECR method). These films are formed by a multi-chamber apparatus and sequentially formed in a vacuum. The a-Si layer may have the same film formation conditions as a general a-Si TFT process.

The high crystalline μc-Si layer 4a and the low crystalline μc-Si layer 4b are formed under the same film forming conditions as in the first embodiment. The low crystalline μc-Si layer 4b may be formed using a capacitively coupled CVD apparatus as in the first embodiment.

The film thickness of the high crystalline μc-Si layer 4a is preferably 20 to 70 nm (30 nm in the present embodiment), and the film thickness of the low crystallinity μc-Si layer 4b is preferably 5 to 25 nm (this embodiment). And the thickness of the a-Si layer 4d is preferably 5 to 30 nm (20 nm in the present embodiment). Note that when the film thickness of the highly crystalline μc-Si layer 4a exceeds 70 nm, the off-current may increase remarkably, and when it is less than 20 nm, the on-current may remarkably decrease. Further, when the thickness of the low crystalline μc-Si layer 4b exceeds 25 nm, the defect density in the low crystalline μc-Si layer may remarkably increase, and when it is less than 5 nm, it may not function as a buffer layer. is there. Furthermore, if the thickness of the a-Si layer 4d exceeds 30 nm, the on-current may be significantly reduced, and if it is less than 5 nm, the off-current may be significantly increased.

The semiconductor layer 4 may or may not have an interface between the constituent layers as in the first embodiment, but from the viewpoint of more effectively suppressing film peeling. It is preferable not to have an interface. In this case, in the present embodiment, the high crystalline μc-Si layer 4a, the low crystalline μc-Si layer 4b, and the a-Si layer 4d may be continuously formed. The film forming pressure of the high crystalline μc-Si layer 4a may be changed to the film forming conditions of the low crystalline μc-Si layer 4b and the film forming conditions of the a-Si layer 4d without interruption. On the other hand, when an interface is formed between the constituent layers, after forming a constituent layer (in this embodiment, the high crystalline μc-Si layer 4a or the low crystalline μc-Si layer 4b), the constituent layers are once formed. The film may be interrupted, and the next constituent layer (low crystalline μc-Si layer 4b or a-Si layer 4d in this embodiment) may be formed.

Next, similarly to the first embodiment, the high crystalline μc-Si layer 4a, the low crystalline μc-Si layer 4b, the a-Si layer 4d, and the contact layer 5 are patterned by the photolithography method, and FIG. The active layer (I island) is formed as shown in FIG.

Next, as shown in FIG. 8D, the patterning of the photoresist 20 and the formation of the source / drain electrode 6 made of an Al / Mo laminated film are performed as in the first embodiment.

Next, as shown in FIG. 8E, the source / drain regions are separated by etching the n ⁺ -Si layer, as in the first embodiment.

Next, as shown in FIG. 8 (f), an embodiment which is a pixel switching element in a liquid crystal display device by forming a passivation film 7, a planarizing film 8 and a transparent electrode 9, as in the first embodiment. 3 semiconductor devices 103 can be manufactured.

According to the semiconductor device 103, since the a-Si layer 4d having a high resistance value and a wide band gap is disposed at a position in contact with the contact layer 5, more effective leakage current reduction, that is, more effective. The off characteristics can be improved. In addition, the highly crystalline μc-Si layer 4a contains microcrystals and has a higher mobility than the a-Si layer 4d, and thus can exhibit excellent on characteristics. Furthermore, the structural change between the low crystalline μc-Si and the high crystalline μc-Si and the structural change between the low crystalline μc-Si and a-Si are a-Si and high crystalline μc-Si. Therefore, the occurrence of structural defects near the interface in the semiconductor layer 4 can be suppressed. Therefore, it is possible to suppress a decrease in on-characteristics, off-characteristics, and reliability due to traps at the interface, and it is possible to improve device characteristics. Since the low crystalline μc-Si layer 4b functions as a buffer layer, the stress difference between the a-Si layer 4d and the highly crystalline μc-Si layer 4a is alleviated, so that the film adheres to the film. Property can be improved and the occurrence of film peeling can be suppressed.

(Embodiment 4)
A semiconductor device according to the fourth embodiment will be described. In addition, while omitting description about the content which overlaps with this embodiment and Embodiment 1-3, the same code | symbol was attached | subjected about the structural member which exhibits the same function. FIG. 9 is a schematic cross-sectional view of the semiconductor device of the fourth embodiment.

As shown in FIG. 9, the semiconductor device 104 differs from the semiconductor device 103 according to the third embodiment in the configuration of the semiconductor layer 4. That is, the semiconductor layer 4 includes, in order from the contact layer 5 side, the a-Si layer 4d, the crystallinity change μc-Si layer 4c, and the crystallinity of the crystallinity change μc-Si layer or higher. And a highly crystalline μc-Si layer 4a having the same structure. Thus, the semiconductor device 104 has the crystallinity change μc-Si layer 4c as a buffer semiconductor layer.

About the manufacturing method of the semiconductor device of Embodiment 4, since it can produce easily by using suitably the manufacturing method of the above-mentioned Embodiment 1-3, the description is abbreviate | omitted. The film thicknesses of the high crystalline μc-Si layer 4a, the crystalline change μc-Si layer 4c, and the a-Si layer 4d are preferably 20 to 70 nm and 5 to 5 nm, respectively, from the same viewpoint as in the third embodiment. 25 nm and 5 to 30 nm.

According to the semiconductor device 104, since the a-Si layer 4d having a high resistance value and a wide band gap is disposed at a position in contact with the contact layer 5, more effective leakage current reduction, that is, more effective. The off characteristics can be improved. In addition, the highly crystalline μc-Si layer 4a contains microcrystals and has a higher mobility than the a-Si layer 4d, and thus can exhibit excellent on characteristics. Further, since the crystalline change μc-Si layer 4c has a relatively small crystallization rate on the a-Si layer 4d side and a relatively large crystallization rate on the high crystalline μc-Si layer 4a side, Generation of structural defects in the vicinity of the interface in the semiconductor layer 4 can be suppressed. Therefore, it is possible to suppress a decrease in on-characteristics, off-characteristics, and reliability due to traps at the interface, and it is possible to improve device characteristics. Since the crystalline change μc-Si layer 4c functions as a buffer layer, the stress difference between the a-Si layer 4d and the highly crystalline μc-Si layer 4a is alleviated. Property can be improved and the occurrence of film peeling can be suppressed.

(Embodiment 5)
A semiconductor device according to the fifth embodiment will be described. In addition, while omitting description about the content which overlaps with this embodiment and Embodiment 1-4, the same code | symbol was attached | subjected about the structural member which exhibits the same function. FIG. 10 is a schematic cross-sectional view of the semiconductor device of the fifth embodiment.

As shown in FIG. 10, the semiconductor device 105 includes a conductive layer 11 and a contact layer 5 disposed on the insulating substrate 1 below the semiconductor layer 4 other than the region facing the gate electrode 2, and an island-shaped semiconductor in plan view. The structure in which the layer 4, the gate insulating film 3, and the gate electrode 2 are stacked, and the gate insulating film 3, the semiconductor layer 4, and the contact layer 5 are disposed on the gate insulating film 3 in a region facing the contact layer 5. The source / drain electrodes 6 are electrically connected to the semiconductor layer 4 by being bonded to the contact layer 5 and the conductive layer 11 through the contact holes 12 formed in the semiconductor layer 4. As described above, the semiconductor device 105 has a top gate structure. In addition, the semiconductor device 105 includes a passivation film 7 and a planarizing film 8 that are formed so as to cover the insulating substrate 1, and a transparent electrode 9 that is formed on the planarizing film 8 and functions as a pixel electrode.

The semiconductor layer 4 includes, in order from the contact layer 5 side, an a-Si layer 4d, a low crystalline μc-Si layer 4b, a microcrystal, and a larger crystallization rate than the low crystalline μc-Si layer 4b. And a highly crystalline μc-Si layer 4a having the same structure. As described above, the semiconductor device 105 includes the low crystalline μc-Si layer 4b as a buffer semiconductor layer, and includes the same semiconductor layer as that of the third embodiment.

Note that the conductive layer 11 is for ensuring the conduction between the contact layer 5 and the source / drain electrode 6. In such a semiconductor device 105 of this embodiment, the current flowing from the source / drain electrode 6 flows from the conductive layer 11 to the contact layer 5, and the a-Si layer 4 d and the crystallinity change μc-Si. After flowing in the thickness direction to the layer 4c and the highly crystalline μc-Si layer 4a, the layer 4c flows in the plane of the highly crystalline μc-Si layer 4a, and then follows the opposite path to again another source / drain electrode. It will flow to 6. Thus, also in the semiconductor device 105, the source / drain electrode 6 is electrically connected to the semiconductor layer 4 mainly through the contact layer 5.

Below, the manufacturing method of the semiconductor device of Embodiment 5 is demonstrated. 11A to 11E are schematic cross-sectional views of the semiconductor device of Embodiment 5 in each manufacturing process.

First, as shown in FIG. 11A, a titanium (Ti) film is formed on a glass substrate which is an insulating substrate 1 by a sputtering method. Next, as in the first embodiment, an n ⁺ -Si layer is formed as the contact layer 5 by plasma CVD. The thickness of the Ti film is 50 nm, and the thickness of the n ⁺ -Si layer is 60 nm. Thereafter, these are patterned by a photolithography method. A dry etching method is used for etching the laminated film.

Next, an a-Si layer 4d, a crystalline change μc-Si layer 4c, and a highly crystalline μc-Si layer 4a are formed. Here, the a-Si layer 4d is formed by a parallel plate type plasma CVD apparatus, and the high crystalline μc-Si layer 4a having microcrystals and the crystalline change μc-Si layer 4c are formed by a high-density plasma CVD apparatus (ICP). System, surface wave plasma system or ECR system). These films are formed by a multi-chamber apparatus and sequentially formed in a vacuum. The a-Si layer 4d may have the same film formation conditions as a general a-Si TFT process.

The highly crystalline μc-Si layer 4a is formed under the same film forming conditions as in the first embodiment. On the other hand, the film formation condition of the crystalline change μc-Si layer 4c is preferably set within the range of film formation pressure = ^{1 to} 500 mTorr (1.33 × 10 ^{−1 to} 6.66 × 10 Pa), In the present embodiment, the deposition pressure is continuously decreased from 60 mTorr (8.00 Pa) to 5 mTorr (6.66 × 10 ⁻¹ Pa), for example, linearly or trigonometrically, and the SiH ₄ / H ₂ ratio is reduced. = 1/1, substrate temperature = 300 ° C. In this way, by controlling the film formation pressure and the SiH ₄ / H ₂ ratio, it is possible to effectively suppress the generation of particles in the crystallinity change μc-Si layer 4c, and the crystallinity change μc-Si layer 4c. The crystallization rate of can be easily controlled. Further, by continuously reducing the film forming pressure, the crystallinity change μc-Si layer 4c gradually increases in the crystallization rate in the thickness direction. More specifically, in this embodiment, the crystallization rate of the crystallinity change μc-Si layer 4c increases from about 70% to about 10%.

The a-Si layer 4d, the crystalline change μc-Si layer 4c, and the highly crystalline μc-Si layer 4a may be formed using a capacitively coupled CVD apparatus. In this case, film formation conditions for the a-Si layer 4d include film formation pressure = 0.75 to 1.5 Torr (1.00 × 10 ^{2 to} 2.00 × 10 ² Pa), SiH ₄ / H ₂ ratio = Although it is preferable to set within the range of 1/1 to 1/20, in this embodiment, the film forming pressure is 1 Torr (1.33 × 10 ² Pa), and the SiH ₄ / H ₂ ratio is 1/5. . The film formation conditions for the crystalline change μc-Si layer 4c include film formation pressure = 0.70 to 3 Torr (9.33 × 10 to 4.00 × 10 ² Pa), SiH ₄ / H ₂ ratio = 1. In this embodiment, the film forming pressure is set to 1 Torr (1.33 × 10 ² Pa) to 3 Torr (4.00 × 10 ² Pa), and SiH is set. _{The 4} / H ₂ ratio is continuously changed from 1/10 to 1/300, for example, linearly or trigonometrically. Furthermore, film formation conditions for the highly crystalline μc-Si layer 4a include film formation pressure = 1.5 to 3.75 Torr (2.00 × 10 ^{2 to} 500 × 10 ² Pa), SiH ₄ / H ₂ ratio = Although it is preferable to set within the range of 1/50 to 1/400, in this embodiment, after the formation of the crystalline change μc-Si layer 4c, the film formation conditions are maintained as they are, that is, the film formation pressure. = 3 Torr (4.00 × 10 ² Pa), SiH ₄ / H ₂ ratio = 1/300. These films are formed in the same chamber with the substrate temperature = 300 ° C. In this way, by controlling the film forming pressure and the SiH ₄ / H ₂ ratio, particles are generated in the a-Si layer 4d, the crystalline change μc-Si layer 4c, and the highly crystalline μc-Si layer 4a. It is possible to easily control the crystallization rate of each layer while suppressing effectively.

The film thickness of the highly crystalline μc-Si layer 4a is preferably 20 to 70 nm (30 nm in the present embodiment), and the film thickness of the crystalline change μc-Si layer 4c is preferably 5 to 25 nm (in this embodiment). 20 nm), and the film thickness of the a-Si layer 4d is preferably 5 to 30 nm (10 nm in this embodiment). Note that when the film thickness of the highly crystalline μc-Si layer 4a exceeds 70 nm, the off-current may increase remarkably, and when it is less than 20 nm, the on-current may remarkably decrease. Further, when the film thickness of the crystalline change μc-Si layer 4c exceeds 25 nm, the defect density in the crystalline change μc-Si layer 4c may increase remarkably, and when it is less than 5 nm, it does not function as a buffer layer. There is. Furthermore, if the thickness of the a-Si layer 4d exceeds 30 nm, the on-current may be significantly reduced, and if it is less than 5 nm, the off-current may be significantly increased.

The semiconductor layer 4 may or may not have an interface between the constituent layers as in the first embodiment, but from the viewpoint of more effectively suppressing film peeling. It is preferable not to have an interface. In this case, in this embodiment, the high crystalline μc-Si layer 4a, the crystalline change μc-Si layer 4c, and the a-Si layer 4d may be continuously formed. The film formation pressure of the high crystalline μc-Si layer 4a may be changed to the film formation conditions of the crystalline change μc-Si layer 4c and the film formation conditions of the a-Si layer 4d without interruption. On the other hand, when forming an interface between the constituent layers, after forming a constituent layer (in this embodiment, the high crystalline μc-Si layer 4a or the crystalline change μc-Si layer 4c), the constituent layers are once formed. The film may be interrupted, and the next constituent layer (in this embodiment, the crystalline change μc-Si layer 4c or the a-Si layer 4d) may be formed.

Next, as shown in FIG. 11B, the high crystalline μc-Si layer 4a, the changed crystalline μc-Si layer 4c, and the contact layer 5 are patterned by a photolithographic method in the same way as in the first embodiment, and activated. A layer (I island) is formed.

Next, as shown in FIG. 11C, a silicon nitride film (SiNx film) having a film thickness of 400 nm is formed as the gate insulating film 3 by plasma CVD as in the first embodiment. In the present embodiment, a silicon oxide film (SiOx) may be used.

Next, as shown in FIG. 11D, after forming the contact hole 12 by a dry etching method, a titanium (Ti) / aluminum (Al) / titanium (Ti) laminated film is formed by a sputtering method. The film thicknesses are Ti = 50 nm, Al = 100 nm, and Ti = 50 nm, respectively. Then, the gate electrode 2 and the source / drain electrode 6 are formed by etching the laminated film by a wet etching method. Note that an SLA etchant is used as the etchant.

Next, as shown in FIG. 11E, an embodiment which is a pixel switching element in a liquid crystal display device by forming a passivation film 7, a planarizing film 8 and a transparent electrode 9 as in the first embodiment. 5 semiconductor devices 105 can be manufactured.

According to the semiconductor device 105, as in the fourth embodiment, it is possible to reduce the leakage current more effectively, that is, to improve the off characteristic more effectively. In addition, excellent on-characteristics can be exhibited. Further, it is possible to suppress a decrease in on-characteristics, off-characteristics, and reliability due to traps at the interface, and it is possible to improve device characteristics. And generation | occurrence | production of film | membrane peeling can be suppressed. In addition, since the semiconductor device 105 has a top gate structure and the crystallization ratio on the gate insulating film 3 side of the high crystalline μc-Si layer 4a is easily increased, the high crystalline μc-Si layer 4a is Compared with the bottom gate structure, higher mobility can be realized.

(Embodiment 6)
A semiconductor device according to the sixth embodiment will be described. In addition, while omitting description about the content which overlaps with this embodiment and Embodiment 1-5, the same code | symbol was attached | subjected about the structural member which exhibits the same function. FIG. 12 is a schematic cross-sectional view of the semiconductor device of the sixth embodiment.

As shown in FIG. 12, the semiconductor device 106 includes an insulating substrate 1, a semiconductor layer 4 having an island shape in plan view, a contact layer 5 disposed on the semiconductor layer 4 other than a region facing the gate electrode 2, and gate insulation. The structure in which the film 4 and the gate electrode 5 are stacked, and the contact layer 5 is disposed on the gate insulating film 3 in a region facing the contact layer 5 and through the contact hole 12 formed in the gate insulating film 3. And the source / drain electrode 6 electrically connected to the semiconductor layer 4. As described above, the semiconductor device 106 has a coplanar top gate structure.

The semiconductor layer 4 includes, in order from the contact layer 5 side, a low crystallinity μc-Si layer 4b, a high crystallinity μc− that contains microcrystals and has a higher crystallization rate than the low crystallinity μc-Si layer 4b. The Si layer 4a is laminated. As described above, the semiconductor device 106 includes the same semiconductor layer as that in the first embodiment.

Below, the manufacturing method of the semiconductor device of Embodiment 6 is demonstrated. 13A to 13D are schematic cross-sectional views of the semiconductor device of Embodiment 6 in each manufacturing process.

First, as shown in FIG. 13A, a high crystalline μc-Si layer 4a, a low crystalline μc-Si layer 4b, and a contact layer 5 are formed on a glass substrate which is an insulating substrate 1 by a plasma CVD method. A certain n ⁺ -Si layer is formed. Here, the high crystalline μc-Si layer 4a and the low crystalline μc-Si layer 4b having microcrystals are formed by a high-density plasma CVD apparatus (ICP method, surface wave plasma method, or ECR method). These films are formed by a multi-chamber apparatus and sequentially formed in a vacuum. Note that the n ⁺ -Si layer may have the same film formation conditions as those of a general a-Si TFT process, and is formed in the same manner as in the first embodiment.

The high crystalline μc-Si layer 4a and the low crystalline μc-Si layer 4b are formed under the same film forming conditions as in the first embodiment. The film thickness of the highly crystalline μc-Si layer 4a is preferably 20 to 70 nm (40 nm in the present embodiment), and the film thickness of the low crystallinity μc-Si layer 4b is preferably 5 to 25 nm (this embodiment). 10 nm). Note that when the film thickness of the highly crystalline μc-Si layer 4a exceeds 70 nm, the off-current may increase remarkably, and when it is less than 20 nm, the on-current may remarkably decrease. On the other hand, if the thickness of the low crystalline μc-Si layer 4b exceeds 25 nm, the on-current may be significantly reduced, and if it is less than 5 nm, the off-current may be significantly increased.

The semiconductor layer 4 may or may not have an interface between the constituent layers as in the first embodiment, but from the viewpoint of more effectively suppressing film peeling. It is preferable not to have an interface.

Next, after patterning the high crystalline μc-Si layer 4a, the low crystalline μc-Si layer 4b, and the contact layer 5 by a dry etching method to form an active layer (I island), FIG. As shown, the source / drain regions are separated by etching the n ⁺ -Si layer, which is the contact layer 5, by dry etching.

Next, as shown in FIG. 13C, a silicon nitride film (SiNx film) having a film thickness of 400 nm is formed as the gate insulating film 3 by plasma CVD as in the first embodiment. In the present embodiment, a silicon oxide film (SiOx) may be used.

Next, as shown in FIG. 13D, after the contact hole 12 is formed by dry etching, a titanium (Ti) / aluminum (Al) / titanium (Ti) laminated film is formed by sputtering. The film thicknesses are Ti = 50 nm, Al = 100 nm, and Ti = 50 nm, respectively. Then, the gate electrode 2 and the source / drain electrode 6 are formed by etching the laminated film.

Next, as shown in FIG. 12, by forming the passivation film 7, the semiconductor device 106 according to the sixth embodiment which is a pixel switching element in the liquid crystal display device can be manufactured.

According to the semiconductor device 106, as in the first embodiment, the leakage current can be reduced, that is, the off characteristics can be improved. In addition, excellent on-characteristics can be exhibited. Furthermore, excellent on-characteristics can be maintained. In addition, it is possible to suppress a decrease in on-characteristics, off-characteristics, and reliability due to a trap or the like at the interface, and it is possible to improve device characteristics.

1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. (A)-(f) is a cross-sectional schematic diagram of the semiconductor device of Embodiment 1 in each manufacturing process. It is an expanded section schematic diagram of a semiconductor layer at the time of forming a μc-Si layer using a high-density plasma CVD apparatus. It is an expanded section schematic diagram of a semiconductor layer at the time of forming a μc-Si layer using a capacity coupling type CVD apparatus. 6 is a schematic cross-sectional view of a semiconductor device according to Embodiment 2. FIG. (A)-(f) is a cross-sectional schematic diagram of the semiconductor device of Embodiment 2 in each manufacturing process. FIG. 6 is a schematic cross-sectional view of a semiconductor device according to a third embodiment. (A)-(f) is a cross-sectional schematic diagram of the semiconductor device of Embodiment 3 in each manufacturing process. FIG. 6 is a schematic cross-sectional view of a semiconductor device according to a fourth embodiment. FIG. 6 is a schematic cross-sectional view of a semiconductor device according to a fifth embodiment. (A)-(e) is a cross-sectional schematic diagram of the semiconductor device of Embodiment 5 in each manufacturing process. FIG. 10 is a schematic cross-sectional view of a semiconductor device according to a sixth embodiment. (A)-(d) is a cross-sectional schematic diagram of the semiconductor device of Embodiment 6 in each manufacturing process. It is a cross-sectional schematic diagram which shows the conventional semiconductor device (TFT) in which a channel layer consists of amorphous (amorphous) silicon (a-Si). It is a cross-sectional schematic diagram showing a conventional semiconductor device (TFT) whose channel layer is made of microcrystalline silicon (μc-Si). Conventional semiconductor device (Si layer / gate insulating film (GI) = a-Si / SiNx) and another conventional semiconductor device (Si layer / gate insulating film (GI) = μc-Si / SiOx and Si layer / gate insulation) It is a graph which shows the Vgd (gate / drain voltage) -Ids (drain / source current) characteristic of a film | membrane (GI) = (micro | micron | mu) c-Si / SiNx). It is a cross-sectional schematic diagram showing a conventional semiconductor device (TFT) in which a semiconductor layer has a laminated structure of a μc-Si layer and an a-Si layer.

Explanation of symbols

1: Insulating substrate 2: Gate electrode 3: Gate insulating film 4: Semiconductor layer 4a: High crystalline μc-Si layer 4b: Low crystalline μc-Si layer 4c: Crystallinity change μc-Si layer 4d: a-Si layer 4e: μc-Si layer 5: contact layer 6: source / drain electrode 7: passivation film 8: planarization film 9: transparent electrode 10: etching stopper layer 11: conductive layer 12: contact hole 20: photoresist 101, 102, 103, 104, 105, 106, 111, 112, 113: Semiconductor device

Claims (58)

A semiconductor device having a structure in which a gate electrode, a gate insulating layer, and a semiconductor layer are stacked in this order on an insulating substrate, and a structure in which a source / drain electrode is electrically connected to the semiconductor layer through a contact layer. And
In order from the contact layer side, the semiconductor layer includes a low crystalline semiconductor layer in which an amorphous phase and a crystalline phase are mixed, and a high crystalline semiconductor layer having a higher crystallization rate than the low crystalline semiconductor layer. A semiconductor device having the structure described above. A semiconductor device having a structure in which a gate electrode, a gate insulating layer, and a semiconductor layer are stacked in this order on an insulating substrate, and a structure in which a source / drain electrode is electrically connected to the semiconductor layer through a contact layer. And
The semiconductor layer has a structure in which, from the contact layer side, a crystalline change semiconductor layer in which the crystallization rate changes in the thickness direction and a highly crystalline semiconductor layer having a crystallization rate higher than that of the crystalline change semiconductor layer are stacked. Have
The semiconductor device characterized in that the crystallinity change rate of the crystalline change semiconductor layer continuously decreases from the highly crystalline semiconductor layer side to the contact layer side. A semiconductor device having a structure in which a gate electrode, a gate insulating layer, and a semiconductor layer are stacked in this order on an insulating substrate, and a structure in which a source / drain electrode is electrically connected to the semiconductor layer through a contact layer. And
The semiconductor layer includes, in order from the contact layer side, an amorphous semiconductor layer, a low crystalline semiconductor layer in which an amorphous phase and a crystalline phase are mixed, and a high crystallization rate that is higher than that of the low crystalline semiconductor layer. A semiconductor device having a structure in which a crystalline semiconductor layer is stacked. A semiconductor device having a structure in which a gate electrode, a gate insulating layer, and a semiconductor layer are stacked in this order on an insulating substrate, and a structure in which a source / drain electrode is electrically connected to the semiconductor layer through a contact layer. And
The semiconductor layer includes, in order from the contact layer side, an amorphous semiconductor layer, a crystalline change semiconductor layer in which the crystallization rate changes in the thickness direction, and a highly crystalline semiconductor having a crystallization rate higher than that of the crystalline change semiconductor layer Having a layered structure,
The semiconductor device according to claim 1, wherein the crystallinity change semiconductor layer has a crystallization rate that continuously decreases from the highly crystalline semiconductor layer side to the amorphous semiconductor layer side. A semiconductor device having a structure in which a gate electrode, a gate insulating layer, and a semiconductor layer are stacked in this order on an insulating substrate, and a structure in which a source / drain electrode is electrically connected to the semiconductor layer through a contact layer. And
The semiconductor layer has a structure in which an amorphous semiconductor layer, a buffer semiconductor layer containing a crystalline phase, and a highly crystalline semiconductor layer having a crystallization rate higher than that of the buffer semiconductor layer are stacked in this order from the contact layer side A semiconductor device comprising: 6. The semiconductor device according to claim 5, wherein the buffer semiconductor layer includes a stress relaxation layer for relaxing stress generated in the semiconductor layer. 6. The semiconductor device according to claim 5, wherein the buffer semiconductor layer includes a structure compensation layer that compensates for a difference in structure between the amorphous semiconductor layer and the highly crystalline semiconductor layer. The buffer semiconductor layer includes a low crystalline semiconductor layer in which an amorphous phase and a crystalline phase are mixed,
6. The semiconductor device according to claim 5, wherein the high crystalline semiconductor layer has a higher crystallization rate than the low crystalline semiconductor layer. The buffer semiconductor layer is configured to include a crystalline change semiconductor layer whose crystallization rate changes in the thickness direction,
The crystallinity changing semiconductor layer continuously decreases in crystallization rate from the high crystalline semiconductor layer side to the amorphous semiconductor layer side,
6. The semiconductor device according to claim 5, wherein the highly crystalline semiconductor layer has a crystallization rate higher than that of the crystalline change semiconductor layer. 10. The semiconductor device according to claim 8, wherein the buffer semiconductor layer has a thickness of 5 to 25 nm. The semiconductor device according to claim 3, wherein the low crystalline semiconductor layer has a thickness of 5 to 25 nm. The semiconductor device according to claim 4, wherein the crystalline change semiconductor layer has a thickness of 5 to 25 nm. 10. The crystallinity changing semiconductor layer according to claim 2, wherein the crystallization ratio in the vicinity of the interface with the highly crystalline semiconductor layer is substantially equal to the crystallization ratio of the highly crystalline semiconductor layer. A semiconductor device according to claim 1. 10. The semiconductor device according to claim 1, wherein the semiconductor device does not have a clear interface between any adjacent layers of the semiconductor layer constituting layers. . The semiconductor device according to claim 2, wherein the crystalline change semiconductor layer is substantially amorphous on a contact layer side. 6. The semiconductor device according to claim 3, wherein the amorphous semiconductor layer has a thickness of 5 to 30 nm. 6. The semiconductor device according to claim 1, wherein the semiconductor device has a structure in which a gate electrode, a gate insulating layer, and a semiconductor layer are stacked in this order from the insulating substrate side. The semiconductor device according to claim 1, wherein the crystalline phase of the semiconductor layer contains microcrystals. The semiconductor device according to claim 18, wherein the microcrystal is a columnar crystal substantially perpendicular to a surface direction of the semiconductor layer. 20. The semiconductor device according to claim 19, wherein the columnar crystal has a maximum diameter of 10 to 40 nm in a highly crystalline semiconductor layer. The semiconductor device according to claim 1, wherein the highly crystalline semiconductor layer has a crystallization rate of 60% or more. 9. The semiconductor device according to claim 1, wherein the low crystalline semiconductor layer has a crystallization ratio of 30 to 60%. 10. The semiconductor device according to claim 2, wherein the crystallinity-changing semiconductor layer has a crystallization rate that continuously changes between 80% and 0%. The semiconductor device according to claim 1, wherein the highly crystalline semiconductor layer contains microcrystals as a crystalline phase and substantially does not contain an incubation layer. The semiconductor device according to claim 1, wherein the semiconductor layer substantially does not contain particles. 6. The contact layer according to claim 1, wherein the contact layer has a structure in which an amorphous semiconductor layer containing impurities and a crystalline semiconductor layer containing impurities are laminated in order from the semiconductor layer side. A semiconductor device according to claim 1. The contact layer has a structure in which a low concentration impurity semiconductor layer containing a low concentration impurity and a high concentration impurity semiconductor layer containing a higher concentration impurity than the low concentration impurity semiconductor layer are stacked in order from the semiconductor layer side. The semiconductor device according to claim 1, comprising: The contact layer has a sheet resistance value of 5 × 10 ^{7 to} 5 × 10 ⁸ Ω / cm ² and a sheet resistance value of 5 × 10 ⁴ to 1 × 10 ⁶ Ω in order from the semiconductor layer side. 6. The semiconductor device according to claim 1, wherein the semiconductor device has a structure in which a low resistance semiconductor layer of / cm ² is stacked. Manufacturing of a semiconductor device having a structure in which a gate electrode, a gate insulating layer, and a semiconductor layer are stacked in this order on an insulating substrate, and a structure in which a source / drain electrode is electrically connected to a semiconductor layer through a contact layer A method,
The manufacturing method of the semiconductor device includes a step of forming a low crystalline semiconductor layer in which an amorphous phase and a crystalline phase are mixed, and
Forming a high crystalline semiconductor layer having a larger crystallization rate than that of the low crystalline semiconductor layer. Manufacturing of a semiconductor device having a structure in which a gate electrode, a gate insulating layer, and a semiconductor layer are stacked in this order on an insulating substrate, and a structure in which a source / drain electrode is electrically connected to a semiconductor layer through a contact layer A method,
The manufacturing method of the semiconductor device includes a step of forming a crystalline change semiconductor layer so that the crystallization rate continuously changes in the thickness direction;
Forming a highly crystalline semiconductor layer having a crystallization rate equal to or higher than that of the crystalline change semiconductor layer. Manufacturing of a semiconductor device having a structure in which a gate electrode, a gate insulating layer, and a semiconductor layer are stacked in this order on an insulating substrate, and a structure in which a source / drain electrode is electrically connected to a semiconductor layer through a contact layer A method,
The method for manufacturing the semiconductor device includes a step of forming an amorphous semiconductor layer,
Forming a low crystalline semiconductor layer in which an amorphous phase and a crystalline phase are mixed;
Forming a high crystalline semiconductor layer having a higher crystallization rate than the low crystalline semiconductor layer. Manufacturing of a semiconductor device having a structure in which a gate electrode, a gate insulating layer, and a semiconductor layer are stacked in this order on an insulating substrate, and a structure in which a source / drain electrode is electrically connected to a semiconductor layer through a contact layer A method,
The method for manufacturing the semiconductor device includes a step of forming an amorphous semiconductor layer,
Forming a crystalline change semiconductor layer such that the crystallization rate continuously changes;
Forming a highly crystalline semiconductor layer having a crystallization rate equal to or higher than that of the crystalline change semiconductor layer. Manufacturing of a semiconductor device having a structure in which a gate electrode, a gate insulating layer, and a semiconductor layer are stacked in this order on an insulating substrate, and a structure in which a source / drain electrode is electrically connected to a semiconductor layer through a contact layer A method,
The method for manufacturing the semiconductor device includes a step of forming an amorphous semiconductor layer,
Forming a buffer semiconductor layer containing a crystalline phase;
Forming a highly crystalline semiconductor layer having a crystallization rate equal to or higher than that of the buffer semiconductor layer. The buffer semiconductor layer includes a low crystalline semiconductor layer in which an amorphous phase and a crystalline phase are mixed,
34. The method of manufacturing a semiconductor device according to claim 33, wherein the high crystalline semiconductor layer has a crystallization rate larger than that of the low crystalline semiconductor layer. The buffer semiconductor layer is configured to include a crystalline change semiconductor layer whose crystallization rate changes in the thickness direction,
The crystallinity changing semiconductor layer continuously decreases in crystallization rate from the high crystalline semiconductor layer side to the amorphous semiconductor layer side,
34. The method of manufacturing a semiconductor device according to claim 33, wherein the highly crystalline semiconductor layer has a crystallization rate higher than that of the crystalline change semiconductor layer. The method of manufacturing the semiconductor device includes a step of forming a gate electrode,
Forming a gate insulating layer on the gate electrode;
34. A method of manufacturing a semiconductor device according to claim 29, further comprising a step of forming a semiconductor layer on the gate insulating layer. The method for manufacturing the semiconductor device includes a step of forming a contact layer on the semiconductor layer;
37. The method of manufacturing a semiconductor device according to claim 36, further comprising a step of removing a region of the contact layer facing the gate electrode. 37. The method for manufacturing a semiconductor device according to claim 36, wherein the method for manufacturing a semiconductor device includes a step of forming an etching stopper layer on the semiconductor layer. The method of manufacturing the semiconductor device includes a step of forming a semiconductor layer,
Forming a gate insulating layer on the semiconductor layer;
34. A method of manufacturing a semiconductor device according to claim 29, further comprising a step of forming a gate electrode on the gate insulating layer. The semiconductor layer forming step uses a capacitively coupled plasma chemical vapor deposition apparatus or a high density plasma chemical vapor deposition apparatus, and controls each of the semiconductor layer constituent layers by controlling the film forming pressure and / or the reaction gas flow rate ratio. 34. The method of manufacturing a semiconductor device according to claim 22, wherein the method is formed. 34. The method of manufacturing a semiconductor device according to claim 29, wherein the highly crystalline semiconductor layer forming step uses a capacitively coupled plasma enhanced chemical vapor deposition apparatus. 34. The method of manufacturing a semiconductor device according to claim 29, wherein the highly crystalline semiconductor layer forming step uses a high-density plasma chemical vapor deposition apparatus. 43. The method of manufacturing a semiconductor device according to claim 42, wherein the high-density plasma chemical vapor deposition apparatus is an inductively coupled plasma system. 43. The method of manufacturing a semiconductor device according to claim 42, wherein the high-density plasma chemical vapor deposition apparatus is a surface wave plasma system. 43. The method of manufacturing a semiconductor device according to claim 42, wherein the high-density plasma chemical vapor deposition apparatus is an electron cyclotron resonance system. 43. The method for manufacturing a semiconductor device according to claim 42, wherein the highly crystalline semiconductor layer forming step has a film forming pressure of 1.33 * 10 < ^-1 > to 4.00 * 10 Pa. The high crystalline semiconductor layer forming step, using SiH ₄ and _{H 2} as the raw material gas, and the semiconductor device according to claim 42, wherein the _SiH 4 / _{H 2} ratio is 1 / 50-1 / 1 Manufacturing method. Method of manufacturing a semiconductor device, a manufacturing method of a semiconductor device according to any one of claims 29 to 33 which before forming highly crystalline semiconductor layer, and performing a surface treatment with H ₂ plasma. 35. The method of manufacturing a semiconductor device according to claim 29, 31 or 34, wherein the low crystalline semiconductor layer forming step uses a capacitively coupled plasma enhanced chemical vapor deposition apparatus. The low-crystalline semiconductor layer forming step, using SiH ₄ and _{H 2} as the raw material gas, and the semiconductor device according to claim 49, wherein the _SiH 4 / _{H 2} ratio is 1 / 150-1 / 30 Manufacturing method. 35. The method of manufacturing a semiconductor device according to claim 29, 31 or 34, wherein the low crystalline semiconductor layer forming step uses a high-density plasma chemical vapor deposition apparatus. 52. The method of manufacturing a semiconductor device according to claim 51, wherein the low crystalline semiconductor layer forming step has a film forming pressure of 6.66 to 6.66 × 10 Pa. 36. The method of manufacturing a semiconductor device according to claim 30, 32, or 35, wherein the crystalline change semiconductor layer forming step uses a capacitively coupled plasma enhanced chemical vapor deposition apparatus. The crystalline change semiconductor layer forming step uses SiH ₄ and H ₂ as source gases and continuously changes the SiH ₄ / H ₂ ratio within a range of 1/400 to 1/5. 54. A method of manufacturing a semiconductor device according to claim 53. 36. The method of manufacturing a semiconductor device according to claim 30, 32, or 35, wherein the crystallinity-change semiconductor layer forming step uses a high-density plasma chemical vapor deposition apparatus. 56. The method of manufacturing a semiconductor device according to claim 55, wherein the crystalline change semiconductor layer forming step has a film forming pressure of 1.33 × 10 ^{−1 to} 6.66 × 10 Pa. A display device comprising the semiconductor device according to claim 1. 34. A display device comprising a semiconductor device manufactured by the method for manufacturing a semiconductor device according to claim 29.

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