JP2008123130A - Coverage measurement method and device and tracing method and device for module - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce data quantity to be analyzed without giving any influence to the operation of a program at all in measuring the degree of progress of test of a software code (program) in an electronic computer for performing main storage management of a virtual storage system. <P>SOLUTION: A central processing unit (CPU 101) performs log-output of the page walk processing of a memory management unit (MMU103) which is likely to be generated in the case of referring to main storage by a virtual storage system by a page request recording means 104, so that it is possible to measure rough coverage (the degree of progress of test) without giving any influence on the operation of a program at all. Also, it is possible to achieve the trace function by page units by limiting the size of a translation look-aside buffer (TLB102). <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a coverage measuring method and apparatus and a module tracing method and apparatus in a test phase of software development.

  Conventionally, in the field of electronic computer (computer) architecture, a virtual storage system is known as a system for managing main memory by an operating system. When a central processing unit (CPU) tries to refer to the main memory by virtualizing the logical main memory, the logical address of the logical main memory and the real address (physical address) corresponding to the virtual address Is automatically converted and the data of the real address is returned.

  The portion where the data of the real address is arranged is not limited to the main storage device but can be arranged in an auxiliary storage device (such as a magnetic disk). Accordingly, when the electronic computer implements the virtual storage system, the main memory can be used exceeding the capacity upper limit of the main storage device (memory) that has a high unit price and is relatively difficult to increase in capacity.

There are two types of virtual storage methods: the segment method (data that has data in units of addresses has a variable length) and the paging method (data that has data in units of addresses has a fixed length). .
The MMU (memory management unit) plays a central role in the virtual storage system. The MMU performs the conversion between the virtual address and the real address with reference to a page table that is often constructed on the main storage device. This action is called paging.

  In addition, since the processing is slow if the MMU accesses the main storage device via the bus for paging, the MMU uses a paging result cache called TLB (Translation Look-aside Buffer). Often has When the MMU inquires of the virtual address to the TLB, the case where the cache exists is generally called a TLB hit, and the case where the cache does not exist is generally called a TLB miss. In this TLB miss case, an action in which the MMU refers to the paging table on the main storage device is called a page walk.

  On the other hand, in the test phase of software development, the degree of test progress may be expressed by the term “coverage”. This coverage is based on how many functions and declarations of software code (software program) are executed to check for errors, all branch statements are executed to check for errors, etc. Captured at some level / stage.

  Therefore, in order to measure the coverage, conventionally, a recording hook has been taken at all of the function code entry and exit or at all branch statements (this method will be described later in the subject of the present invention). There are problems to do).

  Similarly, in a software code test, an act of “taking a module trace” may be performed in order to debug a failure or error trace remaining in the main memory. In many cases, the module trace is a data area (ring structure) in which a certain memory is recursively used, and a name (symbol) and a return code are sequentially entered for each moved module. It is a conventional method to extract and analyze such traced data with a memory dump or the like (this method also has problems as described later).

In the above-described computer architecture that employs the virtual storage system, as a conventional technical idea including testing the above-mentioned software code in association with a mechanism specific to the virtual storage system, for example, the following There existed patent documents 1 to 3.
Regarding software code testing (particularly, a method for measuring coverage), for example, there is Patent Document 4 below.
The conventional invention described in Patent Documents 1 to 4 will be described below.

  The conventional invention described in Patent Document 1 detects whether or not the TLB is unregistered at the time of memory reference in the virtual memory type computer, particularly when referring to page 18 from the lower right 18th line to page 3 lower left 13th line. If this is the case, it is recognized that the address trace method has a configuration in which a logical address is written to a buffer or an external storage device.

  In the conventional invention described in Patent Document 2, in particular, referring to page 3 from the upper left 19th line to the upper right 18th line, in a microprocessor having a virtual storage mechanism, if a TLB is not hit, an interrupt occurs, a virtual address, etc. This information is stored in the main memory (step S2), and is recognized as a microprocessor with a trace function.

  The conventional invention described in Patent Document 3 is a TLB hit in a computer system, particularly referring to page 5 from upper left line 2 to lower right line 20 and page 7 from upper left line 18 to lower right line 2. The presence / absence is judged (step S12), and if there is no hit, usage status information is recorded on the TLB (steps S13 and S14) (note that the recording destination may be the main memory). It is recognized as a method.

The conventional invention described in Patent Document 4 relates to a program coverage tracing method, reads a source program of an object-oriented programming language, analyzes member functions and function types / factors for each class, and obtains coverage based on the analysis. It is recognized that it has a configuration that generates a load file with embedded examples, and executes and aggregates coverage for each class.
Japanese Patent Laid-Open No. 56-051074 JP 63-082525 A Japanese Patent Laid-Open No. 03-144748 JP 09-251400 A

  However, the above-described prior art has the following problems.

  When all the branches of the program are output, there is a case where data to be locally output becomes enormous when there is a looping process such as memcpy, and it is difficult to extract and analyze data without missing.

  Also, function entry and all exits, and in some cases branch statements, and if a recording hook is inserted, it affects the operation of the program.

  In addition, in an embedded device in which a real-time OS is operating, a measurement method that affects the operation performance may affect the actual operation and may not operate properly.

  In view of the above-described problems of the prior art, the present invention does not affect the operation of the program at the time of measuring the progress of the test of the software code (program), and reduces the amount of data to be analyzed.

  In order to achieve the above object, the invention according to claim 1 is a coverage measuring method by an electronic computer having a memory management unit and a high-speed conversion buffer and performing main memory management by a virtual memory system, When the memory management unit refers to the high-speed translation buffer, the page walk occurs whenever the physical address corresponding to the virtual address is not found and a page walk referring to the page table occurs. A page request recording step for recording the virtual address and the data of the virtual address, and the analysis means performs the test of the software code based on the virtual address and the data recorded by the page request recording step. Coverage characterized by performing the step of measuring the coverage of Di-measurement method.

  The invention according to claim 2 is a module tracing method by an electronic computer having a memory management unit and a high-speed conversion buffer and performing main memory management by a virtual memory method, and executing software code to be tested. Even if the physical address corresponding to the virtual address is not found even when the memory management unit refers to the high-speed translation buffer, the virtual address where the page walk occurs and the virtual address each time the page walk refers to the page table occurs. A page request recording step for recording address data, and the analyzing means performs a step of tracing the module of the software code based on the virtual address and the data recorded by the page request recording step. This is a module tracing method characterized by the following.

  A third aspect of the invention is the module tracing method according to the second aspect, wherein the high-speed conversion buffer is set to have only one entry that can be held. Is the method.

  The invention according to claim 4 is a coverage measuring apparatus comprising a memory management unit and a high-speed conversion buffer and performing main memory management by a virtual memory method, wherein the memory management unit is running during execution of software code to be tested Each time a page walk that refers to a page table occurs even if a physical address corresponding to a virtual address is not found even if it refers to the fast translation buffer, the virtual address at which the page walk has occurred, the data of the virtual address, and A page request recording unit for recording the software code, and an analysis unit for measuring the test coverage of the software code based on the virtual address and the data recorded by the page request recording unit. It is a measuring device.

  The invention according to claim 5 is the coverage measuring apparatus according to claim 4, wherein the page request recording means records the virtual address and data by a FIFO method. is there.

  The invention according to claim 6 is the coverage measuring apparatus according to claim 4 or 5, wherein the page request recording means is in an actual storage area.

  A seventh aspect of the present invention is the coverage measuring apparatus according to any one of the fourth to sixth aspects, wherein the virtual address and the data recorded by the page request recording unit are stored in the analyzing unit. It is a coverage measuring apparatus characterized by having a transmission means to transmit.

  The invention according to claim 8 is a tracing apparatus that includes a memory management unit and a high-speed conversion buffer and performs main storage management by a virtual storage method, and the memory management unit is in execution during execution of software code to be tested. Whenever a page walk that refers to a page table occurs because a physical address corresponding to a virtual address is not found even if the fast translation buffer is referenced, the virtual address at which the page walk has occurred and the data of the virtual address are obtained. A tracing apparatus comprising: a page request recording unit for recording; and an analysis unit for tracing the module of the software code based on the virtual address and the data recorded by the page request recording unit. .

  A ninth aspect of the present invention is the trace apparatus according to the eighth aspect, wherein the page request recording means records the virtual address and data by a FIFO method.

  A tenth aspect of the present invention is the tracing apparatus according to the eighth or ninth aspect, wherein the page request recording means is in a real storage area.

  The invention according to claim 11 is the trace apparatus according to any one of claims 8 to 10, wherein the virtual address and the data recorded by the page request recording means are transmitted to the analyzing means. A tracing device characterized in that it has a transmitting means.

  A twelfth aspect of the present invention is the trace apparatus according to any one of the eighth to eleventh aspects, wherein the high-speed conversion buffer is set to a single number of entries that can be held. It is a trace device.

  According to the present invention, when measuring the progress of software code testing, the program operation is not affected at all, and the amount of data to be analyzed is reduced.

Preferred embodiments of the present invention will be described below with reference to the drawings.
[First Embodiment]
FIG. 1 is a block diagram showing a configuration of an electronic computer 100 corresponding to the first embodiment of the present invention. A brief description of each block is given below.

In FIG. 1, a CPU (Central Processing Unit) 101 is a central processing unit and supports main memory management by a virtual memory system. A memory reference request from the CPU 101 is transmitted to the MMU 103.
An MMU (Memory Management Unit) 103 is a memory management unit, and plays a central role in main memory management using a virtual memory system.

A TLB 102 (Translation Look-aside Buffer) saves the result of conversion between a virtual address (logical address) and a real address (physical address) by the page table 107 as a cache, thereby realizing high-speed processing.
The memory 106 is a main storage device of the electronic computer 100 and holds a page table 107 in an internal storage area.

  The page request recording unit 104 is realized by, for example, a UART (Universal Asynchronous Receiver Transmitter) having a FIFO buffer. The virtual address / physical address, internal symbol information, and the like sent from the MMU 103 via the parallel bus when the following predetermined conditions are satisfied are recorded in a buffer and sent to the external interface 105.

  The external interface 105 is realized by a serial port, for example. After the above data is received from the page request recording means 104, it is sent to the connected external analysis means (not shown in FIG. 1).

In the present embodiment (and the examples described later), the analysis means is set to the outside, which is advantageous for enhancing the flexibility and expandability of the entire system. The present invention should not be construed as being limited to such a configuration, and a configuration in which an analysis unit is installed inside without including the external interface 105 is a modification of the present invention.
Above, description of schematic structure of this embodiment is finished. The operation of this embodiment will be described below.

  Normally, the CPU 101 that supports virtual memory accesses the memory 106 via the MMU 103. The MMU 103 searches the page table 107 on the memory 106 and converts the virtual address and the real address. The search process performed by the MMU 103 is called page walk.

  However, since the performance deteriorates every time the page walk is performed, the TLB 102 caches the conversion result to suppress the occurrence of the page walk.

  In this embodiment, the apparatus having the configuration shown in FIG. 1 is used for software code testing, all page walks generated in the MMU 103 are recorded by the page request recording unit 104, and data is extracted via the external interface 105. Analysis by an external electronic computer (not shown) enables measurement of coverage in units of pages.

  The analysis means roughly measures the path coverage of the software code (path) based on the above data including at least the virtual address and the internal symbol information, and traces the module included in the software code.

According to the above-described embodiment, processing that causes performance degradation that generates a page fault for measurement is unnecessary, so the performance of the actual operation is not affected at all, and the MMU page walk processing is output to the outside as a log. Therefore, there is an effect that a rough coverage rate (coverage) can be measured.
In the above embodiment, data is output only when a TLB miss occurs, so the amount of data to be analyzed is very small.

[Other Embodiments]
The present invention can also be implemented in the modes described below.
In the first embodiment, the TLB is set to have only one buffer. With this configuration, all branches exceeding the page range can be output. Therefore, a trace function in units of pages can be realized.

  The above setting is set by a software program for managing the MMU, that is, a kernel driver of the operating system.

  The kernel driver or the like of the above operating system is provided by a recording medium that can be read by a computer even if it cannot be read by human perception, such as a magnetic or optical disk.

The present invention can also be implemented in the following modes.
In the first embodiment, the buffer in the page request recording unit 104 in FIG. 1 is configured to be a large-capacity built-in memory (in the following embodiment, it is referred to as FIFO). With this configuration, software code test coverage (progress) measurement and module tracing can be executed without loss.

The present invention can also be implemented in the following modes.
In the first embodiment, the buffer in the page request recording unit 104 in FIG. 1 is configured to be allocated to a part of the storage area of the memory 106 that is the main storage of the electronic computer 100. That is, it is shared with the memory 106. With this configuration, software code test coverage (progress) measurement and module tracing can be executed without loss.

  An example for more specifically implementing the first embodiment described above will be presented as Example 1 and will be described with reference to the drawings.

  FIG. 2 is a block diagram showing the configuration of the debugger 200 and the PC 210 corresponding to this embodiment. In addition, the same code | symbol is attached | subjected about the part which is common in FIG. 1, and has no possibility of confusion, and abbreviate | omits description.

  In FIG. 2, the debugger 200 includes a page request recording unit 104 including a FIFO memory 208 and a UART 209 having a function as an external communication unit, and an RS-232C (serial port) 205 as an external interface 105. It is the composition which has. A PC (personal computer) 210 for data analysis is provided outside the debugger 200.

The FIFO memory 208 is a buffer memory of the UART 209 that performs data input / output by a FIFO (First in, First out) method.
The UART 209 converts byte data coming from the parallel bus (a signal path from the MMU 103 or the like) of the debugger 200 into a serial bit stream.
The other parts have already been described in FIG.

The present embodiment is configured as described above and operates as follows.
With reference to FIG. 3, the operation flow of the present embodiment will be described.
FIG. 3 is a timing chart for explaining the operation of the present embodiment.

  In FIG. 3, there are two types of cases, Case A (when a TLB hit) and Case B (when a TLB miss) shown in the figure, and Case B is a characteristic operation of this embodiment. Case A will also be described to assist in understanding case B.

  In step S <b> 301, the CPU 101 issues a request for referring to the virtual address data in an attempt to access the memory 106. Upon receiving this request, the MMU 103 inquires in the TLB 102 whether there is a cache having a hash of the corresponding virtual address and physical address (step S302).

  If there is a cache entry in the TLB 102, the physical memory address (physical address) is returned (step S303). Then, the memory 106 is accessed by extending the request in step S301 (step S304).

In response to the access, the memory 106 returns data of the requested address (real address) (step S305). It should be noted that the fact that there was an entry in the TLB 102 has been accessed once in the past, so here in particular, no data is sent outside via the RS-232C 205.
This is the end of the description of Case A.

Next, the case B will be described.
In case B, when the CPU 101 issues a request to access the memory (step S306), first, the MMU 103 makes an inquiry to the TLB 102 (step S307).

  Case B corresponds to the case where there is no cache entry in the page table 107 in the TLB 102, so the TLB 102 responds to the MMU 103 to that effect (step S308).

Receiving the response, the MMU 103 accesses the memory 106 to refer to the page table 107, which is a conversion table (step S309).
The memory 106 returns the data of the requested address, here the address where the data of the conversion table (page table 107) is placed (step S310).

  Since the address of the physical memory is finally found, the MMU 103 accesses the memory 106 by extending the access request in step S306 (step S312). In response to this access, the memory 106 returns data at the requested address (step S313).

In this embodiment, since a page walk has occurred simultaneously with step S312, the requested address is passed to the FIFO 208 (step S311).
When data is accumulated in the FIFO 208, the UART 209 extracts the data (step S314), and notifies the outside via the RS-232C 205 (step S315).

The analysis PC 210 receives data via the RS-232C 205 (step S316) and performs analysis based on internal symbol information.
This is the end of the explanation for Case B.

  Since the above embodiment uses an external computer as an analysis means, there is an effect that the expandability and flexibility of the entire software code test / debug system can be improved.

  The present invention can be used in a test phase in software development, particularly in software development for a real-time OS embedded device.

It is a block diagram which shows the structure of embodiment of this invention. It is a block diagram which shows the structure of one Example of this invention. It is a timing chart for demonstrating one Example of this invention.

Explanation of symbols

100 electronic computer 101 CPU
102 TLB
103 MMU
104 page request recording means 105 external interface 106 memory 107 page table 200 debugger 205 RS-232C
208 FIFO memory 209 UART
210 PC

Claims (12)

A coverage measurement method by an electronic computer comprising a memory management unit and a high-speed conversion buffer and performing main memory management by a virtual memory method,
While running the software code under test,
Even if the physical address corresponding to the virtual address is not found even if the memory management unit refers to the fast translation buffer, a page walk referring to the page table occurs.
A page request recording step of recording a virtual address where the page walk has occurred and data of the virtual address;
A method for measuring coverage, characterized in that the analysis means performs a step of measuring coverage of the test of the software code based on the virtual address and the data recorded in the page request recording step. A module tracing method by an electronic computer having a memory management unit and a high-speed conversion buffer and performing main memory management by a virtual memory method,
While running the software code under test,
Even if the physical address corresponding to the virtual address is not found even if the memory management unit refers to the fast translation buffer, a page walk referring to the page table occurs.
A page request recording step of recording a virtual address where the page walk has occurred and data of the virtual address;
A module tracing method, wherein the analyzing means performs a step of tracing the module of the software code based on the virtual address and the data recorded in the page request recording step. A module tracing method according to claim 2, comprising:
The module trace method according to claim 1, wherein the high-speed conversion buffer is set to have only one entry that can be held. A coverage measuring device comprising a memory management unit and a high-speed conversion buffer and performing main memory management by a virtual memory method,
While running the software code under test,
Even if the physical address corresponding to the virtual address is not found even if the memory management unit refers to the fast translation buffer, a page walk referring to the page table occurs.
Page request recording means for recording the virtual address where the page walk has occurred, and data of the virtual address;
Analyzing means for measuring coverage of the test of the software code based on the virtual address and the data recorded by the page request recording means;
A coverage measuring apparatus comprising: The coverage measurement apparatus according to claim 4,
The page request recording means records the virtual address and data by a FIFO method. The coverage measurement apparatus according to claim 4 or 5,
The page request recording means is in a real storage area. The coverage measuring apparatus according to any one of claims 4 to 6,
A coverage measurement apparatus comprising: a transmission unit configured to transmit the virtual address and the data recorded by the page request recording unit to the analysis unit. A trace device comprising a memory management unit and a high-speed conversion buffer and performing main storage management by a virtual storage method,
While running the software code under test,
Even if the physical address corresponding to the virtual address is not found even if the memory management unit refers to the high-speed translation buffer, a page walk referring to the page table occurs.
Page request recording means for recording the virtual address where the page walk has occurred, and data of the virtual address;
Analyzing means for tracing the module of the software code based on the virtual address and the data recorded by the page request recording means;
A tracing apparatus comprising: The trace device according to claim 8,
The page request recording means records the virtual address and data by a FIFO method. The trace device according to claim 8 or 9, wherein
The tracing apparatus according to claim 1, wherein the page request recording means is in a real storage area. The trace device according to any one of claims 8 to 10,
A tracing apparatus comprising: a transmission unit configured to transmit the virtual address and the data recorded by the page request recording unit to the analysis unit. The trace device according to any one of claims 8 to 11,
The trace apparatus according to claim 1, wherein the high-speed conversion buffer is set to have only one holdable entry.

Images