JP2008119915A - Capacitive load drive device and liquid droplet jet device using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a capacitive load drive device capable of immediately stopping a drive current of a capacitive load in the event of a malfunction, and a liquid droplet jet device using the same. <P>SOLUTION: A drive current supplied to a capacitive load 24 from a drive signal supply section 12 is detected by a current detection section 14 to be integrated by a signal processing section 16. The integration output of the signal processing section 16 is compared with a specified excessive current value by a comparison section 18. When the integration output exceeds the specified excessive current value, a stopping section 20 stops the supply of the drive current from the drive signal supply section 12. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a capacitive load driving device and an improvement of a droplet ejection device using the capacitive load driving device.

  Conventionally, a droplet discharge device for discharging ink droplets has been used in a printing device or the like, and there is a method of using a piezoelectric element that is a capacitive load as one of means for discharging droplets. . In such a printing apparatus or the like, an abnormal current may flow through the capacitive load due to a malfunction of the droplet discharge head or a malfunction of a switch element that selects a capacitive load such as a piezoelectric element. In particular, when the switch element is composed of CMOS (complementary metal oxide semiconductor), the input voltage of the switch element (the driving voltage of the capacitive load) exceeds the power supply voltage of the switch element, or the input voltage of the switch element is When the value becomes negative, there may be a latchup in which an abnormal current flows.

When such an abnormal current occurs, the capacitive load may be damaged. Therefore, it is necessary to quickly detect and stop the abnormal current. However, in general, since the average value of the abnormal current is often smaller than the normal current value flowing through the droplet discharge device, there is a high possibility that the abnormal current cannot be detected accurately. In view of this, Japanese Patent Application Laid-Open No. 2004-228561 discloses a technique that can easily detect a circuit abnormality in an ink jet recording apparatus.
JP 2001-287355 A

  However, in the above conventional technique, the power consumption of the ink jet recording apparatus is measured, and the occurrence of abnormality is detected based on the measured power consumption. There is a problem that it is difficult to quickly stop the driving current of the capacitive load.

  The present invention has been made in view of the above-described conventional problems, and an object of the present invention is to provide a capacitive load driving device capable of quickly stopping the driving current of a capacitive load when an abnormality occurs, and droplet ejection using the capacitive load driving device. To provide an apparatus.

  In order to achieve the above object, the capacitive load driving device according to claim 1 provides a drive signal supply for supplying a drive signal to a capacitive load based on a voltage signal having the same voltage at the start and end of the cycle. Means, a current detection means for detecting a current flowing through the capacitive load, a signal processing means for performing an integration process on the output signal of the current detection means, and an output signal of the signal processing means is predetermined. Comparing means for comparing with an overcurrent specified value is provided.

  The invention according to claim 2 is the invention according to claim 1, wherein the capacitive load is a capacitive load included in a piezoelectric head.

  According to a third aspect of the present invention, in the first or second aspect of the present invention, the drive signal supply means supplies a drive signal to the capacitive load via a switch element.

  According to a fourth aspect of the present invention, in the above-mentioned third aspect of the present invention, the output of the drive signal supply means is connected to the anode, and a diode is connected to the drive power supply of the switch element to the cathode.

  The invention according to claim 5 is the invention according to any one of claims 1 to 4, wherein a hall element is used for the current detecting means.

  The invention according to claim 6 is the voltage value of the drive signal applied to the voltage signal and the capacitive load in the drive signal supply means according to any one of claims 1 to 5. A voltage amplifying circuit that amplifies the difference between the voltage amplifying circuit, a current mirror circuit provided as a load of the voltage amplifying circuit, and an output signal of the voltage amplifying circuit via the current mirror circuit and supplying the output signal to the capacitive load A voltage-current conversion circuit for converting into a current signal, and when the output signal of the signal processing means exceeds a predetermined overcurrent specified value, the stopping means for stopping the current of the current mirror circuit is the capacitor The drive signal supplied to the sexual load is stopped.

  According to a seventh aspect of the present invention, in the capacitive load driving device according to any one of the first to fifth aspects, the drive signal supply means is a drive applied to the voltage signal and the capacitive load. A pulse modulation circuit that modulates the difference between the voltage value of the signal into a pulse signal, a voltage amplification circuit that amplifies the voltage of the pulse signal output from the pulse modulation circuit, and a drive signal that smoothes the output voltage of the voltage amplification circuit And a filter circuit for supplying to the capacitive load, and a pulse from the pulse modulation circuit to the voltage amplification circuit when the output signal of the signal processing means exceeds a predetermined overcurrent specified value. The stop means for stopping the output of the signal stops the drive signal supplied to the capacitive load.

  The invention of a droplet discharge device according to an eighth aspect is characterized in that the capacitive load is driven by the capacitive load driving device according to any one of the first to seventh aspects to discharge a droplet. .

  According to the present invention, by integrating the drive current of the capacitive load, it is possible to discriminate between the instantaneous current at the normal time and the current at the abnormal time, and it is possible to quickly detect a minute abnormal current.

  In addition, when an abnormal current is detected, the supply of the drive current can be quickly stopped by stopping the circuit that supplies the drive current.

  Hereinafter, the best mode for carrying out the present invention (hereinafter referred to as an embodiment) will be described with reference to the drawings.

  FIG. 1 shows a functional block diagram of an embodiment of a capacitive load driving device according to the present invention. In FIG. 1, the capacitive load driving device 10 includes a drive signal supply unit 12, a current detection unit 14, a signal processing unit 16, a comparison unit 18, and a stop unit 20.

  The drive signal supply unit 12 has a function of supplying a drive signal to the capacitive load 24 based on the voltage signal received from the signal generation unit 22. In this drive signal, the voltage (V1) at the start of the cycle is equal to the voltage (V2) at the end. FIG. 2 shows an example of the waveform of the drive signal.

  The voltage signal generated by the signal generator 22 is a signal having a waveform for driving the capacitive load 24, and the voltage at the start and end of the cycle is set to the same value as in the drive signal. Yes.

  The current detection unit 14 has a function of detecting the current value (drive current value) of the drive signal supplied from the drive signal supply unit 12 to the capacitive load 24, and can be configured by, for example, a Hall element.

となる。 The signal processing unit 16 has a function of integrating the current value detected by the current detection unit 14. If the capacitance of the capacitive load 24 is C and the output voltage of the drive signal supply unit 12 is V (t), the current value I (t) detected by the current detection unit 14 is

It becomes.

Here, as described above, since the voltage signal has the same voltage at the start point and end point of the cycle, the drive current supplied to the capacitive load 24 is 1 as shown in the following equation. The integral value Y of the drive cycle (0 <t <T) is 0 (zero).

となる。 On the other hand, when an abnormal current flows through the capacitive load 24, Y ≠ 0, so that the abnormal current can be detected. For example, if the capacitive load 24 is short-circuited to the GND (ground) by the resistor Rs and an abnormal current flows,

It becomes.

  The comparison unit 18 includes a comparison circuit which is a general hysteresis comparator, compares the integral output Y of the signal processing unit 16 with a predetermined overcurrent specified value, and the integrated output Y has an overcurrent specified value. This function generates a stop instruction when it exceeds the limit. Here, the stop instruction is to set the stop signal output from the comparison unit 18 to the “L” level (0 V). When Y does not exceed the overcurrent regulation value (normal state), the stop signal becomes “H” level.

  The stop unit 20 has a function of causing the drive signal supply unit 12 to stop supplying the drive signal to the capacitive load 24 when the comparison unit 18 issues a stop instruction. A specific configuration will be described later.

  The capacitive load 24 corresponds to, for example, a piezo element and is used for a piezoelectric head or the like.

  FIG. 3 shows a configuration example of a droplet discharge device using the capacitive load driving device according to the present embodiment, and the same elements as those in FIG. 1 are denoted by the same reference numerals. In FIG. 3, the drive signal supply unit 12 supplies drive signals to the plurality of capacitive loads 24 via the switch element 26. The switch elements 26 can be configured by, for example, CMOS, and are provided in the same number as the capacitive load 24. The switch element 26 is opened and closed by a selection signal, and the capacitive load 24 to be operated by supplying the drive signal from the drive signal supply unit 12 is selected.

  The drive current value supplied from the drive signal supply unit 12 to the capacitive load 24 via the switch element 26 is detected by the current detection unit 14. By configuring the current detection unit 14 with a Hall element, it is possible to prevent the waveform of the current supplied to the capacitive load 24 from being deteriorated.

  The signal processing unit 16 includes a filter 28 and an integration circuit 30. The filter 28 is a low-pass filter and removes unnecessary noise included in the detection signal of the current detection unit 14. The integration circuit 30 performs integration processing of the current value supplied to the capacitive load 24.

  In the example of FIG. 3, there is one drive signal supply unit 12 and one example of the number of input signals of the signal processing unit 16, but the present invention is not limited to this. For example, when performing droplet size modulation using a plurality of drive signals for one print head, or when printing at high speed using a plurality of heads (for example, arranging paper widths in an array), the drive signal A plurality of supply units 12 are provided. In this case, a current detection unit 14 is provided for each drive signal supply unit 12, and the detection signals are added and input to the filter 28. With such a configuration, it is possible to detect that the drive current from any one of the drive signal supply units 12 is abnormal in one signal processing unit 16.

  When the switch element 26 is composed of CMOS, an overcurrent may flow from the drive signal supply unit 12 to GND (ground) due to latch-up. This latch-up occurs when a relationship of VAMP> VDD is established between the terminal voltage VAMP on the drive signal supply unit 12 side of the switch element 26 and the voltage VDD for driving the switch element 26. The diode 32 is connected to the anode on the output side of the drive signal supply unit 12 and to the cathode side on the VDD side, and has a function of removing the cause of latch-up by short-circuiting VAMP and VDD when the above condition is satisfied.

  4A and 4B show the operation of the signal processing unit 16 and the comparison unit 18 when the drive current value flowing from the drive signal supply unit 12 to the capacitive load 24 is normal and when an abnormality occurs. An illustration is shown. In FIGS. 4A and 4B, the left vertical axis represents voltage and the right vertical axis represents current. The horizontal axis is time (μ seconds).

  In FIG. 4A, when the drive current value is normal, a current obtained by differentiating the periodic voltage signal flows into the capacitive load 24, and the time average of the drive current value becomes zero. Since the signal processing unit 16 integrates this drive current value, the integral output Y becomes 0 and does not exceed the overcurrent specified value Th. For this reason, the comparison unit 18 maintains the stop signal at the “H” level.

  On the other hand, in FIG. 4B, when an abnormal current flows from the timing of time 250 μs, a DC component that is an abnormal current is superimposed on the drive current flowing through the capacitive load 24. For this reason, the output by the integration operation of the signal processing unit 16 becomes 0 with respect to the periodic drive current, but the DC component is integrated, and the integration output Y of the signal processing unit 16 increases with time. The comparison unit 18 compares the overcurrent regulation value Th with the output Y of the signal processing unit 16. In the example of FIG. 4, the integrated output Y of the signal processing unit 16 is overcurrent regulation in the vicinity of 300 μsec. The value Th is exceeded. At this time, the comparison unit 18 sets the stop signal to the “L” level and outputs a stop instruction to the stop unit 20.

  With the above operation, an abnormal current due to a print head failure or a latch-up of the switch element 26 can be quickly detected and stopped. In the example of FIG. 4B, the detection time is about 50 μs, and an abnormal current can be detected in almost one drive cycle.

  FIG. 5 shows a circuit example of the drive signal supply unit 12 and the stop unit 20. In FIG. 5, transistors Q1 and Q2 constitute a differential amplifier circuit 34, which compares the voltage signal generated by the signal generation unit 22 with the drive voltage of the capacitive load 24 fed back through the feedback circuit 36, and generates an error voltage. Is output. The transistor Q3 constitutes a grounded emitter type voltage amplification circuit, and its load is a current mirror circuit 38 comprising transistors Q4 and Q5. The current mirror circuit 38 functions as a constant current source for the voltage amplifier circuit. The transistor Q11 forms a bias circuit together with the resistors R6 and R7. The transistors Q9 and Q10 are voltage-current conversion circuits that receive the voltage signal output from the transistor Q3 via the current mirror circuit 38 and convert it into a current signal, and supply a drive current to the capacitive load 24. The transistors Q7 and Q8 constitute a buffer circuit that buffers the voltage amplification circuit and the voltage-current conversion circuit.

  The dynamic signal supply unit 12 is configured by the differential amplifier circuit 34, the feedback circuit 36, and the amplifier circuit 40 including the transistors Q3, Q4, Q5, Q7, Q8, Q9, Q10, and Q11 described above.

  Further, a transistor Q12 for controlling the start and stop of the current mirror circuit 38 is connected between the transistor Q4 and the GND constituting the current mirror circuit 38. The drive power supply Vcc is connected to the base of the transistor Q12 via the resistor R15, and a stop signal output from the comparison unit 18 is also input. The transistor Q12 functions as the stop unit 20.

  Here, in the normal state shown in FIG. 4A, the stop instruction is not output from the comparison unit 18, the stop signal output from the comparison unit 18 becomes “H” level, and the transistor Q12 is turned on (conductable). It becomes a state. Note that the “H” level of the stop signal in this example is a high impedance state. When the transistor Q12 is turned on, the transistors Q4 and Q5 are also energized and operate as the current mirror circuit 38. On the other hand, in the state where the abnormal current shown in FIG. 4B is generated, the stop signal becomes “L” level, the base voltage of the transistor Q12 becomes “L” level, and the OFF (non-conducting) state. It becomes. Therefore, no current flows between the emitter and collector of the transistor Q4. In this case, the base potential of the transistor Q5 is VDD and is turned off. By this operation, the transistors Q7 and Q9 are also turned off, and the drive current from the voltage amplifier circuit formed by the transistor Q3 to the switch element 26 and the capacitive load 24 is stopped. Thereby, the abnormal current flowing through the switch element 26 and the capacitive load 24 is quickly stopped, and the switch element 26 and the capacitive load 24 can be protected.

  As shown in FIG. 5, a decoupling capacitor for removing noise is provided in VDD, and since its capacity is large, it takes time for the voltage to drop even if current supply from VDD is stopped ( An abnormal current does not stop immediately. On the other hand, in the present embodiment, the abnormal signal can be quickly stopped by setting the stop signal to the “L” level and stopping the current mirror circuit 38.

  FIG. 6 shows another circuit example of the drive signal supply unit 12 and the stop unit 20, and the same elements as those in FIG. In FIG. 6, an operational amplifier 42 constitutes a differential amplifier circuit 34, which compares the voltage signal generated by the signal generator 22 with the drive voltage of the capacitive load 24 fed back through the feedback circuit 36, thereby generating an error voltage S1. Is output. The comparator 44 compares the error voltage S1 with the voltage of the reference triangular wave S2, generates a pulse width modulation signal S3 corresponding to the error voltage S1, and outputs it to the gate circuit 46. Here, the differential amplifier circuit 34 and the comparator 44 constitute a pulse modulation circuit of the present invention.

  7A and 7B are explanatory diagrams of pulse width modulation in the comparator 44 and stop control in the gate circuit 46. FIG. FIG. 7A shows a normal operation, and FIG. 7B shows a case where an abnormal current occurs. As shown in FIGS. 7A and 7B, the pulse width modulation signal S3 is generated according to the comparison result between the error voltage S1 and the reference triangular wave S2.

  Here, in the normal operation shown in FIG. 7A, the stop signal output from the comparison unit 18 is at the “H” level, and the output of the gate circuit 46 is also the gate output pulse corresponding to the pulse width modulation signal S3. Signals S4 and S5. Since the amplitudes of the gate output pulse signals S4 and S5 are on the order of several volts, the voltage is amplified by the digital voltage amplification circuit 48 in the next stage.

  FIG. 8 shows a circuit example of the digital voltage amplification circuit 48. In FIG. 8, transistors Q13 and Q14 constitute a voltage amplification circuit for the gate output pulse signal S4, and transistors Q23 and Q24 constitute a voltage amplification circuit for the gate output pulse signal S5. The transistors Q17 and Q27 are voltage-current conversion circuits that receive the voltage signal output from the voltage amplification circuit and convert it into a current signal, and supply a drive current to the capacitive load 24. The transistors Q15 and Q16 and the transistors Q25 and Q26 constitute a buffer circuit that buffers the voltage amplification circuit and the voltage-current conversion circuit.

  The gate output pulse signals S4 and S5 amplified by the digital voltage amplifier circuit 48 are smoothed by the filter circuit 50 including the inductor L1, the resistor R17, and the capacitive load 24, and become the drive signal shown in FIG.

  On the other hand, when an abnormal current occurs, the stop signal becomes “L” level. In this case, the operation of the gate circuit 46 causes the gate output pulse signal S4 to be at the “H” level and S5 to be at the “L” level, as shown in FIG. Q14 is always ON, and the base voltage of the transistor Q15 becomes “L” level and is OFF (non-passage state) As a result, the transistor Q17 that supplies the drive current to the capacitive load 24 is turned OFF, and the capacitance The supply of drive current to the load 24 is stopped, and the gate circuit 46 in this case functions as the stop unit 20.

  6 and 8 described above, the abnormal current can be quickly stopped from being supplied to the capacitive load 24 when the abnormal current is generated.

It is a functional block diagram in one Embodiment of the capacitive load drive device concerning this invention. It is a figure which shows the example of the waveform of a drive signal. It is a figure which shows the structural example of the droplet discharge apparatus using the capacitive load drive device concerning this invention. It is explanatory drawing of operation | movement of a signal processing part and a comparison part when the drive current value which flows into a capacitive load from a drive signal supply part is normal, and when abnormality generate | occur | produces. It is a figure which shows the circuit example of a drive signal supply part and a stop part. It is a figure which shows the other circuit example of a drive signal supply part and a stop part. It is explanatory drawing of the pulse width modulation in a comparator and stop control in a gate circuit. It is a figure which shows the circuit example of a digital voltage amplifier circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Capacitive load drive device, 12 Drive signal supply part, 14 Current detection part, 16
Signal processing unit, 18 comparison unit, 20 stop unit, 22 signal generation unit, 24 capacitive load, 26 switch element, 28 filter, 30 integration circuit, 32 diode, 34 differential amplification circuit, 36 feedback circuit, 38 current mirror circuit , 40 amplifier circuit, 42 operational amplifier, 44 comparator, 46 gate circuit, 48 digital voltage amplifier circuit, 50 filter circuit.

Claims (8)

Drive signal supply means for supplying a drive signal to the capacitive load based on a voltage signal having equal voltages at the start and end of the cycle;
Current detecting means for detecting a current flowing through the capacitive load;
Signal processing means for performing integration processing on the output signal of the current detection means;
Comparison means for comparing the output signal of the signal processing means with a predetermined overcurrent specified value;
A capacitive load driving device comprising:   2. The capacitive load driving device according to claim 1, wherein the capacitive load is a capacitive load included in a piezoelectric head.   3. The capacitive load drive device according to claim 1, wherein the drive signal supply means supplies a drive signal to the capacitive load via a switch element.   4. The capacitive load driving device according to claim 3, further comprising a diode that connects an output of the driving signal supply means to an anode and a driving power source of the switch element to a cathode.   5. The capacitive load driving device according to claim 1, wherein a hall element is used for the current detection means. 6. The capacitive load driving device according to claim 1, wherein the drive signal supply means amplifies a difference between the voltage signal and a voltage value of a drive signal applied to the capacitive load. Voltage amplification circuit, a current mirror circuit provided as a load of the voltage amplification circuit, and an output signal of the voltage amplification circuit via the current mirror circuit, and converted into a current signal supplied to the capacitive load A voltage-current conversion circuit,
When the output signal of the signal processing means exceeds a predetermined overcurrent specified value, the drive signal supplied to the capacitive load is stopped by the stop means for stopping the current of the current mirror circuit. Capacitive load driving device. 6. The capacitive load driving device according to claim 1, wherein the drive signal supply means pulses a difference between the voltage signal and a voltage value of a drive signal applied to the capacitive load. 7. A pulse modulation circuit that modulates the signal, a voltage amplification circuit that amplifies the voltage of the pulse signal output from the pulse modulation circuit, and smoothes the output voltage of the voltage amplification circuit as a drive signal, which is supplied to the capacitive load A filter circuit,
When the output signal of the signal processing means exceeds a predetermined overcurrent prescribed value, the output is supplied to the capacitive load by a stopping means for stopping the output of the pulse signal from the pulse modulation circuit to the voltage amplification circuit. A capacitive load driving device, wherein the driving signal is stopped.   A liquid droplet ejection apparatus, wherein a capacitive load is driven by the capacitive load driving apparatus according to claim 1 to eject liquid droplets.

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