JP2008118237A - Video editing device - Google Patents

Abstract

【Task】
Even when the video is switched, additional information unique to the frame or field is appropriately associated with the video.
[Solution]
The video signal selector switch 12 selects one of the video signals 32 and 36. The selected video signal is stored in the frame buffer 20 via the time code separation device 16 and the decoding device 18. The control circuit 25 controls the video signal to be read from the frame buffer 20 and the time code generated by the time code generation device 24 according to the operation status of the decoding device 18. The frame buffer 20 reads the designated video signal in synchronization with the reference signal from the reference signal generator 22. The signal superimposing device 26 superimposes the time code from the time code generating device 24 on the video signal from the frame buffer 20.
[Selection] Figure 1

Description

  The present invention relates to a video editing apparatus that inputs a video signal from an imaging apparatus such as a digital video camera (DVC), and more specifically to a video editing apparatus that synchronizes a video signal and additional information in units of fields or frames.

  In recent years, with the widespread use of large-screen televisions that support high-definition images, there is an increasing need for shooting with high-definition image quality. In addition, there is a demand for shooting with a plurality of DVCs and editing with a simple system, and various editing modes and methods have been proposed.

For example, Patent Document 1 describes a video signal processing device that performs time axis correction using a memory. When replacing the synchronizing signal of the video signal read from the memory with the reference synchronizing signal, data in the vertical blanking period is prevented from being lost.
JP 05-130568 A

  SDI (Serial Digital Interface) signals are widely used for transmission of video signals between video devices in broadcasting stations and studios. Broadcast stations, studios, and the like use house sync signals to synchronize time when editing is performed. An editor or the like has a frame synchronization function, and synchronizes the video signal to transmit the SDI signal. The decoder of the editing machine that handles the encoded video signal also has a frame synchronization function.

  When additional information specific to a frame or field such as VITC (Vertical Interval Time Code) is superimposed on the video signal input to the decoder, the video signal decoded by the decoder also supports the frame or field. The attached additional information must be superimposed.

  However, when synchronizing the time using a house sync signal, when one frame is skipped in the decoding process or when the same frame is repeatedly output, the decoded video signal is processed. It is difficult to accurately associate additional information unique to a frame or field.

  In view of the above problems, an object of the present invention is to provide a video editing apparatus having a simple configuration capable of appropriately associating additional information unique to a frame or field with a video.

  In order to achieve the above object, a video editing apparatus according to the present invention includes a video selection means for selecting one of a plurality of input videos, and a video processing means for processing a video selected by the video selection means. A video buffer for storing the video processed by the video processing means, additional information generating means for generating additional information specific to the frame or field, and additional information generated by the additional information generating means A superimposing unit that superimposes the video read from the buffer and a control unit that controls additional information generated by the additional information generating unit according to a processing status of the video processing unit.

  According to the present invention, even when the video is switched, video can be continuously output by superimposing appropriate additional information unique to the frame or field.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a schematic block diagram of a video editing apparatus according to an embodiment of the present invention. A video signal 32 is input from the imaging device 30 and a video signal 36 is input from the imaging device 34 to the video editing device 10. The video signals 32 and 36 are, for example, encoded elementary streams (ES).

  The video signal selector switch 12 of the video editing device 10 selects either the video signal 32 from the imaging device 30 or the video signal 36 from the imaging device 34. Then, the selected video signal is supplied to the video signal detection device 14 and the time code separation device 16.

  The vertical synchronization detection device 14 detects a frame pulse (INPUT_Frame) or a vertical synchronization signal Vsync from the video signal 32 or 36 selected by the video signal changeover switch 12. The vertical synchronization detection device 14 applies the detected frame pulse to the frame buffer 20. Although details will be described later, the frame buffer 20 takes in the output data of the decoding device 18 in synchronization with the frame pulse Vsync from the vertical synchronization detection device 14.

  The time code separation device 16 separates, that is, deletes the time code as additional information added to each frame or field from the video signal 32 or 36 selected by the video signal changeover switch 12. The time code separation device 16 supplies the video signal from which the time code has been removed to the decoding device 18. In this way, regardless of which video signal 32 or 36 is selected by the switch 12, the encoded video signal from which the additional information is removed is input to the decoding device 18. When the decoding device 18 ignores the additional information when decoding the encoded video signal, the time code separation device 16 is unnecessary.

  The decoding device 18 decodes the encoded video signal from the time code separation device 16 by a method according to the encoding method, and applies the video signal restored by the decoding to the frame buffer 20. The frame buffer 20 takes in the output video signal of the decoding device 18 in accordance with the frame pulse Vsync from the vertical synchronization detection device 14. The frame buffer 20 has a capacity capable of storing video signals for several frames.

  The reference signal generator 22 includes a self-running oscillator, generates a reference vertical synchronization signal, that is, a vertical synchronization reference signal Vsync-ref, and applies it to the frame buffer 20 and the time code generator 24.

  The time code generation device 24 generates a unique time code for each frame or each field in synchronization with the vertical synchronization reference signal Vsync-ref and applies it to the signal superimposing device 26. The control circuit 25 monitors the decoding state in the decoding device 18, and the time code generated by the time code generation device 24 according to the decoding state of the decoding device 18 at the rising edge of the vertical synchronization reference signal Vsync-ref. To control. That is, the time code generated by the time code generation device 24 is independent of the time code added to the input video signals 32 and 36, but depends on the decoding state of the decoding device 18. Details of this will be described later in accordance with a specific example.

  The frame buffer 20 reads the stored video signal to the signal superimposing device 26 according to the vertical synchronization reference signal Vsync-ref from the reference signal generating device 22.

  The signal superimposing device 26 superimposes the time code from the time code generating device 24 on the video signal from the frame buffer 20. The superimposition result of the signal superimposing device 26 is output to the outside as the output 40 of the video editing device 10.

  The frame synchronization function of the video editing apparatus 10 will be described. For convenience of explanation, it is assumed that the delay due to the decoding process of the decoding device 18 is one frame. 2 to 5, the frames of the video signal 32 are denoted by Fa1 to Fa7, and the frames of the video signal 36 are denoted by Fb1 to Fb7. 1 to 7 are frame numbers.

  First, the operation when the period of the vertical synchronization reference signal Vsync-ref is slightly shorter than the frame pulse period of the video signals 32 and 36 will be described with reference to FIGS.

  FIG. 2 shows a timing chart when the video signal 32 is continuously selected. FIG. 2A shows a frame pulse Vsync detected by the vertical synchronization detector 14. (2) is a video signal (frame) selected by the switch 12. (3) is an output video signal (frame) of the decoding device 18. (4) is the vertical synchronization reference signal Vsync-ref output from the reference signal generator 22. (5) is a video signal (frame) read out from the frame buffer 20. (6) is a time code generated by the time code generator 24.

  In the example shown in FIG. 2, the cycle of the vertical synchronization reference signal Vsync-ref is slightly shorter than the cycle of the vertical synchronization signal of the selected video signal 32. Therefore, the next frame Fa4 does not exist in the frame buffer 20 at the rising edge of the vertical synchronization reference signal Vsync-ref after the frame Fa3 is read from the frame buffer 20. This fact can be recognized by the control circuit 25 by continuously monitoring the operating state of the decoding device 18. When this situation is detected, the control circuit 25 instructs to read the frame Fa3 from the frame memory 20 again, and instructs the time code generation circuit 24 to repeatedly output the same time code value. As a result, as shown in FIG. 2 (5), the frame Fa3 is repeated twice as an output frame. As shown in FIG. 2 (6), the same time code “3” is applied to the two same frames Fa3. "Is added.

  FIG. 3 shows that the changeover switch 12 is immediately switched from the video signal 32 to the video signal 36 in response to a user instruction before or during the decoding of the frame Fa4 of the video signal 32 by the decoding device 18. The timing chart in the case is shown. FIG. 3A shows a frame pulse Vsync detected by the vertical synchronization detection device 14. (2) is a video signal (frame) selected by the switch 12. (3) is an output video signal (frame) of the decoding device 18. (4) is the vertical synchronization reference signal Vsync-ref output from the reference signal generator 22. (5) is a video signal (frame) read out from the frame buffer 20. (6) is a time code generated by the time code generator 24.

  In the example of FIG. 3, after the first frame Fa 3 is read from the frame buffer 20, neither the next frame Fa 4 nor the frame Fb 1 of the video signal after switching is stored in the frame buffer 20. Therefore, the control circuit 25 instructs rereading of the last frame Fa3 of the video signal 32 before switching, and instructs the time code generation circuit 24 to repeatedly output the same time code value. This operation is repeated until the frame Fb1 of the video signal after switching is also stored in the frame buffer 20.

  Eventually, after the frame Fa3 is read from the frame buffer 20, at the time of three rises of the vertical synchronization reference signal Vsync-ref, the next frame Fa4 of the video signal 32 is also transferred to the frame buffer 20 after the switching. This frame Fb1 also does not exist. In this way, in the example shown in FIG. 3, the frame Fa3 of the video signal before switching is repeatedly output four times, and the same time code “3” is added to these frames. After that, the frames Fb1 and Fb2 of the video signal 36 after switching are output in order with time codes “1” and “2” added thereto, respectively.

  In FIG. 4, in response to a user switching instruction from the video signal 32 to the video signal 36, after the decoding process of the last frame Fa 4 of the video signal 32 is completed and stored in the frame buffer 20, the changeover switch 12 performs the video switching. A timing chart when the signal 32 is switched to the video signal 36 is shown. The difference from FIG. 3 is that the frame Fa4 of the video signal 32 can be output, and the timing code generated by the time code generator 24 is also updated accordingly. FIG. 4A is a frame pulse Vsync detected by the vertical synchronization detection device 14. (2) is a video signal (frame) selected by the switch 12. (3) is an output video signal (frame) of the decoding device 18. (4) is the vertical synchronization reference signal Vsync-ref output from the reference signal generator 22. (5) is a video signal (frame) read out from the frame buffer 20. (6) is a time code generated by the time code generator 24.

  In the example shown in FIG. 4, after the first frame Fa3 is read from the frame buffer 20, neither the next frame Fa4 nor the frame Fb1 of the switched video signal 36 is stored in the frame buffer 20. Therefore, the same time code “3” is added to the frame Fa3 and repeatedly output.

  At the time when the vertical synchronization reference signal Vsync-ref subsequently rises, the frame Fa4 of the video signal 32 is stored in the frame buffer 20, and the frame Fb1 of the video signal 36 after switching is not stored. At this time, the frame Fa4 of the video signal before switching is output with the time code “4” added.

  Further, the next frame Fa4 of the switched video signal 36 is stored in the frame buffer 20 at the rising edge of the next vertical synchronization reference signal Vsync-ref, and the frame Fb1 of the switched video signal 36 is not stored. . At this time, the frame Fa4 of the video signal 32 before switching is output again with the time code “4” added.

  After the frame Fa4 is output twice, the next frame Fb1 of the switched video signal 36 is stored in the frame buffer 20 at the rising edge of the vertical synchronization reference signal Vsync-ref. At this time, the control circuit 25 instructs the frame buffer 20 to read the frame Fb1, and instructs the time code generation circuit 24 to update the time code.

  In this way, in the example shown in FIG. 4, after the frame Fa3 of the video signal 32 before switching is output twice and the frame Fa4 is output twice, the frame Fb1 of the video signal 36 after switching is output. The same time code is added to each of the frames Fa3 and Fa4 that are output a plurality of times, and a unique time code that is different for each frame is added to the video signal after switching.

  When the same frame is repeatedly output, different time codes may be assigned without giving the same time code to the same frame. FIG. 5 is a timing chart in the case of assigning different time codes to the same frames Fa3 and Fa4 in the same example as shown in FIG. FIG. 5A shows a frame pulse Vsync detected by the vertical synchronization detector 14. (2) is a video signal (frame) selected by the switch 12. (3) is an output video signal (frame) of the decoding device 18. (4) is the vertical synchronization reference signal Vsync-ref output from the reference signal generator 22. (5) is a video signal (frame) read out from the frame buffer 20. (6) is a time code generated by the time code generator 24.

  In the example shown in FIG. 5, the control circuit 25 instructs the timing code generation device 24 to update the time code for the output of the same frame.

  With reference to FIGS. 6 and 7, the operation when the period of the vertical synchronization reference signal Vsync-ref is slightly longer than the frame pulse period of the video signals 32 and 36 will be described.

  FIG. 6 shows a timing chart when the video signal 32 is continuously selected. FIG. 6 (1) shows a frame pulse Vsync detected by the vertical synchronization detector 14. (2) is a video signal (frame) selected by the switch 12. (3) is an output video signal (frame) of the decoding device 18. (4) is the vertical synchronization reference signal Vsync-ref output from the reference signal generator 22. (5) is a video signal (frame) read out from the frame buffer 20. (6) is a time code generated by the time code generator 24.

  In the example shown in FIG. 6, the decoding of the frame Fa4 is started at the third rise and the second rise of the vertical synchronization reference signal Vsync-ref, and it can be read from the frame buffer 20. Therefore, as shown in FIG. 6 (5), after reading the frame Fa2, the frame Fa3 is skipped and the frame Fa4 is read from the frame buffer 20.

  As described above, in the example illustrated in FIG. 6, thinning is appropriately performed because the period of the vertical synchronization reference signal Vsync-ref is long. However, regarding the time code, the continuity of the original video is respected and the time code is skipped in consideration of thinning. That is, when skipping a frame to be read from the frame buffer 20, the control circuit 25 causes the time code generation device 24 to generate the skipped time code in the same manner.

  FIG. 7 shows a timing chart of an example in which the video signal 32 is continuously selected and the time code is not skipped even if the frame is skipped. FIG. 7A shows a frame pulse Vsync detected by the vertical synchronization detector 14. (2) is a video signal (frame) selected by the switch 12. (3) is an output video signal (frame) of the decoding device 18. (4) is the vertical synchronization reference signal Vsync-ref output from the reference signal generator 22. (5) is a video signal (frame) read out from the frame buffer 20. (6) is a time code generated by the time code generator 24.

  In the example illustrated in FIG. 7, the control circuit 25 causes the time code generation device 24 to generate a different time code for each frame regardless of whether or not to skip a frame read from the frame buffer 20.

  Although the time code is exemplified as the information added to the frame, other information that should be unique to the frame can be the additional information of the present invention.

It is a schematic block diagram of one Example of this invention. It is a timing chart of the 1st operation example of a present Example. It is a timing chart of the 2nd operation example of a present Example. It is a timing chart of the 3rd operation example of a present Example. It is a timing chart of the 4th example of operation of this example. It is a timing chart of the 5th operation example of a present Example. It is a timing chart of the 6th operation example of a present Example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Video editing apparatus 12 Video signal changeover switch 14 Vertical synchronization detection apparatus 16 Time code separation apparatus 18 Decoding apparatus 20 Frame buffer 22 Reference signal generation apparatus 24 Time code generation apparatus 25 Control apparatus 26 Signal superimposition apparatus

Claims (3)

Video selection means (12) for selecting one of a plurality of input videos;
Video processing means (18) for processing the video selected by the video selection means;
A video buffer (20) for storing video processed by the video processing means;
Additional information generating means (24) for generating additional information specific to the frame or field;
Superimposing means (26) for superimposing the additional information generated by the additional information generating means on the video read from the video buffer;
Control means (25) for controlling the additional information generated by the additional information generating means according to the processing status of the video processing means
And a video editing apparatus.   The video editing apparatus according to claim 1, wherein the additional information is a time code.   The video editing apparatus according to claim 1, wherein the control unit further controls reading of the video from the video buffer according to a processing status of the video processing unit.

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