JP2008112926A - THIN FILM TRANSISTOR, ITS MANUFACTURING METHOD, LIQUID CRYSTAL DISPLAY DEVICE, AND OLED LIQUID CRYSTAL DISPLAY DEVICE - Google Patents

Abstract

A thin film transistor realizing a TFT structure in which a good drain current flows even with a small drain voltage and a method for manufacturing the same are obtained.
A gate electrode is formed on a glass substrate, an a-Si layer is disposed on the gate electrode via a gate insulating film, and an ohmic contact layer is formed on the a-Si layer. A thin film transistor that has a source electrode 3A and a drain electrode 4A arranged via each other, and forms a channel region in a facing portion between the source electrode 3A and the drain electrode 4A, and the ohmic contact layer 12A includes an a-Si The source electrode 3A and the drain electrode 4A are directly connected to the portion of the a-Si layer 2 where the channel layer 2a is formed via the ohmic contact layer 12A. It is configured as follows.
[Selection] Figure 1

Description

  The present invention relates to a thin-film transistor (TFT) having a bottom gate structure and a method for manufacturing the same, and a liquid crystal display device and an OLED display device using the thin film transistor, and in particular, between a source electrode and a channel layer, and a drain electrode The present invention relates to a thin film transistor in which a resistance component between a channel layer is reduced and a drain current is secured, a manufacturing method thereof, a liquid crystal display device, and an OLED display device.

Conventionally, for example, a thin film transistor having a bottom gate structure is used in a driving circuit such as a liquid crystal display device.
In this type of thin film transistor, first, a gate electrode and a gate insulating film are formed on an insulating substrate (glass substrate), and then an intrinsic semiconductor layer (i · a-Si) is formed on the gate electrode via the gate insulating film. Layer) and an ohmic contact layer (low resistance semiconductor layer: n ⁺ a-Si layer) are simultaneously patterned and formed on the semiconductor layer composed of the intrinsic semiconductor layer and the low resistance semiconductor layer via the ohmic contact layer. An electrode is formed, and finally, an ohmic contact layer in a region excluding the source electrode and the drain electrode is removed (see, for example, Patent Document 1).

FIG. 12 is a plan view schematically showing the conventional thin film transistor disclosed in Patent Document 1 in a simplified manner.
In FIG. 12, a thin film transistor (TFT) includes a gate electrode 1 formed so as to correspond to a channel region having a channel width W and a channel length L, and amorphous silicon formed on the gate electrode 1 via a gate insulating film. A layer (hereinafter referred to as “a-Si layer”) 2, and a source electrode 3 and a drain electrode 4 disposed on the a-Si layer (semiconductor layer) 2 so as to face each other.

Although not recognized in the plan view of FIG. 12, an ohmic contact layer (low level) is provided between the source electrode 3 and the drain electrode 4 and the a-Si layer (an intrinsic semiconductor layer, i · a-Si layer described later) 2. A resistive semiconductor layer, an n ⁺ -type a-Si layer) is interposed. As a result, the channel region between the source electrode 3 and the drain electrode 4 forms a TFT structure that operates as an n ^- channel by applying a positively charged gate voltage Vgs (described later with reference to FIG. 13).
In FIG. 12, illustration of an insulating substrate (glass substrate) on which the gate electrode 1 is formed and a gate insulating film covering the upper surface of the gate electrode 1 is omitted in order to avoid the complexity of the drawing. In addition, the shapes of the source electrode 3 and the drain electrode 4 are simplified here.

13 is a cross-sectional view taken along line AA ′ in FIG.
In FIG. 13, the thin film transistor is formed on the glass substrate (insulating substrate) 10, the gate electrode 1 formed on the glass substrate 10 so as to correspond to the channel region, and the glass substrate 10 so as to cover the gate electrode 1. The gate insulating film 11, the a-Si layer 2 formed on the gate electrode 1 through the gate insulating film 11 so as to be positioned in the channel region of the TFT, and the a-Si layer 2 are opposed to each other. The source electrode 3 and the drain electrode 4, and the ohmic contact layer 12 formed in the contact surface of the a-Si layer 2 and each electrode 3 and 4 are comprised.

An ohmic contact layer 12 is formed on the upper surface of the a-Si layer 2. The source electrode 3 and the drain electrode 4 are disposed opposite to each other on the a-Si layer 2 via the ohmic contact layer 12 to form a TFT structure. A contact portion 13 (see dotted line) is formed at the contact portion between the a-Si layer 2 and the ohmic contact layer 12.
The a-Si layer 2 includes a channel layer 2a that forms a channel having a thickness corresponding to the gate voltage Vgs when a positively charged gate voltage Vgs is applied, and a resistance layer 2b that functions as a resistance component without forming a channel. (Resistance component) can be considered separately.

Next, a manufacturing process of the conventional thin film transistor shown in FIGS. 12 and 13 will be schematically described.
First, the gate electrode 1 of the TFT is formed on the glass substrate 10, and the gate insulating layer 11 is formed on the gate electrode 1 by P (plasma) -CVD.
Subsequently, an i (intrinsic) · a-Si layer is formed on the gate electrode 1 via the gate insulating film 11, and is continuously formed on the upper surface of the i · a-Si layer by a P-CVD method. An ohmic contact layer 12 made of an n ⁺ a-Si layer is formed.

Next, an a-Si island composed of the a-Si layer 2 and the ohmic contact layer 12 is formed by photolithography and etching, and a source / drain electrode material is formed on the a-Si island by sputtering. Form a film. Subsequently, the source electrode 3 and the drain electrode 4 patterned as shown in FIG. 12 are formed by photolithography and etching.
Finally, by dry etching, the ohmic contact layer (n ⁺ a-Si layer) 12 other than both electrodes is removed using the source electrode 3 and the drain electrode 4 as a mask, and a thin film transistor as shown in FIG. 13 is completed. To do.

Next, the operation of the conventional thin film transistor will be described.
In FIG. 13, when a positively charged gate voltage Vgs is applied to the gate electrode 1, a channel serving as an electron path is formed in the channel layer 2 a of the a-Si layer 2. At this time, when a positive drain voltage Vds is applied to the drain electrode 4 and the source electrode 3 is grounded, the drain electrode 4 changes from the drain electrode 4 to the source electrode 3 in the channel layer 2a of the a-Si layer 2 due to the potential difference between the two electrodes. On the other hand, a drain current Ids (see a broken line arrow) depending on the magnitudes of the gate voltage Vgs and the drain voltage Vds flows.

By the way, in a bottom gate type TFT structure generally used in a liquid crystal display device (LCD), as shown in FIG. 13, the a-Si layer 2, the source electrode 3, and the drain electrode 4 are composed of an a-Si layer. 2 are connected via an ohmic contact layer 12 (n ⁺ a-Si layer) formed on the surface of 2.
Therefore, when the drain current Ids flows through the channel layer 2a in the a-Si layer 2, the resistance layer 2b between the drain electrode 4 and the channel layer 2a and the resistance between the channel layer 2a and the source electrode 3 are used. The drain current Ids flows through the layer 2b.

As a result, for example, when the drain voltage Vds decreases, the drain current Ids decreases depending on the thickness of the resistance layer 2b in the a-Si layer 2.
Here, in the TFT / LCD, when writing operation to each liquid crystal cell by the TFT is taken into account, an insufficient image writing occurs due to a decrease in the drain current Ids, and an afterimage phenomenon caused by applying a DC bias to the liquid crystal. A phenomenon that adversely affects image quality occurs.

JP 2004-356646 A

In the conventional thin film transistor, the a-Si layer 2 and the ohmic contact layer 12 are simultaneously formed at the time of manufacture to form an a-Si island, so that the ohmic contact layer 12 is directly connected to the channel layer 2a of the a-Si layer 2. In other words, when the gate voltage Vgs is applied, the drain current Ids flows through the resistance layer 2b of the a-Si layer 2, so that the drain current Ids is reduced.
In particular, when it is used in a liquid crystal display device, there is a problem in that an insufficient image writing occurs due to a decrease in the drain current Ids, which adversely affects image quality.

  The present invention has been made to solve the above-described problems. The source electrode and the drain electrode are connected to the i.a-Si layer (intrinsic semiconductor layer) through the ohmic contact layer (low resistance semiconductor layer). A thin film transistor capable of realizing a TFT structure in which a good drain current flows even with a small drain voltage, a manufacturing method thereof, a liquid crystal display device using the thin film transistor, and a liquid crystal display device using the thin film transistor An object is to obtain an OLED display device.

  A thin film transistor according to the present invention includes a gate electrode formed on an insulating substrate, an intrinsic semiconductor layer disposed on the gate electrode via a gate insulating film, and a low resistance semiconductor layer disposed on the intrinsic semiconductor layer. A low-resistance semiconductor layer is a portion where a channel layer of an intrinsic semiconductor layer is formed (a thin film transistor having a source electrode and a drain electrode), and forming a channel region in a facing portion between the source electrode and the drain electrode ( the source electrode and the drain electrode are configured to be connected to the channel layer of the intrinsic semiconductor layer through the low-resistance semiconductor layer. is there.

  The thin film transistor manufacturing method according to the present invention includes a step of forming a gate electrode on an insulating substrate, a step of forming an island of an intrinsic semiconductor layer on the gate electrode via a gate insulating film, and an island of the intrinsic semiconductor layer. Forming a low-resistance semiconductor layer on the gate insulating film including, and forming a source electrode and a drain electrode through the low-resistance semiconductor layer on the upper portion including the peripheral edge of the island of the intrinsic semiconductor layer, A step of forming a channel region opposite to the drain electrode and a step of removing the low-resistance semiconductor layer excluding the lower portion of the source electrode and the drain electrode, wherein one of the portions where the channel layer of the intrinsic semiconductor layer is formed A low resistance semiconductor layer is formed so as to cover the portion.

  According to the present invention, as in a general MOS transistor, the source electrode and the drain electrode are formed in a TFT structure in which the source electrode and the drain electrode can be in direct contact with the channel layer in the intrinsic semiconductor layer. Therefore, a thin film transistor in which a good drain current flows even with a small drain voltage, a manufacturing method thereof, a liquid crystal display device using the thin film transistor, and an OLED display device can be obtained.

Embodiment 1 FIG.
Hereinafter, the thin film transistor according to the first embodiment of the present invention will be described in detail with reference to the drawings.
Here, as described above, a case where an a-Si layer (amorphous silicon layer) is used as the intrinsic semiconductor layer and the low-resistance semiconductor layer will be described as an example.

FIG. 1 is a plan view schematically showing a thin film transistor according to the first embodiment of the present invention. The same components as those described above (see FIG. 12) are denoted by the same reference numerals as those described above or “ Detailed description is omitted with “A”. Also in FIG. 1, in order to avoid complication, illustration of an insulating substrate and a gate insulating film (described later with reference to FIG. 2) is omitted.
In FIG. 1, the source electrode 3 </ b> A and the drain electrode 4 </ b> A are formed so as to be directly connected to a part of the portion of the a-Si layer 2 where the channel layer 2 a is formed. Although not recognized in the plan view of FIG. 1, an ohmic contact layer 12A is interposed on the entire lower surface of the source electrode 3A and the drain electrode 4A.

FIG. 2 is a cross-sectional view taken along the line BB ′ in FIG. 1, and the same components as those described above (see FIG. 13) are denoted by the same reference numerals as those described above or denoted by “A” after the reference numerals. Detailed description is omitted.
In FIG. 2, the thin film transistor according to the first embodiment of the present invention is formed on the glass substrate 10 so as to cover the gate electrode 1 and the gate electrode 1 formed on the glass substrate 10 so as to correspond to the channel region. A gate insulating film 11, an a-Si layer 2 formed on the gate insulating film 11 so as to be positioned in the channel region, a source electrode 3A and a drain electrode 4A disposed on the a-Si layer 2 to face each other, and an ohmic contact layer 12A formed between the a-Si layer 2 and the source electrode 3A and the drain electrode 4A.

In this case, the ohmic contact layer 12A is formed so as to cover the side surface of the peripheral end portion of the a-Si layer 2, and is in contact with the side surface of the channel layer 2a.
Thereby, the contact portion 13A with the ohmic contact layer 12A is also formed on the side surface of the channel layer 2a. Therefore, when the positively charged gate voltage Vgs is applied, the source electrode 3A and the drain electrode 4A are directly connected to the channel layer 2a via the contact portion 13A of the ohmic contact layer 12A, so that the drain current Ids (broken arrow) Flows without going through the resistance layer 2b.

Next, a method for manufacturing the thin film transistor according to the first embodiment of the present invention shown in FIGS. 1 and 2 will be described with reference to the plan views of FIGS.
First, in FIG. 3 (first step), the gate electrode 1 is formed on the glass substrate 10 so as to correspond to the channel region.

  Subsequently, in FIG. 4 (second step), the gate insulating film 11 is formed on the glass substrate 10 by the P-CVD method so as to cover the entire glass substrate 10 including the upper surface of the gate electrode 1 and continuously. Then, an i · a-Si layer is formed on the gate insulating film 11 so as to be located in the channel region, and then an island of the a-Si layer 2 is formed by photolithography and etching.

Next, in FIG. 5 (third step), the entire upper surface of the glass substrate 10 including the gate electrode 1, the gate insulating film 11, and the a-Si layer 2 is made of an n ⁺ a-Si layer by P-CVD. The ohmic contact layer 12A is formed, and then a source / drain electrode material is formed on the ohmic contact layer 12A by sputtering, and the a-Si layer 2 via the ohmic contact layer 12A is formed by photolithography and etching. A source electrode 3A and a drain electrode 4A are formed so as to face each other.

In FIG. 5 (third step), only the ohmic contact layer 12A (n ⁺ a-Si layer) on the a-Si layer 2 is typically shown, but at this stage, the ohmic contact layer 12A is The glass substrate 10 including the gate insulating film 11 is also formed.

Finally, in FIG. 6 (fourth step), all the ohmic contact layers 12A except for the lower portions of the source electrode 3A and the drain electrode 4A are removed by dry etching, and the ohmic contact between the source electrode 3A and the drain electrode 4A is removed. The contact layer 12A is removed. Thereby, the thin film transistor shown in FIGS. 1 and 2 is formed.
That is, there is always an ohmic contact layer 12A in contact with the side surface of the peripheral edge of the a-Si layer 2 immediately below the source electrode 3A and the drain electrode 4A. The source electrode 3A and the drain electrode 4A It will always overlap with the end of the two islands.

As described above, according to the first embodiment of the present invention, after the gate insulating film 11 and the i.a-Si layer are formed by P-CVD, the gate in which the transistor is formed using photolithography and etching techniques. After the island of the a-Si layer 2 is formed on the inner side of the electrode 1, the ohmic contact layer 12A (n ⁺ a-Si layer) is formed by P-CVD so that the side surface portion of the island of the a-Si layer 2 is also formed. Then, the source electrode 3A and the drain electrode 4A are formed on the gate electrode 1 through the gate insulating film 11 and the ohmic contact layer 12A, and the extra ohmic contact layer 12A is formed. The TFT structure is obtained by removing.

As a result, the channel layer 2a formed in the a-Si layer 2 by the application of the gate voltage Vgs is directly connected to the source electrode 3A and the drain electrode 4A through the ohmic contact layer 12A. Similar to the conventional MOS transistor, a TFT structure in which a current can flow without using the resistance layer 2b can be realized even in a bottom gate thin film transistor.
Therefore, even with a low drain voltage Vds, the drain current Ids with reduced resistance loss can be flowed satisfactorily.
Further, due to the decrease in write resistance, for example, insufficient writing to the liquid crystal of the liquid crystal display device can be reduced.

  FIG. 7 is a characteristic diagram showing an increase effect of the drain current Ids according to the first embodiment of the present invention. Each gate voltage Vgs (Vgs = 20 [V], 15 [V], 10 [V], 5 [V]) ) Shows the relationship between the drain voltage Vds (horizontal axis) and the drain current Ids (vertical axis). In FIG. 7, the dotted line curve shows the characteristics of the conventional TFT structure (see FIGS. 12 and 13), and the solid line curve shows the characteristics of the TFT structure of Embodiment 1 (see FIGS. 1 and 2) of the present invention. Show.

  As is apparent from FIG. 7, the drain current Ids characteristics (solid curve) according to the first embodiment of the present invention are lower than the conventional characteristics (dotted curve) at any gate voltage Vgs. <20 [V]), the current increase effect is remarkable, and it can be seen that the drain current Ids flows well even at a low drain voltage Vds.

  In the conventional TFT structure (FIGS. 12 and 13), when the drain voltage Vds is lowered due to the influence of the resistance layer 2b (resistance component) in the a-Si layer 2 which is the path of the drain current Ids, the drain current Ids becomes a dotted line. It will decrease like a curve. Further, in this case, when the gate voltage Vgs applied to the gate electrode 1 is lowered, the thickness of the channel layer 2a in the a-Si layer 2 is also reduced, and conversely, the resistance layer 2b is increased, so that the drain current Ids is further increased. Get smaller.

  On the other hand, in the TFT structure (FIGS. 1 and 2) according to the first embodiment of the present invention, the channel layer 2a formed in the a-Si layer 2 by the gate voltage Vgs applied to the gate electrode 1 and the source electrode 3A And the drain electrode 4A are directly connected to each other through the ohmic contact layer 12A (not having a large resistance component), so that even in a region where the drain voltage Vds is low without being affected by the current decrease due to the resistance layer 2b. The drain current Ids can be made to flow satisfactorily.

Embodiment 2. FIG.
Although the channel protective film is not mentioned in the first embodiment, it is needless to say that the present invention can be applied to a channel protective TFT structure having a channel protective film.
FIG. 8 is a plan view showing a thin film transistor according to Embodiment 2 of the present invention, taking the case of a channel protection TFT as an example, and FIG. 9 is a cross-sectional view taken along the line CC ′ in FIG. 8 and 9, the same parts as those described above (see FIGS. 1 and 2) are denoted by the same reference numerals as those described above, and detailed description thereof is omitted.
In this case, the second embodiment is the same as the first embodiment except that the channel protective film 14 is formed on the upper surface of the a-Si layer 2 located between the source electrode 3A and the drain electrode 4A.

As shown in FIGS. 8 and 9, when the channel protective film 14 is formed on the a-Si layer 2, the thickness of the a-Si layer 2 (usually 100 nm) is used in the case of normal exposure using a mask. There is no need to set restrictions on
On the other hand, when the channel protective film 14 is formed by performing backside exposure from the back surface of the glass substrate 10 using a positive resist, light is absorbed by the a-Si layer 2 and the exposure intensity is attenuated. Therefore, the thickness of the a-Si layer 2 is limited to about 100 nm at the maximum.

Embodiment 3 FIG.
In the first embodiment, the planar shapes of the a-Si layer 2, the source electrode 3A, and the drain electrode 4A are not particularly mentioned, but it goes without saying that the present invention can also be applied to a U-shaped TFT structure.
FIG. 10 is a plan view showing a thin film transistor according to a third embodiment of the present invention, taking the case of a U-shaped TFT as an example, and FIG. 11 is a cross-sectional view taken along line DD ′ in FIG. 10 and 11, the same parts as those described above (see FIGS. 1 and 2) are denoted by the same reference numerals as those described above, or “B” after the reference numerals, and detailed description thereof is omitted.

  In this case, the source electrode 3B is formed in a U shape so as to surround both sides of the drain electrode 4B so that a large drain current Ids can flow, and the drain electrode 4B is formed in a U shape of the source electrode 3B. It is arranged at the center of the shape. Thus, the gate electrode 1, the a-Si layer 2B, the source electrode 3B, and the drain electrode 4B realize a U-shaped TFT structure.

When the U-shaped TFT structure of FIGS. 10 and 11 is applied, a slit 15 is formed in the lower a-Si layer 2B where the drain electrode 4B is formed using a mask used when forming an a-Si island. Then, it is necessary to configure the contact portion 13B so that the ohmic contact layer 12B below the drain electrode 4B is in contact with the side wall of the a-Si layer 2B.
Thereby, similarly to the above, the drain electrode 4B and the channel layer 2a can be directly connected without interposing the resistance layer 2b of the a-Si layer 2B.

In the first to third embodiments, the glass substrate 10 is used as the insulating substrate, but another insulating substrate may be used.
Further, although the a-Si layer is used as the intrinsic semiconductor layer and the low resistance semiconductor layer, other semiconductor layers may be used.
The thin film transistor may be applied to a peripheral circuit portion or a pixel portion of a liquid crystal display device.

Similarly, when applied to an O (organic) LED (Light-Emitting-Diode) display device, the charge retention characteristics of the OLED display device using an a-Si-TFT can be improved.
Further, the thin film transistor may be used in a peripheral circuit portion of a display device or may be used in a pixel portion where a large current is not required.

1 is a plan view schematically showing a thin film transistor according to Embodiment 1 of the present invention. It is sectional drawing by the B-B 'line in FIG. It is a top view which shows the 1st step of the manufacturing method of the thin-film transistor which concerns on Embodiment 1 of this invention. It is a top view which shows the 2nd step of the manufacturing method of the thin-film transistor which concerns on Embodiment 1 of this invention. It is a top view which shows the 3rd step of the manufacturing method of the thin-film transistor which concerns on Embodiment 1 of this invention. It is a top view which shows the 4th step of the manufacturing method of the thin-film transistor which concerns on Embodiment 1 of this invention. It is a characteristic view for demonstrating the effect of the thin-film transistor which concerns on Embodiment 1 of this invention. It is a top view which shows typically the thin-film transistor which concerns on Embodiment 2 of this invention. It is sectional drawing by the C-C 'line | wire in FIG. It is a top view which shows typically the thin-film transistor which concerns on Embodiment 3 of this invention. It is sectional drawing by the D-D 'line | wire in FIG. It is a top view which shows the conventional thin-film transistor typically. It is sectional drawing by the A-A 'line in FIG.

Explanation of symbols

1 gate electrode, 2, 2B a-Si (amorphous silicon layer, intrinsic semiconductor layer, i · a-Si layer), 2a channel layer, 3b resistance layer, 3A, 3B source electrode, 4A, 4B drain electrode, 10 glass substrate (Insulating substrate), 11 gate insulating layer, 12 ohmic contact layer (low resistance semiconductor layer, n ⁺ a-Si layer), 13A, 13B contact portion, 14 channel protective film, 15 slit, Ids drain current, Vds drain voltage, Vgs Gate voltage.

Claims (7)

A gate electrode formed on an insulating substrate; an intrinsic semiconductor layer disposed on the gate electrode via the gate insulating film; a source electrode disposed on the intrinsic semiconductor layer via a low-resistance semiconductor layer; and A thin film transistor having a drain electrode and forming a channel region in a facing portion between the source electrode and the drain electrode,
The thin film transistor according to claim 1, wherein the source electrode and the drain electrode are directly connected to a portion of the intrinsic semiconductor layer where the channel layer is formed via the low-resistance semiconductor layer.   The thin film transistor according to claim 1, wherein the intrinsic semiconductor layer and the low-resistance semiconductor layer are made of an amorphous silicon layer. A channel protective film formed on the upper surface of the channel region between the source electrode and the drain electrode;
3. The thin film transistor according to claim 1, wherein a thickness of the intrinsic semiconductor layer is set to 100 nm or less.   The said source electrode is formed in U shape, and the said drain electrode is arrange | positioned in the U-shaped center part of the said source electrode, The any one of Claim 1 to 3 characterized by the above-mentioned. Thin film transistor. It is a manufacturing method of the thin-film transistor of any one of Claim 1- Claim 4, Comprising:
Forming the gate electrode on the insulating substrate;
Forming an intrinsic semiconductor layer island on the gate electrode through the gate insulating film;
Forming the low-resistance semiconductor layer on the gate insulating film including the island of the intrinsic semiconductor layer;
The source electrode and the drain electrode are formed on the upper part including the peripheral edge of the island of the intrinsic semiconductor layer via the low-resistance semiconductor layer, and the channel region is formed at a portion facing the source electrode and the drain electrode. Forming step;
Removing the low-resistance semiconductor layer excluding the lower part of the source electrode and the drain electrode,
A method of manufacturing a thin film transistor, wherein the low-resistance semiconductor layer is formed so as to cover a part of a portion of the intrinsic semiconductor layer where a channel layer is formed.   5. A liquid crystal display device using the thin film transistor according to claim 1 in a pixel portion or a peripheral circuit portion.   An OLED display device comprising the thin film transistor according to any one of claims 1 to 4 in a pixel portion or a peripheral drive portion.

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