JP2008112909A - Thin film semiconductor device and manufacturing method thereof - Google Patents

Abstract

A thin film semiconductor device having good electrical characteristics and a method for manufacturing the same are provided.
A thin film semiconductor device is formed flat without providing a pattern or the like up to a semiconductor film, a gate insulating film, and a gate electrode, and further, a step is formed under the semiconductor layer and the gate insulating film. The layer which produces is not formed. Therefore, the gate insulating film 18 can be provided with the thin film semiconductor device 10 that is free from cracks and the like, can suppress gate leakage current, and has good electrical characteristics.
[Selection] Figure 3

Description

  The present invention relates to a thin film semiconductor device and a manufacturing method thereof, and more particularly to a thin film semiconductor device formed on a substrate or film made of glass or resin and a manufacturing method thereof.

  For example, liquid crystal display devices are used in electrical devices such as personal computers and televisions. In the liquid crystal display device, high definition, high speed signal processing, and large screen are regarded as important issues for technological development. In order to solve these problems, the performance of thin film transistors (hereinafter referred to as TFTs) used to drive pixels constituting a liquid crystal display device has been improved. Major problems to be solved by TFT include improvement of carrier mobility and reduction of current when the transistor is not driven (referred to as off current or subthreshold current: Ioff).

  Various structures have been proposed as thin film transistors. Specifically, a top gate type and a bottom gate type are employed. The former is characterized in that the gate electrode is formed under the semiconductor thin film layer, and the latter is characterized in that the gate electrode is formed above the semiconductor layer. A top gate type TFT is disclosed in, for example, Patent Document 1.

  In general, a TFT using an amorphous silicon semiconductor thin film adopts a bottom gate type, and is made of polycrystalline silicon using a laser annealing technique (sometimes called polysilicon or poly Si), so-called low-temperature polycrystalline silicon. Many TFTs are of the top gate type.

  In recent high-performance liquid crystal display devices, the use of top gate type TFTs using low-temperature polycrystalline silicon is increasing for the following reasons. The first factor is that when the bottom gate type is applied, when silicon is melted, the gate electrode such as a gate insulating film or metal is heated in the lower layer, and there is a possibility that these will react, and on the base step This is because, when the silicon film is melted and recrystallized, there is a drawback that crystal grain growth is inhibited on the step.

  The grain size of the crystal grains constituting the polycrystalline silicon film is often small near the base interface and large on the surface side of the film. This is because of the initial crystal nuclei formed on the substrate at the initial stage of film formation and the factors resulting from the underlying layer, such as bonding to the base material elements, adhesion, and cohesive strength when melted and recrystallized by laser irradiation. This is because the growth of crystal grains is suppressed. As the distance from the interface increases, the influence of these factors on crystal grain growth becomes smaller, and the grains become larger.

Carriers in the polycrystalline semiconductor film are mainly scattered at the crystal grain boundaries, and the mobility is lowered. Therefore, it is desired that the crystal grains are large in order to realize a high-performance TFT with high mobility. That is, a top gate TFT structure is employed in which the channel region is in the vicinity of the surface of a relatively large crystal grain both in terms of mobility and within the same film.
JP 2002-50764 A (FIG. 1)

  By the way, in the top gate type thin film semiconductor device disclosed in Patent Document 1, a polycrystalline silicon layer is formed and a region functioning as a semiconductor layer is formed, and then a gate insulating film is formed on the semiconductor layer. Further, a gate electrode is formed on the gate insulating film. Therefore, there is a problem that a step is generated in the gate insulating film and the gate electrode formed in the peripheral region of the semiconductor layer, and the gate insulating film and the gate electrode are cracked due to the step. When such a crack occurs, a leak current is generated, a dielectric breakdown voltage is lowered, and the electrical characteristics of the thin film semiconductor device are lowered.

  The present invention has been made in view of the above-described circumstances, and an object thereof is to provide a thin film semiconductor device having good electrical characteristics and a method for manufacturing the same.

In order to achieve the above object, a thin film semiconductor device according to the first aspect of the present invention provides:
A substrate,
A semiconductor layer formed on the substrate;
A gate insulating film provided on the semiconductor layer;
A gate electrode formed on the gate insulating film;
The gate insulating film and the semiconductor layer are formed flat so as not to cause a step.

  An insulating film may be formed between the substrate and the semiconductor layer.

  A sidewall insulating film formed on the semiconductor layer may be further provided so as to cover the gate electrode and the side surface of the gate insulating film.

A first impurity diffusion region in which impurities are diffused is formed in the surface region of the semiconductor layer,
Further, a second impurity diffusion region in which impurities are diffused is formed under the sidewall insulating film,
The impurity concentration of the second impurity diffusion region may be lower than the impurity concentration of the first impurity diffusion region.

  The said board | substrate may be comprised from a glass substrate and a resin film.

  The semiconductor layer may be composed of a single layer made of silicon, germanium, a mixture thereof, or a carbide of these materials, or a stacked structure of these materials.

  The semiconductor layer may be composed of a single layer of a chalcogenide film such as an oxide, carbide, sulfide, selenium compound or tellurium compound having semiconductor characteristics, or a stacked structure of these material thin films.

In the semiconductor layer, phosphorus, arsenic, antimony, boron, aluminum, indium, or the like may be diffused.

  The semiconductor layer may be composed of a plurality of elements, and the constituent elements may have a distribution in the composition in the film thickness direction of the thin film.

In order to achieve the above object, a method of manufacturing a thin film semiconductor device according to the second aspect of the present invention includes:
A semiconductor film is formed over the substrate, an insulating film is formed over the semiconductor film, a conductive film is formed over the insulating film, and a stacked film including the semiconductor film, the insulating film, and the conductive film is formed. A laminated film forming step;
Forming a conductive film in a predetermined pattern and forming a gate electrode;
Forming a gate insulating film by forming the insulating film in a predetermined pattern; and
A semiconductor layer forming step of forming the semiconductor film in a predetermined pattern and forming a semiconductor layer is provided.

Further comprising an insulating film processing step of forming the insulating film in a pattern corresponding to an operation region;
In the semiconductor layer forming step, the semiconductor layer may be formed using the insulating film formed in a pattern corresponding to an operation region as a mask.

  In the gate insulating film forming step, the gate insulating film may be formed by removing the insulating film formed on the semiconductor layer using the gate electrode as a mask.

  An impurity introducing step of introducing impurities into the semiconductor layer through the insulating film in a state where the insulating film is formed on the semiconductor layer may be further provided.

  An impurity introducing step of introducing impurities into the semiconductor layer through the insulating film in a state where the insulating film on the semiconductor layer is removed may be further provided.

  The said board | substrate may be comprised from a glass substrate and a resin film.

  The semiconductor layer may be composed of a single layer made of silicon, germanium, a mixture thereof, or a carbide of these materials, or a stacked structure of these materials.

  The semiconductor layer may be composed of a single layer of a chalcogenide film such as an oxide, carbide, sulfide, selenium compound or tellurium compound having semiconductor characteristics, or a stacked structure of these material thin films.

The semiconductor layer may contain phosphorus, arsenic, antimony, boron, aluminum, indium, gallium, or the like.

  The semiconductor layer may be composed of a plurality of elements, and the constituent elements may have a distribution in the composition in the film thickness direction of the thin film.

  According to the present invention, it is possible to provide a thin film semiconductor device having good electrical characteristics and a method for manufacturing the same by forming the base of the gate insulating film flat.

  Hereinafter, a thin film semiconductor device and a manufacturing method thereof according to an embodiment of the present invention will be described with reference to the drawings.

  A thin film semiconductor device 10 according to an embodiment of the present invention is shown in FIGS. FIG. 1 is a plan view showing a thin film semiconductor device 10. 2 is a sectional view taken along line II-II shown in FIG. 1, and FIG. 3 is a sectional view taken along line III-III shown in FIG. The thin film semiconductor device 10 is used for supplying a signal to a pixel electrode of a liquid crystal display device, for example.

  The thin film semiconductor device 10 according to this embodiment includes a substrate 11, a first insulating layer (undercoat layer) 12, a semiconductor layer 13, a channel region 14, a source region 15, a drain region 16, and an interlayer insulating film 17. A gate insulating film 18, a gate electrode 21, a source electrode 22, a drain electrode 23, and a gate extraction electrode 24. The thin film semiconductor device 10 is formed with a transparent electrode 31 for supplying a predetermined signal to a liquid crystal display device (not shown) in which the thin film semiconductor device 10 is installed.

  The substrate 11 is made of, for example, a glass substrate or a resin substrate. A first insulating layer (undercoat layer) 12 is formed on the substrate 11. As the substrate 11, a sapphire substrate, a silicon single crystal substrate, other insulating, semi-insulating or semiconductor substrates, a resin film such as a plastic, and a composite thereof can also be used.

  The first insulating layer (undercoat layer) 12 is formed on the main surface of the substrate 11. The first insulating layer 12 includes a silicon nitride film 12a formed to a thickness of 100 nm, for example, and a silicon oxide film 12b formed on the silicon nitride film 12a to a thickness of 100 nm, for example. When impurities contained in the substrate diffuse into the semiconductor layer 13 or the gate insulating film 18 in a process such as a case where a high temperature heat treatment such as a laser heat treatment is applied, the stability of the MOS transistor characteristics such as the threshold voltage and the reliability of the TFT In the present embodiment, the formation of the first insulating layer 12 can prevent impurities from diffusing into the semiconductor layer and the like, so that stability of characteristics and good reliability can be obtained. be able to.

  The semiconductor layer 13 is made of, for example, SiGe. The semiconductor layer 13 is formed on the first insulating layer 12 and has a thickness of, for example, 100 nm. A channel region 14, a source region 15, and a drain region 16 are formed in the surface region of the semiconductor layer 13. In this embodiment, as will be described in detail later, the upper surface of the semiconductor layer 13 is formed flat. As described above, the upper surface of the semiconductor layer 13 is formed flat, whereby the gate insulating film 18 and the gate electrode 21 can be formed flat. Further, the surface region of the semiconductor layer 13 is formed with a larger crystal grain size than that in the case where the annealing is not performed by performing the processing by lamp annealing as will be described in detail later. Thereby, the mobility of electrons / holes in the semiconductor layer 13 can be improved.

  The semiconductor layer 13 is made of a so-called chalcogenide such as an oxide such as ZnO other than Si / Ge, a carbide such as SiC, a sulfide such as ZnS, a selenium compound such as ZnSe, and a tellurium compound such as ZnTe. It may be formed from a single layer film or a laminated film in which thin films of these materials are laminated.

  The source region 15 is formed in the surface region of the semiconductor layer 13. In the source region 15, n-type or p-type impurities such as phosphorus and boron are diffused. A source electrode 22 is formed on the upper surface of the source region 15.

  The drain region 16 is formed in the surface region of the semiconductor layer 13. In the drain region 16, n-type or p-type impurities such as phosphorus and boron are diffused. A drain electrode 23 is formed on the upper surface of the drain region 16. Note that when the semiconductor layer forming the source and drain is not a Si-based material such as Si or SiGe such as ZnO, an impurity capable of forming an n-type or p-type impurity in the semiconductor material is introduced. For example, when the semiconductor layer is ZnO, typical impurities include gallium or aluminum in the n-type region, and nitrogen or lithium is introduced into the p-type region.

The channel region 14 is formed on the upper surface of the semiconductor layer 13. The channel region 14 is a region where the conductivity type is reversed and a channel is formed when a predetermined voltage is applied to the gate electrode 21. When the semiconductor layer is Si-based, impurities such as phosphorus and boron are diffused. Sometimes. In order to realize a predetermined threshold voltage, doping of the order of 10 ¹³ atoms / cm ² to 10 ¹⁴ atoms / cm ² is performed by an ion implantation method or the like.

  The interlayer insulating film 17 is made of an insulating material such as a silicon oxide film or a silicon nitride film, and is formed so as to cover the upper surfaces of the first insulating layer 12 and the semiconductor layer 13. A contact hole 17s for forming the source electrode 22, a contact hole 17d for forming the drain electrode 23, and a contact hole 17g for forming the gate lead electrode 24 are formed in the interlayer insulating film 17. The The interlayer insulating film 17 is formed with a thickness of 500 nm, for example.

  The gate insulating film 18 is made of an insulating material such as a silicon oxide film or a silicon nitride film, and is formed on the semiconductor layer 13. A gate electrode 21 (gate electrode wiring) is formed on the gate insulating film 18. As will be described in detail later, the gate insulating film 18 is formed by forming a SiGe film on the undercoat layer 12, further forming a silicon oxide film on the SiGe film, and forming the gate insulating film 18 by patterning. As a result, the gate insulating film 18 is formed flat, and particularly, as shown in FIGS. 2 and 3, the gate insulating film 18 is formed without causing a step in the peripheral portion of the semiconductor layer 13. Thereby, generation | occurrence | production of the crack resulting from a level | step difference can be suppressed, generation | occurrence | production of leak current can be suppressed, and the thin film semiconductor device 10 is provided with a favorable electrical property. The gate insulating film 18 is formed with a thickness of 100 nm, for example.

  The gate electrode 21 is made of a conductive material such as chromium or tungsten, and is formed on the gate insulating film 18. The gate electrode 21 is formed with a thickness of 150 nm, for example. Further, in the present embodiment, the gate electrode 21 is formed on the semiconductor layer 13 formed flat as will be described in detail later, and then the gate electrode 21 is formed. Therefore, the gate electrode 21 is formed on the gate insulating film 18. It is formed flat. A voltage is applied to the gate electrode 21 from a contact hole 17 g provided in the interlayer insulating film 17. Therefore, for example, unlike the case where a gate insulating film is formed so as to cover a semiconductor layer formed in a predetermined pattern and a step is formed, and a gate electrode is formed thereon, a step is formed in the gate electrode 21 as shown in FIG. It can be formed flat without causing it. Accordingly, the stability and reliability of the operation of the gate electrode 21 can be ensured.

  The source electrode 22 is made of a conductive material, such as aluminum, and is formed so as to fill the contact hole 17 s provided in the interlayer insulating film 17. A titanium nitride film is formed as a barrier layer on the side wall of the contact hole 17s.

  The drain electrode 23 is made of a conductive material, such as aluminum, and is formed so as to fill the contact hole 17 d provided in the interlayer insulating film 17. A titanium nitride film is formed as a barrier layer on the side wall of the contact hole 17d.

  The transparent electrode 31 is made of, for example, a light-transmitting material, indium tin oxide (ITO), and applies a voltage to a liquid crystal display unit (not shown) in which the thin film semiconductor device 10 is installed. The transparent electrode 31 is formed with a thickness of 100 nm, for example.

  In the thin film semiconductor device 10 of the present embodiment, the gate insulating film 18 is formed flat under the region where the gate insulating film 18 is formed. Therefore, the gate insulating film 18 has no step, and the gate insulation in which cracks and the like due to the step are suppressed. A membrane 18 is provided. Therefore, it is possible to provide the thin film semiconductor device 10 that can be satisfactorily suppressed from being deteriorated in electrical characteristics due to generation of cracks and the like and has good electrical characteristics.

  In particular, the present invention is useful for a thin film semiconductor device including a glass substrate or a resin substrate having a low melting point used in a practical TFT. This is because an LSI (Large Scale Integration) formed on a silicon substrate having a relatively high melting point of about 1400 ° C., for example, undergoes a high-temperature thermal process of 800 ° C. to 1050 ° C. during and / or after film formation. It is also possible to reduce defects generated in the film during the high temperature thermal process. However, in a low-melting glass substrate or plastic film, which is generally used for TFT, the process for forming a semiconductor film or a gate insulating film is required to be performed at a low temperature of about 500 ° C. or less, and heat treatment after film formation is also performed. Limited to similar temperatures. Therefore, it is difficult to reduce defects generated in the film. As a method for reducing defects generated in the film, it is conceivable to use a material having a low melting point that has fluidity even at a low temperature heat treatment of about 500 ° C. However, in this case, atom migration is likely to occur even when the process temperature after film formation is as low as about 100 ° C. to 200 ° C., and in the long-term reliability test performed by applying heat, the electrical characteristics such as the threshold voltage of the transistor fluctuate. This is because it is difficult to apply to a practical TFT.

  Next, a method for manufacturing the thin film semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS.

  First, for example, a substrate 11 made of a glass substrate is prepared. On one main surface of the substrate 11, a silicon nitride film 12a is formed with a thickness of, for example, 100 nm by, for example, a CVD (Chemical Vapor Deposition) method. Further, a silicon oxide film 12b is formed on the silicon nitride film 12a with a thickness of, for example, 100 nm by, eg, CVD. As a result, as shown in FIG. 4A, a first insulating layer (undercoat layer) 12 is formed.

  Next, a SiGe layer 81 made of, for example, SiGe is formed on the upper surface of the first insulating layer 12 to a thickness of, for example, 100 nm. The SiGe film formation temperature is preferably 400 ° C. or higher, for example, 450 ° C., which is relatively high. Thus, a film having coarse crystal grains can be obtained in the film formation process, and the mobility of electrons / holes in the semiconductor layer can be increased.

  Subsequently, a second insulating layer 82 made of, for example, a silicon oxide film, a silicon nitride film, or the like is formed on the entire upper surface of the SiGe layer 81 with a thickness of 100 nm, for example, as shown in FIG.

  Next, the SiGe layer 81 is irradiated with a light pulse of several nanoseconds with a YAG laser (excimer laser is used depending on the sample) through the second insulating layer 82 to recrystallize the entire film. In this way, when a film of coarse crystal grains is obtained by performing heat treatment after the semiconductor layer is formed, it is better to prepare a film in a microcrystalline state that is as amorphous as possible at the time of film formation. It may be easy to obtain a polycrystalline film having the same.

Next, as shown in FIG. 4C, a mask 83 in which openings 83a corresponding to the channel region, the source region, and the drain region are formed is formed on the second insulating layer 82 as shown in FIG. 4C. An impurity concentration of about 10 ¹³ atoms / cm ² to 10 ¹⁴ atoms / cm ² is formed through an opening 83a formed in the mask 83 in order to realize a thin film transistor having a threshold voltage of impurities such as phosphorus and boron. Then, the SiGe layer 82 is introduced. Thereby, an impurity layer 85 is formed as shown in FIG.

  A metal film 86 made of, for example, chromium or tungsten is formed on the second insulating layer 82 by a PVD (Physical Vapor Deposition) method or the like with a thickness of, for example, 150 nm as shown in FIG.

  Subsequently, a silicon nitride film is formed on the metal film 86 as a mask for processing into a gate electrode pattern (not shown). Next, a silicon nitride film is formed in a pattern corresponding to the gate electrode by using a photolithography technique and a dry etching technique. Using this silicon nitride film as a mask, the metal film 86 is patterned by dry etching. Thereby, the gate electrode 21 is formed as shown in FIG.

  Next, the second insulating film 82 formed around the gate electrode 21 is removed by etching or the like so that a region corresponding to the semiconductor layer 13 remains as shown in FIG. .

  Next, as shown in FIG. 6G, the gate insulating film 18 and the semiconductor layer 13 other than the device region are removed. A plurality of semiconductor devices are formed on the substrate 11, and the separation between the semiconductor devices is performed by removing only a portion where the semiconductor layer is used as a thin film semiconductor device. The semiconductor layer removal step for element isolation is performed at any stage after the semiconductor thin film is formed, after the gate insulating film is formed, and further after the gate electrode and the source / drain regions are formed.

  Subsequently, impurities such as phosphorus and boron are further introduced through the insulating film 18 using the gate electrode 21 as a mask, thereby forming the source region 15 and the drain region 16 as shown in FIG. Thus, by using the gate electrode 21 as a mask, the source region 15 and the drain region 16 are formed in a self-aligned manner with respect to the gate electrode 21 without using a photoresist mask for forming the source region and the drain region. Can do.

  Next, an interlayer insulating film 17 made of, for example, a silicon oxide film or a silicon nitride film is formed to a thickness of, for example, 500 nm so as to cover the overcoat layer 12, the semiconductor layer 13, and the gate electrode 21 by a CVD method or the like.

  Contact holes 17s, 17d, and 17g (openings) are provided at predetermined positions of the source region 15, the drain region 16, and the interlayer insulating film 17 and the gate insulating film 18 on the gate electrode, and the contact hole has a thickness of 10 nm as a barrier layer. After forming the titanium nitride film, an aluminum film having a thickness of 0.9 μm is formed, and the overlapping layer of these metal films is processed into the source electrode 22 and the drain electrode 23 by using a normal lithography technique and dry etching.

Subsequently, an ITO film having a thickness of, for example, 100 nm is formed by a sputtering method, a vacuum evaporation method, or the like.
From the above steps, the thin film semiconductor device 10 is manufactured as shown in FIG.

  In the method of manufacturing the thin film semiconductor device of this embodiment, the semiconductor layer 13, the insulating layer (gate insulating film), and the conductive film (gate electrode) are stacked on the flatly formed first insulating layer 12. The conductive film is processed into a desired gate electrode pattern to form the gate insulating film 18 and the semiconductor layer 13. Thereby, since the gate insulating film 18 can be formed flat, a step does not occur in the gate insulating film. Therefore, it is possible to prevent the occurrence of defects in the film due to the level difference as in the prior art. In the present embodiment, the gate electrode 21 can also be formed flat, so that the stability and reliability of the operation of the gate electrode 21 can be ensured.

  In addition, since the present invention can prevent the occurrence of defects in the film due to a step, a heat treatment or the like for repairing the defects is unnecessary, and a thin film semiconductor device is formed on a glass substrate or plastic film having a particularly low melting point. Useful in cases.

  In the present embodiment, the crystal grain size of the surface region of the semiconductor layer 13 can be increased by irradiating the semiconductor layer 13 with a laser to promote recrystallization. Thereby, the mobility of electrons / holes in the semiconductor layer 13 can be increased.

  Further, in the thin film semiconductor device 10 of the present embodiment, the diffusion of impurities from the substrate 11 to the semiconductor layer 13 can be prevented by forming the undercoat layer 12. Thereby, the reliability and stability of the thin film semiconductor device 10 can be ensured.

  Further, the source region 15 and the drain region 16 can be formed in a self-aligned manner with respect to the gate electrode 21 by doping impurities such as phosphorus and boron by ion implantation using the gate electrode 21 as a mask. As a result, it is possible to reduce the overlap capacitance between the gate electrode and the source / drain in the conventional thin film semiconductor device, and to improve performance such as speeding up of the element.

(Embodiment 2)
A thin film semiconductor device 50 according to Embodiment 2 of the present invention will be described with reference to the drawings. The thin film semiconductor device 50 according to the present embodiment is different from the thin film semiconductor device 10 according to the first embodiment in that an insulating layer is formed on the periphery of the gate insulating film and the gate electrode, and an impurity concentration gradient is further generated in the source region and the drain region. It is in the point provided. Constituent elements common to the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

  A thin film semiconductor device 50 is shown in FIG. FIG. 7 is a cross-sectional view of the thin film semiconductor device 50.

  As illustrated, the thin film semiconductor device 50 according to the present embodiment includes a substrate 11, a first insulating layer (undercoat layer) 12, a semiconductor layer 13, a channel region 14, a first source region 15, and a first source region 15. 2 source region 55, first drain region 16, second drain region 56, interlayer insulating film 17, gate insulating film 18, first sidewall insulating film 52, second sidewall insulating film 53, and gate electrode 21, a source electrode 22, a drain electrode 23, and a gate extraction electrode 24. The thin film semiconductor device 50 is formed with a transparent electrode 31 for supplying a predetermined signal to a liquid crystal display device (not shown) in which the thin film semiconductor device 50 is installed.

  The first sidewall insulating film 52 is made of an insulating material, for example, a silicon nitride film, is formed so as to cover the side surfaces of the gate insulating film 18 and the gate electrode 21, and further the upper surfaces of the second source region 55 and the second drain region 56. Formed.

  The second sidewall insulating film 53 is made of an insulating material such as a silicon nitride film, and is formed on the overcoat film 12 so as to cover the side surface of the semiconductor layer 13.

  The second source region 55 is formed under the first sidewall insulating film 52. As will be described in detail later, the first source region 15 and the second source region 55 are formed by introducing an impurity into the surface region of the semiconductor layer 13 and then introducing the impurity using the first sidewall insulating film 52 as a mask. The Thus, the second source region 55 is formed in a self-aligned manner with respect to the first sidewall insulating film 52, and the impurity concentration of the second source region 55 is formed lower than the impurity concentration of the first source region 15. .

  The second drain region 56 is formed under the first sidewall insulating film 52. As will be described in detail later, the first drain region 16 and the second drain region 56 are formed by introducing impurities into the surface region of the semiconductor layer 13 and then introducing the impurities using the first sidewall insulating film 52 as a mask. The As a result, the second drain region 56 is formed in a self-aligned manner with respect to the first sidewall insulating film 52, and the impurity concentration of the second drain region 56 is formed lower than the impurity concentration of the first drain region 16. .

  The thin film semiconductor device 50 of this embodiment includes a first side wall insulating film 52, a first source region 15, a second source region 55, a first drain region 16, and a second drain region 56 that are further provided with a concentration gradient. In addition to suppressing gate leakage current and maintaining a dielectric breakdown voltage, it is possible to weaken the electric field strength at the drain end in the semiconductor layer at the gate electrode end.

  That is, the thin film semiconductor device is also miniaturized in order to increase the definition of the liquid crystal and increase the operation speed of the thin film semiconductor device. When the power supply applied to the thin film semiconductor device is lowered with the miniaturization, the characteristic deterioration is improved. However, the power source is proportional to the miniaturization due to an external factor with the device in which the thin film semiconductor device is used. The voltage is rarely reduced. As a result, the increase in the electric field strength at the drain end due to miniaturization becomes more prominent. When a thin film semiconductor device is used for a long period of time, there are problems such as deterioration of transistor characteristics, such as threshold voltage fluctuation and reduction of mutual conductance. Arise. In the present embodiment, these distances are separated by the film thickness of the side wall insulating film provided on the side wall, whereby the breakdown voltage characteristics of the gate insulating film can be improved as compared with the thin film semiconductor device 10 of the first embodiment.

  Next, a method for manufacturing the thin film semiconductor device 50 according to the present embodiment will be described with reference to the drawings. The manufacturing method of this embodiment is different from the manufacturing method of the thin film semiconductor device 10 of Embodiment 1 in that the second insulating layer is formed and that concentration gradients are provided in the source region and the drain region. Detailed description of the configuration common to the first embodiment is omitted.

  As in the first embodiment, a first insulating layer (undercoat layer) 12 is formed on a substrate 11 such as a glass substrate, and a SiGe layer and a second insulating layer are formed. Subsequently, a mask in which openings corresponding to the channel region, the source region, and the drain region are formed is formed, and the impurity layer 85 is formed. Next, a metal film is formed on the second insulating layer. This metal film is formed into a predetermined pattern by etching, and a gate electrode 21 is formed as shown in FIG. Further, the gate insulating film 18 and the semiconductor layer 13 are formed by etching or the like.

  Subsequently, impurities are introduced into the impurity layer 85 by ion implantation or the like using the gate electrode 21 as a mask. Thereby, regions 65 and 66 into which impurities are introduced in a self-aligned manner with respect to the pattern of the gate electrode 21 are formed in the surface region of the semiconductor layer 13.

  Next, as shown in FIG. 8C, the gate insulating film 18 is etched using the gate electrode 21 as a mask to expose the semiconductor layer 13.

  Subsequently, a silicon nitride film (not shown) is formed so as to cover the undercoat layer 12, the semiconductor layer 13, and the gate electrode 21, respectively. Next, the silicon nitride film formed on the flat surfaces of the undercoat layer 12, the semiconductor layer 13, and the gate electrode 21 is removed by plasma etching or the like, and the gate electrode 21 and the gate are formed as shown in FIG. A first sidewall insulating film 52 is formed so as to cover the side surface of the insulating film 18, and a second sidewall insulating film 53 is formed so as to cover the side surface of the semiconductor layer 13.

  Next, impurities are introduced into the surface region of the semiconductor layer 13 by ion implantation or the like using the first sidewall insulating film 52 as a mask. As a result, as shown in FIG. 9E, the first source region 15, the second source region 55 having a lower impurity concentration than the first source region 15, and the first drain are formed on the surface region of the semiconductor layer 13. A region 16 and a second drain region 56 having a lower impurity concentration than the first drain region 16 are formed. The second source region 55 and the second drain region 56 are formed in a self-aligned manner with respect to the pattern of the gate electrode 21 and the first sidewall insulating film 52.

Next, as in the first embodiment, an interlayer insulating film 17 made of, for example, a silicon oxide film or a silicon nitride film is formed so as to cover the overcoat layer 12, the semiconductor layer 13, and the gate electrode 21. Then, contact holes 17s, 17d, and 17g (openings) are provided at predetermined positions of the interlayer insulating film 17, and after forming a 10 nm-thick titanium nitride film as a barrier layer in the contact holes, for example, 0.9 μm-thick aluminum A film is formed. Subsequently, an overlapping layer of these metal films is formed in a predetermined pattern using a lithography technique and dry etching, and a source electrode 22 and a drain electrode 23 are formed. Next, an ITO film having a thickness of, for example, 100 nm is formed by sputtering, vacuum deposition, or the like.
From the above steps, the thin film semiconductor device 50 is manufactured as shown in FIG.

  According to the method of manufacturing the thin film semiconductor device of this embodiment, impurities are introduced using the gate electrode as a mask, and further, after the sidewall insulating film is formed, the impurity is introduced using the gate electrode and the sidewall insulating film as a mask, A source region and a drain region having a concentration gradient in a self-aligned manner with respect to the gate electrode and the sidewall insulating film can be formed. As described above, by providing the source electrode and the drain electrode with a concentration gradient, the gate insulating film can be formed flat as in the first embodiment, and the leakage current can be suppressed. In addition, the semiconductor layer at the gate electrode end can be suppressed. An effect of weakening the electric field strength at the drain end can be obtained.

(Example 1)
First, non-alkali glass is prepared as the substrate 11 and the undercoat layer 12 is formed using the plasma CVD method at a substrate temperature of 400 ° C. as described above.

  Next, a SiGe film having a thickness of 100 nm was formed using an ECR (Electron Cyclotron Resonance) sputtering apparatus. In addition, the substrate temperature at the time of film formation was 400 ° C. or higher, for example, 450 ° C., and a sample formed at 400 ° C. or lower was also prepared for comparison. At the time of this film formation, a sputtering target in which a Si plate and a Ge plate were bonded together in a mosaic shape was used. The ratio of the area where the Si plate and Ge plate are arranged is set to be the same as the Si / Ge ratio of the SiGe film to be formed. For example, when forming a SiGe film containing 50% each of Si and Ge, the Si plate and the Ge plate are arranged with the same area ratio. In addition, as a result of obtaining the elemental composition of the 100 nm-thick SiGe film obtained by such a film forming method using a normal mass spectrometer, it was found that the atomic composition of Si and Ge was almost equal.

Further, the ECR sputtering apparatus has a plurality of sputtering chambers, and different types of films can be continuously formed by moving between the chambers in a vacuum without exposing the sample to the atmosphere. In this example, using this function, after forming the SiGe film, the sample was moved to another sputtering chamber in a vacuum, and an SiO ₂ film (gate insulating film) having a thickness of 100 nm was formed by ECR sputtering.

Next, a region other than the region functioning as an n-channel transistor is covered with a high heat resist using a lithography technique. Subsequently, using an ion implantation apparatus, boron ions are implanted at 50 keV through the silicon oxide film at a substrate temperature of 400 ° C. into a region of the SiGe film not covered with the high heat resistance resist. For example, boron ions are implanted at a dose of 5 × 10 ¹³ atoms / cm ² . A region where boron ions are implanted functions as a channel region.

Next, after removing the resist, the region other than the region functioning similarly as a p-channel transistor is covered with the resist. Subsequently, phosphorus ions were implanted at 2 × 10 ¹³ atoms / cm ² at 110 keV using this resist as a mask. This resist was removed by a so-called asher device using oxygen plasma, wet-cleaned, and then the surface of the silicon oxide film was cleaned with ultraviolet rays or ozone + sulfuric acid.

  Subsequently, a tungsten (W) film having a thickness of 200 nm was formed using a normal magnetron sputtering apparatus. Thereafter, a silicon nitride film having a thickness of 150 nm was formed using a plasma CVD (Chemical Vapor Deposition) apparatus.

  This silicon nitride film was processed into a gate electrode / wiring pattern using a lithography technique and a dry etching technique. Subsequently, the tungsten film was processed using the pattern made of the silicon nitride film as a mask to form gate electrodes / wirings.

Next, in the same procedure as in the previous ion implantation, phosphorus ions are implanted at 125 keV at a dose of 5 × 10 ¹⁵ atoms / cm ^{2 at} a substrate temperature of 450 ° C. using the gate electrode as a mask, and a p-channel is formed. Similarly, boron is implanted at 5 × 10 ¹⁵ atoms / cm ^{2 at} a substrate temperature of 450 ° C. and 50 keV in the transistor region. In these ion implantations, a high heat resist is used as a mask material in order to select ions implanted into the n-channel region and the p-channel region in the ion implantation step for the threshold voltage control described above. The same technique was adopted in this ion implantation process.

  Next, using the gate electrode as a mask, the peripheral silicon oxide film was removed by a dry etching technique to expose the SiGe film.

  Next, an interlayer insulating film 17 made of a silicon oxide film having a thickness of 500 nm was formed at 400 ° C. using a plasma CVD apparatus. Contact holes 17a and 17b are formed in a predetermined portion of the insulating film by using a lithography technique and a dry etching technique, and titanium nitride is deposited to a thickness of 10 nm using a sputtering apparatus. An aluminum film was formed. Then, a source electrode and a drain electrode were formed by processing the stacked structure of the titanium nitride film and the aluminum film using a photolithography technique and a dry etching technique.

  When the thin film semiconductor device thus formed is used as a switching element of an active matrix liquid crystal, an ITO film or a zinc oxide film, which is a transparent conductive film, is formed thereafter to form a liquid crystal driving electrode. In this embodiment, this step and subsequent steps are omitted.

  The characteristics of the thin film semiconductor device thus obtained were evaluated. In this example, the SiGe film formation temperature was 450 ° C. and a relatively high temperature. This is for the purpose of obtaining a film having coarse crystal grains in the film forming process.

  As a result of observing the cross section of the element with a transmission electron microscope (TEM), it was found that the film had a coarse crystal grain size of 50 nm to 200 nm. At the same time, the element cross section was analyzed with an energy dispersive X-ray analyzer, and the elemental composition in the film was evaluated. The SiGe film was found to be composed of 55% Si and 45% Ge, which are close to the elemental composition expected from the sputter target.

In support of these results, the electron mobility obtained from the n-channel MOS transistor obtained from the relationship between the source-drain current of the thin film semiconductor device and the applied voltage between the source and gate electrodes is 100 cm ² / V · s to 150 cm. ^The hole mobility obtained from the p-channel MOS transistor was 50 cm ² / V · s to 80 cm ² / V · s.

  These values showed high mobility almost equal to that of a polycrystalline silicon film (generally called low-temperature polysilicon) whose crystal was coarsened by annealing using an excimer laser. The source-drain current (also referred to as off-state current) when the transistor is not driven is a MOS transistor having a channel length of 10 μm and a channel width of 10 μm, and 0.5 pA / mm to 1 for an n-channel transistor. .3 pA / mm, and the p-channel transistor showed the same characteristics as the transistor formed on the single crystal substrate, which was 0.1 pA / mm to 0.8 pA / mm.

  In this example, a thin film semiconductor device having high mobility was obtained without forming a heat treatment for crystal grain coarsening after the formation of the semiconductor film as in the case of low-temperature polysilicon. This is due to the fact that the temperature of the substrate is higher than the commonly used substrate temperature, and because the energy of flying particles is high in ECR sputtering, the coarse crystal grains are obtained due to the effect that the substrate surface can be moved relatively easily during deposition. .

  In order to confirm the effect of this example, a TFT having a source / drain electrode layer used in the conventional TFT shown in FIG. 10 and a semiconductor layer and a gate insulating layer formed thereon was fabricated. For example, as shown in FIG. 10, a conventional thin film semiconductor device 90 includes a substrate 91, a first insulating layer 92 composed of a silicon nitride film 92a and a silicon oxide film 92b, a semiconductor layer 93, a source region 94, and a drain region. 95, a source electrode 96, a drain electrode 97, a gate insulating film 98, and a gate electrode 99.

In this element structure, the growth direction of crystal grains is nonuniform in the semiconductor layer 93 on the ends of the source electrode 96 and the drain electrode 97. Accordingly, the semiconductor layer near the end of the electrode has nonuniform crystal grains and poor orientation, and coarse crystal grains cannot be grown. Thus, the electron mobility in the n-channel TFT is ^{30 cm 2 / V · s~60cm 2} / V · s, the hole mobility of the p-channel TFT is ^{10cm 2 / V · s~30 cm 2} / V · s And showed a low value.

  The off-state current was about 100 pA / mm, which was higher in the order of digits than in this example. This is because the gate insulating film leak current becomes excessive because of the material and structural defects of the film, such as non-uniform location in the gate insulating film on the step and, in extreme cases, discontinuity on the edge of the step. it is conceivable that.

  The reason why the thin film semiconductor device exhibiting such a low off-state current is obtained is that the element structure in which no step is generated between the semiconductor layer and the gate insulating layer in the region under the gate electrode according to the embodiment of the present invention. .

(Example 2)
In Example 2, the performance of a thin film semiconductor device formed in the same manner as in Embodiment 2 is verified.

  First, similarly to Example 1, a tungsten (W) film having a thickness of 200 nm was formed using a normal magnetron sputtering apparatus. Thereafter, a silicon nitride film having a thickness of 150 nm was formed using a plasma CVD (Chemical Vapor Deposition) apparatus. This silicon nitride film was processed into a gate electrode and a gate wiring pattern using a lithography technique and a dry etching technique. Subsequently, the tungsten film was processed using the pattern made of the silicon nitride film as a mask to form gate electrodes and gate wirings.

Next, in the region where the n-channel transistor is to be formed using the gate electrode as a mask, phosphorus ions are implanted at a substrate temperature of 450 ° C. at 115 keV and a dose of 5 × 10 ¹⁴ atoms / cm ² , and boron is implanted into the p-channel transistor region at 5 × By implanting 10 ¹⁴ atoms / cm ^2, a source region and a drain region containing impurities at a lower concentration than in Example 1 were formed in each TFT in a self-aligned manner with respect to the gate electrode.

Subsequently, a silicon nitride film was formed so as to cover the first insulating layer, the semiconductor layer, and the gate electrode. Subsequently, the nitride film was etched using a plasma etching apparatus having strong processing anisotropy. By this etching process, the silicon nitride film in the flat region was removed, and the silicon nitride film was left only on the side wall portion of the gate electrode. Next, using the gate electrode and the side wall insulating film as a mask, the region for forming the n-channel transistor is implanted at a substrate temperature of 450 ° C. and a dose of 5 × 10 ¹⁵ atoms / cm ² at 125 keV, as in Example 1. Boron is implanted at a dose of 5 × 10 ¹⁵ atoms / cm ² at 50 keV into the region for forming the p-channel transistor. Thus, the source region and the drain region were formed in a self-aligned manner with respect to the gate electrode pattern. The manufacturing process after this process was performed in the same manner as in Example 1.

  When a thin film semiconductor device is manufactured by the above manufacturing method, as shown in FIGS. 8 and 9, a concentration gradient is formed in a self-aligned manner in the impurity distribution in the source / drain region below the end of the gate electrode. This concentration gradient has an effect of weakening the electric field strength at the drain end in the semiconductor layer at the gate electrode end. This effect is not significant in the thin film semiconductor device having a gate length of 10 μm and a long channel as in the first embodiment, but in the case of a short channel thin film semiconductor device having a gate length of 1 to 2 μm or less, the characteristics due to the electric field strength at the drain end. Deterioration becomes obvious.

  That is, the thin film semiconductor device is also miniaturized in order to increase the definition of the liquid crystal and increase the operation speed of the thin film semiconductor device. When the power supply applied to the thin film semiconductor device is lowered with the miniaturization, the characteristic deterioration is improved. However, the power source is proportional to the miniaturization due to an external factor with the device in which the thin film semiconductor device is used. The voltage is rarely reduced. As a result, the increase in the electric field strength at the drain end due to miniaturization becomes more prominent. When a thin film semiconductor device is used for a long period of time, there are problems such as deterioration of transistor characteristics, such as threshold voltage fluctuation and reduction of mutual conductance. Arise. When the source / drain end concentration gradient of Example 1 was not provided and when the gradient of this example was provided, the variation rate of the mutual conductance due to long-term driving with a gate length of 1 μm and a power supply voltage of 5 V was compared. The drive time when the mutual conductance ratio reached 10% was defined as the lifetime of the device. It was confirmed that the lifetime of the TFT produced in this example was about orders of magnitude longer than that of the TFT of Example 1. In addition, the off-state current can be reduced by about a half order of magnitude due to the effect of electric field relaxation. Further, the leakage current of the gate insulating film can be reduced by one to one digit from the first embodiment under the same power supply voltage and gate voltage conditions. In addition, the breakdown voltage of the gate oxide film is improved by 10% to 15%.

(Example 3)
Next, in each of the above examples, the metal film for the gate electrode was formed with the SiGe film and the silicon oxide film formed, and no special heat treatment was applied to the SiGe film. In this example, after forming a silicon oxide film, a light pulse of several nanoseconds was irradiated with a YAG laser (excimer laser was used depending on the sample). The irradiation position was moved while repeating this pulsed light 10 to 300 times per site (the number of times varies depending on sample conditions), and the entire film was recrystallized.

By this laser irradiation, the average crystal grain size of the polycrystalline SiGe film can be increased by about 2-3 times before the heat treatment (in the case of Example 1 and Example 2). Further, in the TFT formed by the same process as in Example 2 due to the coarsening of the crystal grains, the electron mobility of the n-channel transistor is 150 cm ² / V · s to 500 cm ² / V · s, and the hole movement of the p-channel transistor. Once again it was greatly improved than the example of the ^{80 cm 2 / V · s~200cm 2} / V · s.

  A TFT in which the polycrystalline film was recrystallized by directly irradiating the SiGe film with laser light without covering the silicon oxide film was also fabricated. In this case, since there is no layer that hinders growth on the upper part of the film during the recrystallization process, the crystal grains are further coarser than when the silicon oxide film is coated. However, in this case, since the crystal grains can grow in the thickness direction of the film as well as in the plane, the unevenness of the film surface increased. As a result, the effect of the coarsening of the crystal grains is remarkable in the mobility, but as expected from the grain size, reflecting the increase of the carrier scattering factor due to the unevenness of the gate oxide film interface region which is important in the MOS type TFT. There was no improvement in mobility. That is, the mobility obtained in the SiGe-TFT subjected to the laser heat treatment with the silicon oxide film formed was not much different.

  In this embodiment, as in the other embodiments, the SiGe film and the gate oxide film have no underlying step, so that the semiconductor layer or the gate insulating film layer is discontinuous or nonuniform due to the underlying step found in the conventional TFT. Since no spots were generated, the off current, the leakage current of the gate insulating film, and the like could be suppressed to the same low current as in the above embodiments.

  In this example, unlike Example 1 and Example 2, the SiGe film was formed by setting the substrate temperature to room temperature. When a film is formed at a low temperature, a film close to amorphous is formed, and when it is crystallized by irradiating a laser in an amorphous state, the film formed at a high temperature and having coarse crystal grains is subjected to a heat treatment and regenerated. This is because a uniform film having a coarser particle diameter can be obtained than when crystallized. Of course, it is needless to say that the crystal grains can be further coarsened by heat-treating the film having coarse crystal grains during film formation.

In each of the above embodiments, a silicon nitride film and a silicon oxide film are laminated on the substrate. In these cases, when the substrate is at a high temperature during film formation as in Example 1 and Example 2, or when high temperature heat treatment such as laser heat treatment after film formation is applied as in Example 3, these heats are applied. The purpose is to prevent impurities contained in the substrate in the process from diffusing into a semiconductor layer such as SiGe or a gate insulating film layer. That is, if impurities from the underlying layer such as a glass substrate diffuse into these layers, the instability and long-term reliability of the TFT MOS transistor characteristics (threshold voltage, etc.) are impaired. In each of the above embodiments, when the undercoat layer 12 is provided, the TFT bias-temperature test when not coated (generally called BT-test, bias-temperature test, which heats the TFT at a temperature of about 100 ° C.) In this state, a voltage was applied to the gate electrode for a certain period of time, and a kind of accelerated life test was conducted to investigate the characteristic fluctuation before and after the test. In this test, a heating temperature of 125 ° C., a voltage of 10 V applied to the gate (+10 V for an n-channel MOS transistor, −10 V for a p-channel MOS transistor) is left for 30 minutes, and then the transistors before and after the test are tested at room temperature. The threshold voltage variation was evaluated. As a result, in the TFT having the undercoat layer, the amount fluctuating in the test was reduced by about 2V to 3V compared to the TFT having no undercoat layer. In the TFT with the undercoat layer, the fluctuation amount was in the range of 0.5V to 1.5V.

In each of the above embodiments, a single-layer SiGe film is used as the semiconductor layer. A TFT in which a SiGe film was formed as a semiconductor layer on an amorphous Si film having a thickness of 10 nm under the same conditions as in the above example was also fabricated. In this case, the adhesion of the SiGe film to the underlayer was improved and the coarsening of the crystal grains was further improved. Although depending on the manufacturing method of the above-mentioned Examples, the crystal grains were 30% to 80% larger in all cases. A 10 nm SiGe film was formed on the amorphous Si film, and a 150 nm thick Ge film was further formed thereon to form a semiconductor layer. By applying the same heat treatment as in Example 3 in this structure, a Ge-TFT having coarse crystal grains with a diameter of 300 nm to 800 nm could be produced. It showed very high Hall mobility and ^{200 cm 2 / V · s~400cm 2} / V · s in p-channel MOS transistor of the TFT.

  Although slightly inferior to this, even if a Ge film is formed directly on the amorphous Si or glass substrate or resin film to form a TFT, a MOS transistor having high mobility can be realized.

The present invention is not limited to the above-described embodiments, and various modifications and applications are possible. For example, in the above-described embodiment, the case where a semiconductor layer that does not cause a step under the gate insulating film is used has been described as an example. However, the present invention is not limited to this, and a predetermined pattern may be formed in the semiconductor layer to cause a step.
When a step is formed in the semiconductor layer when the semiconductor layer is formed in a predetermined pattern, an insulating material is embedded in the region where the semiconductor layer is removed around the pattern, and is planarized by a CMP (Chemical Mechanical Polishing) method or the like, and is embedded on the upper surface of the semiconductor layer. The upper surface of the insulating material is flush with the gate insulating film.

  As the semiconductor layer, other than the Si / Ge system, carbides such as SiC having semiconductor characteristics, oxides such as ZnO, sulfides such as ZnS, selenium compounds such as ZnSe, tellurium compounds such as ZnTe, and so-called chalcogenides Even if a single layer film of a film or a laminated film in which thin films of these materials are laminated is used, there is no step in the off current or the leakage current of the gate insulating film unless a step is provided under the semiconductor layer of the present invention. A remarkable reduction effect can be obtained as compared with the TFT having the same.

  In each of the above embodiments, a metal such as tungsten is used as the gate electrode, but it is needless to say that silicon, silicon-german compound, germanium, etc. which have been reduced in resistance by containing phosphorus, arsenic, boron or antimony can be used. . It is also possible to apply an appropriate threshold voltage to the n-channel MOS transistor as a gate electrode by applying an n-type impurity such as phosphorus, arsenic, or antimony and a p-channel MOS transistor containing the semiconductor film containing p-type impurity such as boron. Needless to say, this is the basis for manufacturing a TFT having the same.

  In the above-described embodiments, when referring to the number of elements and the like (including composition, chemical formula, number, numerical value, amount, range, etc. of the compound), it is limited to a specific number when clearly indicated and in principle. Except sometimes, it is not limited to the specific number, and may be a specific number or more. For example, when a SiGe film is described, the film composition display includes the entire composition range of the plurality of elements other than a film made of a simple substance such as Si or Ge.

  Further, when referring to a silicon oxide film, unless otherwise specified, generally, various silicon oxide films containing various additives and auxiliary components, that is, PSG (Phospho Silicate Glass) film, BPSG (Boro It shall include other single films or composite films such as -Phospho Silicate Glass) film, TEOS (Tetra-Ethoxy Silane) oxide film, silicon oxynitride film.

Furthermore, the term “silicon nitride”, “silicon nitride”, or “silicon nitride” includes not only Si ₃ N ₄ but also an insulating film having a similar composition of silicon nitride.

  The gate insulating film includes a silicon thermal oxide film, a silicon oxynitride film, other thermal oxide films, a deposited film, and a coating system film, and in terms of materials, a non-silicon metal oxide other than a silicon oxide film, Insulating nitride such as silicon nitride, or a composite film thereof is included.

  In addition, the term “silicon” or “silicon base” refers to the material of the conductive film, in addition to a relatively pure silicon member, silicon with impurities and additives, and silicon, unless otherwise specified. A conductive member (for example, SiGe alloy containing Ge as a silicon base alloy, etc., for example, gate polysilicon part or channel region is made SiGe, etc.) or “metal base” In addition to a simple metal, it includes silicon, germanium, and compounds with other elements. They also allow a high resistance at the beginning of formation unless they are technically inconsistent.

  In addition, although the deposited film is amorphous at the beginning of deposition, it may become polycrystalline immediately after the subsequent heat treatment. It may be displayed in a later form. For example, polycrystalline silicon (polysilicon) may be in an amorphous state at the beginning of deposition and is changed to polycrystalline silicon by a subsequent heat treatment. However, it goes without saying that polycrystalline silicon can be used from the beginning. The amorphous state at the beginning of deposition has advantages such as prevention of channeling in ion implantation, avoidance of difficulty in workability depending on the shape of agglomerates during dry etching, and low sheet resistance after heat treatment.

  The present invention is not limited to the case where it is used as a switching element for selectively driving each pixel of a liquid crystal display device as in the above-described embodiment, but a display device represented by a driver circuit, a logic circuit, a memory, or the like. It is also possible to use the peripheral circuit device in an integrated device in which the peripheral circuit device is disposed on the same glass substrate, resin film or the like.

It is a top view which shows the structural example of the thin film semiconductor device which concerns on Embodiment 1 of this invention. It is the II-II sectional view taken on the line of the thin film semiconductor device shown in FIG. It is the III-III sectional view taken on the line of the thin film semiconductor device shown in FIG. It is a figure which shows the manufacturing method of the thin film semiconductor device which concerns on Embodiment 1 of this invention. It is a figure which shows the manufacturing method of the thin film semiconductor device which concerns on Embodiment 1 of this invention. It is a figure which shows the manufacturing method of the thin film semiconductor device which concerns on Embodiment 1 of this invention. It is sectional drawing which shows the structural example of the thin film semiconductor device which concerns on Embodiment 2 of this invention. It is a figure which shows the manufacturing method of the thin film semiconductor device which concerns on Embodiment 2 of this invention. It is a figure which shows the manufacturing method of the thin film semiconductor device which concerns on Embodiment 2 of this invention. It is sectional drawing which shows the conventional thin film semiconductor device.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Thin film semiconductor device, 11 ... Board | substrate, 12 ... 1st insulating layer, 13 ... Semiconductor layer, 14 ... Channel region, 15 ... Source region, 16 ... Drain region, 17 ... Interlayer insulating film, 18 ... Gate insulating film, 21 ... Gate electrode, 22 ... Source electrode, 23 ... Drain electrode, 24 ... Gate extraction electrode, 31 ... Transparent electrode

Claims (19)

A substrate,
A semiconductor layer formed on the substrate;
A gate insulating film provided on the semiconductor layer;
A gate electrode formed on the gate insulating film,
The thin film semiconductor device, wherein the gate insulating film and the semiconductor layer are formed flat so as not to cause a step.   The thin film semiconductor device according to claim 1, wherein an insulating film is formed between the substrate and the semiconductor layer.   The thin film semiconductor device according to claim 1, further comprising a sidewall insulating film formed on the semiconductor layer so as to cover the gate electrode and a side surface of the gate insulating film. A first impurity diffusion region in which impurities are diffused is formed in the surface region of the semiconductor layer,
Further, a second impurity diffusion region in which impurities are diffused is formed under the sidewall insulating film,
The thin film semiconductor device according to claim 3, wherein an impurity concentration of the second impurity diffusion region is lower than an impurity concentration of the first impurity diffusion region.   The thin film semiconductor device according to claim 1, wherein the substrate is made of a glass substrate or a resin film.   6. The semiconductor layer according to claim 1, wherein the semiconductor layer comprises a single layer made of one of silicon, germanium, a mixture thereof, and a carbide of these materials, or a stacked structure of these materials. The thin film semiconductor device according to item.   7. The semiconductor layer according to claim 1, wherein the semiconductor layer is composed of a single layer of a chalcogenide film such as an oxide, a carbide and a sulfide, a selenium compound, a tellurium compound or the like having a semiconductor characteristic or a stacked structure of these material thin films. The thin film semiconductor device according to claim 1.   The thin film semiconductor device according to claim 1, wherein the semiconductor layer contains phosphorus, arsenic, antimony, boron, aluminum, indium, gallium, or the like.   The thin film according to any one of claims 1 to 8, wherein the semiconductor layer is composed of a plurality of elements, and the constituent elements have a distribution in the composition in a film thickness direction of the thin film. Semiconductor device. A semiconductor film is formed over the substrate, an insulating film is formed over the semiconductor film, a conductive film is formed over the insulating film, and a stacked film including the semiconductor film, the insulating film, and the conductive film is formed. A laminated film forming step;
Forming a conductive film in a predetermined pattern and forming a gate electrode;
Forming a gate insulating film by forming the insulating film in a predetermined pattern; and
A method for manufacturing a thin film semiconductor device, comprising: forming a semiconductor layer by forming the semiconductor film in a predetermined pattern. Further comprising an insulating film processing step of forming the insulating film in a pattern corresponding to an operation region;
11. The method of manufacturing a thin film semiconductor device according to claim 10, wherein, in the semiconductor layer forming step, the semiconductor layer is formed using the insulating film formed in a pattern corresponding to an operation region as a mask.   11. The thin film semiconductor device according to claim 10, wherein the gate insulating film forming step forms a gate insulating film by removing the insulating film formed on the semiconductor layer using the gate electrode as a mask. Manufacturing method.   13. The semiconductor device according to claim 10, further comprising an impurity introduction step of introducing impurities into the semiconductor layer through the insulating film in a state where the insulating film is formed on the semiconductor layer. A manufacturing method of the thin film semiconductor device according to the above.   13. The semiconductor device according to claim 10, further comprising an impurity introduction step in which the insulating film on the semiconductor layer is removed or an impurity is introduced into the semiconductor layer through the insulating film. A manufacturing method of the thin film semiconductor device according to the above.   The method of manufacturing a thin film semiconductor device according to claim 10, wherein the substrate is made of a glass substrate and a resin film.   16. The semiconductor layer according to claim 10, wherein the semiconductor layer comprises a single layer made of one of silicon, germanium, a mixture thereof, and a carbide of these materials, or a stacked structure of these materials. A method for manufacturing the thin film semiconductor device according to item.   17. The semiconductor layer according to claim 10, wherein the semiconductor layer comprises a single layer of a chalcogenide film such as an oxide, carbide and sulfide, selenium compound or tellurium compound having semiconductor characteristics, or a stacked structure of these material thin films. The manufacturing method of the thin film semiconductor device of any one of Claims 1.   18. The method of manufacturing a thin film semiconductor device according to claim 10, wherein the semiconductor layer contains phosphorus, arsenic, antimony, boron, aluminum, indium, gallium, or the like.   The thin film according to any one of claims 10 to 18, wherein the semiconductor layer is composed of a plurality of elements, and the constituent elements have a distribution in the composition in a film thickness direction of the thin film. A method for manufacturing a semiconductor device.

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