JP2008112900A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

A semiconductor device capable of suppressing crosstalk noise and preventing malfunctioning and a method for manufacturing the same are provided.
A Si substrate, a Si layer provided on the Si substrate, and insulating isolation layers and covering the bottom and side surfaces of the Si layer in the MOS region are provided. The insulating separation layer 5 includes an insulating film 5a and a conductive layer 5b, and insulates and separates the Si layer 12 in the MOS region from the Si layer 12 in the other region. The insulating separation layer 6 includes an insulating film 6a and a conductive layer 6b, and insulates and separates the Si layer 12 and the Si substrate 1 from each other. Since the conductive layers 5b and 6b are made of a metal or a low-resistance semiconductor, the electric lines of force are blocked between the Si layer 12 in the MOS region and the Si layer 12 in the other region, and between the Si layer 12 and the semiconductor substrate. can do.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device having an SOI structure and a method of manufacturing the same, and more particularly, a mixed mounting of SOI-CMOS and a bipolar device, a mixed mounting of a digital circuit and an analog circuit, or a low voltage / low current driving circuit and a high voltage / high current. The present invention relates to a technique effective for noise reduction in a semiconductor device or the like including a drive circuit.

Field effect transistors formed on an SOI substrate are attracting attention because of their ease of element isolation, latch-up freeness, and low source / drain junction capacitance. In particular, since a fully depleted SOI transistor can operate at low power consumption and at high speed and can be easily driven at a low voltage, research for operating the SOI transistor in a fully depleted mode has been actively conducted. Here, Non-Patent Document 1 discloses a method in which an SOI transistor can be formed at low cost by forming an SOI layer on a bulk substrate. In this method, a Si / SiGe layer is formed on a Si substrate, and only the SiGe layer is selectively removed by utilizing the difference in etching rate between Si and SiGe, whereby the Si substrate and the Si layer are removed. A cavity is formed in Then, the SiO ₂ film (that is, the BOX layer) is formed between the Si substrate and the Si layer by performing thermal oxidation of Si exposed in the cavity.
T.A. Sakai et al. “Separation by Bonding Si Islands (SBSI) for LSI Applications”, Second International SiGe Technology and Device Meeting, Meeting Abstract, pp. 230-231, May (2004)

However, when the bulk structure and the SOI structure are mixedly mounted on the same substrate, the circuit block having the SOI structure is excellent in current interruption with other circuit blocks, but is easily affected by high voltage noise and causes a decrease in reliability. There was a risk of becoming. In particular, an SOI circuit block such as a low voltage / low power driving MOSFET is susceptible to the voltage noise of the high voltage driving circuit block disposed on the same substrate, and the SOI layer back surface (that is, the SOI layer) on the BOX layer. The portion in the vicinity of the BOX layer) may be inverted and malfunctioned.
Accordingly, the present invention has been made in view of such circumstances, and provides a semiconductor device capable of suppressing crosstalk noise between elements and circuit blocks and preventing malfunction, and a method for manufacturing the same. Objective.

[Invention 1] In order to achieve the above object, a semiconductor device of Invention 1 covers a semiconductor substrate, a semiconductor layer provided on the semiconductor substrate, and a bottom surface and a side surface of the semiconductor layer in a predetermined region, An insulating isolation layer that insulates and isolates the semiconductor layer in the predetermined region from both the semiconductor substrate and the semiconductor layer in another region, and the insulating isolation layer includes an insulating layer sandwiching the conductive layer from both sides. And a film. Here, the material of the “conductive layer” is a metal or a low-resistance semiconductor. Further, “insulating and separating” in the present invention means separating so as to maintain an insulated state not only in terms of current but also in terms of electric lines of force.
According to the semiconductor device of the first aspect, the lines of electric force generated between the semiconductor layer in the predetermined region and the semiconductor layer of the other region and the electric lines of force generated between the semiconductor layer and the semiconductor substrate are blocked by the insulating separation layer. The crosstalk noise can be suppressed between them. Thereby, malfunction of the semiconductor device can be prevented.

[Invention 2] A method of manufacturing a semiconductor device of Invention 2 includes a step of forming a first semiconductor layer on a semiconductor substrate, a step of forming a second semiconductor layer on the first semiconductor layer, and the second semiconductor layer. And the first semiconductor layer are partially etched to form a first groove penetrating the second semiconductor layer and the first semiconductor layer, and a first insulation is formed on a bottom surface and a side surface of the first groove. Forming a film, and subsequently forming a first conductive layer in the first groove in which the first insulating film is formed, thereby providing a support for supporting the second semiconductor layer in the first groove. A step of forming, a step of partially etching the second semiconductor layer and the first semiconductor layer to form a second groove exposing a side surface of the first semiconductor layer, and the second semiconductor layer In the specific etching conditions that the first semiconductor layer is more easily etched, Etching the first semiconductor layer through the second groove to form a cavity between the semiconductor substrate and the second semiconductor layer, upper and lower surfaces in the cavity, and the first Forming a second insulating film on each of the bottom and side surfaces of the two grooves, forming a second conductive layer in each of the cavity where the second insulating film is formed and in the second groove; It is characterized by including. Here, the material of the “first conductive layer” and the “second conductive layer” is a metal or a low-resistance semiconductor.

  According to the method for manufacturing a semiconductor device of the second aspect of the present invention, between the second semiconductor layer in the predetermined region and the second semiconductor layer in the other region by the support including the first insulating film and the first conductive layer. Insulating and separating can be performed, and electric lines of force generated therebetween can be blocked. In addition, the second insulating film and the second conductive layer can insulate and separate the second semiconductor layer and the semiconductor substrate, and can block lines of electric force generated between the second semiconductor layer and the semiconductor substrate. Therefore, crosstalk noise can be suppressed between them, and malfunction of the semiconductor device can be prevented.

[Invention 3] The semiconductor device manufacturing method of Invention 3 is characterized in that, in the semiconductor device manufacturing method of Invention 2, the materials of the first conductive layer and the second conductive layer are each a refractory metal. It is. Here, the "high melting point metal", for example, tungsten (W), tungsten silicide (WSi _2), molybdenum silicide (MOSi _2), tantalum (Ta), tantalum silicide (TaSi _2), tantalum nitride (TaN), etc. Is mentioned.
According to the method for manufacturing a semiconductor device of the third aspect, the first and second conductive layers can be prevented from melting when, for example, a gate insulating film is formed on the second semiconductor layer. In addition, since metal is excellent in thermal conductivity, it is possible to efficiently dissipate heat generated in the second semiconductor layer during device operation to the outside.

[Invention 4] The method of manufacturing a semiconductor device of Invention 4 is the method of manufacturing a semiconductor device of Invention 2 or 3, wherein the second conductive layer is made of a refractory metal and the second conductive layer is formed. Then, by introducing a functional liquid into the cavity where the second insulating film is formed, and subsequently subjecting the functional liquid to a heat treatment to evaporate the solvent component, the second conductive layer is formed. It is characterized by forming. With such a method, the film forming material for the second conductive layer can be made to reach deep inside the cavity, and the cavity can be embedded without a gap.

[Invention 5] A method for manufacturing a semiconductor device according to Invention 5 is the method for manufacturing a semiconductor device according to any one of Inventions 2 to 4, wherein the potential of at least one of the first conductive layer and the second conductive layer is fixed. A step of forming a potential fixing contact electrode for this purpose. With such a method, the electric lines of force from the surrounding devices and substrates can be completely blocked by the first conductive layer and the second conductive layer. Therefore, the effect of reducing crosstalk noise can be further enhanced.

[Invention 6] A method for manufacturing a semiconductor device according to Invention 6 is the method for manufacturing a semiconductor device according to any one of Inventions 2 to 5, wherein at least one of the first conductive layer and the second conductive layer is a substance having a large heat capacity. And a step of forming a heat dissipation contact electrode connected to. With such a method, the heat dissipation effect by the first conductive layer or the second conductive layer during device operation can be further enhanced.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1A is a plan view showing a configuration example of a semiconductor device according to an embodiment of the present invention, and FIG. 1B is a cross-sectional view taken along line XX ′ in FIG. FIG.1 (c) is sectional drawing when FIG.1 (a) is cut | disconnected by the YY 'line | wire.
As shown in FIGS. 1A to 1C, this semiconductor device is formed on a silicon (Si) substrate 1, insulating isolation layers 5 and 6 formed on the Si substrate 1, and an insulating isolation layer 6. The formed Si layer 12, the MOS transistor 50 formed on the Si layer 12, the interlayer insulating film 61 formed over the entire surface of the Si substrate 1 to cover the MOS transistor 50, and the gate electrode 53 of the MOS transistor 50 are connected to each other. The first contact electrode 63 for leading out onto the insulating film 61, the second contact electrode 65 for fixing the potential of the insulating separation layer 5 to a predetermined value, and the insulating separation layers 5 and 6 are electrically connected to each other. And a third contact electrode 67 for this purpose. In this figure, in order to avoid complication of the drawing, the entry of the lead electrode for the MOSFET source / drain is omitted.

  Here, the insulating isolation layer 5 is a layer for insulating and isolating the Si layer 12 in the region where the MOS transistor 50 is formed (hereinafter referred to as the MOS region) and the Si layer 12 in the other region in the horizontal direction (that is, Element isolation layer), which is composed of a conductive layer 5b made of a refractory metal or a low-resistance semiconductor, and an insulating film 5a sandwiching the conductive layer 5a from the left and right sides in a sectional view. The insulating isolation layer 6 is a layer (ie, a BOX layer) for insulating and isolating the Si layer 12 in the MOS region and the Si substrate 1 in the depth direction, and is a conductive material made of a refractory metal or a low resistance semiconductor. A layer 6b and an insulating film 6a sandwiching the conductive layer 6a from the upper and lower sides in a cross-sectional view are configured. As shown in FIGS. 1A to 1C, the Si layer 12 in the MOS region is surrounded by the insulating isolation layer 5 from the planar direction and is surrounded by the insulating isolation layer 6 from the depth direction. ing.

When the conductive layers 5b and 6b are made of a refractory metal, the material is, for example, tungsten (W), tungsten silicide (WSi ₂ ), molybdenum silicide (MOSi ₂ ), tantalum (Ta), tantalum silicide (TaSi ₂ ). Or tantalum nitride (TaN). In the case where the conductive layers 5b and 6b are made of a low-resistance semiconductor, the material is N + doped polysilicon (N + Poly Si) to which an N-type impurity such as phosphorus is added. The insulating films 5a and 5b are, for example, a silicon oxide (SiO ₂ ) film or a silicon nitride (SiN) film. Next, a method for manufacturing a semiconductor device having the above structure will be described.

2 to 13 are views showing a method of manufacturing a semiconductor device according to the embodiment of the present invention. Specifically, FIGS. 2A to 13A are diagrams illustrating a process until the XX ′ cross-sectional structure illustrated in FIG. 1B is formed. FIGS. 2B to 13B are diagrams showing a process until the YY ′ cross-sectional structure shown in FIG. 1C is formed.
As shown in FIGS. 2A and 2B, first, a single crystal silicon germanium (SiGe) layer 11 and a single crystal Si layer 12 are sequentially stacked on a single crystal Si substrate 1. These SiGe layer 11 and Si layer 12 are formed by, for example, an epitaxial growth method. The film thickness of the SiGe layer 11 and the Si layer 12 is, for example, about 1 to 200 nm. Next, a SiO ₂ film 21 is formed on the surface of the Si layer 12 by thermal oxidation or CVD. Then, a silicon nitride (SiN) film 23 is formed on the entire surface of the SiO ₂ film 21 by the CVD method. The SiN film 23 functions as an antioxidant film for preventing oxidation of the Si layer 12 and also functions as a stopper layer when performing CMP (Chemical Mechanical Polishing) in a later process.

Next, as shown in FIGS. 3A and 3B, the SiN film 23, the SiO ₂ film 21, the Si layer 12, and the SiGe layer 11 are patterned by using a photolithography technique and an etching technique. A groove 31 for exposing the surface of the substrate 1 is formed. In the etching step for forming the groove 31, the etching may be stopped on the surface of the Si substrate 1, or the Si substrate 1 may be over-etched to form a recess in the Si substrate 1. Further, the arrangement position of the groove 31 corresponds to a part of the element isolation region in the Si layer 12.

Next, as shown in FIGS. 4A and 4B, an insulating film 5 a is formed on the entire surface of the Si substrate 1 including the bottom surface and side surfaces of the groove 31. As described above, the insulating film 5a is, for example, a SiO ₂ film or a SiN film, and is formed by thermal oxidation or a CVD method. Then, as shown in FIGS. 5A and 5B, a conductive layer 5b is formed in the groove 31 so that the entire surface of the substrate is covered by the CVD method. Here, the conductive layer 5b is a refractory metal or a low resistance semiconductor. As described above, when a refractory metal is used for the conductive layer 5b, for example, W, WSi ₂ , MOSi ₂ , Ta, TaSi ₂ or TaN is formed. When a low resistance semiconductor is used as the conductive layer 5b, for example, N + Poly Si to which an N-type impurity such as phosphorus is added is formed. The conductive layer 5b and the insulating film 5a constitute a SBSI support. When the SiGe layer 11 is etched in a later process, the Si layer 12 is supported on the Si substrate 1 by the support. The Rukoto.

Next, the conductive layer 5 b is planarized by, for example, CMP to leave the conductive layer only in the groove 31, and the conductive layer is removed from the insulating film other than the groove 31. Then, as shown in FIGS. 6A and 6B, an insulating film 25 having excellent etching resistance (that is, difficult to be etched with a hydrofluoric acid solution) is formed on the entire surface of the Si substrate 1. For example, a SiO ₂ film or a SiN film is formed as the insulating film 25 by a CVD method. At this time, the support is composed of the conductive layer 5b, the insulating film 5a, and the insulating film 25.

Next, as shown in FIGS. 7A and 7B, the insulating film 25, the SiN film 23, the SiO ₂ film 21, the Si layer 12, and the SiGe layer 11 are patterned using a photolithography technique and an etching technique. Thus, a groove 35 exposing the surface of the Si substrate 1 is formed. In the etching step for forming the groove 35, the etching may be stopped on the surface of the Si substrate 1, or the Si substrate 1 may be over-etched to form a recess in the Si substrate 1. Further, the position of the groove 35 corresponds to a part of the element isolation region in the Si layer 12, and the direction thereof is, for example, a direction substantially orthogonal to the formation direction of the previously formed groove 31 in plan view.

  Next, as shown in FIGS. 8A and 8B, the SiGe layer 11 is removed by etching through the groove 35 to form a cavity 37 between the Si substrate 1 and the Si layer 12. Here, since the support body including the insulating film 5a and the conductive layer 5b is provided in the groove 31 (see FIG. 3A), even when the SiGe layer 11 is removed, the Si layer 12 is formed into Si. It can be supported on the substrate 1. Further, since the groove 35 is provided separately from the groove 31, the etching gas or the etchant can be brought into contact with the SiGe layer 11 under the Si layer 12. For this reason, it is possible to form the cavity 37 between the Si substrate 1 and the Si layer 12 without deteriorating the quality of the Si layer 12. Note that a hydrofluoric acid solution is preferably used for etching the SiGe layer 11. Thus, only the SiGe layer 11 can be removed by etching while sufficiently suppressing the etching of the Si substrate 1 and the Si layer 12. When there is no etching resistance of the conductive layer 5b, the position where the groove 35 is opened is made not to overlap the position where the conductive layer 5b is present in a plane. Thereby, etching of the conductive layer 5b can be avoided.

Next, as shown in FIGS. 9A and 9B, upper and lower surfaces in the cavity portion 37 (that is, the surface of the Si substrate 1 facing the cavity portion 37 and the back surface of the Si layer 12), the groove Insulating films 6a are respectively formed on the bottom and side surfaces of 35 (that is, the surface of the Si substrate 1 facing the groove 35 and the side surfaces of the SiN film 23, the SiO ₂ film 21, and the Si layer 12). As described above, the insulating film 6a is, for example, a SiO ₂ film or a SiN film, and is formed by thermal oxidation or a CVD method.

Next, as shown in FIGS. 10A and 10B, a conductive layer 6b is formed in the cavity. When using a low resistance semiconductor as the conductive layer 6b, for example, N + Poly Si is formed by a CVD method. When a refractory metal is used for the conductive layer 6b, for example, WSi ₂ , MOSi ₂ , Ta, TaSi ₂ or TaN is formed by a CVD method or a liquid metal embedding method.

Here, the liquid metal embedding method will be described. First, in FIGS. 9A and 9B, the Si substrate 1 is immersed in a predetermined chemical solution to make the entire substrate including the inside of the cavity 37 lyophilic. Here, for example, any one of the following A) to D) is used as the predetermined chemical solution.
A) Hydrogen peroxide solution (H ₂ O ₂ + H ₂ O)
B) Ammonia hydrogen peroxide (NH ₄ OH + H ₂ O ₂ + H ₂ O)
C) Sulfuric acid / hydrogen peroxide (H ₂ SO ₄ + H ₂ O ₂ + H ₂ O)
D) Hydrochloric acid overwater (HCl + H ₂ O ₂ + H ₂ O)

  Next, in FIGS. 9A and 9B, for example, Ar or F is ion-implanted from the upper side of the Si substrate 1 toward the surface of the insulating film 25 to make the surface lyophobic. In this ion implantation process, the implantation energy is adjusted to be low so that the depth of impurity distribution (Rp: project range) is near the surface of the insulating film 25. As a result, impurities are ion-implanted only on the surface of the insulating film 25 and the bottom surface of the groove 35, and the surface becomes lyophobic. Since almost no impurities reach the cavity 37, the cavity remains lyophilic. Note that the lyophobic treatment is not limited to ion implantation, and may be, for example, Ar plasma treatment. Here, the Ar plasma treatment is a treatment that exposes the Si substrate 1 to an Ar plasma atmosphere and damages the surface thereof.

Next, a functional liquid is introduced into the cavity 37 through the groove 35. Here, for example, any one of the following a) to c) is used as the functional liquid.
a) Liquid in which metal particles or semiconductor particles are dispersed in a solvent b) MOD (Metal Organic Decomposition) solution c) Silicon compound selected from liquid higher order silane solution, cyclopentasilane and silylcyclopentasilane, and inert organic medium Examples of methods for introducing the functional liquid into the cavity 37 include spin coating and ink jet. Then, after filling the cavity 37 with the functional liquid, the Si substrate 1 is annealed to evaporate the solvent component contained in the functional liquid and solidify the functional liquid. This completes the liquid metal embedding method.

Next, in FIGS. 10A and 10B, planarization is performed on the entire upper surface of the Si substrate 1 by CMP, etch back, or wet etching, so that the conductive layer 6b is formed on the Si substrate 1 other than the trenches. The insulating film 25 and the insulating film 5a are sequentially removed. At this time, the SiN film 23 functions as a stopper for the planarization process. Subsequently, the SiN film 23 is removed by, for example, wet etching using hot phosphoric acid, and the SiO ₂ film 21 is removed by, for example, wet etching using a hydrofluoric acid solution. In this way, as shown in FIGS. 11A and 11B, the surface of the Si layer 12 is exposed.
Next, as shown in FIGS. 12A and 12B, the Si layer 12 is thermally oxidized to form a gate insulating film 51 on the surface thereof. Next, for example, N + Poly Si is formed on the gate insulating film 51 by the CVD method. Then, this N + Poly Si is patterned by using a photolithography technique and an etching technique to form the gate electrode 53.

  Next, using the gate electrode 53 as a mask, impurities such as As, P, and B are ion-implanted into the Si layer 12, and LDD layers (see FIG. (Not shown). Next, an insulating film is formed on the Si layer 12 on which the LDD layer is formed by CVD, and this insulating film is etched back to form a side wall (not shown) on the side wall of the gate electrode 53. Then, using the gate electrode 53 and the sidewall as a mask, impurities such as As, P, and B are ion-implanted into the Si layer 12 to form a source and a drain (not shown).

  Next, as shown in FIGS. 13A and 13B, an interlayer insulating film 61 is formed on the entire upper surface of the Si substrate 1 by a CVD method. Then, the interlayer insulating film 61 is partially etched using photolithography and etching techniques to form contact holes directly above the gate electrode 53 and above the conductive layers 5b and 6b. Then, for example, aluminum (Al) or the like is formed on the entire upper surface of the Si substrate 1 by sputtering to fill the contact holes. Thereafter, the aluminum is patterned by using a photolithography technique and an etching technique to form contact electrodes 63, 65, and 67 (see FIG. 1). Thus, the semiconductor device shown in FIGS. 1A to 1C is completed.

  As described above, according to the embodiment of the present invention, the insulating isolation layer 5 composed of the insulating film 5a and the conductive layer 5b provides the insulating isolation between the Si layer 12 in the MOS region and the Si layer 12 in the other region. Then, the Si layer 12 and the Si substrate 1 are insulated and separated by the insulating separation layer 6 including the insulating film 6a and the conductive layer 6b. Further, the potentials of the respective conductive layers of the insulating separation layers 5 and 6 are fixed to predetermined values via the contact electrodes 65 and 67, so that between the MOS region and other regions, and between the Si layer 12 and the semiconductor substrate The electric lines of force can be efficiently blocked between the two.

  As a result, crosstalk noise can be reduced between the MOS transistor 50 and a device (for example, a MOS transistor or a bipolar transistor) formed in another region, and both regions sandwiching the insulating isolation layer 5 can be reduced. It is possible to contribute to high accuracy and high reliability of device characteristics (for example, transistor operation characteristics). In addition, when circuit blocks configured by a plurality of devices such as MOS transistors 50 are formed in both regions sandwiching the insulating isolation layer 5, crosstalk noise is reduced between the circuit blocks in both regions. Therefore, it is possible to contribute to high accuracy and high reliability of both circuit block characteristics.

Further, when the conductive layers 5b and 6b are made of metal, the thermal conductivity is large, and the amount of heat generated by high speed operation or large current operation can be dispersed throughout the LSI. For example, if the contact electrodes 65 and 67 are connected to a cooling material having a large heat capacity, the amount of heat can be released to the cooling material. In addition, since the device alone and the circuit block are covered with the insulating separation layers 5 and 6, the latch-up resistance is excellent as in the case of normal SOI.
As described above, according to the embodiment of the present invention, it is excellent in latch-up and crosstalk noise resistance, suppresses a local temperature rise of an LSI chip due to circuit operation heat generation, and provides a highly accurate and highly reliable semiconductor device. It becomes possible to do.

  In this embodiment, the Si substrate 1 corresponds to the “semiconductor substrate” of the present invention, the SiGe layer 11 corresponds to the “first semiconductor layer” of the present invention, and the Si layer 12 corresponds to the “semiconductor layer” of the present invention. This corresponds to the “second semiconductor layer”. Further, the groove 31 corresponds to the “first groove” of the present invention, and the groove 35 corresponds to the “second groove” of the present invention. Furthermore, the insulating film 5a corresponds to the “first insulating film” of the present invention, the conductive layer 5b corresponds to the “first conductive layer” of the present invention, and the insulating film 6a corresponds to the “second insulating film” of the present invention. Correspondingly, the conductive layer 6b corresponds to the “second conductive layer” of the present invention. Further, both of the contact electrodes 65 and 67 correspond to the “potential fixing contact electrode” or the “heat dissipation contact electrode” of the present invention.

FIG. 10 illustrates a configuration example of a semiconductor device according to an embodiment. FIG. 6 is a diagram (No. 1) illustrating a method for manufacturing a semiconductor device according to an embodiment. FIG. 6 is a diagram (part 2) illustrating the method for manufacturing the semiconductor device according to the embodiment. FIG. 3 is a diagram (part 3) illustrating the method for manufacturing the semiconductor device according to the embodiment. FIG. 4 is a diagram (part 4) illustrating the method for manufacturing the semiconductor device according to the embodiment. FIG. 5 is a diagram (No. 5) for explaining a method for manufacturing a semiconductor device according to the embodiment; FIG. 6 illustrates a method for manufacturing a semiconductor device according to the embodiment (No. 6). FIG. 7 is a diagram (No. 7) for explaining a method for manufacturing a semiconductor device according to an embodiment. FIG. 8 is a view (No. 8) illustrating the method for manufacturing the semiconductor device according to the embodiment. FIG. 9 is a diagram (No. 9) for illustrating a method for manufacturing a semiconductor device according to an embodiment; FIG. 10 is a view showing the method for manufacturing a semiconductor device according to the embodiment (No. 10). FIG. 11 illustrates a method for manufacturing a semiconductor device according to the embodiment (part 11); FIG. 12 is a view showing a method for manufacturing a semiconductor device according to the embodiment (part 12);

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Si substrate, 5 Insulation isolation layer (element isolation layer), 5a, 6a Insulation film, 5b, 6b Conductive layer (refractory metal or low resistance semiconductor), 6 Insulation isolation layer (BOX layer), 11 SiGe layer, 12 Si Layer (SOI layer), 21 SiO ₂ film, 23 SiN film, 25 insulating film, 31 groove (groove for support), 35 groove (groove for introducing hydrofluoric acid solution), 37 cavity, 50 transistor, 51 gate Insulating film, 53 gate electrode, 61 Interlayer insulating film, 63, 65, 67 Contact electrode

Claims (6)

A semiconductor substrate;
A semiconductor layer provided on the semiconductor substrate;
An insulating separation layer that covers a bottom surface and a side surface of the semiconductor layer in a predetermined region and insulates and isolates the semiconductor layer in the predetermined region from both the semiconductor substrate and the semiconductor layer in another region;
The insulating isolation layer includes a conductive layer and an insulating film sandwiching the conductive layer from both sides. Forming a first semiconductor layer on a semiconductor substrate;
Forming a second semiconductor layer on the first semiconductor layer;
Partially etching the second semiconductor layer and the first semiconductor layer to form a first groove penetrating the second semiconductor layer and the first semiconductor layer;
Forming a first insulating film on a bottom surface and a side surface of the first groove, and subsequently forming a first conductive layer in the first groove in which the first insulating film is formed; Forming a support in the first groove for supporting
Partially etching the second semiconductor layer and the first semiconductor layer to form a second groove exposing a side surface of the first semiconductor layer;
The semiconductor substrate and the second semiconductor are etched by etching the first semiconductor layer through the second groove under a specific etching condition in which the first semiconductor layer is more easily etched than the second semiconductor layer. Forming a cavity between the layers;
Forming a second insulating film on each of the upper and lower surfaces in the cavity and the bottom and side surfaces of the second groove;
Forming a second conductive layer in the cavity where the second insulating film is formed and in the second groove, respectively.   3. The method of manufacturing a semiconductor device according to claim 2, wherein the first conductive layer and the second conductive layer are each made of a refractory metal. The material of the second conductive layer is a refractory metal,
In the step of forming the second conductive layer,
The functional liquid is introduced into the cavity where the second insulating film is formed, and then the functional liquid is subjected to heat treatment to evaporate the solvent component, thereby forming the second conductive layer. The method for manufacturing a semiconductor device according to claim 2, wherein:   5. The method according to claim 2, further comprising: forming a potential fixing contact electrode for fixing a potential of at least one of the first conductive layer or the second conductive layer. A method for manufacturing the semiconductor device according to the item.   6. The method according to claim 2, further comprising: forming a heat dissipation contact electrode that connects at least one of the first conductive layer and the second conductive layer to a substance having a large heat capacity. A method for manufacturing the semiconductor device according to the item.

Images