JP2008112898A - Nonvolatile semiconductor memory device and manufacturing method thereof - Google Patents

Abstract

There is provided a charge trap type nonvolatile semiconductor memory device capable of preventing change in data state due to charge transfer and realizing miniaturization.
A memory transistor includes a first gate structure including a central gate insulating film and a lower gate electrode, which are sequentially stacked on a central portion of a channel region in a semiconductor substrate, and a semiconductor. A second gate structure 52 comprising a charge trap film 4 and a sidewall gate electrode 12 which are sequentially stacked on one end of a channel region in the substrate 1 and on one side surface of the first gate structure 51; and a semiconductor A third gate structure 53 composed of the charge trap film 4 and the sidewall gate electrode 12 formed on the other end of the channel region in the substrate 1 and sequentially stacked on the other side surface of the first gate structure 51; Have. The central gate insulating film 11 does not have charge trapping properties, and the charge trapping film 4 has charge trapping properties.
[Selection] Figure 2

Description

  The present invention relates to a nonvolatile semiconductor memory device and a manufacturing method thereof, and more particularly to a nonvolatile semiconductor memory device having a charge trap film and a manufacturing method thereof.

  In recent years, with high integration and low cost of non-volatile semiconductor memory devices, a MONOS (metal oxide nitride oxide semiconductor) type non-volatile memory having a virtual ground type array and locally trapping charges in a gate insulating film Technology is drawing attention.

  A conventional local trap type nonvolatile semiconductor memory device and a manufacturing method thereof will be described below with reference to the drawings.

  First, a first conventional example will be described with reference to FIGS. 11 to 14 (see, for example, Patent Document 1).

  FIG. 11 shows a planar configuration of a memory cell array according to the first conventional example. As shown in FIG. 11, for example, a plurality of diffusion layer bit lines 102 are formed in the column direction on the semiconductor substrate 101, and a plurality of word line electrodes 103 are formed in the row direction on the semiconductor substrate 101. Has been. Here, the word line electrode 103 functions as a word line. Each memory transistor is formed below the word line electrode 103 sandwiched between a pair of diffusion layer bit lines 102.

  FIG. 12A shows a cross-sectional configuration taken along line XIIa-XIIa in FIG. As shown in FIG. 12A, a plurality of diffusion layer bit lines 102 extending in the column direction are formed on the semiconductor substrate 101 at intervals. In a region sandwiched between the diffusion layer bit lines 102 on the semiconductor substrate 101, a charge trap film 104, which is an ONO film or a silicon oxide film containing fine silicon particles, is formed. A lower gate electrode 105 is formed on each charge trapping film 104, and a buried insulating film 106 is formed between the lower gate electrodes 105 so that the upper surface is aligned with the upper surface of the lower gate electrode 105. Yes. A word line electrode 103 extending in the row direction is formed on the lower gate electrode 105 and the buried insulating film 106. Here, the ONO film is a laminated film in which a silicon nitride film is sandwiched between silicon oxide films.

  FIGS. 12B, 12C, and 12D show cross-sectional structures taken along lines XIIb-XIIb, XIIc-XIIc, and XIId-XIId in FIG. 11, respectively.

  Hereinafter, the manufacturing method of the first conventional example will be described using a cross section taken along line XIIa-XIIa in FIG.

  First, as shown in FIG. 13A, an insulating film 104A and a first conductive film 105A are sequentially deposited on the main surface of the semiconductor substrate 101.

  Next, as shown in FIG. 13B, the first conductive film 105A and the insulating film 104A are selectively etched sequentially using the lower gate processing mask, so that the first conductive film 105A A lower gate electrode 105 is formed, and a charge trap film 104 is formed from the insulating film 104A. Subsequently, a diffusion layer bit line 102 is formed on the semiconductor substrate 101 by ion implantation of, for example, n-type dopant into the semiconductor substrate 101 from the opening using the lower gate processing mask by ion implantation. Thereafter, the lower gate processing mask is removed.

  Next, as shown in FIG. 13C, the buried insulating film 6 is deposited on the semiconductor substrate 101 so as to cover the lower gate electrode 105 and to bury a region between the lower gate electrodes 105 adjacent to each other. .

  Next, as shown in FIG. 14A, the buried insulating film 6 is planarized by the chemical mechanical polishing (CMP) method or the etch back method until the lower gate electrode 105 is exposed.

  Next, as illustrated in FIG. 14B, a second conductive film 103 </ b> A is deposited on the lower gate electrode 105 and the buried insulating film 106. Thereafter, the deposited second conductive film 103A and the lower gate electrode 105 are patterned using a word line processing mask, so that the word line electrode 103 is formed from the second conductive film 103A as shown in FIG. Form. At this time, each lower gate electrode 105 is formed in an island shape in a region on the semiconductor substrate 101 between the bit line diffusion layers 102 and in a region below the word line electrode 103. Thereafter, the process proceeds to a wiring process or the like.

  As described above, in the first conventional example, the diffusion layer bit lines 102 extending in the column direction and adjacent to each other are used as the source and drain, and are located between the adjacent diffusion layer bit lines 102. A memory array is formed by connecting memory transistors having the charge trap film 104 having a thickness as a gate insulating film and the lower gate electrode 105 as a gate electrode by a word line electrode 103 extending in the row direction.

  Next, the basic operation of the nonvolatile semiconductor memory device according to the first conventional example will be described with reference to the drawings.

  First, FIG. 15 shows a first write operation. In FIG. 15, electrons are injected into the left end portion of the charge trapping film 104 in the memory transistor located on the right side in the drawing. Specifically, a voltage of 9V is applied to the word line electrode 103, the diffusion layer bit line 102 located on the left side is opened (opened), and a voltage of 5V is applied to the diffusion layer bit line 102 located in the center. A voltage of 0 V is applied to the right diffusion layer bit line 102 and the semiconductor substrate 101. As a result, electrons flow from the diffusion layer bit line 102 located on the right side to the central diffusion layer bit line 102, and electrons are converted into hot electrons near the right end of the central diffusion layer bit line 2. Thereby, electrons can be injected into the left end portion of the charge trap film 104 of the right memory transistor.

  Next, a case of injecting electrons into the right end portion of the charge trap film 104 in the memory transistor located on the right side in FIG. 16 in the second write operation will be described. The difference from FIG. 15 is that 0 V is applied to the central diffusion layer bit line 102 and 5 V is applied to the right diffusion layer bit line 102.

  Next, FIG. 17 shows an erase operation. As shown in FIG. 17, the erasing operation is performed by injecting holes into the left end portion of the charge trap film 104 in the right memory transistor and neutralizing the charge of the electrons already injected. Specifically, a voltage of −7 V is applied to the word line electrode 103, the left and right diffusion layer bit lines 102 are opened, a voltage of 5 V is applied to the central diffusion layer bit line 102, and 0 V is applied to the semiconductor substrate 101. Apply a voltage of. As a result, holes are generated in the central diffusion layer bit line 102 by the band-to-band tunnel current on the left and right, and become hot holes near the right end of the central diffusion layer bit line 102. Thereby, holes can be injected into the left end portion of the charge trapping film 104 in the memory transistor located on the right side.

  Next, FIG. 18 shows a read operation. FIG. 18 shows a case where the state of the right end portion of the charge trap film 104 in the right memory transistor is read as a read operation. Specifically, a voltage of 5V is applied to the word line electrode 103, the left diffusion layer bit line 102 is opened, a voltage of 1V is applied to the central diffusion layer bit line 102, and the right diffusion layer bit line is applied. A voltage of 0 V is applied to 102, and a voltage of 0 V is applied to the semiconductor substrate 101. As a result, when electrons are accumulated at the right end of the charge trapping film 104, no current flows. Conversely, when electrons and holes are accumulated at the right end of the charge trapping film 104, the current flows. Flows. In this manner, the charge accumulation state at the right end of the charge trap film 104 in the memory transistor located on the right side can be read.

  However, in the nonvolatile semiconductor memory device according to the first conventional example, when each operation described above is performed, as shown in FIG. 19, the nonvolatile semiconductor memory device is provided at the left end portion and the right end portion of the charge trap film 104 in the memory transistor. In some cases, the injected electrons and holes move inside the charge trapping film 104 to change the charge state. In particular, holes are easier to move than electrons, and this phenomenon appears remarkably.

  In order to solve such a problem related to the first conventional example, a second conventional example shown below has been proposed (see, for example, Patent Document 2).

  Hereinafter, the second conventional example will be described with reference to FIG.

  As shown in FIG. 20, a plurality of diffusion layer bit lines 102 are formed on the semiconductor substrate 101 at intervals, and a region sandwiched between the diffusion layer bit lines 102 on the semiconductor substrate 101 has a charge. A central gate insulating film 111 having no trapping property and a U-shaped cross section is formed, and charge trap films 104 are formed on both sides of the central gate insulating film 111, respectively.

  A lower gate electrode 105 is formed inside the central gate insulating film 111, and a sidewall gate electrode 112 is formed outside the central gate insulating film 111 and above the charge trapping film 104. The lower gate electrode 105 and the sidewall gate electrode 112 are electrically connected to the word line electrode 103 at the upper part thereof.

  In the case of the second conventional example, the memory cell array is assumed to be a normal NOR type array using drain contacts.

As described above, in the case of the second conventional example, the charge trap film 104 formed under the memory transistor is divided into the left and right by the central gate insulating film 111 having a U-shaped cross section. Changes in the charge state due to movement are unlikely to occur. Further, since the central gate insulating film 111 can be made thinner than the charge trapping film 104, a finer transistor can be formed.
US Pat. No. 5,168,334 JP 2004-312009 A

  However, the nonvolatile semiconductor memory device according to the second conventional example has a complicated manufacturing method, and the unit cell size can be reduced as in the array structure of the nonvolatile semiconductor memory device according to the first conventional example. Since this is not a suitable virtual ground type array structure but a NOR type array structure that requires about 0.5 contacts per unit cell, there is a problem that it is not practical.

  In view of the above-described conventional problems, an object of the present invention is to prevent a change in data state due to charge transfer and to realize miniaturization of a semiconductor memory device.

  In order to achieve the above object, according to the present invention, a nonvolatile semiconductor memory device has a configuration in which a sidewall gate electrode is formed in a sidewall shape on a side surface of a lower gate electrode.

  Specifically, the non-volatile semiconductor memory device according to the present invention includes a gate electrode, a source diffusion layer, a drain diffusion layer, and a channel formed below the gate electrode in the semiconductor substrate, each arranged in a matrix on the semiconductor substrate. A plurality of memory transistors having a region, a plurality of word lines extending by connecting gate electrodes of memory transistors arranged in the row direction among the plurality of memory transistors, and a memory arranged in the column direction among the plurality of memory transistors And a bit line extending in common with the source diffusion layer or the drain diffusion layer of the transistors, and each memory transistor is formed by sequentially stacking on the central portion of the channel region in the semiconductor substrate. And a first gate structure comprising the first gate electrode and one end of the channel region in the semiconductor substrate A second gate structure composed of a second gate insulating film and a second gate electrode, which are sequentially stacked on top of each other, and a third gate formed by sequentially stacking on the other end of the channel region in the semiconductor substrate A third gate structure including an insulating film and a third gate electrode, and the word line is commonly connected to the first gate electrode, the second gate electrode, and the third gate electrode to form a word line electrode; The first gate insulating film is made of a first insulating film having no charge trapping property, and the second gate insulating film and the third gate insulating film include a second insulating film having a charge trapping property. And

  According to the nonvolatile semiconductor memory device of the present invention, the second insulating film having the trapping property (the second gate insulating film and the third gate insulating film) formed on both sides of the first gate structure has the trapping property. It is formed on both side surfaces of the first gate structure including the first insulating film (first gate insulating film) that does not have. For this reason, since the second gate structure and the third gate structure are electrically insulated by the first gate structure, the movement of electric charges is prevented, so that the data retention characteristic is improved. In addition, since the charge trapping film (second insulating film) and the second and third gate electrodes can be formed by a conventional semiconductor manufacturing process such as a sidewall method, it can be easily manufactured.

  In the nonvolatile semiconductor memory device of the present invention, the second gate insulating film and the second gate electrode in the second gate structure are stacked on one end of the channel region and on one side surface of the first gate structure. The third gate insulating film and the third gate electrode in the third gate structure are formed by being stacked on the other end of the channel region and on the other side surface of the first gate structure. It is preferable.

  In the nonvolatile semiconductor memory device of the present invention, the length of contact between the second gate electrode and the word line electrode in the word line extending direction and the length of contact between the third gate electrode and the word line electrode in the word line extending direction. The length is preferably at least half of the length of each lower end portion of the second gate electrode and the third gate electrode in the extending direction of the word line.

  In the nonvolatile semiconductor memory device of the present invention, the second insulating film preferably has a stacked structure including a silicon oxide film, a silicon nitride film, and a silicon oxide film that are sequentially formed from the semiconductor substrate side.

  In the nonvolatile semiconductor memory device of the present invention, the second insulating film preferably includes particles made of silicon and a silicon oxide film mixed with the particles.

  In the nonvolatile semiconductor memory device of the present invention, one of the source diffusion layer and the drain diffusion layer is formed in a region of the semiconductor substrate on the side opposite to the first gate structure, and the source diffusion layer and the drain are formed. The other of the diffusion layers is preferably formed in a region of the semiconductor substrate opposite to the first gate structure of the third gate structure.

  A first non-volatile semiconductor memory device manufacturing method according to the present invention includes a plurality of memory transistors arranged in a matrix on a semiconductor substrate, and a gate electrode of memory transistors arranged in a row direction among the plurality of memory transistors. Manufacturing of non-volatile semiconductor memory device having a plurality of word lines extending commonly connected to each other and a plurality of bit lines extending commonly connecting source diffusion layers or drain diffusion layers of memory transistors arranged in the column direction (A) sequentially forming a first insulating film having no charge trapping property and a first conductive film on a semiconductor substrate, and the first conductive film and the first insulation. By selectively etching the film, the first gate insulating film is formed from the first insulating film on the central portion of the channel region of each memory transistor, and the first gate film is formed from the first conductive film. Forming a first electrode, forming a first gate structure from the formed first gate insulating film and the first gate electrode, and covering the upper surface and side surfaces of the first gate structure on the semiconductor substrate. And (c) sequentially forming a second insulating film having a charge trapping property and a second conductive film, and selectively and anisotropically etching the second conductive film and the second insulating film. Thus, the second gate insulating film and the third gate insulating film are formed from the second insulating film on both side surfaces in the channel length direction of the channel region in the first gate structure, respectively, and from the second conductive film. A second gate electrode and a third gate electrode are formed, a second gate structure is formed from the formed second gate insulating film and the second gate electrode, and a third gate structure is formed from the third gate insulating film and the third gate electrode. Step (d), and A step (e) of forming a source diffusion layer and a drain diffusion layer to be bit lines on the outer side of the second gate structure and the third gate structure with respect to the first gate structure on the conductor substrate, respectively; (F) forming a buried insulating film that covers the first gate structure, the second gate structure, and the third gate structure and that embeds between adjacent memory transistors, and the formed buried insulation. Etching the upper portion of the film to expose the first gate electrode, the second gate electrode, and the third gate electrode, and leaving a buried insulating film between adjacent memory transistors; A process of forming a third conductive film on the semiconductor substrate so as to be in contact with the upper portions of the first gate electrode, the second gate electrode, and the third gate electrode. (H) and a step (I) of forming a word line electrode from the third conductive film by selectively etching the third conductive film.

  A second non-volatile semiconductor memory device manufacturing method according to the present invention includes a plurality of memory transistors arranged in a matrix on a semiconductor substrate, and gates of memory transistors arranged in a row direction among the plurality of memory transistors. A nonvolatile semiconductor memory device comprising: a plurality of word lines extending by connecting electrodes in common; and a plurality of bit lines extending by commonly connecting source diffusion layers or drain diffusion layers of memory transistors arranged in a column direction (A) sequentially forming a first insulating film having no charge trapping property, a first conductive film, and an etching stopper film on a semiconductor substrate, the etching stopper film, the first By selectively etching the conductive film and the first insulating film, the first gate electrode is formed from the first insulating film on the central portion of the channel region of each memory transistor. (B) forming an insulating film, forming a first gate electrode from the first conductive film, and forming a first gate structure from the formed etching stopper film, first gate insulating film, and first gate electrode; A step (c) of sequentially forming a second insulating film having a charge trapping property and a second conductive film on the semiconductor substrate so as to cover the upper surface and the side surface of the first gate structure; By selectively and anisotropically etching the conductive film and the second insulating film, the second insulating film to the second gate are respectively formed on both side surfaces in the channel length direction of the channel region of the first gate structure. Forming an insulating film and a third gate insulating film, forming a second gate electrode and a third gate electrode from the second conductive film, forming the second gate structure from the second gate insulating film and the second gate electrode, and 3rd gate A step (d) of forming a third gate structure from the edge film and the third gate electrode; and a bit line on the outside of the second gate structure and the outside of the third gate structure with respect to the first gate structure in the semiconductor substrate, respectively. A step (e) of forming a source diffusion layer and a drain diffusion layer, and a memory that covers the first gate structure, the second gate structure, and the third gate structure on the semiconductor substrate and is adjacent to each other The step (f) of forming a buried insulating film embedded between the transistors and etching the upper portion of the formed buried insulating film expose the etching stopper film, the second gate electrode, and the third gate electrode, and A step (g) of leaving a buried insulating film between adjacent memory transistors, and an etching stopper film in the first gate structure The step (h) of exposing the first gate electrode by removing the third gate electrode on the semiconductor substrate so as to be in contact with the exposed first gate electrode, second gate electrode, and third gate electrode. A step (I) of forming a conductive film; and a step (J) of forming a word line electrode from the third conductive film by selectively etching the third conductive film. To do.

  According to the manufacturing method of the first or second nonvolatile semiconductor memory device, the channel region in the first gate structure is obtained by selectively and anisotropically etching the second conductive film and the second insulating film. The second gate insulating film and the third gate insulating film are formed from the second insulating film and the second gate electrode and the third gate electrode are formed from the second conductive film on both side surfaces in the channel length direction, respectively. The second gate structure is formed from the formed second gate insulating film and the second gate electrode, and the third gate structure is formed from the third gate insulating film and the third gate electrode. As a result, the second gate structure and the third gate structure are electrically insulated by the first gate structure and the movement of charges is prevented, so that the data retention characteristic is improved. In addition, since the charge trapping film (second insulating film) and the second and third gate electrodes can be formed by a conventional semiconductor manufacturing process such as a sidewall method, it can be easily manufactured.

  In the second method for manufacturing a nonvolatile semiconductor memory device, the etching stopper film preferably contains silicon nitride.

  In the manufacturing method of the first or second nonvolatile semiconductor memory device, in the step (g), the length in which the second gate electrode and the word line electrode are in contact with each other in the extending direction of the word line and the first extending direction in the extending direction of the word line. Etching so that the length of contact between the 3 gate electrode and the word line electrode is at least half of the length at the lower end of each of the second gate electrode and the third gate electrode in the extending direction of the word line. Is preferred.

  In the first or second nonvolatile semiconductor memory device manufacturing method, the second insulating film has a stacked structure including a silicon oxide film, a silicon nitride film, and a silicon oxide film sequentially formed from the semiconductor substrate side. Preferably it is.

  In the first or second nonvolatile semiconductor memory device manufacturing method, the second insulating film preferably includes particles made of silicon and a silicon oxide film mixed with the particles.

  According to the nonvolatile semiconductor memory device and the method of manufacturing the same according to the present invention, the charge trap film constituting the memory transistor is divided and formed at both ends of the channel region, so that the movement of the charge injected into the charge trap film is prevented. As a result, the data retention characteristics are improved. In addition, since a conventional semiconductor manufacturing process can be employed, manufacturing can be performed easily and reliably. Further, since a virtual ground type array using a buried diffusion layer can be adopted, the memory cell size can be reduced.

(First embodiment)
A nonvolatile semiconductor memory device according to a first embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 shows a planar configuration of a nonvolatile semiconductor memory device according to the first embodiment of the present invention. As shown in FIG. 1, for example, a plurality of diffusion layer bit lines 2 are formed in a column direction on a semiconductor substrate 1 made of, for example, silicon, and a plurality of word line electrodes 3 are formed on the semiconductor substrate 1. It is formed in the row direction. Here, the word line electrode 3 functions as a word line. Each memory transistor 50 is formed below the word line electrode 3 sandwiched between a pair of diffusion layer bit lines 2.

  FIG. 2 shows a cross-sectional configuration taken along line II-II in FIG. As shown in FIG. 2, a plurality of diffusion layer bit lines 2 extending in the column direction are formed on the semiconductor substrate 1 at intervals. Memory transistors 50 are respectively formed in regions sandwiched between the diffusion layer bit lines 2 on the semiconductor substrate 1.

  The memory transistor 50 includes a first gate structure 51 formed at a substantially central portion on a region sandwiched between the diffusion layer bit lines 2 in the semiconductor substrate 1 and both ends of the first gate structure 51 on the row direction side. The second gate structure 52 and the third gate structure 53 are formed in the part. Here, a region below the memory transistor 50 in the semiconductor substrate 1, that is, a region between the diffusion layer bit lines 2 in the semiconductor substrate 1 is a channel region 1a.

  The first gate structure 51 is made of, for example, conductive polysilicon formed on the central gate insulating film 11 made of, for example, silicon oxide and the like, which has no charge trapping property, formed on the semiconductor substrate 1. And the lower gate electrode 5.

  The second gate structure 52 and the third gate structure 53 are formed on the semiconductor substrate 1 and on each side surface of the first gate structure 51 and have charge trapping properties, for example, the charge trap film 4 which is an ONO film. And a sidewall gate electrode 12 made of, for example, conductive polysilicon, formed on the charge trap film 4.

  A buried insulating film 6 made of, for example, silicon oxide is formed between the memory transistors 50 on the semiconductor substrate 1. A word line electrode 3 made of, for example, conductive polysilicon and extending in the row direction is formed on the lower gate electrode 5 and each sidewall gate electrode 12 and on the planarized buried insulating film 6. . The word line electrode 3 is electrically connected to the upper part of the lower gate electrode 5 and the sidewall gate electrode 12, respectively.

  In FIG. 2, the charge trap film 4 is formed between the side surfaces where the lower gate electrode 5 and the side wall gate electrode 12 are opposed to each other. There is no need, and a silicon oxide film may be used. Furthermore, the lower gate electrode 5 and the sidewall gate electrode 12 may be in direct contact without providing an insulating film. These structures can be changed depending on the manufacturing process.

  FIGS. 3A, 3B, and 3C show cross-sectional structures taken along lines IIIa-IIIa, IIIb-IIIb, and IIIc-IIIc in FIG. 1, respectively.

  Hereinafter, a method of manufacturing the nonvolatile semiconductor memory device configured as described above will be described with reference to FIGS. 4 (a) to 4 (c), FIGS. 5 (a) to 5 (c), and FIG. .

  First, as shown in FIG. 4A, a first insulating film 11A is formed on a main surface of a semiconductor substrate 1 made of silicon by a thermal oxidation method or a chemical vapor deposition (CVD) method. Then, the first conductive film 5A is deposited on the first insulating film 11A by the CVD method.

  Next, as shown in FIG. 4B, a first mask pattern (not shown) for forming the lower gate electrode is formed by lithography, and etching is performed using the formed first mask pattern. Then, the lower gate electrode 5 is formed from the first conductive film 5A, and the central gate insulating film 11 is formed from the first insulating film 11A. Thereafter, the first mask pattern is removed.

  Next, as shown in FIG. 4C, the second insulating film 4 </ b> A and the second conductive film 12 </ b> A are covered on the semiconductor substrate 1 so as to cover the lower gate electrode 5 and the central gate insulating film 11. Deposit sequentially.

  Next, as shown in FIG. 5A, anisotropic etching is performed on the deposited second conductive film 12 </ b> A to form sidewall-shaped sidewall gate electrodes 12 on both side surfaces of the lower gate electrode 5. Form. Thereafter, an unnecessary portion of the second insulating film 4A is selectively removed to form the charge trap film 4 between the sidewall gate electrode 12, the semiconductor substrate 1, and the lower gate electrode 5. Subsequently, for example, an n-type dopant is ion-implanted into the semiconductor substrate 1 by ion implantation using the lower gate electrode 5, the charge trap film 4 and the sidewall gate electrode 12 as a mask, thereby diffusing into the upper portion of the semiconductor substrate. Layer bit line 2 is formed in a self-aligning manner.

  Next, as shown in FIG. 5B, a buried insulating film 6 is deposited on the semiconductor substrate 1 so as to cover the lower gate electrode 5, the charge trap film 4 and the sidewall gate electrode 12.

  Next, as shown in FIG. 5C, the buried insulating film 6 is planarized by a chemical mechanical polishing (CMP) method or an etch back method, and the lower gate electrode 5 and the sidewall gate electrode 12 are exposed. At this time, polishing or etchback is performed excessively so that the upper portion of the sidewall gate electrode 12 is exposed with a predetermined width. In the case of performing etch back, etching may be performed as a separate process instead of continuously performing excessive etch back. In this way, by sufficiently exposing the upper portion of the sidewall gate electrode 12, the electrical contact between the sidewall gate electrode 12 and the word line electrode 3 to be performed in the next process can be reliably performed. The electrical resistance between the word line electrode 3 can be reduced.

  Next, as shown in FIG. 6, a third conductive film 3 </ b> A is deposited on the buried insulating film 6 so as to cover the lower gate electrode 5, the charge trap film 4 and the sidewall gate electrode 12. Thereafter, a second mask pattern for forming the word line electrode is formed by lithography, and the second mask pattern thus formed is used to form the word line electrode 3 from the third conductive film 3A as shown in FIG. Further, the lower gate electrode 5 and the sidewall gate electrode 12 are patterned in an island shape. Subsequent wiring steps and the like are omitted.

  Here, when the word line electrode 3, the lower gate electrode 5 and the sidewall gate electrode 12 are simultaneously patterned, the buried insulating film 6 on the sidewall gate electrode 12 serves as a mask and is positioned between adjacent cells in the column direction. There is a possibility that the sidewall gate electrode 12 is not removed by etching and may cause a short circuit. In order to prevent this, the exposed width of the upper portion of the sidewall gate electrode 12 (width L1 shown in FIG. 5C) is set to at least the width of the lower end portion of the sidewall gate electrode 12 (width L2 shown in FIG. 5C). It is necessary to keep at least one half of.

  For example, when the width (L2) of the lower end portion of the sidewall gate electrode 12 is 20 nm, if the exposed width (L2) of the upper portion is set to about 10 nm, the column direction can be improved by isotropic etching and wet etching such as cleaning. Since the side wall gate electrode 12 positioned between adjacent cells can be reliably removed, a short circuit between adjacent cells can be avoided.

  As described above, in the first embodiment, as shown in FIG. 2, extending in the column direction, the adjacent diffusion layer bit lines 2 are used as a source and a drain, and between adjacent diffusion layer bit lines 2. The formed memory transistor 50 includes a first gate structure 51, a second gate structure 52 and a third gate structure 53 formed on both sides thereof. As described above, the first gate structure 51 includes the lower gate electrode 5 and the central gate insulating film 11, and the second gate structure 52 and the third gate structure 53 include the sidewall gate electrode 12 and the charge trap film, respectively. It consists of four. Each memory transistor 50 is electrically connected to the lower gate electrode 5 and the sidewall gate electrode 12 by the word line electrode 3 extending in the row direction, thereby forming a memory array.

  As described above, in the first embodiment, as the gate insulating film of the memory transistor, the central gate insulating film 11 is disposed at the central portion, and the charge trap film 4 is formed at both ends of the central gate insulating film 11. Since the arrangement is adopted, the charges trapped in the charge trap film 4 are difficult to move, and the charge retention characteristics are excellent.

  In addition, since the charge trap film 4 and the sidewall gate electrode 12 can be formed by a conventional semiconductor manufacturing process such as a sidewall method, it can be easily manufactured.

  Here, the central gate insulating film 11 is preferably silicon oxide, and its film thickness is preferably about 10 nm. Further, the central gate insulating film 11 may be partially nitrided.

  The charge trap film 4 is preferably composed of a so-called ONO insulating film having three layers of silicon oxide, silicon nitride and silicon oxide from the bottom and having a total film thickness of about 20 nm. Further, the charge trap film 4 may include a silicon oxide film having a film thickness of about 20 nm, including particles made of silicon having a particle diameter of about 1 nm.

The lower gate electrode 5, the sidewall gate electrode 12, and the word line electrode 3 are preferably made of polysilicon containing arsenic (As) or phosphorus (P) having a carrier concentration of about 1 × 10 ²⁰ cm ^−3. It is. Furthermore, it is desirable that the upper portion of the word line electrode 3 is metal silicided with nickel (Ni) or titanium (Ti).

  The buried insulating film 6 is preferably composed of a silicon oxide film deposited by a CVD method. For example, in FIG. 2, it is desirable that the lower gate electrode 5 has a gate length of about 45 nm and the sidewall gate electrode 12 has a gate length of about 20 nm. In FIG. 3C, the lower gate electrode 5 and the word line electrode 3 preferably have a line width and a space width of about 45 nm.

(Second Embodiment)
A nonvolatile semiconductor memory device according to the second embodiment of the present invention will be described below with reference to the drawings.

  FIG. 7 shows a cross-sectional configuration of a nonvolatile semiconductor memory device according to the second embodiment of the present invention. The planar configuration of the nonvolatile semiconductor memory device according to the second embodiment is the same as that of the first embodiment of FIG. 1, and FIG. 7 corresponds to the cross section taken along the line II-II of FIG. Here, in FIG. 7, the same components as those shown in FIG.

  As shown in FIG. 7, the difference between the second embodiment and the first embodiment is that the height of the lower gate electrode 5 is formed lower than the height of the sidewall gate electrode 12. This is due to the manufacturing method described below.

  8A to 8C, FIG. 9A to FIG. 9C, FIG. 10A, and FIG. 10 for the manufacturing method of the nonvolatile semiconductor memory device configured as described above. This will be described with reference to (b).

  First, as shown in FIG. 8A, a first insulating film 11A made of silicon oxide is formed on the main surface of a semiconductor substrate 1 made of silicon by a thermal oxidation method or a CVD method, and then CVD is performed. By the method, a first conductive film 5A made of polysilicon doped with arsenic or the like and a third insulating film 21A are sequentially deposited on the first insulating film 11A.

  Next, as shown in FIG. 8B, a first mask pattern (not shown) for forming the lower gate electrode is formed by lithography, and etching is performed using the formed first mask pattern. Then, the etching stopper film 21 is formed from the third insulating film 21A, the lower gate electrode 5 is formed from the first conductive film 5A, and the central gate insulating film 11 is formed from the first insulating film 11A. Thereafter, the first mask pattern is removed.

  Next, as shown in FIG. 8C, the second insulating film 4 </ b> A and the second conductive film 12 </ b> A are formed on the semiconductor substrate 1 by using the etching stopper film 21, the lower gate electrode 5, and the central gate insulating film 11. It deposits so that it may cover.

  Next, as shown in FIG. 9A, anisotropic etching is performed on the deposited second conductive film 12 </ b> A to form sidewall-shaped sidewall gate electrodes 12 on both side surfaces of the lower gate electrode 5. Form. Thereafter, an unnecessary portion of the second insulating film 4A is selectively removed to form the charge trap film 4 between the sidewall gate electrode 12, the semiconductor substrate 1, and the lower gate electrode 5. Subsequently, ion implantation is performed on the semiconductor substrate 1 using the etching stopper film 21, the charge trap film 4 and the sidewall gate electrode 12 as a mask by ion implantation, and the diffusion layer bit line 2 is formed on the semiconductor substrate. Form consistently.

  Next, as shown in FIG. 9B, a buried insulating film 6 is deposited on the semiconductor substrate 1 so as to cover the etching stopper film 21, the charge trap film 4, and the sidewall gate electrode 12.

  Next, as shown in FIG. 9C, the buried insulating film 6 is flattened by the CMP method or the etch back method, and the etching stopper film 21 and the sidewall gate electrode 12 are exposed. At this time, polishing or etchback is performed excessively so that the upper portion of the sidewall gate electrode 12 is exposed with a predetermined width. In the case of performing etch back, etching may be performed as a separate process instead of continuously performing excessive etch back.

  Next, as shown in FIG. 10A, the etching stopper film 21 on each lower gate electrode 5 is selectively removed. In this way, by sufficiently exposing the upper portion of the sidewall gate electrode 12, the electrical contact between the sidewall gate electrode 12 and the word line electrode 3 to be performed in the next process can be reliably performed. The electrical resistance between the word line electrode 3 can be reduced.

  Next, as shown in FIG. 10B, a third conductive film 3A is deposited on the buried insulating film 6 so as to cover the exposed lower gate electrode 5, charge trap film 4, and sidewall gate electrode 12. . Thereafter, a second mask pattern for forming the word line electrode is formed by lithography, and the second mask pattern thus formed is used to form the word line electrode 3 from the third conductive film 3A as shown in FIG. Further, the lower gate electrode 5 and the sidewall gate electrode 12 are patterned in an island shape. Subsequent wiring steps and the like are omitted.

  Here, when the word line electrode 3, the lower gate electrode 5 and the sidewall gate electrode 12 are simultaneously patterned, the buried insulating film 6 remaining above the sidewall gate electrode 12 serves as a mask, and adjacent cells in the column direction are connected to each other. The sidewall gate electrode 12 located between them is not removed by etching, and as a result, there is a possibility of causing a short circuit. To prevent this, the exposed width of the upper portion of the sidewall gate electrode 12 (width L1 shown in FIG. 10A) is set to at least the width of the lower end portion of the sidewall gate electrode 12 (width L2 shown in FIG. 10A). It is necessary to keep at least one half of.

  For example, when the width (L2) of the lower end portion of the sidewall gate electrode 12 is 20 nm, if the exposed width (L2) of the upper portion is set to about 10 nm, the column direction can be improved by isotropic etching and wet etching such as cleaning. Since the side wall gate electrode 12 positioned between adjacent cells can be reliably removed, a short circuit between adjacent cells can be avoided.

  As described above, in the second embodiment, by providing the etching stopper film 21 on each lower gate electrode 5, the buried insulating film 6 can be more reliably planarized.

  The etching stopper film 21 is preferably composed of a silicon oxide film having a thickness of about 10 nm and a silicon nitride film having a thickness of about 100 nm formed thereon. In this case, in order to selectively remove the etching stopper film 21 in the step shown in FIG. 10A, first, the upper silicon nitride film is removed by a phosphoric acid boil wet etching method using hot phosphoric acid. Then, it is desirable to remove the lower silicon oxide film by wet etching using hydrofluoric acid as an etchant.

  Further, when a silicon oxide film is grown on the exposed surface of each sidewall gate electrode 12 by thermal oxidation or the like between the step shown in FIG. 9C and the step shown in FIG. It is preferable that the sidewall gate electrode 12 is not etched when the silicon nitride film on the etching stopper film 21 is removed by the wet etching method.

  The nonvolatile semiconductor memory device and the manufacturing method thereof according to the present invention have the effect of being excellent in charge retention characteristics, facilitating the manufacturing process, and being able to cope with miniaturization, having a charge trapping film, and having a virtual ground type This is useful for nonvolatile semiconductor memory devices that can employ arrays.

1 is a plan view showing a nonvolatile semiconductor memory device according to a first embodiment of the present invention. It is sectional drawing in the II-II line of FIG. (A) is sectional drawing in the IIIa-IIIa line | wire of FIG. (B) is sectional drawing in the IIIb-IIIb line | wire of FIG. (C) is sectional drawing in the IIIc-IIIc line | wire of FIG. (A)-(c) is sectional drawing of the order of a process which shows the manufacturing method of the non-volatile semiconductor memory device which concerns on the 1st Embodiment of this invention. (A)-(c) is sectional drawing of the order of a process which shows the manufacturing method of the non-volatile semiconductor memory device which concerns on the 1st Embodiment of this invention. It is sectional drawing of 1 process which shows the manufacturing method of the non-volatile semiconductor memory device which concerns on the 1st Embodiment of this invention. FIG. 4 is a cross-sectional view showing a nonvolatile semiconductor memory device according to a second embodiment of the present invention and corresponding to the II-II line of FIG. 1. (A)-(c) is sectional drawing of the order of a process which shows the manufacturing method of the non-volatile semiconductor memory device which concerns on the 2nd Embodiment of this invention. (A)-(c) is sectional drawing of the order of a process which shows the manufacturing method of the non-volatile semiconductor memory device which concerns on the 2nd Embodiment of this invention. (A) And (b) is sectional drawing of the order of a process which shows the manufacturing method of the non-volatile semiconductor memory device based on the 2nd Embodiment of this invention. It is sectional drawing which shows the non-volatile semiconductor memory device concerning a 1st prior art example. (A) is sectional drawing in the XIIa-XIIa line | wire of FIG. (B) is sectional drawing in the XIIb-XIIb line | wire of FIG. (C) is sectional drawing in the XIIc-XIIc line | wire of FIG. (D) is sectional drawing in the XIId-XIId line | wire of FIG. (A)-(c) is sectional drawing of the order of a process which shows the manufacturing method of the non-volatile semiconductor memory device based on a 1st prior art example. (A) or (b) is sectional drawing of the order of a process which shows the manufacturing method of the non-volatile semiconductor memory device concerning a 1st prior art example. FIG. 10 is a schematic cross-sectional view for explaining a first write operation of the nonvolatile semiconductor memory device according to the first conventional example. FIG. 10 is a schematic cross-sectional view for explaining a second write operation of the nonvolatile semiconductor memory device according to the first conventional example. FIG. 10 is a schematic cross-sectional view for explaining an erasing operation of the nonvolatile semiconductor memory device according to the first conventional example. FIG. 10 is a schematic cross-sectional view for explaining a read operation of the nonvolatile semiconductor memory device according to the first conventional example. FIG. 10 is a schematic cross-sectional view for explaining charge transfer in the nonvolatile semiconductor memory device according to the first conventional example. It is sectional drawing which shows the non-volatile semiconductor memory device concerning a 2nd prior art example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 1a Channel region 2 Diffusion layer Bit line 3 Word line electrode 3A Third conductive film 4 Charge trap film 4A Second insulating film 5 Lower gate electrode 5A First conductive film 6 Buried insulating film 11 Central gate insulation Film 11A first insulating film 12 sidewall gate electrode 12A second conductive film 21 etching stopper film 21A third insulating film 50 memory transistor 51 first gate structure 52 second gate structure 53 third gate structure

Claims (12)

A plurality of memory transistors, each of which is arranged in a matrix on a semiconductor substrate, and has a gate electrode, a source diffusion layer, a drain diffusion layer, and a channel region formed below the gate electrode in the semiconductor substrate;
Among the plurality of memory transistors, a plurality of word lines extending by commonly connecting the gate electrodes of the memory transistors arranged in a row direction;
A bit line extending commonly connected to the source diffusion layer or the drain diffusion layer of the memory transistors arranged in a column direction among the plurality of memory transistors;
Each of the memory transistors is
A first gate structure including a first gate insulating film and a first gate electrode, which are sequentially stacked on a central portion of the channel region in the semiconductor substrate;
A second gate structure including a second gate insulating film and a second gate electrode, which are sequentially stacked on one end of the channel region in the semiconductor substrate;
A third gate structure including a third gate insulating film and a third gate electrode, which are sequentially stacked on the other end of the channel region in the semiconductor substrate;
The word line is commonly connected to the first gate electrode, the second gate electrode, and the third gate electrode to form a word line electrode,
The first gate insulating film is a first insulating film having no charge trapping property,
The nonvolatile semiconductor memory device, wherein the second gate insulating film and the third gate insulating film include a second insulating film having a charge trapping property. The second gate insulating film and the second gate electrode in the second gate structure are formed by being laminated on one end of the channel region and on one side surface of the first gate structure,
The third gate insulating film and the third gate electrode in the third gate structure are formed by being stacked on the other end of the channel region and on the other side surface of the first gate structure. The nonvolatile semiconductor memory device according to claim 1.   The length of contact between the second gate electrode and the word line electrode in the extending direction of the word line and the length of contact between the third gate electrode and the word line electrode in the extending direction of the word line are 3. The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device has a length equal to or more than one half of a length of each lower end portion of the second gate electrode and the third gate electrode in a word line extending direction.   The second insulating film has a stacked structure including a silicon oxide film, a silicon nitride film, and a silicon oxide film sequentially formed from the semiconductor substrate side. 2. The nonvolatile semiconductor memory device according to item 1.   4. The nonvolatile semiconductor memory device according to claim 1, wherein the second insulating film includes particles made of silicon and a silicon oxide film mixed with the particles. 5. One of the source diffusion layer and the drain diffusion layer is formed in a region of the semiconductor substrate opposite to the first gate structure of the second gate structure,
The other of the source diffusion layer and the drain diffusion layer is formed in a region of the semiconductor substrate opposite to the first gate structure of the third gate structure. 6. The nonvolatile semiconductor memory device according to any one of 5 above. A plurality of memory transistors arranged in a matrix on a semiconductor substrate, a plurality of word lines extending by connecting gate electrodes of memory transistors arranged in a row direction among the plurality of memory transistors, and a column direction A method for manufacturing a nonvolatile semiconductor memory device comprising a plurality of bit lines extending commonly connected to source diffusion layers or drain diffusion layers of memory transistors arranged in a row,
(A) sequentially forming a first insulating film having no charge trapping property and a first conductive film on the semiconductor substrate;
By selectively etching the first conductive film and the first insulating film, a first gate insulating film is formed from the first insulating film on a central portion of the channel region of each memory transistor. Forming a first gate electrode from the first conductive film, and forming a first gate structure from the formed first gate insulating film and first gate electrode;
A step (c) of sequentially forming a second insulating film having a charge trapping property and a second conductive film on the semiconductor substrate so as to cover an upper surface and a side surface of the first gate structure;
By selectively and anisotropically etching the second conductive film and the second insulating film, the second conductive film and the second insulating film are respectively formed on both side surfaces in the channel length direction of the channel region in the first gate structure. A second gate insulating film and a third gate insulating film are formed from the second insulating film, and a second gate electrode and a third gate electrode are formed from the second conductive film. Forming a second gate structure from the gate electrode and a third gate structure from the third gate insulating film and the third gate electrode;
Forming a source diffusion layer and a drain diffusion layer to be bit lines on the outside of the second gate structure and the third gate structure with respect to the first gate structure in the semiconductor substrate, respectively (e);
Forming a buried insulating film on the semiconductor substrate so as to cover the first gate structure, the second gate structure, and the third gate structure, and fill the space between the adjacent memory transistors (f); )When,
The upper part of the formed buried insulating film is etched to expose the first gate electrode, the second gate electrode, and the third gate electrode, and the buried insulating film remains between the memory transistors adjacent to each other. A step (g) of
Forming a third conductive film on the semiconductor substrate so as to be in contact with the exposed upper portions of the first gate electrode, the second gate electrode, and the third gate electrode;
And (I) forming a word line electrode from the third conductive film by selectively etching the third conductive film. A method for manufacturing a nonvolatile semiconductor memory device . A plurality of memory transistors arranged in a matrix on a semiconductor substrate, a plurality of word lines extending by connecting gate electrodes of memory transistors arranged in a row direction among the plurality of memory transistors, and a column direction A method for manufacturing a nonvolatile semiconductor memory device comprising a plurality of bit lines extending commonly connected to source diffusion layers or drain diffusion layers of memory transistors arranged in a row,
(A) sequentially forming a first insulating film having no charge trapping property, a first conductive film, and an etching stopper film on the semiconductor substrate;
By selectively etching the etching stopper film, the first conductive film, and the first insulating film, the first gate insulating film is formed from the first insulating film on the center portion of the channel region of each memory transistor. Forming a first gate electrode from the first conductive film, and forming a first gate structure from the formed etching stopper film, the first gate insulating film, and the first gate electrode (b) When,
A step (c) of sequentially forming a second insulating film having a charge trapping property and a second conductive film on the semiconductor substrate so as to cover an upper surface and a side surface of the first gate structure;
By selectively and anisotropically etching the second conductive film and the second insulating film, the second conductive film and the second insulating film are respectively formed on both side surfaces in the channel length direction of the channel region in the first gate structure. A second gate insulating film and a third gate insulating film are formed from the second insulating film, and a second gate electrode and a third gate electrode are formed from the second conductive film. Forming a second gate structure from the gate electrode and a third gate structure from the third gate insulating film and the third gate electrode;
Forming a source diffusion layer and a drain diffusion layer to be bit lines on the outside of the second gate structure and the third gate structure with respect to the first gate structure in the semiconductor substrate, respectively (e);
Forming a buried insulating film on the semiconductor substrate so as to cover the first gate structure, the second gate structure, and the third gate structure, and fill the space between the adjacent memory transistors (f); )When,
The upper portion of the formed buried insulating film is etched to expose the etching stopper film, the second gate electrode, and the third gate electrode, and leave the buried insulating film between the memory transistors adjacent to each other. Step (g);
(H) exposing the first gate electrode by removing the etching stopper film in the first gate structure;
Forming a third conductive film on the semiconductor substrate so as to be in contact with the exposed upper portions of the first gate electrode, the second gate electrode, and the third gate electrode;
And a step (J) of forming a word line electrode from the third conductive film by selectively etching the third conductive film. .   9. The method of manufacturing a nonvolatile semiconductor memory device according to claim 8, wherein the etching stopper film contains silicon nitride.   In the step (g), the length of contact between the second gate electrode and the word line electrode in the extending direction of the word line and the third gate electrode and the word line electrode in the extending direction of the word line are 8. The etching is performed so that a contact length becomes one half or more of a length at each lower end portion of the second gate electrode and the third gate electrode in the extending direction of the word line. Or a method of manufacturing the nonvolatile semiconductor memory device according to 8.   The said 2nd insulating film has a laminated structure containing the silicon oxide film, silicon nitride film, and silicon oxide film which were sequentially formed from the said semiconductor substrate side. 2. A method for manufacturing a nonvolatile semiconductor memory device according to item 1.   11. The non-volatile semiconductor memory device according to claim 7, wherein the second insulating film includes particles made of silicon and a silicon oxide film mixed with the particles. Method.

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