JP2008109073A - Wiring board and mounting structure - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring board having high density wiring which is excellent in connection reliability and lamination reliability. <P>SOLUTION: This wiring board is provided with an insulating substrate and a conductive part formed on the insulating substrate, to which a chip component is electrically connected, wherein the insulating substrate is configured of base materials composed of a fiber bundle configured of a single fiber or a plurality of single fibers and a resin part covering the base material. The single fiber is configured of resin materials having a linear expansion coefficient smaller than that of the materials of the chip member, and the resin part is configured of resin materials having a linear expansion coefficient larger than that of the materials of the chip component. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a wiring board used for electronic devices such as various AV devices, home appliances, communication devices, computer devices and peripheral devices thereof, and more particularly to a wiring substrate on which a silicon chip is flip-chip mounted.

  In the present invention, the “substantially the same number” is synonymous with 80% or more and 100% or less of the number of other single fibers. In the present invention, “substantially the same” includes the same.

  2. Description of the Related Art Conventionally, a wiring board includes a large number of active elements typified by semiconductor elements such as IC (Integrated Circuit) and LSI (Large Scale Integration) and passive elements such as capacitive elements and resistive elements to constitute a predetermined electronic circuit. Used in hybrid integrated circuits. This wiring board is usually manufactured as follows. (1) A so-called double-sided copper-clad substrate obtained by adhering copper foil to the upper and lower surfaces of an insulating substrate formed by impregnating an epoxy resin into a glass cloth is processed into a wiring conductor having a wiring pattern by a subtractive method. (2) Thereafter, a base is formed by forming a through hole (through hole) penetrating the wiring conductor and the insulating substrate by a drill, and forming a through conductor formed by depositing a conductor layer by plating in the through hole. Is produced. (3) A wiring board is manufactured by laminating an insulating layer called a solder resist on the main surface (see, for example, Patent Documents 1 and 2).

  Alternatively, in order to further increase the wiring density, an insulating layer made of an epoxy resin or the like is laminated on the main surface of the substrate manufactured in (2), and a through hole (via hole) is formed in the insulating layer by irradiating a laser beam. After forming, the conductor layer is formed inside the through hole by plating, and the process of forming the wiring conductor on the surface of the insulating layer is repeated several times. It is manufactured (see, for example, Patent Document 3).

In a multilayer wiring board, an insulating layer is usually formed on an inner circuit board on which an inner layer circuit is formed, a metal layer is formed thereon, a hole penetrating the entire wiring board is formed, and a via reaching the inner layer circuit is formed. A hole is formed to electrically connect the inner layer circuit and the metal foil, and unnecessary portions of the metal foil are removed by etching. With a normal insulating material, the coefficient of thermal expansion is about 16 ppm / ° C. There was a big difference between 3ppm / ° C of silicon chip.
JP 2002-198658 A JP 2002-212394 A JP 2005-86164 A

  In recent years, there is a tendency that a low dielectric constant material is used for a silicon surface with the increase in speed and function of LSI. Although the lowest dielectric constant material is air, there is a problem in circuit retention, so low dielectric constant material candidates tend to be materials containing many bubbles. Since the low dielectric constant material containing many bubbles has low strength, if a silicon chip using such a low dielectric constant material containing bubbles is flip-chip mounted on a conventional substrate, the heat generated between the substrate and the silicon chip Due to the difference in expansion coefficient, there is a problem that the low dielectric constant material on the surface of the silicon chip cracks during the cooling process after flip chip mounting, and the circuit is disconnected.

  For this reason, a package for mounting a silicon chip using a low dielectric constant material containing bubbles must be as small as possible in the thermal expansion coefficient difference from the silicon chip so as not to cause thermal stress in the silicon chip. For this reason, the thermal expansion coefficient of the package substrate is required to be as close as possible to the thermal expansion coefficient of the silicon chip.

  Further, LSIs tend to be large because they process a lot of data at the same time. As LSIs increase in size, it is necessary to increase I / O (Input / Output) for inputting and outputting data. I / O is currently on the order of thousands, but is expected to reach 10,000 in the future. For this reason, there is a tendency to reduce the size of the connection portion (bump) between the semiconductor element and the wiring board. Currently, bumps having a diameter of 100 μm and a pitch of 220 μm will be reduced to a size of 50 μm to 75 μm and a pitch of 100 μm to 125 μm. Is required. When bumps are downsized, the mechanical strength decreases and the distance between the silicon chip and the substrate shrinks. Therefore, due to the difference in thermal expansion coefficient between the substrate and the silicon chip, the bumps are formed by repeated heating and cooling during product use. There is a problem that the system stops because it breaks and the circuit is disconnected.

  For this reason, a package for mounting a silicon chip requiring a large bump with a large I / O must be as small as possible in the thermal expansion coefficient difference from the silicon chip so as not to cause thermal stress in the silicon chip. For this reason, the thermal expansion coefficient of the wiring board is required to be as close as possible to the thermal expansion coefficient of the silicon chip.

  However, a normal insulating substrate obtained by impregnating a glass cloth with an epoxy resin has a large coefficient of thermal expansion of the glass cloth, and it has been difficult to achieve a thermal expansion coefficient equivalent to that of a silicon chip. In addition, since it is difficult to drill a glass cloth with a drill or a laser beam, there is a limit to miniaturization of the through conductor, and because the thickness of the glass cloth is not uniform, a through conductor with a uniform hole diameter is required. There was a problem that it was difficult to form.

  The present invention has been completed in view of the problems of the prior art, and an object thereof is to provide a wiring board having high-density wiring and excellent connection reliability and lamination reliability.

  The wiring board of the present invention is a wiring board provided with a conductive portion in which a chip component is electrically connected to an insulating substrate, and the insulating substrate is a base material composed of a single fiber or a fiber bundle made of a plurality of single fibers. And the resin part covering the base material, wherein the single fiber is made of a resin material having a smaller linear expansion coefficient than the material of the chip part, and the resin part is linearly expanded than the material of the chip part. It is made of a resin material having a large coefficient.

  In the wiring board according to the present invention, the chip component is a silicon chip.

  The wiring board of the present invention is characterized in that the base material is composed of a woven fabric formed by weaving the single fibers or the fiber bundles.

  In the wiring board of the present invention, the single fiber has a corrugated shape corresponding to a pitch at which the woven fabric is knitted, and a single fiber length corresponding to one period with respect to the period of the corrugated shape. Is more than 1 time and 1.20 times or less.

  The wiring board according to the present invention is characterized in that the cross section of the fiber bundle as viewed by cutting along a virtual plane perpendicular to the longitudinal direction is a horizontally long flat shape.

  In the wiring board of the present invention, the fiber bundle in one direction among the fiber bundles intersecting the two directions is substantially the same as the number of other single fibers in the group of single fibers adjacent to the fiber bundle in the other direction. It is the same number or more than the same number.

  In the wiring board of the present invention, the base material is configured by arranging the single fibers or the fiber bundles in a plurality of rows.

  In the wiring board of the present invention, the Young's modulus of the single fiber is 10 GPa or more, and the Young's modulus of the resin material is 0.05 GPa or more.

  In the wiring board of the present invention, the linear expansion coefficient (25 ° C. or more and 200 ° C. or less) of the single fiber is −10 ppm / ° C. or more and 0 ppm / ° C. or less, and the linear expansion coefficient (25 ° C. or more) of the resin material. 200 ° C. or less) is characterized by being 10 ppm / ° C. or more and 60 ppm / ° C. or less.

  In the wiring board of the present invention, the resin material is made of an epoxy resin containing 20 wt% or more and 80 wt% or less of a nonmetallic inorganic filler.

  The wiring board of the present invention is characterized in that a volume ratio of the base material to the substrate is 40% by volume or more and 70% by volume or less.

  The wiring board of the present invention is characterized in that a groove is formed along the longitudinal direction of the surface portion of the single fiber.

  In the wiring board of the present invention, the single fiber is a resin fiber made of any of aromatic polyamide, wholly aromatic polyester, and polyparaphenylene benzobisoxazole.

  The wiring board of the present invention is characterized in that a wiring layer formed by alternately laminating insulating layers and circuit layers is formed on at least one main surface side of the insulating substrate.

  According to another aspect of the present invention, there is provided a mounting structure including the wiring board and a semiconductor element bonded to a conductive portion formed on the wiring board via a bump.

  The wiring board of the present invention is a resin portion made of a resin material having a linear expansion coefficient larger than that of a chip part material, in which a fiber or a bundle of single fibers having a lower linear expansion coefficient than that of the chip part material is used. Since it is coated, the following effects are obtained.

  The thermal expansion coefficient of the entire wiring board can be made substantially the same as the chip material. Therefore, even if the difference in thermal expansion between the semiconductor element and the wiring board is small and a temperature change occurs due to a change in the switching mode of the semiconductor element, a large distortion caused by the difference in thermal expansion occurs at the connection part between the wiring board and the semiconductor element. The reliability of the connection, that is, the reliability of the product is maintained. Therefore, in the wiring board of the present invention, disconnection does not occur when performing flip chip mounting of a semiconductor chip using an insulating material having a low dielectric constant, and the performance of the semiconductor element can be sufficiently exhibited. It becomes. Therefore, it is possible to realize a wiring board having high-density wiring and excellent connection reliability and lamination reliability.

  Further, according to the present invention, even if the chip component is a silicon chip, it is possible to maintain a thermal expansion coefficient substantially the same as that of silicon as a wiring board by using a single fiber having a lower linear expansion coefficient than silicon. Thereby, even when a silicon chip is mounted on the wiring board, a large distortion due to a difference in thermal expansion does not occur in the connection portion, and connection reliability is maintained.

  According to the invention, when the base material is made of a woven fabric formed by weaving single fibers or fiber bundles, the single fibers or fiber bundles are arranged in a wave shape on one and the other in the thickness direction of the substrate. Has been. The greater the swell, the more “spring” effect (referred to as the spring effect) is exhibited, and the effect of using low thermal expansion fiber is reduced. Therefore, it is desirable that the value indicating the degree of undulation is such that the length of the single fiber corresponding to one period is greater than 1 and less than or equal to 1.20 times of the waveform period. When this value is “1”, it indicates that there is no wave and the fibers are straight. If the numerical value is less than “1”, the change in one or the other of the fibers in the thickness direction is small, so that the thermal expansion coefficient of the wiring board can be lowered, but there is a problem that the resin is easily peeled off at the interface where the fibers are laminated. .

  When the numerical value is greater than “1” and equal to or less than “1.20”, the spring effect is small, so that the resin does not peel off at the interface and the effect of reducing the thermal expansion coefficient is large. This numerical range is optimally from 1.02 to 1.10. Within that numerical range, the spring effect can be made as small as possible, the peeling of the resin at the interface can be surely prevented, and the effect of reducing the thermal expansion coefficient can be further increased. When the numerical value exceeds “1.20”, the spring effect becomes large, and it becomes difficult to obtain a low thermal expansion coefficient that is almost the same as that of the semiconductor element as a whole regardless of the low thermal expansion fiber used.

  Further, according to the present invention, when the base material is made of a single fiber or a woven fabric formed by weaving fiber bundles, the cross-sectional shape of the fiber bundle is made to be a horizontally long flat shape so that the single crosses in two directions. The contact portion of the fiber can be enlarged. This can prevent the deformation of the fiber near the intersection as much as possible. In other words, it is possible to reduce the spring effect in the vicinity of the intersection.

  On the contrary, when the cross-sectional shape of the fiber bundle is not a horizontally long flat shape, the contact portion of the single fiber in the vicinity of the intersection is small, and deformation of the fiber is observed in the vicinity of the intersection. For this reason, a spring effect is observed in this portion, and it becomes difficult to obtain a low thermal expansion coefficient substantially the same as that of the semiconductor element as a whole even if any low thermal expansion fiber is used.

  Further, according to the present invention, when the substrate is made of a single fiber or a woven fabric formed by weaving fiber bundles, the fiber bundle in one direction has the number of groups of single fibers adjacent to the fiber bundle in the other direction. The contact portion of the single fibers intersecting in two directions can be increased by being approximately the same number or more than the number of other single fibers. This can prevent the deformation of the fiber near the intersection as much as possible. Therefore, even when a temperature change occurs, distortion due to a difference in thermal expansion does not occur at the connection portion between the wiring board and the semiconductor element, and connection reliability is maintained.

  On the other hand, when the number of single fibers in the group is smaller than the number of other single fibers, the contact portion of the single fibers intersecting in two directions is small, and deformation of the fibers is observed in the vicinity of the intersection. . For this reason, a spring effect is observed in this portion, and it becomes difficult to obtain a low thermal expansion coefficient substantially the same as that of the semiconductor element as the whole wiring board, no matter what low thermal expansion fiber is used.

  According to the present invention, the wiring board of the present invention can be realized by a single fiber having a Young's modulus of 10 GPa or more and a resin material having a Young's modulus of 0.05 GPa or more.

  According to the invention, the linear expansion coefficient in the longitudinal direction of the single fiber is −10 ppm / ° C. or more and 0 ppm / ° C. or less, and the linear expansion coefficient of the resin material is 10 ppm / ° C. or more and 60 ppm / ° C. or less. Depending on the conditions, the thermal expansion coefficient of the entire wiring board can be lowered to a level equivalent to that of the semiconductor element.

  Further, according to the present invention, a wiring board can be realized by a resin material made of an epoxy resin containing 20 wt% or more and 80 wt% or less of a nonmetallic inorganic filler.

  Moreover, according to this invention, a nonmetallic inorganic filler can be implement | achieved by spherical silica.

  Moreover, according to this invention, the effect which makes the whole insulating substrate the low thermal expansion coefficient can be heightened by making the volume ratio of the said base material with respect to an insulating substrate into 40 volume% or more and 70 volume% or less. If the volume ratio of the base material is less than 40% by volume, there is little effect of making the entire insulating substrate have a low coefficient of thermal expansion, and if the volume ratio of the base material exceeds 70% by volume, voids are generated between the fibers, This may cause defects such as insulation failure or substrate swelling. Thus, the volume% of the substrate is preferably 40% by volume or more and 70% by volume or less, and the optimum range is preferably 45% by volume or more and 55% by volume or less.

  Further, according to the present invention, since the groove portion is formed along the longitudinal direction, that is, the axial direction, on the surface portion of the single fiber, the contact area between the fiber and the resin portion is increased and both are firmly bonded. Thereby, peeling with a fiber and a resin part can be reduced.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings. In addition, a figure is this schematic and does not necessarily correspond with an actual dimension ratio. FIG. 1 is a cross-sectional view of a main part of a wiring board 1A according to the first embodiment of the present invention. FIG. 2 is an enlarged cross-sectional view (enlarged cross-sectional view of FIG. 1) showing the relationship between the fiber bundle 4y in one direction and the fiber bundle 4x in the other direction. A wiring board 1A according to the first embodiment (also referred to as a first wiring board) is used in electronic devices such as various AV devices, home appliances, communication devices, computer devices, and peripheral devices thereof. However, it is not necessarily limited to these devices and apparatuses. The following description also includes a description of a method for manufacturing a wiring board. 1 A of 1st wiring boards are provided with the wiring conductors 2 and 3 as an electroconductive part in an insulating substrate, and have the resin woven fabric 4 as a base material, and the resin part 5 which coat | covers this resin woven fabric 4. As shown in FIG.

  First, the resin woven fabric 4 will be described. The resin woven fabric 4 is formed by weaving a single fiber made of a resin material such as wholly aromatic polyamide, wholly aromatic polyester, or polyparaphenylene benzobisoxazole, or a fiber bundle formed by bundling a plurality of single fibers in two directions. In this embodiment, fiber bundles are used. One direction of the two directions means one direction perpendicular to the thickness direction of the first wiring board 1. The other direction of the two directions means a direction perpendicular to the one direction and the thickness direction. Of the two directions, one direction is defined as the x direction, the other direction is defined as the y direction, and the thickness direction is defined as the z direction.

  In the resin woven fabric 4, the linear expansion coefficient of the resin is defined as a lower linear expansion coefficient than that of silicon which is a material of a silicon chip to be mounted on the first wiring substrate 1. The single fibers 4a are arranged in a wave shape on one side and the other side in the z direction, and have a wave shape corresponding to the pitch at which the resin woven fabric 4 is knitted. At the same time, the single fiber 4a has a single fiber length S corresponding to one period with respect to the wave-like period L and is defined to be greater than 1 and not greater than 1.20 times.

  In other words, the greater the swell, the more the swell exhibits a “spring” effect (referred to as a spring effect), and thus the effect of using a fiber having a low thermal expansion coefficient is reduced. As for the value indicating the degree of the undulation, it is desirable that the single fiber length S corresponding to one period is greater than 1 time and equal to or less than 1.20 times the wave period L. When this value is “1”, it indicates that there is no wave and the fibers are straight. If the numerical value is less than “1”, the change in one or the other in the thickness direction of the fiber is small, so that the thermal expansion coefficient of the substrate can be lowered, but there is a problem that the resin is easily peeled off at the interface where the fibers are laminated.

  When the numerical value is greater than “1” and equal to or less than “1.20”, the spring effect is small, so that the resin does not peel off at the interface and the effect of reducing the thermal expansion coefficient is large. This numerical range is optimally from 1.02 to 1.10. Within that numerical range, the spring effect can be made as small as possible, the peeling of the resin at the interface can be surely prevented, and the effect of reducing the thermal expansion coefficient can be further increased.

  In other words, the fiber bundle is formed such that the cross-sectional shape of the fiber bundle as viewed by cutting along a virtual plane perpendicular to the longitudinal direction is a horizontally long flat shape. Here, as shown in FIG. 7, “flat” means that the maximum width of the cross-sectional shape of the fiber bundle is w and the maximum thickness is t, and (w / t) ≧ 10. The cross-sectional shape refers to a shape formed by connecting tangent lines drawn with respect to single fibers constituting the fiber bundle. In addition, the maximum width w and the maximum thickness t are average values when measured in a cross section when the fiber bundle is viewed by cutting at five virtual planes perpendicular to the longitudinal direction. Thus, the contact part of the single fiber 4a which cross | intersects two directions can be enlarged by making the cross-sectional shape of a fiber bundle into a horizontally long flat shape. This can prevent the deformation of the fiber near the intersection as much as possible. In other words, it is possible to reduce the spring effect in the vicinity of the intersection. On the contrary, when the cross-sectional shape of the fiber bundle is not a horizontally long flat shape, the contact portion of the single fiber 4a in the vicinity of the intersection is small, and deformation of the fiber is observed in the vicinity of the intersection. Here, FIG. 4 is a cross-sectional view of a main part of a conventional wiring board 10. FIG. 5 is an enlarged cross-sectional view showing the relationship between the fiber bundle 11 in one direction and the fiber bundle 12 in the other direction in the conventional wiring board 10. For this reason, a spring effect is observed in this portion, and it becomes difficult to obtain a low thermal expansion coefficient substantially the same as that of the semiconductor element as a whole even if any low thermal expansion fiber is used.

  In other words, in the fiber bundle 4y in one direction among the fiber bundles intersecting with the xy direction, the number α of the single fibers 4a adjacent to the fiber bundle 4x in the other direction is substantially equal to the number β of the other single fibers 4a. Same number or more. Here, “the single fiber 4a adjacent to the fiber bundle 4x in the other direction” means, as shown in FIG. 8, a fiber bundle 4x in contact with the single fiber 4a constituting the fiber bundle 4y (4x) in one direction and in the other direction. When the perpendiculars down to (4y) are P1 and P2, no other single fiber exists in the region (hatched portion in the figure) surrounded by the perpendiculars P1 and P2, the single fiber 4a, and the fiber bundle 4x in the other direction. This refers to the single fiber 4a (hereinafter also referred to as “close single fiber”). For example, among the three single fibers 4a of the unidirectional fiber bundle 4y shown in FIG. 8, the lower two are adjacent single fibers, but the upper one is not the adjacent single fibers. The “number α of single fibers 4a” is an average value of the number of adjacent single fibers in a cross section when the fiber bundle is viewed by cutting at five virtual planes perpendicular to the longitudinal direction. “Number β of single fibers 4a” is an average value of the number of single fibers other than adjacent single fibers in the same cross section. Thus, by making the number α of adjacent single fibers substantially the same as or more than the number β of other single fibers, the contact portion of the single fibers 4a intersecting in two directions can be increased, and the vicinity of the intersection It is possible to prevent the deformation of the fiber at the maximum. Therefore, even when a temperature change occurs, a large distortion due to a difference in thermal expansion does not occur at the connection portion between the substrate and the semiconductor element, and connection reliability is maintained.

  On the contrary, when the number α of the adjacent single fibers is smaller than the number β of the other single fibers, the contact portion of the single fibers intersecting in two directions is small, and deformation of the fibers is observed in the vicinity of the intersection. The For this reason, a spring effect is observed in this portion, and it becomes difficult to obtain a low thermal expansion coefficient substantially the same as that of the semiconductor element as a whole even if any low thermal expansion fiber is used.

  In the 1st wiring board 1, the single fiber 4a whose Young's modulus is 10 GPa or more is used suitably. Moreover, the linear expansion coefficient (25 ° C. or more and 200 ° C. or less) in the longitudinal direction of the single fiber 4a is applied from −10 ppm / ° C. to 0 ppm / ° C. Further, the volume ratio of the resin woven fabric 4 to the substrate is set to 40% by volume or more and 70% by volume or less. This can enhance the effect of making the entire substrate have a low coefficient of thermal expansion. If the volume ratio of the resin woven fabric 4 is less than 40% by volume, the effect of reducing the overall thermal expansion coefficient of the substrate is small, and if the volume ratio of the resin woven fabric 4 exceeds 70% by volume, there is a gap between the fibers. This causes a failure such as an insulation failure or a swelling of the substrate. Thus, the volume% of the resin woven fabric 4 is preferably 40 volume% or more and 70 volume% or less, and the optimal range is preferably 45 volume% or more and 55 volume%.

  FIG. 3 is a cross-sectional view showing the groove 6 of the single fiber 4a. Since the groove part 6 is formed in the surface part of the said single fiber 4a along the longitudinal direction, ie, an axial direction, there exist the following effects. By increasing the contact area between the single fiber 4a and the resin portion 5 and firmly bonding them, the separation between the single fiber 4a and the resin portion 5 can be reduced.

  Next, the resin part 5 will be described.

  The resin portion 5 that covers the resin woven fabric 4 is made of a resin material having a linear expansion coefficient larger than the linear expansion coefficient of 3 ppm / ° C. of the silicon chip. As this resin material, one having a Young's modulus of 0.05 GPa or more is applied, and one having a linear expansion coefficient (25 ° C. or more and 200 ° C. or less) of 10 ppm / ° C. or more and 60 ppm / ° C. or less is applied. The resin material is made of an epoxy resin containing 20 wt% or more and 80 wt% or less of a nonmetallic inorganic filler (for example, spherical silica). The first wiring board 1 can be formed by the resin portion 5 made of such a resin material.

Table 1 is a table showing individual data (such as Young's modulus) of wiring boards numbered from “1” to “17”.

Table 2 is a table showing individual data (such as Young's modulus) of wiring boards numbered from “18” to “34”. The S glass, T glass, and E glass in Table 2 are SiO ₂ of 50 wt% or more and 70 wt% or less, the balance is Al ₂ O ₃ , and impurities are MgO, CaO, B ₂ O ₃ , Na ₂ O, K _2. It is synonymous with glass containing a small amount of O and ZrO ₂ .

Table 3 is a table showing the test results of the wiring boards numbered from “1” to “17”.

Table 4 is a table showing the test results of the wiring boards numbered from “18” to “34”.

  According to the first wiring board 1 described above, a single fiber 4a made of resin having a lower linear expansion coefficient than silicon or a fiber bundle made of a plurality of single fibers 4a are arranged in two directions and knitted together. Since the resin woven fabric 4 is covered with the resin portion 5 made of a resin material having a larger linear expansion coefficient than silicon, the following effects can be obtained.

  The coefficient of thermal expansion of the entire first wiring board can be made substantially the same as that of silicon. Accordingly, the difference in thermal expansion between the semiconductor element and the substrate is reduced, and even when a temperature change occurs due to a change in the switching mode of the semiconductor element, a large strain due to the thermal expansion difference is generated at the connection portion between the substrate and the semiconductor element. It does not occur and connection reliability, that is, product reliability is maintained. Therefore, the first wiring board 1 can fully exhibit the performance of the semiconductor element without causing disconnection when performing flip chip mounting of a semiconductor chip using a low dielectric constant insulating material. It becomes. Therefore, it is possible to realize a wiring board having high-density wiring and excellent connection reliability and lamination reliability.

  The use of the single fiber 4a having a linear expansion coefficient lower than that of silicon is because the thermal expansion coefficient of the copper wiring part inevitably included in the wiring board is 16 ppm / ° C., and therefore the first wiring board 1 includes the copper wiring part. Even if it is a case, it is for maintaining a thermal expansion coefficient substantially the same as that of silicon as a substrate. When a silicon chip is mounted on the first wiring substrate 1 as described above, a large distortion due to a difference in thermal expansion does not occur in the connection portion, and connection reliability is maintained.

  The 1st wiring board 1 is realizable with the single fiber 4a whose Young's modulus is 10 GPa or more, and the resin material whose Young's modulus is 0.05 GPa or more. In the first wiring board 1, it is important that the Young's modulus of the single fiber 4a is 10 GPa or more. Since the thermal expansion coefficient of the copper wiring portion inevitably included in the first wiring board 1 is 16 PPM / ° C., the Young's modulus of the fiber is 65 GPa or more in order to reduce the overall thermal expansion coefficient including the copper wiring. Some are preferred. The higher the Young's modulus of the fiber, the better. However, since the fiber having a higher Young's modulus tends to decrease the adhesive force with the insulating resin, a fiber of about 200 to 270 GPa is desirable.

  Further, if the Young's modulus of the resin is less than 0.05 Gpa, the force for holding the fibers becomes weak and the fibers move in various directions, so that there is a problem that the deformation of the substrate becomes large. When the Young's modulus of the resin is high and the thermal expansion coefficient of the resin is high, there is a problem that the effect of lowering the thermal expansion of the entire substrate by the fibers having a low thermal expansion coefficient is reduced. When the Young's modulus of the resin is high and the thermal expansion coefficient of the resin is 10 PPM / ° C. or less, the thermal expansion coefficient of the entire substrate can be lowered for simulation, but a resin material having such characteristics is currently commercially available. It has not been.

  The Young's modulus of the single fiber and the resin material can be measured by the following method.

  In the case of resin, the tensile stress per unit cross-sectional area obtained by cutting a film prepared by curing under the same conditions as when producing a wiring board into a rectangular test piece and measuring this test piece with a tensile tester Can be measured by dividing by the amount of elongation of the resin. Moreover, in the case of a single fiber, it can be measured by dividing the tensile stress per unit cross-sectional area obtained by measuring a fiber bundle with a tensile tester by the amount of elongation of the fiber.

  Moreover, it can also measure from the state used as the wiring board. In the case of resin, the resin is cut into a thin piece, an indenter such as a quadrangular prism or a triangular pyramid is pushed into the surface of the thin piece, and the load applied to the indenter at that time and the projected area under the indenter are obtained. In the case of a single fiber, the fiber bundle can be taken out by removing the resin, and the tensile stress per unit cross-sectional area obtained by measuring the fiber bundle with a tensile tester can be divided by the amount of elongation of the fiber. Alternatively, the Young's modulus of the resin is measured in advance from the resin cut into a thin piece as described above, and the Young's modulus is measured in the state of a composite of the resin and the fiber. From the Young's modulus, the Young's modulus of the single fiber can also be measured by simulation.

  The linear expansion coefficient in the longitudinal direction (axial direction) of the single fiber 4a is −10 ppm / ° C. to 0 ppm / ° C., and the linear expansion coefficient of the resin material is 10 ppm / ° C. to 60 ppm / ° C. and other conditions. The thermal expansion coefficient of the entire substrate can be lowered to the same level as that of the semiconductor element. The lower the linear expansion coefficient in the axial direction of the single fiber 4a, the better. The linear expansion coefficient is suitably used as long as it is 0 ppm / ° C. or less. If it exceeds 0 ppm / ° C., the effect of making the whole substrate have a low coefficient of thermal expansion is lost. The lower the linear expansion coefficient of the resin material, the better. However, a resin material having a linear expansion coefficient of 10 ppm / ° C. or less is not commercially available, and thus has not been tested. The linear expansion coefficient of the resin material is preferably 10 ppm / ° C. or more and 50 ppm / ° C. or less. This is because if it exceeds 50 ppm / ° C., the thermal expansion coefficient of the entire first wiring board cannot be made equal to that of silicon.

  The linear expansion coefficient in the longitudinal direction of the single fiber can be measured by the following method, and the linear expansion coefficient of the resin material can be measured by the following method.

In the case of resin, for example, a test piece of 2 × 3 × 15 mm is cut out, and the temperature is raised while contacting a test probe for dimension measurement with this test piece. In the case of a single fiber, the measurement can be performed by attaching the fiber bundle to a probe for measuring dimensions, increasing the temperature while applying a load in the direction of pulling the fiber bundle, and measuring the dimensional change due to the temperature change.

  Moreover, it can also measure from the state used as the wiring board. In the case of resin, the resin is cut into thin pieces of appropriate size, this thin piece is attached to a dimensional measurement probe as a test piece, the temperature is increased while applying a load in the direction of pulling the test piece, and the dimensional change due to temperature change is changed. It can be measured by measuring. In the case of single fibers, the resin is removed and the fiber bundle is taken out. The fiber bundle is attached to a dimensional measurement probe, the temperature is increased while applying a load in the direction of pulling the fiber bundle, and the dimensional change due to the temperature change is measured. Can be measured. Alternatively, the thermal expansion coefficient of the resin is measured in advance from the resin cut into a thin piece as described above, the thermal expansion coefficient is measured in the state of the composite of the resin and the fiber, and the thermal expansion coefficient of the composite The thermal expansion coefficient of the single fiber can also be measured by simulation from the thermal expansion coefficient of the resin alone.

  FIG. 6 is a cross-sectional view showing a modification of the wiring board 1A according to the first embodiment of the present invention and an example of the mounting structure 20 of the present invention.

  A wiring board 1A shown in FIG. 6 has a wiring layer 13 formed by alternately laminating insulating layers 14 and circuit layers 15 on both main surfaces of an insulating substrate.

  The insulating layer 14 is made of a resin film set so that the thickness dimension is about 12 μm or more and 50 μm or less. In order to lower the thermal expansion coefficient of the entire substrate to the same level as that of the semiconductor element, it is preferable that the Young's modulus of the resin film is 10 GPa or more and the linear expansion coefficient is 3 ppm / ° C. or less. As the material, polyparaphenylene benzobisoxazole (polybenzoxazole), polyimide benzoxazole, wholly aromatic polyamide, wholly aromatic polyester, or liquid crystal polymer can be used. This resin film contains a filler for adjusting the thermal expansion coefficient and improving the mechanical strength. As the ceramic material used as the inorganic filler, silica (silicon dioxide), aluminum oxide or the like is used. The particle shape of the filler includes a substantially spherical shape, a needle shape and a flake shape, and a substantially spherical shape is preferable from the viewpoint of filling properties.

  On the other hand, the circuit layer 15 is formed by plating a metal material such as copper, and the thickness thereof is set to 3 to 18 μm, for example. The circuit layers 15 are connected to each other by a via conductor 18 provided in the insulating layer 14. The via conductor 18 is formed by copper plating or the like, like the circuit layer 15.

  Between the insulating layer 14 and the circuit layer 15 or between the insulating layers 14, an adhesive 17 mainly composed of any one of acrylic resin, epoxy resin, urethane resin, and silicon resin is interposed. The insulating layer 14 and the circuit layer 15 or the insulating layers are bonded to each other by this adhesive. The combination of materials of the insulating layer 14 and the adhesive 17 is selected so that the adhesiveness between the insulating layer 14 and the adhesive 17 is good and the heat resistance is high. As a result, when the wiring board is mounted on another external board using solder or the like, the heat resistance becomes good. The combination of the material of the insulating layer 14 and the adhesive 17 is selected so that the difference in thermal expansion coefficient between the insulating layer 14 and the adhesive 17 is small. As a result, the stress due to the difference in thermal expansion coefficient can be reduced, and peeling at the interface between the circuit layer 15 and the insulating layer 14 can be prevented. Further, the overall warpage of the wiring board 1A can be reduced, and a wiring board that can better cope with the narrowing of the pitch of the terminals of the semiconductor elements mounted on the surface thereof can be obtained.

  The circuit layer 15 in the wiring layer 13 on the one main surface side of the insulating substrate and the circuit layer 15 in the wiring layer 13 on the other main surface side are through holes provided on the inner wall surface of the through hole penetrating in the thickness direction of the insulating substrate. It is electrically connected through the conductor 16.

  The mounting structure 20 includes a wiring board 1A and a semiconductor element mounted on the wiring board 1A. The semiconductor element is a silicon chip 21 and is mounted on a pad 23 as a conductive portion formed on one main surface of the wiring substrate 1A via bumps 22 made of a conductive material such as solder or gold. The silicon chip 21 has a function of controlling a predetermined electric signal or a function of retaining predetermined information, and is manufactured using, for example, a low dielectric constant material (Low k material) such as diamond-like carbon. It is. By using such a Low k material, signals can be processed at high speed, while the silicon chip 21 made of the Low k material has low strength. Therefore, in the conventional wiring board, when such a silicon chip is mounted, there is a disadvantage that the silicon chip is easily damaged due to mismatch of thermal expansion coefficients between the silicon chip and the wiring board. On the other hand, when the silicon chip 21 is mounted on the wiring board according to the present invention, since the difference in the thermal expansion coefficient between the silicon chip 21 and the wiring board 1A is small, the stress generated due to the difference in the thermal expansion coefficient is also present. As a result, the silicon chip 21 can be prevented from being damaged.

  Next, a wiring board 1B according to a second embodiment of the present invention will be described with reference to FIGS. Note that the wiring board 1B according to the second embodiment will be described with a focus on the configuration different from the wiring board 1A according to the first embodiment described above, and the same reference numerals will be given to the same configuration and description thereof will be given. Is omitted.

  FIG. 9 is a cross-sectional view of the wiring board 1B according to the second embodiment, and FIG. 10 is a perspective view of each sheet constituting the wiring board 1B. In the wiring board 1A according to the first embodiment, a woven fabric formed by weaving single fibers or fiber bundles is used as the base material, whereas in the wiring board 1B according to the second embodiment, the base material is used. As described above, a plurality of single fibers or a plurality of fiber bundles arranged in a plurality of rows are used. In this way, the wiring board 1B made of a base material in which single fibers or fiber bundles are aligned in one direction basically does not exhibit the fiber spring effect, and therefore the linear expansion coefficient in the longitudinal direction of the fibers can be made extremely small. . On the other hand, the linear expansion coefficient is not so small in the direction orthogonal to the longitudinal direction of the fiber. Therefore, in the wiring board 1B according to the present embodiment, as shown in FIG. 10, a plurality of resin sheets 51, 52, 53, and 54 made of the resin portion 5 that covers the fibers that are aligned in one direction are arranged as fibers. They are stacked in different directions. More specifically, when the longitudinal direction of the fibers of the uppermost resin sheet 51 is 0 °, the longitudinal direction of the fibers of each resin sheet is 0 °, 90 °, 90 °, and 0 ° in order from the top. Thus, the wiring substrate 1B is formed by stacking. By laminating in this way, low thermal expansion can be realized while uniformizing the linear expansion coefficient of the entire wiring board 1B. In addition, the direction of the longitudinal direction of a fiber is not restricted to the above, For example, 0 degree, 60 degrees, 120 degrees, 0 degrees, etc. may be sufficient.

  Next, a method for manufacturing a wiring board will be described with reference to Tables 1 and 2.

  As the woven fabric 4, there were prepared three types of resin fibers and three types of glass fibers, and various changes in the thickness of the yarn and the pitch of the weave. Moreover, about the wholly aromatic polyamide and the polyparaphenylene benzobisoxazole fiber, the sheet | seat which arranged the fiber aligned in one direction was also prepared.

  An insulating resin was prepared as a resin material. The resin used was an epoxy resin, a cyanate resin, or a bismaleimide triazine resin. These resins and curing agents were dissolved in a solvent such as methyl ethyl ketone and mixed well so that no solid matter remained. Next, the spherical silica powder which performed the silane coupling process previously about the predetermined resin was mixed. The spherical silica subjected to the silane coupling treatment was mixed with a solvent of the same type as the solvent in which the resin was dissolved in advance to loosen the particles. Next, the resin and silica powder were mixed in a solvent and further filtered through a nylon filter to remove undissolved resin and coarse aggregated particles of silica. Next, the mixture was dried while mixing to produce a varnish having a predetermined concentration and viscosity.

  Next, the prepared varnish was impregnated into a sheet in which the woven fabric and the fibers were arranged in one direction. After impregnation, the excess varnish was removed with a squeeze roll, and the amount of resin adhered to the fiber was adjusted. This sheet was dried with a dryer to obtain a prepreg. A predetermined number of the prepregs were stacked, and copper foils having a thickness of 8 μm were stacked on the front and back surfaces, and heated and pressed at 200 ° C. for 60 minutes under a pressure of 3.5 MPa with a vacuum press device to prepare a substrate with copper foils on both sides.

  The hole processing and core substrate circuit will be described.

  After the substrate was prepared, both surfaces of the substrate were cleaned to remove foreign substances such as resin adhering to the surface, and then a through hole was processed with a laser device. The processed hole was cleaned again, and electroless plating and electrolytic plating were performed to complete the through-hole conductor 16. Furthermore, a photosensitive resist is applied, exposure and development of a desired circuit is performed, etching is performed to form a copper circuit, finally the resist is peeled off, and a core substrate having a circuit layer 15 on each side one layer It was.

  The build-up process will be described.

  A wiring board was also produced in which a wiring layer 13 formed by alternately laminating insulating layers 14 and circuit layers 15 on the front and back of the core board was formed by a build-up method. Build-up was performed using the semi-additive method. That is, an epoxy-based insulating material is applied to the core substrate, via holes are formed by laser processing, electroless plating is performed on the front surface, a photosensitive resist is applied to the surface, and exposure and development of the plating film are performed. Then, the circuit layer 15 was formed by energizing the electroless plating layer to form a circuit pattern by electroplating, and then removing the resist and removing the electroless copper plating layer by etching. . Further, by repeating this process once more, the wiring board shown in FIG. 6 in which three wiring layers 13 were formed per side was produced.

  The substrate thickness when the build-up process is performed is, for example, not less than 400 μm and not more than 500 μm. Further, the thickness of the circuit layer 15 is, for example, 10 μm or more and 12 μm or less, and the linear expansion coefficient of copper used as the material of the circuit layer 15 is, for example, 16 ppm / ° C. The insulating layer 14 has a thickness of 20 μm, for example.

  The substrate evaluation method will be described with reference to Tables 3 and 4.

  The thermal expansion coefficient was measured as a basic characteristic from the produced substrate. In addition, a solder float test was performed to confirm the presence of internal defects such as bubbles. Furthermore, the presence or absence of destruction of the silicon chip after mounting the silicon chip was examined.

  The measurement of the coefficient of thermal expansion will be described.

  About the produced core board | substrate, the sample for thermal expansion coefficient measurement was cut out from the board | substrate without copper foil, and the board | substrate after circuit formation, and the thermal expansion coefficient was measured. Moreover, the sample was cut out from the board | substrate which performed the build-up process and the number of circuit layers is 2 layers per layer, and 3 layers, and measured the thermal expansion coefficient.

  The solder float test will be described.

  Solder float is a test in which a sample floats in a heated solder bath. When defects such as bubbles remain in the inside, peeling and swelling of the layer occur from the defects, so that the defect can be identified. Specifically, the prepared sample was floated in a solder bath heated to 280 ° C., and the presence or absence of swelling of the sample was observed. A sample in which discoloration due to blistering or peeling of the layer was observed was judged as defective. In Tables 3 and 4, a sample determined to be defective was indicated as “x”, and a sample determined as non-defective was indicated as “◯”.

  A destructive test after chip mounting will be described.

  The silicon chip was flip-chip mounted, and the surface of the mounted silicon chip was examined with an ultrasonic microscope and a micro X-ray microscope for the presence or absence of the chip after mounting. The results are shown in Tables 3 and 4. In Tables 3 and 4, "x" indicates that the chip is cracked, and "◯" indicates that the chip is not cracked.

  The sample used in this test is a mounting structure in which bumps are formed on a prototype wiring board, and a silicon chip manufactured using diamond-like carbon (abbreviated as DLC) which is a kind of low k material is mounted on the wiring board. Is the body. Since a silicon chip made of a low k material has low strength, generally, the low k material portion tends to be easily broken due to mismatch in thermal expansion coefficient between the silicon chip and the wiring board after mounting. On the other hand, in the mounting structure using the wiring board of the present invention, the silicon chip can be prevented from being broken. The wiring boards Nos. 12 and 13 were not damaged by the silicon chip, but the board was greatly deformed, and it was confirmed that the silicon chip was not mounted correctly.

  In addition, this invention is not limited to the above-mentioned embodiment, A various change, improvement, etc. are possible in the range which does not deviate from the summary of this invention.

  In the present embodiment described above, the fiber bundles are arranged in two directions in the x and y directions, but this arrangement direction is not limited to only two directions. For example, there may be a case where fiber bundles are arranged in three or more directions and knitted together. In this case, the rigidity strength of the wiring board can be increased as compared with those arranged in two directions. In addition, fiber bundles arranged in two directions may be perpendicular to the z direction but may not intersect perpendicularly.

  In the above-described embodiment, an example in which a single groove portion 6 is formed on the surface of the single fiber 4a has been shown. However, a plurality of groove portions 6 are formed along the axial direction around the surface portion of the single fiber 4a. It may be. By increasing the groove portion 6, the contact area between the fiber and the resin portion 5 increases, and both can be bonded more firmly. Therefore, peeling between the fiber and the resin portion 5 can be reduced.

  Further, the non-metallic inorganic filler in the above-described embodiment is not necessarily limited to spherical silica. For example, even non-spherical silica has substantially the same effect as this embodiment.

  In the above-described embodiment, the silicon chip 21 is mounted as a semiconductor element on the wiring conductor. However, the semiconductor element is not necessarily limited to the silicon chip, and may be an equivalent silicon chip.

  In the above-described embodiment, the mounting structure in which the silicon chip 21 is mounted on the wiring board provided with the wiring layers 13 on both main surfaces of the insulating board has been described. However, the silicon chip is not provided on the wiring board in which the wiring layer 13 is provided. 21 may be implemented.

  In addition, the present invention can be implemented in various forms without departing from the spirit of the present invention.

It is sectional drawing of the principal part of the wiring board which concerns on the 1st Embodiment of this invention. It is sectional drawing (enlarged sectional drawing of FIG. 1) which expands and shows the relationship between the fiber bundle of one direction, and the fiber bundle of another direction. It is sectional drawing showing the groove part of a single fiber. It is sectional drawing of the principal part of the conventional wiring board. In the conventional wiring board, it is sectional drawing which expands and shows the relationship between the fiber bundle of one direction, and the fiber bundle of another direction. It is sectional drawing of the principal part of the wiring board which concerns on other embodiment of this invention. It is sectional drawing for demonstrating the fiber bundle of this invention. It is sectional drawing for demonstrating a proximity | contact single fiber. It is sectional drawing of the wiring board which concerns on the 2nd Embodiment of this invention. It is a perspective view of each sheet | seat which comprises the wiring board shown in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... 1st wiring board 2, 3 ... Wiring conductor 4 ... Resin woven cloth 4a ... Single fiber 5 ... Resin part 6 ...・ Groove

Claims (15)

A wiring board comprising: an insulating substrate; and a conductive portion formed on the insulating substrate and electrically connected to a chip component,
The insulating substrate includes a base material made of a fiber bundle composed of a single fiber or a plurality of single fibers, and a resin portion that covers the base material,
The single fiber is made of a resin material having a smaller linear expansion coefficient than the material of the chip part,
The wiring board, wherein the resin portion is made of a resin material having a larger coefficient of linear expansion than the material of the chip component.   The wiring board according to claim 1, wherein the chip component is a silicon chip.   The wiring board according to claim 1, wherein the base material is composed of a woven fabric formed by weaving the single fibers or the fiber bundles with each other.   The single fiber has a wave shape corresponding to the pitch at which the woven fabric is knitted, and the single fiber length corresponding to one cycle is greater than 1 time and greater than 1.20 with respect to the period of the wave shape. The wiring board according to claim 3, wherein the wiring board is twice or less.   The wiring board according to claim 3, wherein the fiber bundle has a horizontally long flat shape as viewed from a virtual plane perpendicular to the longitudinal direction.   The fiber bundle in one direction among the fiber bundles intersecting the two directions is such that the number of single fibers in a group adjacent to the fiber bundle in the other direction is substantially the same as or more than the number of other single fibers. The wiring board according to claim 3.   The wiring board according to claim 1, wherein the base material is configured such that the single fibers or the fiber bundles are arranged in a plurality of rows.   The wiring board according to claim 1, wherein the single fiber has a Young's modulus of 10 GPa or more, and the resin material has a Young's modulus of 0.05 GPa or more.   The linear expansion coefficient (25 ° C. or higher and 200 ° C. or lower) in the longitudinal direction of the single fiber is −10 ppm / ° C. or higher and 0 ppm / ° C. or lower, and the linear expansion coefficient (25 ° C. or higher and 200 ° C. or lower) of the resin material is 10 ppm / ° C. The wiring board according to claim 1, wherein the wiring board is 60 ppm / ° C. or less.   The wiring board according to claim 1, wherein the resin material is made of an epoxy resin containing a nonmetallic inorganic filler in an amount of 20 wt% to 80 wt%.   The wiring substrate according to claim 1, wherein a volume ratio of the base material to the substrate is 40% by volume or more and 70% by volume or less.   The wiring board according to claim 1, wherein a groove portion is formed along a longitudinal direction of the surface portion of the single fiber.   The wiring board according to any one of claims 1 to 12, wherein the single fiber is a resin fiber made of wholly aromatic polyamide, wholly aromatic polyester, or polyparaphenylene benzobisoxazole.   The wiring board according to any one of claims 1 to 13, wherein a wiring layer formed by alternately laminating insulating layers and circuit layers is formed on at least one main surface side of the insulating board. A wiring board according to any one of claims 1 to 14,
And a semiconductor element flip-chip mounted on the insulating substrate.

Images