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JP2008108953A - Semiconductor substrate backside foreign matter removal method - Google Patents

Semiconductor substrate backside foreign matter removal method Download PDF

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JP2008108953A
JP2008108953A JP2006291035A JP2006291035A JP2008108953A JP 2008108953 A JP2008108953 A JP 2008108953A JP 2006291035 A JP2006291035 A JP 2006291035A JP 2006291035 A JP2006291035 A JP 2006291035A JP 2008108953 A JP2008108953 A JP 2008108953A
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semiconductor substrate
foreign matter
back surface
pbn
fluorine
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Toshiki Ehata
敏樹 江畑
Yuji Morikawa
裕次 森川
Fan Wei
ウエイ・ファン
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Momentive Performance Materials Japan LLC
Momentive Performance Materials Inc
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Momentive Performance Materials Inc
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Abstract

【課題】熱分解窒化ホウ素(PBN)を最表面層とする試料台に半導体基板を保持して該半導体基板にプロセス処理を行ったときに、該半導体基板の裏面に付着したBN薄片を効果的に除去する。
【解決手段】PBNを最表面層22とする試料台21に半導体基板Wを保持して該半導体基板にプロセス処理を行ったときに該半導体基板の裏面に付着したPBN薄片を除去する方法であって、該プロセス処理後の半導体基板をリフトピン11などによりその裏面が実質的に開放された状態に保持し、該半導体基板の裏面に付着したPBN薄片をフッ素系ガスのプラズマ12中で除去する。PBNはフッ素系ガスに対する耐食性がきわめて小さいので、フッ素系ガスに晒されることにより短時間で効果的且つ選択的に除去される。
【選択図】図2
When a semiconductor substrate is held on a sample stage having pyrolytic boron nitride (PBN) as the outermost surface layer and the semiconductor substrate is processed, BN flakes adhering to the back surface of the semiconductor substrate are effectively removed. To remove.
A method of removing PBN flakes adhering to the back surface of a semiconductor substrate when a semiconductor substrate is held on a sample stage having PBN as the outermost surface layer and the semiconductor substrate is processed. Then, the semiconductor substrate after the process treatment is held in a state in which the back surface thereof is substantially opened by lift pins 11 or the like, and the PBN flakes adhering to the back surface of the semiconductor substrate are removed in the fluorine-based gas plasma 12. Since PBN has extremely low corrosion resistance against fluorine-based gas, it is effectively and selectively removed in a short time by being exposed to fluorine-based gas.
[Selection] Figure 2

Description

この発明は、ウエハなどの半導体基板の裏面に付着した異物を除去する方法に関し、より詳しくは、熱分解窒化ホウ素を最表面層とする試料台に半導体基板を保持して該半導体基板にプロセス処理を行ったときに、該半導体基板の裏面に付着した熱分解窒化ホウ素薄片を効果的に除去する方法に関する。   The present invention relates to a method for removing foreign substances adhering to the back surface of a semiconductor substrate such as a wafer. More specifically, the semiconductor substrate is held on a sample stage having pyrolytic boron nitride as the outermost surface layer, and the semiconductor substrate is processed. The present invention relates to a method for effectively removing pyrolytic boron nitride flakes adhering to the back surface of the semiconductor substrate.

半導体基板を保持するために用いる試料台としては、金属表面にAlなどのセラミック被膜を形成したものや、AlやAlNなどの焼結セラミックが広く使用されている。試料台には、加熱用ヒーター電極および/または静電吸着用電極が埋め込まれ、両者の電極を併用する場合は静電吸着ヒーターとしての機能を備えた試料台として用いられる。 As a sample stage used for holding a semiconductor substrate, a ceramic base such as Al 2 O 3 formed on a metal surface or a sintered ceramic such as Al 2 O 3 or AlN is widely used. The sample stage is embedded with a heater electrode for heating and / or an electrode for electrostatic adsorption, and when both electrodes are used together, it is used as a sample stage having a function as an electrostatic adsorption heater.

このような試料台に半導体基板を保持して、CVDやスパッタリングなどによる成膜処理、エッチング処理、加熱処理などの所定のプロセス処理を施す場合、材料台の最表面層が基板との接触によって削り取られてパーティクルを発生し、このパーティクルが基板裏面に付着するという問題がある。   When holding a semiconductor substrate on such a sample stage and performing a predetermined process such as a film forming process such as CVD or sputtering, an etching process, or a heating process, the outermost surface layer of the material stage is scraped by contact with the substrate. There is a problem that particles are generated and the particles adhere to the back surface of the substrate.

この問題を解決するため、下記特許文献1において、「プラズマ装置内でウエハをデバイス形成面とその反対面との双方がプラズマと接触可能となるごとく該反対面側にて支持した状態で、前記デバイス形成面を前記プラズマ中に生成する堆積性物質を堆積させてなる堆積物層で保護しながら、前記反対面上に付着した異物を該プラズマ中のラジカルにより除去することを特徴とするウエハ異物除去方法」(請求項1より引用)が提案されている。
特開平6−120175号公報
In order to solve this problem, in Patent Document 1 below, “in the plasma apparatus, the wafer is supported on the opposite surface side so that both the device forming surface and the opposite surface can come into contact with the plasma. A foreign substance on a wafer, wherein a foreign substance adhering to the opposite surface is removed by radicals in the plasma while protecting a device formation surface with a deposit layer formed by depositing a depositing substance generated in the plasma. "Removal method" (cited from claim 1) is proposed.
JP-A-6-120175

プロセス処理において、処理中の基板温度は重要な条件として処理の結果を左右するため、基板は試料台の表面に密着して保持されることが要求される。しかしながら、前述の試料台に用いられるAlやAlNなどのセラミック材料は脆性が大きく、半導体基板を点接触で保持することになる。プロセス処理は減圧下で行われるため、これらセラミック系の試料台上に点接触で保持される半導体基板には試料台からの熱移動がほとんどなく、両者の間にHeなどの気体を充填してガスによる伝熱で半導体基板を加熱することが一般的であった。 In process processing, the substrate temperature during processing affects the processing result as an important condition, and therefore the substrate is required to be held in close contact with the surface of the sample stage. However, ceramic materials such as Al 2 O 3 and AlN used for the sample stage described above are highly brittle and hold the semiconductor substrate in point contact. Since the process is performed under reduced pressure, the semiconductor substrate held in point contact on these ceramic sample stands has almost no heat transfer from the sample stand, and a gas such as He is filled between them. It has been common to heat a semiconductor substrate by heat transfer with a gas.

一方、非脆性である熱分解窒化ホウ素(PBN)を最表面層とする試料台は、基板との密着性に優れ、したがって試料台から基板への熱移動が大きく、従来必要としていたガス充填が不要となり、温度制御の点で大きな利点を有している。このため、従来のAl系セラミック材料に代わって、PBN最表面層を有する試料台を使用して半導体基板を面接触で支持しながらプロセス処理を行うことが有望視されるに至り、実際の使用においても成果を発揮している。   On the other hand, the sample stage having the non-brittle pyrolytic boron nitride (PBN) as the outermost surface layer has excellent adhesion to the substrate, and therefore heat transfer from the sample stage to the substrate is large, and the gas filling that has been required in the past can be achieved. This is unnecessary and has a great advantage in terms of temperature control. For this reason, instead of the conventional Al-based ceramic material, it has become promising to perform a process while supporting a semiconductor substrate in surface contact using a sample stage having a PBN outermost surface layer. Has also been successful.

ところが、PBN最表面層が基板に対して優れた密着性を有することは、反面、基板の裏面にPBNの薄片が付着しやすいという問題を生じさせる原因となっている。このPBN薄片は、従来のAl系セラミック材料が基板と接触して削り取られるパーティクル状の異物とは異なり、薄く且つ基板裏面の比較的大きな面積を覆うように被着することとなるため、Al系セラミック材料のパーティクルを基板裏面から除去することを目的とした従来の異物除去方法では完全に除去することが困難である。   However, the fact that the PBN outermost surface layer has excellent adhesiveness to the substrate, on the other hand, causes a problem that PBN flakes are likely to adhere to the back surface of the substrate. The PBN flakes are thin and are deposited so as to cover a relatively large area on the backside of the substrate, unlike the conventional foreign particles that are scraped off when the Al-based ceramic material comes into contact with the substrate. It is difficult to completely remove the particles of the ceramic material by the conventional foreign matter removing method aiming at removing particles from the back surface of the substrate.

年々厳しくなる半導体デバイスの微細化に伴う技術的要求を考慮するとき、基板裏面に付着したPBN薄片がプロセス処理に与える影響を無視することができず、このPBN薄片を基板裏面から効果的に除去することが不可欠の課題である。   When considering the technical demands associated with the miniaturization of semiconductor devices, which are becoming stricter year by year, the effect of PBN flakes attached to the backside of the substrate on the process cannot be ignored, and this PBN flakes are effectively removed from the backside of the substrate It is an essential task.

上記課題を解決するため、本発明は、PBNを最表面層とする試料台に半導体基板を保持して該半導体基板にプロセス処理を行ったときに、該半導体基板の裏面に付着したBN薄片を効果的に除去する方法を提供する。   In order to solve the above-mentioned problems, the present invention provides a BN flake adhering to the back surface of a semiconductor substrate when a semiconductor substrate is held on a sample stage having PBN as the outermost surface layer and the semiconductor substrate is processed. Provide a method for effective removal.

より具体的には、フッ素系ガスに対してきわめて腐食性が大きいというPBNの特性を利用して、基板裏面に付着したPBN薄片をフッ素系ガスによって除去しようとするものである。   More specifically, the PBN flakes adhering to the back surface of the substrate are removed by the fluorine-based gas by utilizing the characteristic of PBN that is extremely corrosive to the fluorine-based gas.

すなわち、請求項1に係る本発明は、PBNを最表面層とする試料台に半導体基板を保持して該半導体基板にプロセス処理を行ったときに該半導体基板の裏面に付着したPBN薄片を除去する方法であって、該プロセス処理後の半導体基板をその裏面が実質的に開放された状態に保持し、該半導体基板の裏面に付着したPBN薄片をフッ素系ガスにより除去することを特徴とする、半導体基板裏面異物除去方法である。   That is, the present invention according to claim 1 removes PBN flakes adhering to the back surface of the semiconductor substrate when the semiconductor substrate is held on the sample stage having PBN as the outermost surface layer and the semiconductor substrate is processed. The semiconductor substrate after the process is held in a state where the back surface thereof is substantially open, and the PBN flakes adhering to the back surface of the semiconductor substrate are removed with a fluorine-based gas. This is a method for removing foreign matter on the back surface of a semiconductor substrate.

請求項2に係る本発明は、請求項1記載の異物除去方法において、半導体基板の裏面に付着したPBN薄片をフッ素系ガスのプラズマ雰囲気中で除去することを特徴とする。   According to a second aspect of the present invention, in the foreign matter removing method according to the first aspect, the PBN flakes adhering to the back surface of the semiconductor substrate are removed in a plasma atmosphere of a fluorine-based gas.

請求項3に係る本発明は、請求項1または2記載の異物除去方法において、フッ素系ガスとしてNFガスを用いることを特徴とする。 The present invention according to claim 3 is characterized in that in the foreign matter removing method according to claim 1 or 2, NF 3 gas is used as the fluorine-based gas.

請求項4に係る本発明は、請求項3記載の異物除去方法において、NFガスが高周波放電で生成されたものであることを特徴とする。 According to a fourth aspect of the present invention, in the foreign matter removing method according to the third aspect , the NF 3 gas is generated by high-frequency discharge.

請求項5に係る本発明は、請求項1ないし4のいずれか記載の異物除去方法において、半導体基板に電位が印加されない状態でフッ素系ガスにより処理することを特徴とする。   According to a fifth aspect of the present invention, in the foreign matter removing method according to any one of the first to fourth aspects, the treatment is performed with a fluorine-based gas without applying a potential to the semiconductor substrate.

請求項6に係る本発明は、請求項1ないし5のいずれか記載の異物除去方法において、前記プロセス処理のための反応室とは別の反応室で異物除去処理を行うことを特徴とする。   According to a sixth aspect of the present invention, in the foreign matter removing method according to any one of the first to fifth aspects, the foreign matter removing process is performed in a reaction chamber different from the reaction chamber for the process treatment.

請求項7に係る本発明は、請求項6に記載の異物除去方法において、前記プロセス処理のための反応室に隣接した反応室で異物除去処理を行うことを特徴とする。   According to a seventh aspect of the present invention, in the foreign matter removing method according to the sixth aspect, the foreign matter removing process is performed in a reaction chamber adjacent to the reaction chamber for the process treatment.

請求項8に係る本発明は、請求項1ないし7のいずれか記載の異物除去方法において、前記プロセス処理後の半導体基板をその裏面の数ヶ所においてリフトピンで支持することを特徴とする。   According to an eighth aspect of the present invention, in the foreign matter removing method according to any one of the first to seventh aspects, the semiconductor substrate after the process is supported by lift pins at several places on the back surface thereof.

請求項9に係る本発明は、請求項1ないし7のいずれか記載の異物除去方法において、前記プロセス処理後の半導体基板をその外周部で保持して裏面全面をフッ素系ガスにより処理可能としたことを特徴とする。   According to a ninth aspect of the present invention, in the foreign matter removing method according to any one of the first to seventh aspects, the semiconductor substrate after the process treatment is held at an outer peripheral portion thereof, and the entire back surface can be treated with a fluorine-based gas. It is characterized by that.

本発明によれば、PBNを最表面層とする試料台に半導体基板を保持して該半導体基板にプロセス処理を行ったときに該半導体基板の裏面にPBN薄片が異物として付着しても、これをフッ素系ガスで処理することにより、効果的に除去することができる。PBNはフッ素系ガスに対してきわめて腐食性が大きいという特性を持つので、この特性を利用して、異物であるPBN薄片を選択的に除去することができる。   According to the present invention, when a semiconductor substrate is held on a sample stage having PBN as the outermost surface layer and the semiconductor substrate is processed, even if PBN flakes adhere to the back surface of the semiconductor substrate, Can be effectively removed by treating with a fluorine-based gas. Since PBN has a characteristic that it is extremely corrosive to fluorine-based gas, it is possible to selectively remove PBN flakes that are foreign substances by using this characteristic.

PBNがフッ素ガスに対してきわめて腐食しやすい特性を持つことを実証するため、次の条件でエッチングテストを行った。   In order to demonstrate that PBN has a characteristic that it is extremely susceptible to corrosion by fluorine gas, an etching test was conducted under the following conditions.

平行平板型ドライエッチング装置において、大きさ概略50mm角の各種材料(Si、石英、PBN、AlN)からなる試料片を水冷された石英製の試料台に置き、NFガスおよびArガスをそれぞれ毎分16ccおよび毎分34ccの流量で混合して反応室に導入した。反応室内の圧力を100mTorrに保持し、試料台に13.56MHzの高周波電力を400W印加した。高周波電力の印加によって生成されたプラズマにより試料片がFイオンやFラジカルでエッチングされる。1時間以上連続してプラズマ中でエッチングし、試料重量のエッチング前後の変化量を試料の裏面を除く表面積で規格化することによりエッチング速度を求めた。図1はその結果をグラフに示したものである。 In a parallel plate type dry etching apparatus, sample pieces made of various materials (Si, quartz, PBN, AlN) having a size of approximately 50 mm square are placed on a water-cooled quartz sample stage, and NF 3 gas and Ar gas are respectively supplied. Mixing at a flow rate of 16 cc per minute and 34 cc per minute was introduced into the reaction chamber. The pressure in the reaction chamber was kept at 100 mTorr, and 400 W of high frequency power of 13.56 MHz was applied to the sample stage. The sample piece is etched with F ions or F radicals by the plasma generated by the application of the high frequency power. Etching rate was determined by etching in plasma continuously for 1 hour or longer and normalizing the amount of change in the sample weight before and after etching with the surface area excluding the back surface of the sample. FIG. 1 is a graph showing the results.

図1に示されるように、PBNは毎分1ミクロン以上でエッチングされ、Siより20倍以上、石英(SiO)より40倍以上、AlNに至っては300倍以上も大きなエッチング速度を示した。このことは、半導体基板の下地がSiやSiOであっても、下地へのエッチングによる影響を実質的に抑えつつPBNのみを選択的に除去できることを示している。 As shown in FIG. 1, PBN was etched at 1 micron or more per minute, and showed an etching rate 20 times or more higher than Si, 40 times higher than quartz (SiO 2 ), and 300 times higher than that of AlN. This indicates that even if the base of the semiconductor substrate is Si or SiO 2 , only PBN can be selectively removed while substantially suppressing the influence of etching on the base.

この試験結果を基にして、PBN膜を最表面層とする静電吸着ヒーターを400℃に昇温保持し、直流電圧1kVでウエハを静電吸着ヒーターに静電吸着させ、2分間保持後、リフトピンでウエハを静電吸着ヒーターから離して反応室から搬出した。このウエハについて、裏面に付着した異物(PBN薄片)をパーティクルカウンターで測定した後、NFプラズマで処理を行い、該NFプラズマ処理後になおウエハ裏面に付着している異物を再度パーティクルカウンターで測定して、異物の除去効果を評価した。NFプラズマは、ウエハを水冷試料台に搭載した真空チェンバー中にNFガスを50sccm導入し、圧力を0.5Paに維持して、13.56MHzの高周波電源から500Wの電力を投入して生成した。プラズマによる処理時間は5分とした。表1にその結果を示す。 Based on this test result, the electrostatic adsorption heater having the PBN film as the outermost surface layer is heated and held at 400 ° C., the wafer is electrostatically adsorbed to the electrostatic adsorption heater at a DC voltage of 1 kV, and held for 2 minutes. The wafer was removed from the electrostatic adsorption heater with a lift pin and carried out of the reaction chamber. This wafer, after foreign matters adhered to the back surface of the (PBN flakes) measured by a particle counter, NF 3 by plasma processing, the NF 3 plasma treatment after Incidentally measured again particle counter the foreign matter adhering to the wafer back surface Thus, the effect of removing foreign matters was evaluated. NF 3 plasma is generated by introducing 50 sccm of NF 3 gas into a vacuum chamber in which a wafer is mounted on a water-cooled sample stage, maintaining the pressure at 0.5 Pa, and supplying 500 W of power from a 13.56 MHz high frequency power source. did. The plasma treatment time was 5 minutes. Table 1 shows the results.

Figure 2008108953
Figure 2008108953

表1に示されるように、NFプラズマ処理を行うことにより、ウエハ裏面に付着した異物が効果的に除去され、特に大きな異物が効果的に除去されることが確認された。 As shown in Table 1, it was confirmed that, by performing the NF 3 plasma treatment, foreign matters attached to the back surface of the wafer were effectively removed, and particularly large foreign matters were effectively removed.

上述の実施例においては、ウエハ裏面の異物除去のためのプラズマ処理にNFを使用したが、これに限らず、CF、SF、ClF(3フッ化塩素)などプラズマ中でフッ素原子を電離するフッ素系ガスであれば本発明において使用可能である。また、プラズマ生成はkHzからGHzまでのいかなる周波数の高周波電源であっても、フッ素系ガスのプラズマを生成できるものであれば、上述の実施例における13.56MHzに限るものではない。 In the above embodiment, although using NF 3 plasma treatment for removing foreign substances wafer backside, not limited thereto, CF 4, SF 6, ClF 3 (3 chlorine fluoride) such as fluorine atom in the plasma Any fluorine-based gas that ionizes can be used in the present invention. The plasma generation is not limited to 13.56 MHz in the above-described embodiment as long as it can generate a fluorine-based gas plasma with any high-frequency power source of kHz to GHz.

図2は、この異物除去プラズマ処理のための装置構成の一例および使用法を示す。この装置10は、PBNを最表面層22とする試料台(静電吸着ヒーター)21にウエハWを保持してウエハWに所定のプロセス処理を行うプロセス処理装置20に隣接して設けられ、プロセス処理装置20とは別の反応室を有する。   FIG. 2 shows an example of an apparatus configuration for this foreign substance removal plasma processing and its usage. The apparatus 10 is provided adjacent to a process processing apparatus 20 that holds a wafer W on a sample table (electrostatic adsorption heater) 21 having PBN as the outermost surface layer 22 and performs a predetermined process process on the wafer W. A reaction chamber separate from the processing apparatus 20 is provided.

プロセス処理装置20において、複数本のリフトピン23が試料台1を貫通して昇降可能に設けられ、ウエハWに対してプロセス処理を行うときはリフトピン23を下降位置に待避させた状態にして、ウエハWを試料台21に静電吸着保持する。所定時間のプロセス処理終了後、リフトピン23を上昇させてウエハWを試料台21から離し、搬送アームなどのウエハ搬送手段24によりプロセス処理装置20から搬出し、ゲートバルブ25から、隣接する異物除去プラズマ処理装置10内に移送して、複数本のリフトピン11上に載置する。この状態でフッ素系プラズマ12を発生させて、ウエハWの裏面に付着した異物(PBN薄片)を除去する。異物除去処理終了後、搬送アーム24と略同様または任意構成のウエハ搬出手段13でウエハWを装置10外へ搬出する。フッ素系プラズマ12の発生には、マイクロ波でNFガスを励起してフッ素ラジカルを導入する、いわゆるリモートプラズマを採用することができる。 In the process processing apparatus 20, a plurality of lift pins 23 are provided so as to be able to move up and down through the sample stage 1, and when the wafer W is processed, the lift pins 23 are retracted to the lowered position, W is electrostatically held on the sample stage 21. After completion of the predetermined time of process processing, the lift pins 23 are raised to separate the wafer W from the sample stage 21 and are unloaded from the process processing apparatus 20 by the wafer transfer means 24 such as a transfer arm, and from the gate valve 25 to the adjacent foreign substance removal plasma. It is transferred into the processing apparatus 10 and placed on the plurality of lift pins 11. In this state, fluorine-based plasma 12 is generated to remove foreign matters (PBN flakes) adhering to the back surface of the wafer W. After the foreign substance removal processing is completed, the wafer W is unloaded from the apparatus 10 by the wafer unloading means 13 which is substantially the same as the transfer arm 24 or an arbitrary configuration. For generation of the fluorine-based plasma 12, so-called remote plasma in which NF 3 gas is excited by microwaves to introduce fluorine radicals can be employed.

異物除去プラズマ処理装置10はプロセス処理装置10と離れた場所に設置しても良いが、ウエハWの搬送効率を良好にする上で図2に示すように隣接設置することが好ましく、特に、一般にプロセス処理装置10にはゲートバルブ24を介して搬送室が隣接されているので、この搬送室を改造して上記異物除去プラズマ処理装置10とすることが実際上有利である。   The foreign substance removal plasma processing apparatus 10 may be installed at a location distant from the process processing apparatus 10, but it is preferable to install adjacently as shown in FIG. 2 in order to improve the transfer efficiency of the wafer W. Since the transfer chamber is adjacent to the process processing apparatus 10 via the gate valve 24, it is practically advantageous to modify the transfer chamber to form the foreign substance removal plasma processing apparatus 10.

図2の実施形態では、異物除去プラズマ処理装置10においてリフトピン11でウエハWを支持するようにしているが、これに限らず、たとえばウエハWをその外周部で支持するような構造のウエハ支持手段を設けても良い。また、ウエハ搬送手段24を異物除去プラズマ処理装置10におけるウエハ支持手段として兼用させても良い。ウエハ搬送手段23としては、ウエハWを裏面から数点で支持する構造や、ウエハWをその外周部で支持する構造、あるいはこれらを組み合わせた構造が知られており、本発明ではこれらのいずれの構造のものも採用可能であり、異物除去プラズマ処理装置10におけるウエハ支持手段として兼用させることができる。   In the embodiment shown in FIG. 2, the wafer W is supported by the lift pins 11 in the foreign substance removal plasma processing apparatus 10. However, the present invention is not limited to this. For example, the wafer support means is configured to support the wafer W at its outer periphery. May be provided. Further, the wafer transfer means 24 may be used also as a wafer support means in the foreign matter removal plasma processing apparatus 10. As the wafer transfer means 23, a structure that supports the wafer W at several points from the back surface, a structure that supports the wafer W at its outer peripheral portion, or a structure that combines these structures is known. A structure having a structure can also be employed, and can also be used as a wafer support means in the foreign matter removal plasma processing apparatus 10.

いずれにしても、本発明の目的がウエハWの裏面に付着した異物除去にあることに鑑みれば、異物除去プラズマ処理装置10におけるウエハ支持手段がウエハWの裏面と接触することを排除して、ウエハ支持手段に支持されたウエハWの裏面全面がプラズマ12に晒されることが好ましい。したがって、ウエハWをその外周部のみで支持する構造のウエハ支持手段を採用することが好ましい。   In any case, considering that the object of the present invention is to remove foreign matter attached to the back surface of the wafer W, the wafer support means in the foreign matter removal plasma processing apparatus 10 is excluded from coming into contact with the back surface of the wafer W. It is preferable that the entire back surface of the wafer W supported by the wafer support means is exposed to the plasma 12. Therefore, it is preferable to employ a wafer support means having a structure in which the wafer W is supported only by its outer peripheral portion.

また、リフトピン11その他のウエハ支持手段は、異物除去プラズマ処理装置10において、ウエハWと共にプラズマ12に晒されることになるので、フッ素系ラジカルに耐性の強い材料、たとえばAl、AlNなどのセラミックや、アルミニウム、ステンレスなどの金属材料で形成することが好ましい。 Further, since the lift pins 11 and other wafer support means are exposed to the plasma 12 together with the wafer W in the foreign matter removal plasma processing apparatus 10, a material that is resistant to fluorine radicals, such as Al 2 O 3 , AlN, etc. It is preferable to form with metal materials, such as ceramic, aluminum, and stainless steel.

さらに、ウエハなどの基板裏面の異物除去処理をプラズマ中で行う場合、基板に何らかの電位たとえばバイアス電位が印加されていると、イオン衝撃などによって基板内の素子にダメージを誘起することが考えられるので、基板はプラズマ中に絶縁状態で保持または設置されていることが望ましい。このため、図2の異物除去プラマ処理装置10においてウエハ支持手段としてウエハWの裏面に接するリフトピン11は絶縁材料で形成されていることが好ましい。   Furthermore, when performing foreign matter removal processing on the backside of a substrate such as a wafer in plasma, if any potential, such as a bias potential, is applied to the substrate, damage to the elements in the substrate may be caused by ion bombardment or the like. The substrate is preferably held or placed in an insulating state in the plasma. For this reason, it is preferable that the lift pins 11 in contact with the back surface of the wafer W as the wafer support means in the foreign matter removal plasma processing apparatus 10 of FIG.

なお、異物除去プラズマ処理装置10においてウエハWをプラズマ12で処理すると、ウエハWの裏面のみならず表面もフッ素ラジカルの影響を受けることになるが、ウエハWなどの半導体基板の表面はフッ素ラジカルに対してPBNとの選択比が十分に高い耐食性材料、たとえばSi結晶やSiO結晶またはレジストなどに覆われていることが通常であるので、一般的には特に大きな問題を生じない。しかしながら、ウエハWの表面に高密度なデバイスが形成されているような場合には、図3に示すように、ウエハW表面を覆う保護蓋14を設けることで、ウエハW表面に対するフッ素ラジカルの影響を排除することが好ましい。この場合、ウエハW表面と保護蓋14との間の隙間は1mm以下とすることが好ましい。 When the wafer W is processed with the plasma 12 in the foreign matter removal plasma processing apparatus 10, not only the back surface but also the surface of the wafer W is affected by fluorine radicals, but the surface of the semiconductor substrate such as the wafer W is affected by fluorine radicals. On the other hand, since it is usually covered with a corrosion-resistant material having a sufficiently high selection ratio with PBN, such as Si crystal, SiO 2 crystal, or resist, generally no particular problem arises. However, in the case where a high-density device is formed on the surface of the wafer W, as shown in FIG. 3, by providing a protective lid 14 that covers the surface of the wafer W, the influence of fluorine radicals on the surface of the wafer W is achieved. Is preferably excluded. In this case, the gap between the wafer W surface and the protective lid 14 is preferably 1 mm or less.

NFプラズマによるPBNのエッチング速度を他の材料と比較して示すグラフである。NF 3 is a graph showing the etching rate of the PBN according to the plasma compared with other materials. 異物除去プラズマ処理のための装置構成の一例および使用法を示す概略図である。It is the schematic which shows an example of the apparatus structure for a foreign material removal plasma processing, and its usage. ウエハ表面を覆う保護蓋を設けた装置構成例を示す概略図である。It is the schematic which shows the apparatus structural example which provided the protective cover which covers a wafer surface.

符号の説明Explanation of symbols

10 異物除去プラズマ処理装置
11 リフトピン(ウエハ支持手段)
12 プラズマ
13 ウエハ搬出手段
14 保護蓋
20 プロセス処理装置
21 試料台(静電吸着ヒーター)
22 PBN最表面層
23 リフトピン
24 ウエハ搬送手段
25 ゲートバルブ
W ウエハ
10 Foreign matter removal plasma processing apparatus 11 Lift pin (wafer support means)
12 Plasma 13 Wafer carrying means 14 Protective cover 20 Process processing device 21 Sample stage (electrostatic adsorption heater)
22 PBN outermost surface layer 23 Lift pin 24 Wafer transfer means 25 Gate valve W Wafer

Claims (9)

PBNを最表面層とする試料台に半導体基板を保持して該半導体基板にプロセス処理を行ったときに該半導体基板の裏面に付着したPBN薄片を除去する方法であって、該プロセス処理後の半導体基板をその裏面が実質的に開放された状態に保持し、該半導体基板の裏面に付着したPBN薄片をフッ素系ガスにより除去することを特徴とする、半導体基板裏面異物除去方法。 A method of removing PBN flakes adhering to the back surface of a semiconductor substrate when the semiconductor substrate is held on a sample stage having PBN as the outermost surface layer and the semiconductor substrate is processed. A method of removing foreign matter from a semiconductor substrate back surface, wherein the back surface of the semiconductor substrate is held substantially open, and PBN flakes adhering to the back surface of the semiconductor substrate are removed with a fluorine-based gas. 半導体基板の裏面に付着したPBN薄片をフッ素系ガスのプラズマ雰囲気中で除去することを特徴とする、請求項1記載の異物除去方法。 2. The foreign matter removing method according to claim 1, wherein the PBN flakes adhering to the back surface of the semiconductor substrate are removed in a plasma atmosphere of a fluorine-based gas. フッ素系ガスとしてNFガスを用いることを特徴とする、請求項1または2記載の異物除去方法。 The foreign matter removing method according to claim 1 or 2, wherein NF 3 gas is used as the fluorine-based gas. NFガスが高周波放電で生成されたものであることを特徴とする、請求項3記載の異物除去方法。 4. The foreign matter removing method according to claim 3, wherein the NF 3 gas is generated by high frequency discharge. 半導体基板に電位が印加されない状態でフッ素系ガスにより処理することを特徴とする、請求項1ないし4のいずれか記載の異物除去方法。 5. The foreign matter removing method according to claim 1, wherein the treatment is performed with a fluorine-based gas in a state where no potential is applied to the semiconductor substrate. 前記プロセス処理のための反応室とは別の反応室で異物除去処理を行うことを特徴とする、請求項1ないし5のいずれか記載の異物除去方法。 6. The foreign matter removing method according to claim 1, wherein the foreign matter removing process is performed in a reaction chamber different from the reaction chamber for the process treatment. 前記プロセス処理のための反応室に隣接した反応室で異物除去処理を行うことを特徴とする、請求項6に記載の異物除去方法。 The foreign matter removing method according to claim 6, wherein the foreign matter removing process is performed in a reaction chamber adjacent to the reaction chamber for the process treatment. 前記プロセス処理後の半導体基板をその裏面の数ヶ所においてリフトピンで支持することを特徴とする、請求項1ないし7のいずれか記載の異物除去方法。 8. The foreign matter removing method according to claim 1, wherein the processed semiconductor substrate is supported by lift pins at several places on the back surface thereof. 前記プロセス処理後の半導体基板をその外周部で保持して裏面全面をフッ素系ガスにより処理可能としたことを特徴とする、請求項1ないし7のいずれか記載の異物除去方法。 8. The foreign matter removing method according to claim 1, wherein the semiconductor substrate after the process treatment is held at an outer peripheral portion thereof, and the entire back surface can be treated with a fluorine-based gas.
JP2006291035A 2006-10-26 2006-10-26 Semiconductor substrate backside foreign matter removal method Withdrawn JP2008108953A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2022061860A (en) * 2020-10-07 2022-04-19 東京エレクトロン株式会社 Substrate processing method and substrate processing apparatus

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2022061860A (en) * 2020-10-07 2022-04-19 東京エレクトロン株式会社 Substrate processing method and substrate processing apparatus
JP7450512B2 (en) 2020-10-07 2024-03-15 東京エレクトロン株式会社 Substrate processing method and substrate processing apparatus

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