JP2008103629A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device equipped with a high precise resistive element by activating a silicide reaction of a barrier metal and silicon in a contact structure on which metal silicide is not formed connected to a resistor, and a method of manufacturing the semiconductor device. <P>SOLUTION: The semiconductor device is equipped with: a resistor 102 composed of a silicon film formed on a semiconductor substrate 100 through an insulating film 101; an interlayer insulating film 104 formed on the resistor 102; a contact hole formed at the interlayer insulating film 104; a wiring portion 105 which is formed in the contact hole and connected to the resistor 102; and metal wiring 106 which is formed on the interlayer insulating film 104 and connected to the wiring portion 105. The semiconductor device is also characterized in that the resistor 102 contains an impurity element of a first conductivity-type in a film and an element with heavier atomic weight than that of the silicon at the front surface side of the resistor 102 is doped. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device including a resistance element that requires high accuracy and a method for manufacturing the same.

  One of resistive elements, which is one of the elements constituting an analog circuit mounted on a semiconductor integrated circuit, is a silicon resistor using a silicon film. In recent years, with the miniaturization, metal silicide, which is an alloy of transition metal and silicon, is used for the MOS gate portion and the contact portion, and the structure shown in Patent Document 1 is also used for the silicon resistance element.

  That is, a field oxide film formed of a silicon oxide film is formed on a semiconductor substrate composed of a silicon substrate. A resistor made of polysilicon is formed on the field oxide film. An interlayer insulating film is formed on the resistor, and contact holes are formed in the interlayer insulating film at portions located at the left and right ends of the resistor. A contact plug is formed in the contact hole, and the resistor is connected to the metal wiring via the contact plug.

The contact resistance between the contact plug and the resistor, that is, the contact resistance value is preferably small. As a method for reducing the contact resistance value, metal silicidation, which is an alloy of transition metal and silicon, is generally used. Metal silicide is a technology that lowers resistance by solid-phase reaction between silicon and a high-melting-point transition metal such as titanium, cobalt, or nickel to form titanium silicide, cobalt silicide, or nickel silicide with low resistivity. .
Japanese Patent Laying-Open No. 2004-79893 (FIG. 1)

  According to the configuration of Patent Document 1, only the contact region and the spare region of the resistor are made into a metal silicide, thereby suppressing the variation of the contact resistance due to the film quality and film thickness variation of the metal silicide layer as much as possible. The variation in resistance value can be suppressed.

  The inventors of the present invention have formed a resistance element by metalizing only the contact region and the spare region of the resistor, and evaluating the electric characteristics of the resistance element. It was found that the variation in resistance values of the resistance elements (hereinafter referred to as relative accuracy) deteriorated. Further, it was found that the variation in resistance value of the resistance element within the semiconductor substrate surface (hereinafter referred to as absolute accuracy) does not depend on the presence or absence of metal silicide in the contact region and the spare region.

  As a result of investigating the cause of the relative accuracy deterioration, the contact resistance is reduced by forming the contact region and the spare region into metal silicide, but the metal silicide layer of about 1 to 5Ω / □ and the resistance of about 200 to 600Ω / □ are obtained. It can be inferred that the contact resistance at the body interface is increasing. As a result of the calculation of the contact resistance, it can be seen that the contact resistance is 20 Ω / □ or less, and for a resistance element of several hundred Ω / □, the ratio is several percent. It is considered that the resistance value fluctuated and the relative accuracy was deteriorated.

  In addition, a barrier metal is indispensable for forming a metal material that is a contact plug material, such as W (tungsten). Generally used barrier metals are metal alloys of transition metals such as TiN and TaN. Since these barrier metals have low resistivity and low reactivity with silicon, they are used at the interface between metal wiring and silicon. When W is used as a contact plug material, TiN is often used as a barrier metal. However, TiN has a high contact resistance with silicon, and after a TiN / Ti laminated film is grown, Ti and silicon are silicided by heat treatment. The resistance value is reduced. Therefore, even in a contact structure in which no metal silicide is formed, a silicide reaction occurs between the barrier metal of the contact plug and silicon.

  As described above, in the conventional technique, in the contact connected to the resistor, only the contact region is converted into a metal silicide, thereby reducing the contact resistance and suppressing the variation in the contact resistance as much as possible. However, a high-accuracy resistance element has a problem that fluctuations in relative accuracy caused by fluctuations in resistance value due to fluctuations in the film quality and film thickness of the metal silicide layer cannot be suppressed.

  In view of the above, the present invention provides a semiconductor device including a highly accurate resistance element by activating a silicide reaction between a barrier metal and silicon in a metal silicide non-contact contact structure connected to a resistor, and a method for manufacturing the same The purpose is to provide.

  A semiconductor device according to the present invention is a semiconductor device having a resistor, wherein the resistor is a silicon film formed on a semiconductor substrate via an insulating film, the interlayer insulating film formed on the resistor, A contact hole formed in the interlayer insulating film, a wiring portion formed in the contact hole and connected to the resistor, and a metal wiring formed on the interlayer insulating film and connected to the wiring portion; The resistor includes an impurity element of a first conductivity type in the film, and an element having an atomic weight larger than that of silicon is doped on a surface layer side.

  In the above semiconductor device, the element having an atomic weight larger than that of silicon is doped from the surface layer of the resistor to a depth that is 1/20 or more and 1/5 or less of the film thickness of the resistor. preferable.

  In the above semiconductor device, the dose amount of the element having an atomic weight larger than that of silicon is preferably 1/20 or more and 1/10 or less of the dose amount of the impurity element of the first conductivity type.

  In the above semiconductor device, the silicon film is preferably a polysilicon film or an amorphous silicon film.

  According to the semiconductor device of the present invention, the resistor includes the first conductivity type impurity and suppresses the contact resistance variation due to the film quality and film thickness variation of the silicide layer due to the metal silicidation of the contact region, and on the surface layer side. An element having an atomic weight larger than that of silicon is implanted, and a metal silicide reaction between Ti and silicon of the laminated barrier metal is activated by forming the contact to be connected without metal silicide, thereby providing a highly accurate resistance element. A semiconductor device can be provided.

  In the semiconductor device described above, the element having an atomic weight larger than that of silicon is preferably an element in the same group as the impurity element of the first conductivity type. As a result, an element having an atomic weight larger than that of silicon does not cancel out the impurity element of the first conductivity type, and the substantial impurity amount increases to reduce the resistance value of the silicon surface layer portion. Therefore, it is possible to suppress the variation of the contact resistance value, and it is possible to form a highly accurate resistance element.

  In the above semiconductor device, the element having an atomic weight larger than that of silicon is preferably an element belonging to the same family as silicon or an electrically inactive element. As a result, an element having an atomic weight larger than that of silicon does not cancel out the impurity element of the first conductivity type, and the substantial impurity amount of the silicon surface layer portion does not vary, so the resistance value of the resistor does not vary. Therefore, it becomes possible to form a more accurate resistance element.

  In the above semiconductor device, it is preferable that an element having an atomic weight larger than that of silicon is doped in a contact region of the resistor. Thereby, an element having an atomic weight larger than that of the silicon is selectively injected only into the contact region of the resistor, so that the resistance value of the main body of the resistor does not fluctuate, thereby forming a more accurate resistance element. It becomes possible.

  According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device having a resistor, the step of forming a resistor made of a silicon film over an insulating film on a semiconductor substrate, and the resistor by ion implantation. Doping a first conductivity type impurity element, activating the first conductivity type impurity element in the resistor by heat treatment, forming an interlayer insulating film on the resistor, Forming a contact hole in the interlayer insulating film; forming a wiring portion connected to the resistor in the contact hole; and forming a metal wiring connecting to the wiring portion on the interlayer insulating film. And before forming the interlayer insulating film after the heat treatment, doping the surface layer side of the resistor with an element having an atomic weight larger than that of silicon by ion implantation And butterflies.

  In the method for manufacturing a semiconductor device, it is preferable that an insulating film is formed on the surface of the resistor before the heat treatment.

  In the semiconductor device manufacturing method, ions are implanted with an acceleration energy such that an implantation depth of an element having an atomic weight larger than that of silicon is 1/20 or more and 1/5 or less of the film thickness of the resistor. It is preferable.

  In the method for manufacturing a semiconductor device, the dose of an element having an atomic weight larger than that of silicon may be ion-implanted so that the dose is 1/20 or more and 1/10 or less of the dose of the first conductivity type impurity element. preferable.

  In the semiconductor device manufacturing method, the silicon film is preferably a polysilicon film or an amorphous silicon film.

  According to the method for manufacturing a semiconductor device of the present invention, the resistor includes a first conductivity type impurity in order to suppress contact resistance fluctuation due to film quality and film thickness fluctuation of the silicide layer due to metal silicidation in the contact region, and An element having an atomic weight larger than that of silicon is implanted on the surface layer side, and the metal silicide reaction between Ti and silicon of the laminated barrier metal is activated by making the contact to be connected not to form a metal silicide. A method for manufacturing a semiconductor device including an element can be provided.

  In the method for manufacturing a semiconductor device, the element having an atomic weight larger than that of silicon is preferably an element in the same group as the impurity element of the first conductivity type. As a result, an element having an atomic weight larger than that of silicon does not cancel out the impurity element of the first conductivity type, and the substantial impurity amount increases to reduce the resistance value of the silicon surface layer portion. Therefore, it is possible to suppress the variation of the contact resistance value, and it is possible to form a highly accurate resistance element.

  In the above method for manufacturing a semiconductor device, the element having an atomic weight larger than that of silicon is preferably an element belonging to the same family as silicon or an electrically inactive element. As a result, an element having an atomic weight larger than that of silicon does not cancel out the impurity element of the first conductivity type, and the substantial impurity amount of the silicon surface layer portion does not vary, so the resistance value of the resistor does not vary. Therefore, it becomes possible to form a more accurate resistance element.

  In the semiconductor device manufacturing method, it is preferable that an element having an atomic weight larger than that of silicon is ion-implanted only in a contact region of the resistor by forming a mask on the resistor. Thereby, an element having an atomic weight larger than that of the silicon is selectively injected only into the contact region of the resistor, so that the resistance value of the main body of the resistor does not fluctuate, thereby forming a more accurate resistance element. It becomes possible.

  According to the semiconductor device and the manufacturing method thereof according to the present invention, TiN which is a barrier metal has a large contact resistance with silicon, and generally a TiN / Ti laminated structure film is used, and a TiN / Ti laminated barrier metal film is used. After the growth, a rapid thermal nitride (RTN) process is performed to cause a silicide reaction between Ti and silicon. In the formation of a metal silicide between the barrier metal Ti and silicon, an element having an atomic weight larger than that of silicon is injected into the surface layer of the resistor, so that the silicon surface layer becomes amorphous and the silicide reaction with the barrier metal Ti is activated. Even in a contact structure in which a metal silicide is not formed connected to a resistor, the silicide reaction between the barrier metal and silicon is activated, and the fluctuation of the contact resistance value can be suppressed, and a highly accurate resistance element can be formed. It becomes possible.

(First embodiment)
The semiconductor device and the manufacturing method thereof according to the first embodiment will be described with reference to FIG.

As shown in FIG. 1A, a polysilicon or amorphous silicon film to be a silicon film is grown on a field oxide film 101 to be an insulating film formed on the semiconductor substrate 100. The growth thickness of the silicon film is 300 nm. However, other film thicknesses can be selected for common use with the MOS gate and other elements. After that, a group III element B (boron) is doped as a first impurity to be a first conductivity type impurity in the film by a well-known ion implantation method, and then patterned into a resistor shape by a well-known method. There is no problem if the order of implantation and patterning is reversed. In the implantation of B, the acceleration energy is set to 5 to 40 keV, and the dose amount is set to 1 × 10 ¹³ to 1 × 10 ¹⁶ cm ⁻² . A P-type resistor 102 is formed by doping by ion implantation. At this time, the implantation depth is selected so that the implantation peak is distributed on the surface layer side than the half of the resistor film thickness, and the dose is selected so as to have a target resistance value.

As shown in FIG. 1B, an insulating film 103 of several tens to several hundreds of nanometers is grown on the resistor 102 in order to suppress out diffusion. As the film thickness of the insulating film 103, a film thickness suitable for the device structure is selected. Then, after annealing at 850 ° C. for 45 minutes, As (Arsenic), a group V element having an atomic weight larger than that of silicon, is used as the second impurity, with an acceleration energy of 5 to 80 keV and a dose of 1 × 10. Doping is performed by ion implantation at ¹² to 1 × 10 ¹⁵ cm ⁻² . The acceleration energy is selected from the silicon surface layer side so that the second impurity is 1/20 or more and 1/5 or less of the resistor film thickness, and the dose is 1/20 of the dose of the first impurity. It selects so that it may be 1/10 or less.

As shown in FIG. 1C, after the interlayer insulating film 104 is grown by a well-known technique, a contact hole is formed by an etching method, and Ti / TiN to be a contact barrier metal is grown, and in an N ₂ atmosphere. Then, a silicide reaction between Ti and silicon is caused by rapid heat treatment at 650 ° C. for 30 seconds, and then a contact plug 105 and a metal wiring 106 to be a wiring part are formed.

  According to the first embodiment, by implanting As, which is an element having an atomic weight larger than that of silicon, into the silicon surface layer side of the resistor 102, the silicon surface layer becomes amorphous and the silicide reaction with the barrier metal Ti is activated. Even in the non-metal silicide contact structure connected to the resistor 102, the silicide reaction between the barrier metal and silicon is activated, and the fluctuation of the contact resistance value can be suppressed, and a highly accurate resistance element is formed. Can do.

(Second Embodiment)
A semiconductor device and a manufacturing method thereof according to the second embodiment will be described with reference to FIG.

As shown in FIG. 2A, a polysilicon or amorphous silicon film to be a silicon film is grown on a field oxide film 201 to be an insulating film formed on the semiconductor substrate 200. The growth thickness of the silicon film is 300 nm. However, other film thicknesses can be selected for common use with the MOS gate and other elements. Then, after doping a V group element P (phosphorus) as a first impurity to be a first conductivity type impurity into the film by a well-known ion implantation method, the film is patterned into a resistor shape by a well-known method. There is no problem if the order of implantation and patterning is reversed. In the implantation of P, the acceleration energy is set to 5 to 40 keV, and the dose amount is set to 1 × 10 ¹³ to 1 × 10 ¹⁶ cm ⁻² . The N-type resistor 202 is formed by doping by ion implantation. At this time, the implantation depth is selected so that the implantation peak is distributed on the surface layer side than the half of the resistor film thickness, and the dose is selected so as to have a target resistance value.

As shown in FIG. 2B, an insulating film 203 having a thickness of several tens to several hundreds of nanometers is grown on the resistor 202 to suppress outdiffusion. As the film thickness of the insulating film 203, a film thickness suitable for the device structure is selected. Then, after annealing at 850 ° C. for 45 min, as a second impurity, As of a group V element that is an element having an atomic weight larger than that of a silicon element is accelerated energy 5 to 80 keV, and a dose amount 1 × 10 ¹² to 1 ×. Doping is performed by ion implantation at 10 ¹⁵ cm ⁻² . The acceleration energy is selected from the silicon surface layer side so that the second impurity is 1/20 or more and 1/5 or less of the resistor film thickness, and the dose is 1/20 of the dose of the first impurity. It selects so that it may be 1/10 or less. When the group III element B is used as the first impurity, the same group of In (indium) can be used as the second impurity.

As shown in FIG. 2C, after the interlayer insulating film 204 is grown by a well-known technique, a contact hole is formed by an etching method, and Ti / TiN serving as a contact barrier metal is grown, and the N ₂ atmosphere is formed. Then, a silicide reaction between Ti and silicon is caused by rapid heat treatment at 650 ° C. for 30 seconds, and then a contact plug 205 and a metal wiring 206 serving as wiring parts are formed.

  According to the second embodiment, in addition to the same effects as those of the first embodiment, the first impurity forming the resistor 202 and the second impurity, which is an element having an atomic weight larger than that of silicon, are elements of the same family. Therefore, the second impurity does not cancel out the first impurity, and the substantial impurity amount increases to reduce the resistance value of the silicon surface layer portion, so that the contact resistance value is further reduced and the contact resistance value fluctuates. Therefore, it is possible to form a resistance element with higher accuracy.

(Third embodiment)
A semiconductor device and a manufacturing method thereof according to the third embodiment will be described with reference to FIG.

As shown in FIG. 3A, a polysilicon or amorphous silicon film to be a silicon film is grown on a field oxide film 301 to be an insulating film formed on the semiconductor substrate 300. The growth thickness of the silicon film is 300 nm. However, other film thicknesses can be selected for common use with the MOS gate and other elements. Then, after doping the group III element B as a first impurity to be a first conductivity type impurity into the film by a known ion implantation method, the film is patterned into a resistor shape by a known method. There is no problem if the order of implantation and patterning is reversed. In the implantation of B, the acceleration energy is set to 5 to 40 keV, and the dose amount is set to 1 × 10 ¹³ to 1 × 10 ¹⁶ cm ⁻² . A P-type resistor 302 is formed by doping by ion implantation. At this time, the implantation depth is selected so that the implantation peak is distributed on the surface layer side than the half of the resistor film thickness, and the dose is selected so as to have a target resistance value.

As shown in FIG. 3B, an insulating film 303 having a thickness of several tens to several hundreds of nanometers is grown on the resistor 302 in order to suppress outdiffusion. As the film thickness of the insulating film 303, a film thickness suitable for the device structure is selected. Then, after annealing at 850 ° C. for 45 minutes, Ge (germanium), Kr (krypton) or the like having an atomic weight larger than that of silicon is used as the second impurity, with an acceleration energy of 5 to 80 keV and a dose of 1 ×. Doping is performed at 10 ¹² to 1 × 10 ¹⁵ cm ⁻² by an ion implantation method. The acceleration energy is selected from the silicon surface layer side so that the second impurity is 1/20 or more and 1/5 or less of the resistor film thickness, and the dose is 1/20 of the dose of the first impurity. It selects so that it may be 1/10 or less.

As shown in FIG. 3C, after the interlayer insulating film 304 is grown by a well-known technique, a contact hole is formed by an etching method, and Ti / TiN serving as a contact barrier metal is grown, and the N ₂ atmosphere is formed. Then, a silicide reaction between Ti and silicon is caused by rapid heat treatment at 650 ° C. for 30 seconds, and then a contact plug 305 and a metal wiring 306 to be a wiring portion are formed.

  According to the third embodiment, in addition to the same effects as those of the first embodiment, the same group IV element as silicon as the second impurity, which is an element having a larger atomic weight than silicon, or the electrically inactive group VIII Since the second impurity does not cancel out the first impurity and the substantial impurity amount of the silicon surface layer portion does not vary, the resistance value of the resistor 302 does not vary. An element can be formed.

(Fourth embodiment)
A semiconductor device and a manufacturing method thereof according to the fourth embodiment will be described with reference to FIG.

As shown in FIG. 4A, a polysilicon or amorphous silicon film to be a silicon film is grown on a field oxide film 401 to be an insulating film formed on the semiconductor substrate 400. The growth thickness of the silicon film is 300 nm. However, other film thicknesses can be selected for common use with the MOS gate and other elements. Then, after doping the group III element B as a first impurity to be a first conductivity type impurity into the film by a known ion implantation method, the film is patterned into a resistor shape by a known method. There is no problem if the order of implantation and patterning is reversed. In the implantation of B, the acceleration energy is set to 5 to 40 keV, and the dose amount is set to 1 × 10 ¹³ to 1 × 10 ¹⁶ cm ⁻² . A P-type resistor 402 is formed by doping by ion implantation. At this time, the implantation depth is selected so that the implantation peak is distributed on the surface layer side than the half of the resistor film thickness, and the dose is selected so as to have a target resistance value.

As shown in FIG. 4B, an insulating film 403 of several tens to several hundreds of nanometers is grown on the resistor 402 in order to suppress outdiffusion. As the film thickness of the insulating coating 403, a film thickness suitable for the device structure is selected. Thereafter, furnace annealing is performed at 850 ° C. for 45 minutes, and then, as a second impurity, As which is a group V element having an atomic weight larger than that of silicon element is accelerated energy of 5 to 80 keV, and a dose amount of 1 × 10 ¹² to 1 Doping is performed by ion implantation at × 10 ¹⁵ cm ⁻² . The acceleration energy is selected from the silicon surface layer side so that the second impurity is 1/20 or more and 1/5 or less of the resistor film thickness, and the dose is 1/20 of the dose of the first impurity. It selects so that it may be 1/10 or less. At this time, although the number of processes is increased, by forming the photoresist mask 404 and implanting the second impurity only in the contact region of the resistor 402, it is possible to suppress fluctuations in resistance value and temperature characteristics. .

As shown in FIG. 4C, the photoresist mask 404 is removed by a photoresist removal technique such as ashing or cleaning, an interlayer insulating film 405 is grown by a known technique, and a contact hole is formed by an etching method. Ti / TiN to be a contact barrier metal is grown, and a silicide reaction between Ti and silicon is caused by rapid heat treatment at 650 ° C. for 30 seconds in an N ₂ atmosphere. A wiring 407 is formed.

  According to the fourth embodiment, in addition to the same effects as those of the first embodiment, the second impurity, which is an element having an atomic weight larger than that of silicon, is selectively injected only into the contact region. Therefore, it is possible to form a more accurate resistance element.

(Fifth embodiment)
A semiconductor device and a manufacturing method thereof according to the fifth embodiment will be described with reference to FIG.

As shown in FIG. 5A, a polysilicon or amorphous silicon film that becomes a silicon film is grown on a field oxide film 501 that becomes an insulating film formed on a semiconductor substrate 500. The growth thickness of the silicon film is 300 nm. However, other film thicknesses can be selected for common use with the MOS gate and other elements. Then, after doping the group III element B as a first impurity to be a first conductivity type impurity into the film by a known ion implantation method, the film is patterned into a resistor shape by a known method. There is no problem if the order of implantation and patterning is reversed. In the implantation of B, the acceleration energy is set to 5 to 40 keV, and the dose amount is set to 1 × 10 ¹³ to 1 × 10 ¹⁶ cm ⁻² . A P-type resistor 502 is formed by doping by ion implantation. At this time, the implantation depth is selected so that the implantation peak is distributed on the surface layer side than the half of the resistor film thickness, and the dose is selected so as to have a target resistance value.

As shown in FIG. 5B, an insulating film 503 of several tens to several hundreds of nanometers is grown on the resistor 502 in order to suppress out-diffusion. As the film thickness of the insulating coating 503, a film thickness suitable for the device structure is selected. Thereafter, furnace annealing is performed at 850 ° C. for 45 minutes, and then, as a second impurity, As which is a group V element having an atomic weight larger than that of silicon element is accelerated energy of 5 to 80 keV, and a dose amount of 1 × 10 ¹² to 1 Doping is performed by ion implantation at × 10 ¹⁵ cm ⁻² . The acceleration energy is selected from the silicon surface layer side so that the second impurity is 1/20 or more and 1/5 or less of the resistor film thickness, and the dose is 1/20 of the dose of the first impurity. It selects so that it may be 1/10 or less. At this time, although the number of processes is increased, by forming the hard mask 504 such as an oxide film or a nitride film, the second impurity is injected and implanted only in the contact region of the resistor, thereby causing the resistance value fluctuation and the temperature characteristic fluctuation. Can be suppressed.

As shown in FIG. 5C, after the interlayer insulating film 505 is grown by a well-known technique, a contact hole is formed by an etching method, and Ti / TiN to be a contact barrier metal is grown to be in an N ₂ atmosphere. Then, a silicide reaction between Ti and silicon is caused by rapid heat treatment at 650 ° C. for 30 seconds, and then contact plugs 506 and metal wirings 507 to be wiring parts are formed.

  According to the fifth embodiment, in addition to the same effects as those of the first embodiment, a highly accurate resistance element can be formed in the same manner as in the fourth embodiment.

  The present invention is useful for a semiconductor device provided with a highly accurate resistance element.

Sectional drawing which shows the manufacturing process of the semiconductor device in 1st Embodiment Sectional drawing which shows the manufacturing process of the semiconductor device in 2nd Embodiment Sectional drawing which shows the manufacturing process of the semiconductor device in 3rd Embodiment Sectional drawing which shows the manufacturing process of the semiconductor device in 4th Embodiment Sectional drawing which shows the manufacturing process of the semiconductor device in 5th Embodiment

Explanation of symbols

100, 200, 300, 400, 500 Semiconductor substrate 101, 201, 301, 401, 501 Field oxide film (insulating film)
102, 202, 302, 402, 502 Resistors 103, 203, 303, 403, 503 Interlayer insulating film (insulating film)
104, 204, 304, 405, 505 Interlayer insulating film 105, 205, 305, 406, 506 Contact plug (wiring part)
106, 206, 306, 407, 507 Metal wiring 404 Photoresist mask 504 Hard mask

Claims (11)

In a semiconductor device having a resistor,
A resistor made of a silicon film formed on a semiconductor substrate via an insulating film;
An interlayer insulating film formed on the resistor;
Contact holes formed in the interlayer insulating film;
A wiring portion formed in the contact hole and connected to the resistor;
Metal wiring formed on the interlayer insulating film and connected to the wiring portion,
The resistor includes a first conductivity type impurity element in the film, and an element having an atomic weight larger than that of silicon is doped on a surface layer side. 2. The semiconductor device according to claim 1, wherein the element having an atomic weight larger than that of silicon is an element of the same family as the impurity element of the first conductivity type. 2. The semiconductor device according to claim 1, wherein the element having an atomic weight larger than that of silicon is an element belonging to the same group as silicon or an electrically inactive element. 2. The semiconductor device according to claim 1, wherein an element having an atomic weight larger than that of silicon is doped in a contact region of the resistor. The semiconductor device according to claim 1, wherein the silicon film is a polysilicon film or an amorphous silicon film. In a method for manufacturing a semiconductor device having a resistor,
Forming a resistor made of a silicon film on a semiconductor substrate via an insulating film;
Doping the resistor with a first conductivity type impurity element by ion implantation;
Activating the impurity element of the first conductivity type in the resistor by heat treatment;
Forming an interlayer insulating film on the resistor;
Forming a contact hole in the interlayer insulating film;
Forming a wiring portion connected to the resistor in the contact hole;
Forming a metal wiring connected to the wiring part on the interlayer insulating film,
A method of manufacturing a semiconductor device, comprising: doping an element having a larger atomic weight than silicon on a surface layer side of the resistor by ion implantation before forming the interlayer insulating film after the heat treatment. The method for manufacturing a semiconductor device according to claim 6, wherein an insulating film is formed on a surface of the resistor before the heat treatment. 7. The method of manufacturing a semiconductor device according to claim 6, wherein the element having an atomic weight larger than that of silicon is an element in the same group as the impurity element of the first conductivity type. The method for manufacturing a semiconductor device according to claim 6, wherein the element having an atomic weight larger than that of silicon is an element belonging to the same group as silicon or an electrically inactive element. 7. The ion implantation is performed with an acceleration energy such that an implantation depth of an element having an atomic weight larger than that of silicon is 1/20 or more and 1/5 or less of a film thickness of the resistor. The manufacturing method of the semiconductor device of description. 7. The ion implantation is performed according to claim 6, wherein a dose amount of an element having an atomic weight larger than that of silicon is 1/20 or more and 1/10 or less of a dose amount of the impurity element of the first conductivity type. A method for manufacturing a semiconductor device.

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