JP2008102423A - Electro-optical device drive circuit, electro-optical device drive method, and electro-optical device - Google Patents

Abstract

In an electro-optical device, a long subfield period is set and sufficient gradation is obtained.
By applying an on-voltage and an off-voltage to the electro-optic material by changing a subfield obtained by dividing the field period into a plurality of times on the time axis to change the transmission and non-transmission of light in the electro-optic material, Each pixel is driven. The subfield period, which is the length of the subfield, is set so that one field period includes subfield periods having different lengths. Select the subfield so that the sum of the subfield periods becomes the length corresponding to the gradation to be displayed, apply one of the on-voltage and off-voltage to the selected subfield, and apply to the unselected subfield. By applying the other voltage, gradation is expressed.
[Selection] Figure 6

Description

  The present invention relates to a drive circuit for an electro-optical device, a driving method for the electro-optical device, and an electro-optical device.

  As an electro-optical device, for example, there is a liquid crystal device using liquid crystal as an electro-optical material. A liquid crystal device is widely used as a display unit of various information processing devices or an optical engine of a projector.

  The configuration of a conventional electro-optical device is, for example, as follows. That is, the electro-optical device includes a pixel electrode arranged in a matrix, an element substrate provided with various circuit elements including a switching element such as a TFT (Thin Film Transistor) connected to the pixel electrode, The counter substrate includes a counter substrate on which a counter electrode corresponding to the pixel electrode is formed, and a liquid crystal that is an electro-optic material filled between the substrates.

  In this configuration, a switching signal corresponding to a certain scanning line is made conductive by applying a scanning signal to the switching element via the scanning line on the element substrate. While the switching element is in a conductive state, a voltage signal corresponding to the gradation to be displayed on the pixel is applied to the pixel electrode via the data line on the element substrate, and the pixel electrode and the counter electrode (such as the capacitance of the liquid crystal itself) ). In accordance with the accumulated charges, the alignment state of the liquid crystal changes and the brightness of each pixel changes. In this way, gradation display of pixels is realized.

By the way, in order to obtain a high-quality liquid crystal device, various gradation representations are necessary, and various driving methods for the liquid crystal device have been developed.
An analog driving method, which is one of the driving methods, displays gradation according to the magnitude of the voltage applied to the pixel electrode. In this method, since the gradation is controlled by the magnitude of the voltage, that is, an analog signal, a D / A (digital / analog) conversion circuit or an operational amplifier is required as a peripheral circuit of the liquid crystal device, which increases the cost of the device. End up. In addition, analog signals transmitted through the apparatus are easily affected by variations in the characteristics of individual circuits, resulting in display quality degradation.

  On the other hand, a digital driving method, that is, a method of performing gradation display by applying a voltage pulse to a liquid crystal using a binary voltage signal of an on voltage and an off voltage is advantageous because there is no problem as described above. Specifically, in the digital drive method, one field, which is a period for displaying one image, is divided into a plurality of subfields (SF) on the time axis, and voltage is applied to each pixel for each subfield. The gray scale is changed by controlling (on voltage, off voltage) (time division drive method).

  In general, in the above time-division driving method, the number of gradations that can be expressed is determined by the number of subfields. Therefore, in order to increase the number of gradations, it is necessary to provide subfields in detail. For example, when 256 gradations are expressed, a subfield having a period of 1/256 of one field is required to display the next gradation of the lowest gradation (black). However, when the number of subfields is increased, the time during which a voltage should be applied to the pixel electrode becomes shorter than the operating speed of a transistor such as a TFT, making it difficult to apply voltage effectively.

Therefore, when the subfield period is set to be shorter than the response time required for alignment / relaxation of the liquid crystal, the brightness of the pixel is adjusted using the transient alignment state of the liquid crystal, so that the number of subfields A time-division drive method (equal-division subfield drive method) that can express a large number of gradations has been proposed (for example, see Patent Document 1). According to this method, for example, 256 gradations can be expressed by dividing one field into about 80 subfields. That is, in this case, one subfield period can be increased by about three times from 1/256 to 1/80 of one field.
JP 2003-114661 A

  However, in order to realize higher definition and higher gradation of the liquid crystal device, there is a demand for a driving method that can take a longer subfield period. That is, in the above time-division driving method, vertical / horizontal scanning is performed within one subfield period. Therefore, the higher the definition of the liquid crystal panel, the longer the voltage application time per pixel with the same subfield length. Becomes shorter. Therefore, it is necessary to lengthen the subfield period in order to apply the voltage effectively. Also, under the same transistor performance, it is desirable that the subfield period be long to express the same number of gradations.

  The present invention has been made in view of the above points, and an object of the present invention is to provide a drive circuit for an electro-optical device that can set a long subfield period and obtain sufficient gradation, and an electro-optical device. A driving method and an electro-optical device are provided.

  The present invention has been made to solve the above-described problems, and a drive circuit for an electro-optical device according to the present invention includes each electro-optical material including a variable light transmittance by application of voltage. By supplying an on voltage and an off voltage to a display unit in which a plurality of pixels are arranged, the state of light transmission and non-transmission in the electro-optic material is changed, and the scale is set according to the time ratio of these states. A driving circuit for an electro-optical device that performs tonal expression, wherein a subfield divided into a plurality of field periods on a time axis is used as a control unit, and a subfield period that is the length of the subfield is set as one field period The subfield periods having different lengths are set to be included, and one or a plurality of subfields are set so that the sum of the subfield periods has a length corresponding to the gradation to be displayed. Gradation is expressed by selecting a field and applying one of the on-voltage and the off-voltage to a selected subfield and applying the other voltage to a non-selected subfield. And

  According to such a configuration, the electro-optic material constituting each pixel has a variable light transmittance by applying a voltage, and the on-voltage is controlled by using a subfield obtained by dividing the field period into a plurality of times on the time axis. Each pixel is driven by applying an OFF voltage to the electro-optic material to change transmission and non-transmission of light in the electro-optic material. The subfield period, which is the length of the subfield, is set so that one field period includes subfield periods having different lengths, and the sum of the subfield periods corresponds to the gradation to be displayed. The gradation is expressed by selecting the sub-field so that one of the on-voltage and the off-voltage is applied to the selected sub-field and the other voltage is applied to the non-selected sub-field. Since the ON voltage is applied by combining the subfields having different lengths, the sum of the subfield periods by the combined subfields can be finely controlled, thereby increasing the number of gradations. Therefore, if the number of gradations is the same as the conventional one, the subfield period can be made longer than the conventional one. Since the subfield period is longer than before, it is not necessary to use a transistor with a high operating speed, and the voltage can be applied efficiently to each subfield. Will be able to.

  In the electro-optical device driving circuit according to the present invention, the subfield period may include a response time until the transmittance reaches a saturation state from a non-transmission state when the on-voltage is applied, or the off-voltage. When applied, the transmittance is set shorter than a response time until the transmittance reaches a non-transmissive state from a saturated state.

  According to such a configuration, since the brightness of the pixel is controlled using the transient alignment state of the liquid crystal, the gradation can be expressed more finely. Therefore, even if the subfield period is long and the number of subfields is small, it is possible to achieve high gradation.

  In addition, the driving method of the electro-optical device according to the present invention applies an on-voltage to a display unit in which a plurality of pixels each including an electro-optical material whose light transmittance is variable by voltage application is arranged. And a method of driving an electro-optical device that changes a light transmission state and a non-transmission state in the electro-optical material by supplying an off voltage, and performs gradation expression according to a time ratio of each state. Using the subfield divided into a plurality of periods on the time axis as a control unit, the subfield period that is the length of the subfield is set so that one field period includes subfield periods having different lengths. Select one or more subfields so that the sum of the subfield periods has a length corresponding to the gradation to be displayed, By applying the other voltage to the ON voltage or the one sub-field voltage has not been applied to select the of the off-voltage, and performs gradation expression.

  The electro-optical device according to the present invention includes a plurality of pixel electrodes, a switching element that controls a voltage applied to each pixel electrode, a counter electrode disposed to face the pixel electrode, and the pixel electrode. And an electro-optical material sandwiched between the counter electrodes, and a drive circuit for the electro-optical device.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a block diagram showing a configuration of a liquid crystal device 10 which is an electro-optical device according to an embodiment of the present invention.
The liquid crystal device 10 includes a display unit 101a in which pixels are arranged in a matrix in m rows and n columns (m and n are integers of 2 or more), and scanning signals G1, G2,... Gm are used as scanning lines of the display unit 101a. A scanning line driving circuit 130 for sequentially supplying and selecting scanning lines, and a data line for driving each pixel by supplying data signals d1, d2,... Dn based on the gradation data D0 to D7 to the data lines of the display unit 101a. A driving circuit 140, a clock generating circuit 150 that generates a clock signal CLK that serves as a reference for control, a timing signal that generates various timing signals that drive the scanning line driving circuit 130, the data line driving circuit 140, and the data conversion circuit 300. A generation circuit 200; a data conversion circuit 300 that converts the gradation data D0 to D7 and supplies the gradation instruction signal Ds to the data line driving circuit 140; And a drive voltage generation circuit 400 for generating a specified voltage to drive the a.

  The display unit 101a forms various circuits such as transistors for driving pixels on an element substrate made of a transparent substrate such as a glass substrate, and is an electro-optic material between the element substrate and a counter substrate facing the element substrate. It is configured by holding a liquid crystal. On the element substrate, m scanning lines 112 are provided at regular intervals in the Y direction, and n data lines 114 are provided at regular intervals in the X direction. Each pixel 110 is where the scanning line 112 and the data line 114 intersect.

  A detailed configuration of the pixel 110 is shown in FIG. Each pixel 110 has a transistor 116 made of a MOS FET (metal oxide semiconductor field effect transistor) on an element substrate. The gate, source, and drain of the transistor 116 are a scanning line 112, a data line 114, and a pixel, respectively. Connected to electrode 118. A liquid crystal 105 is sandwiched between the pixel electrode 118 and the counter electrode 108 on the counter substrate, and a storage capacitor 119 is formed. The counter electrode 108 is formed on the entire surface of the counter substrate.

  When a scanning signal (G 1, G 2,... Gm in FIG. 1) is supplied to the scanning line 112, the transistor 116 corresponding to the pixel 110 on the scanning line 112 is turned on, and a data signal (see FIG. 1 d1, d2,... Dn), a voltage is applied between the pixel electrode 118 and the counter electrode. By applying this voltage, the alignment state of the liquid crystal 105 changes, and the light transmittance of the pixel portion changes.

  In the present liquid crystal device 10, one field, which is a period for displaying one image, is divided into 32 subfields (SF) composed of SF1, SF2,. A voltage is applied to (see FIG. 6 described later). The applied voltage is a binary voltage signal based on an on voltage that causes the liquid crystal 105 to be in a transmissive state and an off voltage that causes the liquid crystal to be in a non-transmissive state. By controlling the application of the voltage pulse for each subfield, the time during which the ON voltage in one field is applied changes, and the brightness of the pixel changes according to the application time. Thus, gradation is expressed by controlling which subfield is applied with the on-voltage.

  As described above, the liquid crystal device 10 drives the display unit 101a using subfields as control units. The 32 subfields have different subfield periods within one field. It is set (that is, one field is divided equally). This point will be described in detail later.

  Next, the timing signal generation circuit 200 generates alternating current in accordance with the clock signal CLK input from the clock generation circuit 150 and the vertical scanning signal Vs, horizontal scanning signal Hs, and dot clock signal DCLK supplied from another circuit (not shown). An enable signal FR, a start pulse signal DY, a scanning side transfer clock CLY, a data enable signal ENBX, and a data transfer clock CLX are generated.

  Here, the alternating signal FR is a signal for inverting the polarity of data writing (application of voltage to the liquid crystal 105) for each field. In the data line driving circuit 140 described below, the alternating signal FR Data signals d1, d2,... Dn are output with the polarity according to the above.

The scanning-side transfer clock CLY is a signal that designates the timing at which the scanning signals G1, G2,... Gm are supplied to each scanning line 112, and is input to the scanning line driving circuit 130.
The data enable signal ENBX is a signal for designating timing for starting the latching of the gradation instruction signal Ds in the data line driving circuit 140 and the supply of the data signal from the data line driving circuit 140 to the data line 114.

  The data transfer clock CLX is a signal that specifies the timing for generating the latch signals (S1, S2,... Sn) in the data line driving circuit 140. In the data line driving circuit 140, the data conversion circuit 300 is in accordance with the timing of the latch signal. The gradation instruction signal Ds sent from is acquired.

  The start pulse signal DY is a signal that defines the start timing of each of the subfields SF <b> 1 to SF <b> 32, and is generated by the start pulse generation circuit 210 in the timing signal generation circuit 200. Details of the start pulse generation circuit 210 will be described below.

  FIG. 3 shows a circuit configuration diagram of the start pulse generation circuit 210. The start pulse generation circuit 210 includes a counter 211, a comparator 212, a multiplexer 213, a ring counter 214, a D flip-flop 215, and an OR circuit 216.

  The counter 211 receives the clock signal CLK, and the counter 211 counts the input clock signal CLK. Counting is performed for each subfield, and the count value is reset at the start of each subfield. Therefore, the output of the OR circuit 216 is returned to the counter 211. Note that a reset signal RSET indicating a high level is supplied to one input terminal of the OR circuit 216 only at the start of the field, and the count value of the counter 211 is reset at the start of each field.

The multiplexer 213 receives subfield period designation data D _{SF1 to} D _SF32 that define the length (subfield period) of each subfield. Based on the output of the ring counter 214 that counts the number of start pulse signals DY output from the start pulse generation circuit 210, the multiplexer 213 outputs subfield period designation data corresponding to the next _subfield from D _{SF1 to} D _SF32. Select and output to the comparator 212. For example, if the count number of the start pulse signal DY by the ring counter 214 is “2”, it means that the current period is the second subfield (SF2), and the multiplexer 213 is in the third subfield (SF3). The subfield period designation data corresponding to, that is, D _SF3 is output.

The comparator 212 compares the count value of the clock signal CLK input from the counter 211 with the subfield period designation data from the multiplexer 213, and outputs a high level coincidence signal if they match. That is, the comparator 212 outputs a coincidence signal for each period sequentially designated by the _subfield period designation data D _SF1 , D _SF2 ,..., D _SF32 .

This coincidence signal is input to the D flip-flop 215 via the OR circuit 216. When the coincidence signal is input, the D flip-flop 215 outputs the start pulse signal DY in synchronization with the scanning side transfer clock CLY.
Since the coincidence signal is input to one input terminal of the OR circuit 216, the count value of the counter 211 is reset for each input of the coincidence signal, that is, for each subfield.

With the above configuration, the start pulse generation circuit 210 can set the subfield periods of the _{subfields SF1 to SF32} to a desired length by appropriately adjusting the _subfield period designation data D _{SF1 to} D _SF32. Has been.

  Next, returning to FIG. 1, when the start pulse signal DY is inputted and each subfield is started, the scanning line driving circuit 130 sequentially applies the scanning signals G1, G1 to the scanning lines 112 in accordance with the scanning side transfer clock CLY. G2,... Gm are supplied.

  The data line driving circuit 140 once latches all the n gradation instruction signals Ds corresponding to the data lines 114, and when the data enable signal ENBX is input, the data line driving circuit 140 follows the gradation instruction signal Ds. .. Dn are simultaneously supplied to the data lines 114 as data signals d1, d2,... Dn (line sequential driving). Each data signal supplied to the data line 114 is input to the source of the transistor 116 (conducting state) provided in the scanning line 112 to which the scanning signal is supplied, and each pixel 110 ( The liquid crystal 105) is driven.

  The drive voltage generation circuit 400 outputs the voltages V1, -V1, and V0 for generating the data signal to the data line drive circuit 140, and the voltage V2 for generating the scan signal is opposed to the scan line drive circuit 130. The electrode voltage VLCCOM is output to the counter electrode 108, respectively.

  The data conversion circuit 300 converts the gradation data D0 to D7 designating the gradation to be displayed by each pixel 110 in each field into the gradation instruction signal Ds and outputs the gradation instruction signal Ds to the data line driving circuit 140. The gradation instruction signal Ds is information indicating whether the liquid crystal 105 of the pixel 110 is in a transmissive state or a non-transmissive state for each subfield. Therefore, the gradation instruction signal Ds for each subfield can be determined by providing gradation data and the subfield periods of all the subfields.

  More specifically, the data conversion circuit 300 is configured to operate in synchronization with the vertical scanning signal Vs, the horizontal scanning signal Hs, and the dot clock signal DCLK, and for each pixel 110 input from a predetermined external circuit (not shown). 8 bits (256 gradations) of gradation data D0 to D7 are written in the field memory. When the start pulse signal DY is input, the gradation data D0 to D7 of each pixel 110 is read from the field memory, and the start pulse signal DY is counted and the current subfield is obtained from the counted number.

On the other hand, subfield period designation data D _{SF1 to} D _{SF32 which} are data defining the subfield periods of all the subfields are input to the data conversion circuit 300. The data conversion circuit 300 determines the gradation instruction signal Ds in the current subfield based on the subfield period designation data and gradation data. Based on the gradation instruction signal Ds thus determined, whether to apply an on voltage or an off voltage to the pixel 110 in each subfield is determined.

  Here, the gradation instruction signal Ds is information (binary information) indicating whether the liquid crystal 105 is in a transmissive state or a non-transmissive state as described above, and the transmissive state is set to a high level signal. Assume that the transmission state corresponds to a low level signal. For example, when displaying the 256th gradation (maximum brightness), since the liquid crystal 105 is controlled to be in a transmissive state in all subfields, the gradation instruction signal Ds is high in all subfields. Become a level.

  FIG. 4 shows a circuit configuration diagram of the data line driving circuit 140. The data line driving circuit 140 includes an X shift register 1410, a first latch circuit 1420, a second latch circuit 1430, and a voltage selection circuit 1440.

When the data enable signal ENBX is input, the X shift register 1410 sequentially supplies the latch signals S1, S2,... Sn to the first latch circuit 1420 in accordance with the data transfer clock CLX.
The first latch circuit 1420 sequentially latches the gradation instruction signal Ds sent from the data conversion circuit 300 at the falling timing of the latch signals S1, S2,.
The second latch circuit 1430 latches the grayscale instruction signal Ds latched by the first latch circuit 1420 all at once with the data enable signal ENBX, and the data signals d1, d2, ... supplied as dn.

  The voltage selection circuit 1440 selects a voltage to be set for the data signals d1, d2,... Dn from the voltages V1, −V1, and V0 given by the drive voltage generation circuit 400 according to the level of the alternating signal FR. Specifically, when the AC signal FR is at a high level, the voltage −V1 is selected when the data signal as the on voltage is output, and the voltage V0 is selected when the data signal as the off voltage is output. To do. When the AC signal FR is at a low level, the voltage V1 is selected when the data signal as the on voltage is output, and the voltage V0 is selected when the data signal as the off voltage is output.

Next, the operation of the liquid crystal device 10 described above will be described using the timing chart shown in FIG.
The AC signal FR is supplied while the high level and the low level are inverted every field period. Hereinafter, the case of the low level will be described, but the case of the high level is basically the same.

Since the liquid crystal device 10 is driven by dividing one field into 32 subfields as described above, 32 start pulse signals DY are supplied in one field. A period from when the start pulse signal DY is supplied to when the next start pulse signal DY is supplied is one subfield period. As will be described later (see FIG. 6), the subfield period is different in one field. (The length of the subfield period is set by the _subfield period designation data D _{SF1 to} D _SF32 input to the start pulse generation circuit 210 as described above).

  When the start pulse signal DY is supplied, the scanning signals G1, G2,... Gm are sequentially supplied to the scanning lines 112 in accordance with the timing of the scanning transfer clock CLY. Here, each scanning signal has a pulse width corresponding to a half cycle of the scanning-side transfer clock CLY, and the first scanning signal G1 (corresponding to the first scanning line) has a start pulse signal DY It is assumed that the first scanning-side transfer clock CLY after being supplied rises after being delayed by at least a half cycle of CLY.

  On the other hand, the data enable signal ENBX is supplied at a timing between the start clock signal DY and the output of the scanning signal G1 for the first one clock (G0), and the subsequent clocks (from G1 to Gm). Is adjusted to be supplied in the same cycle as the half cycle of the scanning-side transfer clock CLY.

  When the first clock (G0) of the data enable signal ENBX is supplied, the latch signals S1, S2,... Sn are sequentially supplied according to the data transfer clock CLX. The first latch circuit 1420 receives the latch signals S1, S2,... Sn and sequentially latches the corresponding gradation instruction signals Ds (sent from the data conversion circuit 300). The gradation instruction signal Ds latched at this time becomes data displayed on the first scanning line 112. The latch is performed at the falling edge of the latch signal.

  After that, when the scanning signal G1 is supplied (to the first scanning line), the transistor 116 of the pixel 110 corresponding to the scanning line is turned on. Then, when the next clock (G1) of the data enable signal ENBX is supplied, the second latch circuit 1430 causes the gradation instruction corresponding to the first scanning line latched in the first latch circuit 1420. The signal Ds is simultaneously output to the data line 114 as the data signals d1, d2,. At the same time, the first latch circuit 1420 latches the gradation instruction signal Ds corresponding to the second scanning line.

In this way, a voltage according to the gradation instruction signal Ds is applied to the pixels 110 of the first scanning line 112, and thereafter, the pixels 110 are also applied to the second to m-th scanning lines by the same operation. A voltage is applied to.
The above is the operation performed for one subfield (here, the subfield SF1), whereby all the pixels 110 of the display portion 101a are driven in accordance with the on voltage or the off voltage. The driving for each subfield is repeated for one field (that is, here, from subfield SF1 to subfield SF32), so that the gradation of the one field is expressed. Next, this point will be described with reference to FIGS.

  FIG. 6 is a diagram schematically showing a configuration of one field in the liquid crystal device 10. As described above, one field is non-equally divided into 32 subfields SF1 to SF32, and one field is composed of subfields having subfield periods of different lengths. Here, in FIG. 6, a period having a length of 1/32 of one field period is represented by “A” for convenience (one field period is 32A).

  In FIG. 6A, the length of the subfield period is set to 0.9A for the subfields SF1, SF3,..., SF31, and the length of the subfield period is set for the subfields SF2, SF4,. 1.1A is set. In this case, if the subfield to which the ON voltage is applied is selected as shown in the left column of FIG. 7A, the sum of the subfield periods in which the ON voltage is applied is as shown in the right column of the figure. In FIG. 7A, only the case where the sum of the subfield periods is 4.0 A or less is shown.

  In FIG. 6A and FIG. 7A, for example, when the ON voltage is applied only to the subfield SF1, the sum of the subfield periods during which the ON voltage is applied is 0.9A, and the ON voltage is applied only to the subfield SF2. When the voltage is applied, the sum of the subfield periods in which the on-voltage is applied is 1.1 A, and when the on-voltage is applied to the subfields SF1 and SF3, the sum of the subfield periods in which the on-voltage is applied is 1.8 A. When the on-voltage is applied to the subfields SF1 and SF2, the sum of the subfield periods in which the on-voltage is applied is 2.0 A. When the on-voltage is applied to the subfields SF2 and SF4, the on-voltage is applied. The sum of the subfield periods is 2.2 A, and when the ON voltage is applied to the subfields SF1, SF3, and SF5, the ON voltage is The sum of the sub-field period to be pressurized is 2.7A.

  Note that the combination of subfield selections that gives the sum of the same subfield periods is not limited to that in the left column of FIG. For example, the sum of the subfield periods is 1.8 A in addition to the combination of subfields SF1 and SF3, in addition to the combination of subfields SF3 and SF5.

  Here, the sum of the sub-field periods to which the ON voltage is applied shown in the right column of FIG. 7A represents the total time for which the liquid crystal 105 of the pixel 110 is driven to transmit in one field. The sum of the field periods corresponds to the brightness of the pixel 110 in the one field. That is, the number of sums of subfield periods shown in the right column of FIG. 7A corresponds to the number of displayed gradations. 7A shows that when one field is configured as shown in FIG. 6A, 11 gradations can be expressed when the sum of subfield periods is 4.0 A or less.

  The drive control by the non-equally divided subfield shown in FIG. 6A is compared with the conventional equally divided subfield drive shown in FIGS. 6D and 7D. In FIG. 6D, one field (one field period is the same as FIG. 6A) is equally divided into 80 subfields SF1 to SF80. The lengths of the subfield periods are all equal to 0.4A (= 32A ÷ 80). In this equally divided sub-field driving, it can be seen from FIG. 7D that 10 gradations can be expressed when the sum of sub-field periods is 4.0 A or less.

  Therefore, the non-equal-division subfield driving by 32 subfields in FIG. 6 (a) can express the gradation equivalent to or higher than the equal-division subfield driving by 80 subfields in FIG. 6 (d). become. Here, when comparing the lengths of the minimum subfield periods in both, 0.9A is the minimum subfield period in non-equal division subfield driving with 32 subfields, and equal division with 80 subfields. In subfield driving, 0.4 A is the minimum subfield period.

  As described above, the non-equal-division subfield driving by 32 subfields enables gradation expression equivalent to or higher than the equal-division subfield driving by 80 subfields, and the subfield period is set longer. It is possible.

Next, FIGS. 6B and 6C show another example in which one field is divided into 32 subfields in an unequal manner.
In FIG. 6B, the length of the subfield period is set to 0.9A for the subfields SF1 to SF16, and the length of the subfield period is set to 1.1A for the subfields SF17 to SF32. . In this case, the relationship between the combination of subfield selections and the sum of the subfield periods is as shown in FIG.

  That is, for example, when the on-voltage is applied only to the subfield SF1, the sum of the subfield periods in which the on-voltage is applied is 0.9A, and when the on-voltage is applied only to the subfield SF17, the on-voltage is applied. The sum of the subfield periods is 1.1 A. When an on voltage is applied to the subfields SF1 and SF2, the sum of the subfield periods to which the on voltage is applied is 1.8 A, and the on voltage is applied to the subfields SF1 and SF17. When the ON voltage is applied, the sum of the subfield periods in which the ON voltage is applied is 2.0 A, and when the ON voltage is applied to the subfields SF17 and SF18, the sum of the subfield periods in which the ON voltage is applied is 2.2 A. Yes, when the on-voltage is applied to the subfields SF1, SF2, and SF3, the sub-field to which the on-voltage is applied The sum of the field period is 2.7A.

In this way, even in the case of non-uniform division subfield driving in FIG. 6B, when the sum of subfield periods is 4.0 A or less, 11 gradations can be expressed as in FIG. 6A. . Also, the minimum subfield period is 0.9 A, which is the same as in the case of FIG.
Therefore, even with non-equal-division subfield driving with 32 subfields as shown in FIG. 6B, gradation expression equivalent to or higher than that with equal subdivision subfield driving with 80 subfields can be achieved. It is possible to set a longer period.

  As a third example, in the non-uniform division subfield driving of FIG. 6C, the subfield period of the subfield SF1 is set to 0.9A, the subfield period of the subfield SF2 is set to 0.8A, The subfield period of subfield SF3 is set to 1.1A, the subfield period of subfield SF4 is set to 1.2A, and the subsequent subfields are repeated with the same subfield period as subfields SF1 to SF4. Is set to In this case, the relationship between the combination of subfield selections and the sum of the subfield periods is as shown in FIG.

  That is, for example, when the on-voltage is applied only to the subfield SF2, the sum of the subfield periods in which the on-voltage is applied is 0.8A, and when the on-voltage is applied only to the subfield SF1, the on-voltage is applied. The sum of the subfield periods is 0.9 A, and when the ON voltage is applied only to the subfield SF3, the sum of the subfield periods to which the ON voltage is applied is 1.1 A, and the ON voltage is applied only to the subfield SF4. Then, the sum of the subfield periods to which the ON voltage is applied is 1.2A.

  Further, when the on-voltage is applied to subfields SF2 and SF6, the sum of the subfield periods during which the on-voltage is applied is 1.6 A, and when the on-voltage is applied to subfields SF1 and SF2, the on-voltage is applied. The sum of the subfield periods is 1.7 A. When an on voltage is applied to the subfields SF1 and SF5, the sum of the subfield periods to which the on voltage is applied is 1.8 A, and the on voltage is applied to the subfields SF2 and SF3. Is applied, the sum of the subfield periods in which the on-voltage is applied is 1.9 A.

  Further, when an on-voltage is applied to subfields SF1 and SF3 or SF2 and SF4, the sum of subfield periods during which the on-voltage is applied is 2.0 A, and when an on-voltage is applied to subfields SF1 and SF4, The sum of the subfield periods in which the voltage is applied is 2.1 A, and when the on voltage is applied to the subfields SF3 and SF7, the sum of the subfield periods in which the on voltage is applied is 2.2 A, and the subfield SF3 When the ON voltage is applied to SF4 and SF4, the sum of the subfield periods in which the ON voltage is applied is 2.3A, and when the ON voltage is applied to subfields SF4 and SF8, the sum of the subfield periods in which the ON voltage is applied Is 2.4A.

  Further, when the on-voltage is applied to the subfields SF1, SF2, and SF6, the sum of the subfield periods in which the on-voltage is applied is 2.5A, and when the on-voltage is applied to the subfields SF1, SF2, and SF5, The sum of the subfield periods to which is applied is 2.6A, and when the on-voltage is applied to the subfields SF1, SF5 and SF9, the sum of the subfield periods to which the on-voltage is applied is 2.7A.

  Although not described below, in the case of unequal division subfield driving in FIG. 6C, 28 gradations can be expressed when the sum of subfield periods is 4.0 A or less, and the above two unequal It can be seen that the number of gradations can be increased as compared with the divided subfield driving. In other words, if the number of gradations equivalent to 80 subfield equal division subfield driving (FIG. 6 (d)) is sufficient, the number of non-uniform division of one field into subfields is set. It can be less than 32. In such a case, the minimum subfield period among the non-equally divided subfields is longer than 0.8 A in the case of FIG. Therefore, even if the number of gradations is the same, the subfield period can be further increased.

In the above description, the brightness of the pixel 110 has been described as being proportional to the number of subfields to which the ON voltage is applied. However, in actuality, the brightness of the pixel 110 is determined by the transmission of the liquid crystal 105. When the rate changes with time, it is proportional to the integral value of the transmittance.
Therefore, in the present liquid crystal device 10, the response time of the liquid crystal 105, that is, when the ON voltage is applied to the pixel 110, the transmittance of the liquid crystal 105 is changed from the non-transmissive state (the transmittance is about 0%) to the saturated state (the transmittance). Than the response time until the transmittance of the liquid crystal 105 reaches the non-transmissive state from the saturated state when an off-voltage is applied to the pixel 110. A driving method in which subfields are set so that the length is shorter can be used.

  In this method, for example, when there is a subfield to which an off voltage is applied between subfields to which an on voltage is applied, the transmittance of the liquid crystal 105 is adjusted to the alignment of the liquid crystal during the subfield period to which the off voltage is applied. Since it decreases due to the relaxation of the state, the integral value of the transmittance also decreases, and the brightness of the pixel 110 becomes smaller than when the on-voltage is continuously applied. Thereby, even if the number of subfields to which the on voltage is applied is the same, the gradation can be changed more finely by changing the order in which the on voltage and the off voltage are applied.

  As described above, the embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to the above, and various design changes and the like can be made without departing from the scope of the present invention. It is possible to

  For example, in the above embodiment, the liquid crystal is described as being in a transmissive state when an on voltage is applied. However, the present invention is also applied to a liquid crystal device in which the liquid crystal is in a transmissive state when an off voltage is applied. Can do.

1 is a block diagram illustrating a configuration of an electro-optical device (a liquid crystal device) according to an embodiment of the present invention. It is a block diagram of the pixel formed in the display part of a liquid crystal device. It is a circuit block diagram of a start pulse generation circuit. It is a circuit block diagram of a data line drive circuit. 6 is a timing chart for explaining the operation of the liquid crystal device. It is the figure which showed typically the structure of the field divided | segmented into the subfield. It is a figure explaining the number of gradations implement | achieved by subfield drive.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Liquid crystal device 101a ... Display part 130 ... Scanning line drive circuit 140 ... Data line drive circuit 150 ... Clock generation circuit 200 ... Timing signal generation circuit 300 ... Data conversion circuit 400 ... Drive voltage generation circuit

Claims (4)

The light in the electro-optic material is supplied by supplying an on-voltage and an off-voltage to a display unit in which a plurality of pixels each including an electro-optic material whose light transmittance is variable by voltage application is arranged. A driving circuit for an electro-optical device that changes a transmission state and a non-transmission state, and performs gradation expression according to a time ratio of each state.
A subfield that is divided into multiple field periods on the time axis is used as a control unit.
A subfield period that is the length of the subfield is set so that one field period includes subfield periods having different lengths, and
One or a plurality of subfields are selected so that the sum of the subfield periods becomes a length corresponding to the gradation to be displayed, and one of the on-voltage and the off-voltage is applied to the selected subfield. A drive circuit for an electro-optical device, characterized in that gradation expression is performed by applying the other voltage to an unselected subfield.   The sub-field period is a response time until the transmittance reaches a saturated state from the non-transmissive state when the on-voltage is applied, or the transmittance is from a saturated state to a non-transmissive state when the off-voltage is applied. 2. The drive circuit for an electro-optical device according to claim 1, wherein the drive time is set to be shorter than a response time until reaching. The light in the electro-optic material is supplied by supplying an on-voltage and an off-voltage to a display unit in which a plurality of pixels each including an electro-optic material whose light transmittance is variable by voltage application is arranged. A method of driving an electro-optical device that changes a transmission state and a non-transmission state, and performs gradation expression according to a time ratio of each state.
A subfield that is divided into multiple field periods on the time axis is used as a control unit.
A subfield period that is the length of the subfield is set so that one field period includes subfield periods having different lengths, and
One or a plurality of subfields are selected so that the sum of the subfield periods becomes a length corresponding to the gradation to be displayed, and one of the on-voltage and the off-voltage is applied to the selected subfield. A method for driving an electro-optical device, characterized in that gradation expression is performed by applying the other voltage to an unselected subfield. A plurality of pixel electrodes;
A switching element for controlling a voltage applied to each pixel electrode;
A counter electrode disposed to face the pixel electrode;
An electro-optic material sandwiched between the pixel electrode and the counter electrode;
An electro-optical device comprising the drive circuit for the electro-optical device according to claim 1.

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