JP2008198783A - Field effect transistor - Google Patents

Abstract

There is provided a field effect transistor which is a normally-off semiconductor device and has a small variation in thickness of an electron supply layer directly under a gate electrode and a small variation in a threshold ON voltage of a gate.
A field effect transistor having an electron transit layer (13) made of GaN and an electron supply layer (15) having a substantially larger band gap than the electron transit layer (13), the gate electrode (18) The thickness of the electron supply layer in the immediately lower portion is smaller than the thickness of the electron supply layer in the other portion, and at least a part of the electron supply layer (15) is a BN layer, an InN layer, a GaN layer, and an AlN layer. A field effect transistor having a multilayer structure in which at least two layers selected from the group consisting of:
[Selection] Figure 1

Description

  The present invention relates to a field effect transistor, and in particular, a field-effect transistor (Field-Effect Transistor, which does not flow current between a source electrode and a drain electrode when a voltage is not applied to a gate electrode, and performs a so-called normally-off operation. FET).

  Nitride-based compound semiconductor materials such as GaN, InGaN, AlGaN, and AlInGaN have higher band gap energy than GaAs-based materials, so electronic devices using these have high heat resistance and excellent high-temperature operation. . In particular, application of electronic devices such as FETs using GaN as power supply devices is expected.

  When considering the use of an FET as a power supply device, the FET needs to exhibit normally-off characteristics in order to realize a power supply circuit such as a converter or an inverter with an existing circuit configuration.

  FIG. 7 is a schematic cross-sectional view showing the structure of an FET that uses a conventional heterojunction of a GaN-based compound semiconductor to form an electron transit layer 72 by forming a high mobility electron layer. As shown in FIG. 7A, this FET includes a buffer layer 71 made of GaN, an electron transit layer 72 made of undoped GaN, and an undoped AlGaN that is thinner than the electron transit layer 72 on a sapphire substrate 70. It has a layer structure (heterojunction structure) in which the electron supply layers 74 made of Further, due to the strain generated due to the difference in lattice constant between the electron supply layer 74 and the electron transit layer 72 and the spontaneous polarization of the electron supply layer 74, a high concentration of mobility is high in the vicinity of the electron supply layer 74 inside the electron transit layer 72. A layer 73 of two-dimensional electron gas (2DEG) is formed, and as a result, a FET having a low ON resistance (resistance of the element when current flows) is realized. Such an electron transit layer using 2DEG is hereinafter referred to as an HFET (Heterojunction FET). The contact layer 75 is a layer having a high carrier concentration so that an ohmic contact with the source electrode 76 and the drain electrode 77 can be easily obtained.

The electron supply layer is a layer that applies a stress sufficient to form a two-dimensional electron gas (2DEG) layer inside the electron transit layer and generates polarization, and is usually a layer having a lattice constant different from that of the electron transit layer. Stress is applied by forming it to a certain thickness or more. In addition, a crystalline material that generates polarization is used for the electron supply layer. The magnitude of the stress per unit thickness varies depending on the difference in lattice constant between the electron transit layer and the electron supply layer, but typically, as shown in FIG. 8, the electron supply layer exceeds a certain thickness. 2DEG is generated in the electron transit layer, and the ON resistance between the source and the drain is drastically lowered. This thickness is called a threshold thickness (Tth). If the thickness of the electron supply layer is too large, the crystal of the electron transit layer is broken due to stress, and 2DEG disappears. Therefore, normally, when the electron supply layer is Ga _0.75 Al _0.25 N and the electron transit layer is GaN, the thickness of the electron supply layer is about 20 nm.

  When the electron supply layer is formed to be thicker than Tth, a so-called normally-on operation in which a current continues to flow between the source electrode and the drain electrode when no voltage is applied to the gate electrode, and a source is applied when no voltage is applied to the gate electrode. A normally-off operation in which no current flows between the electrode and the drain electrode cannot be realized. In the normally-on operation, when the HFET is used as a switching element of an electronic device, there is a problem in safety because the device switch cannot be cut off in an emergency such as a power failure or disconnection.

  Here, as a method for realizing a normally-off operation in the HFET, for example, as shown in FIG. 7B, a deep etching groove 79 is formed in a portion of the electron supply layer 74 where the gate electrode 78 is formed. A method is known in which the thickness of the electron supply layer 74a in the portion where the gate electrode 78 is formed is sufficiently thinner than the other portions (recess etching) (see, for example, Patent Documents 1 and 2).

The reason why the normally-off operation can be realized by the recess etching is as follows. By making the electron supply layer 74 thinner, the polarization becomes smaller and the pinch-off voltage V _T increases. Therefore, in a state where no voltage is applied to the gate electrode 78, the two-dimensional electron gas layer 33 having a high mobility disappears in the gate electrode portion and is depleted, and the resistance between the source and the drain is increased. That is, the source and drain are electrically turned off. When the recess etching is performed, if the electron supply layer 74 is too thin, the ON voltage becomes too high. Therefore, the thickness of the electron supply layer 74a in the gate electrode formation portion must be precisely controlled.
JP 2000-277724 A JP 2005-183733 A

  As described above, in order to realize an HFET that performs normally-off operation, it is necessary to reduce the thickness of the electron supply layer in the gate electrode formation portion with good controllability. However, the dry etching method conventionally used for thinning the electron supply layer has a slow etching rate and can be etched relatively uniformly, but it is very thin electrons of several tens of nm. It was not sufficient to cut the supply layer with good controllability and uniformity. For this reason, the threshold ON voltage (threshold voltage: Vth) varies every time it is manufactured, and the threshold ON voltage varies depending on the location of the wafer. Further, when the etching groove is deepened, the etching time becomes longer, and the unevenness of the surface of the electron supply layer after etching becomes larger due to the nonuniformity of the etching rate. For this reason, there is a problem that the adhesion of the gate electrode is deteriorated.

  The present invention has been made to solve the above-described problems, and an object of the present invention is a field-effect transistor that performs a normally-off operation, in which there is little variation in the thickness of the electron supply layer directly under the gate electrode, and It is an object of the present invention to provide a field effect transistor with little variation in threshold ON voltage.

  The present invention solves the above problems by forming a part or all of the electron supply layer into a multilayer structure in which two or more types of layers having different crystal compositions and hence different etching rates are alternately laminated. As a result, the present invention has been completed. That is, the present invention is as follows.

  The present invention is a field effect transistor having an electron transit layer made of GaN and an electron supply layer having a substantially larger band gap than the electron transit layer, and the thickness of the electron supply layer immediately below the gate electrode is And at least part of the electron supply layer is alternately formed of at least two layers selected from the group consisting of a BN layer, an InN layer, a GaN layer, and an AlN layer. It is a field effect transistor having a multilayered structure.

Here, the electron supply layer may further include an Al _x Ga _1-x N layer (0 ≦ x ≦ 1). In this case, the Al _x Ga _1-x N layer is preferably formed in contact with the electron transit layer.

  The layer directly under the gate electrode is preferably a layer that does not substantially contain Al.

  According to the present invention, there is provided a normally-off field effect transistor in which there is little variation in the thickness of the electron supply layer directly under the gate electrode portion, and there is little variation in the gate threshold ON voltage.

Hereinafter, the present invention will be described in detail with reference to embodiments.
<First Embodiment>
FIG. 1 is a schematic cross-sectional view showing a preferred example of the field effect transistor of the present invention. The HFET shown in FIG. 1 has a layer structure in which a buffer layer 12 made of non-doped GaN, an electron transit layer 13 made of undoped GaN, and an electron supply layer 15 are sequentially laminated on a silicon substrate 11. . Further, due to the strain generated by the difference in lattice constant between the electron supply layer 15 and the electron transit layer 13 and the spontaneous polarization of the electron supply layer 15, a high concentration two-dimensional electron gas is present in the vicinity of the electron supply layer 15 inside the electron transit layer 13. The (2DEG) layer 14 is formed, and as a result, an HFET having a low ON resistance (resistance of the element when current flows) is realized.

  Further, a source electrode 16 and a drain electrode 17 are formed on the electron supply layer 15, and the recess of the electron supply layer 15 formed by recess etching is completely filled and spread over a part of the surface of the electron supply layer 15. Thus, a gate electrode 18 is provided. A normally-off operation is realized by such recess etching. By forming the gate electrode 18 so as to completely close the concave portion and spread over a part of the surface of the electron supply layer 15, the width of the concave portion formed by recess etching can be narrowed. An increase in resistance at the lower portion can be suppressed, and the electric field can be concentrated on the gate end by relaxing the electric field between the drain and the gate by forming it so as to spread on the surface of the electron supply layer 15.

  Here, although not shown in FIG. 1, the electron supply layer 15 has a multilayer structure in which two types of layers having different crystal compositions are alternately stacked. Specifically, as shown in FIG. The GaN layer 21 and the AlN layer 22 having different crystal compositions are alternately stacked. More specifically, the layer in contact with the electron transit layer 13 is the AlN layer 22, and the GaN layer 21 and the AlN layer 22 are sequentially formed thereon, and the outermost surface (electrode formation surface) is the GaN layer 21. It is. The number of layers to be stacked is not limited to the number shown in FIG. The electron supply layer having a multilayer structure in which the GaN layer 21 and the AlN layer 22 are alternately stacked is dry-etched using an etching gas having a different etching rate depending on the crystal composition, so that the etching rate can be adjusted within the wafer surface. Therefore, even when the wafer is replaced and etched, it is possible to reduce the thickness variation of the electron supply layer in the recess etched portion. In addition, since the surface of the electron supply layer in the recess formed by recess etching is uniform or substantially uniform, the adhesion of the gate electrode can be improved. Furthermore, since the outermost surface of the electron supply layer is a GaN layer that does not contain Al, the interface state with the electrode can be reduced compared to the case of using a layer containing highly oxidizable Al. Adhesiveness with an electrode can be improved.

  In the present embodiment, the thickness of the GaN layer 21 and the AlN layer 22 constituting the electron supply layer does not exceed the threshold thickness (Tth) described with reference to FIG. 8 in order to realize a normally-off operation. Specifically, they are 2.5 nm and 1.25 nm, respectively. The GaN layer 21 and the AlN layer 22 have crystal structures as shown in FIG. 3A and FIG. 3B, respectively, and when viewed from the thickness direction of the layers, group III atoms (Ga atoms) The surface (A surface) composed only of 31 or Al atoms 34) and the surface (surface B) composed only of group V atoms (N atoms 32) appear alternately. One A-plane to the next A-plane (the same from one B-plane to the next B-plane) is called one atomic layer, and the thickness of both GaN and AlN is about 0.25 nm. Therefore, the electron supply layer (electron supply layer 15 in FIG. 1) according to the present embodiment has a GaN layer 21 and an AlN layer 22 each having a thickness of 10 atomic layers and 5 atomic layers, and these are alternately stacked (however, As described above, an AlN layer formed in contact with the electron transit layer is a multilayer structure.

The thickness of the entire electron supply layer is preferably selected so that the carrier concentration of the two-dimensional electron gas (2DEG) layer is 5 × 10 ¹² to 15 × 10 ¹² / cm ^2. , 30 nm. In other words, this is a configuration in which one set of AlN layer and GaN layer is stacked. As described above, if the electron supply layer is too thick, the crystal of the electron transit layer is destroyed by stress, and thus the 2DEG layer may disappear. However, in the electron supply layer of this embodiment, There is no phenomenon, and an HFET having a low ON resistance is realized. This is thought to be because the thickness of each GaN layer and AlN layer is sufficiently thin, and the magnitude of stress is almost the same as that of an electron supply layer composed of an AlGaN layer having a composition obtained by averaging these layers. .

  In the present embodiment, the thickness of the electron supply layer remaining under the recess formed by the recess etching is 7.5 nm. That is, two sets of AlN layers and GaN layers remain. With such a configuration, electrons in the electron transit layer are expelled by the electric field of the Schottky electrode formed in the gate portion, and a so-called normally-off in which no current flows between the drain and the source when the gate voltage is OFF can be realized. In addition, an HFET with a small variation in threshold voltage can be realized.

  Next, an example of a method for manufacturing the HFET of FIG. 1 will be described with reference to FIG. FIG. 4 is a schematic process diagram showing an example of a method for manufacturing the HFET of FIG. 1, and is a schematic cross-sectional view of the HFET in the middle of manufacturing. First, a buffer layer 12 made of non-doped GaN, an electron transit layer 13 made of undoped GaN, and an electron supply layer 15 are sequentially laminated on the silicon substrate 11 using a conventionally known method (FIG. 4A). Here, the electron supply layer 15 is formed by laminating a total of eight sets of AlN layers and GaN layers alternately. Next, although not shown, the source electrode 16 and the drain electrode 17 are formed on the GaN layer that is the outermost surface of the electron supply layer 15. These ohmic electrodes can be formed by, for example, sequentially stacking Ti / Al / Ti / Au or Hf / Al / Hf / Au from the GaN layer side.

Next, the electron supply layer in the portion where the gate electrode 18 is to be formed is etched using a dry etching method such as an ICP method to form the recess 19 (FIG. 4B). An ICP etching apparatus can be used for etching, and a mixed gas of SiCl ₄ and Cl ₂ can be used as an etching gas. First, etching is performed on the outermost GaN layer under the conditions that the etching rate of the GaN layer> the etching rate of the AlN layer, that is, the ICP power of 500 W and the DC bias of −150 V, and then the etching rate of the GaN layer <AlN layer The exposed AlN layer is etched under the conditions of the etching rate of ICP power 1000 W and DC bias −30V. Etching under these two conditions was alternately repeated to selectively etch the AlN layer and the GaN layer sequentially, thereby removing a total of six sets of GaN layers and AlN layers, leaving two sets remaining.

  Thereafter, a metal film is sequentially formed in the formed recess 19 to form a gate electrode 18 having Schottky characteristics, and the HFET element shown in FIG. 1 is completed.

For example, the HFET of this embodiment manufactured as described above performs a good normally-off operation with good reproducibility. Further, it had a low ON resistance of ² mΩcm ² . Furthermore, the threshold ON voltage of the HFET of this embodiment is 0.3 ± 0.01 V, and the variation of the threshold ON voltage is very small. Note that the variations in the ON resistance and the threshold ON voltage are measured as follows.
ON resistance: Using a semiconductor parameter analyzer, the current value I _ds when the source-drain voltage V _{ds was} 1 V was measured at a gate voltage V _{g of} 2 V, and the ON resistance was calculated from the following equation.
ON resistance = V _ds / I _ds × Device area threshold ON voltage variation: The gate voltage Vg was changed at a source-drain voltage V _{ds of} 5 V, and the gate voltage at which I _ds was 10 μA was measured.

  Here, the first embodiment can be modified as follows, for example, within a range that does not impair the object of the present invention. First, in the first embodiment, the electron supply layer has a multilayer structure in which AlN layers and GaN layers are alternately stacked. However, the electron supply layer is made of a material that can form a good crystalline thin film (layer) that is substantially lattice matched with the substrate. And a multilayer structure composed of two or more layers having different crystal compositions and different etching rates. Specifically, two or more types of layers selected from the group consisting of a BN layer, an InN layer, a GaN layer, and an AlN layer can be mentioned. Examples of the combination of the two types of layers include an AlN layer and a GaN layer. In addition, an AlN layer and an InN layer, a GaN layer and an InN layer, and the like can be given. Examples of combinations of the three types of layers include GaN / AlN / InN. Among these, a combination of an AlN layer and a GaN layer and a combination of GaN / AlN / InN are preferable because the lattice constants of GaN are close to each other.

The electron supply layer has a multilayer structure in which two or more types of Al _x Ga _1-x N layers (0 ≦ x ≦ 1) having different x are laminated in addition to the multilayer structure of, for example, an AlN layer and a GaN layer as described above. There may be. Two or more layers constituting a multilayer structure have completely different constituent atoms. For example, a combination of binary mixed crystals composed of two kinds of atoms such as GaN, AlN, and InN uses the same constituent atoms. Compared with the case where a combination of layers having different compositions (ratio) is used, it is preferable because a difference in etching rate is easily generated.

The thickness of the entire electron supply layer is not limited to 30 nm in the first embodiment, and can be changed as appropriate. If the total thickness is about 20 to 40 nm, a good ON resistance of about 1 to 3 mΩcm ² can be obtained. The thicknesses of the GaN layer and the AlN layer constituting the electron supply layer in the first embodiment and the number of pairs to be stacked are not limited to the above values. The GaN layer and the AlN layer can each independently be, for example, 1 to 10 atomic layers. By making the GaN layer and the AlN layer thinner, it is possible to control the variation in the thickness of the electron supply layer in the recess etched portion more precisely. The number of layers to be stacked (one AlN layer and one GaN layer is one) can be 4 to 80, for example. As described above, the thickness of the entire electron supply layer is It is preferable to be 20 to 40 nm.

  The number of remaining sets of the AlN layer and the GaN layer constituting the electron supply layer after dry etching is not particularly limited, but the number of remaining sets is 2 to 40 sets with respect to the number of stacked sets of 4 to 80 sets. Preferably there is. When the number of remaining pairs is one, the characteristics of GaN and AlN become obvious. Moreover, when the number of remaining pairs is 41 or more, characteristics tend to deteriorate due to crystal defects.

  The width of the recess formed by recess etching is not particularly limited, but is preferably 0.5 μm or more, for example, in order to suppress the leakage current between the source and the drain. Further, from the viewpoint of reducing the device size, the thickness is preferably 3 μm or less, more preferably 1 μm or less.

  Changing the ratio of the thicknesses of the GaN layer and the AlN layer can change the average composition of the electron supply layer, and thus change the magnitude of polarization. For example, by making the thickness of the AlN layer thicker than that of the GaN layer, the composition of Al increases, and the polarization and stress also increase, so that the thickness of the entire electron supply layer can be reduced and the process is shortened. There are advantages. Even when the AlN layer is thickened, if the outermost surface on which the gate electrode is formed is a GaN layer not containing Al, the problem of electrode peeling due to oxidation does not occur.

When forming the gate electrode in the recess formed by recess etching, the gate electrode may be formed directly, or after forming a dielectric film such as SiO ₂ , Ta ₂ O ₅ , NbO, etc., on the gate An electrode may be formed. Further, the gate electrode may be formed so as to close the recess and spread over the surface of the electron supply layer as in the first embodiment, or as shown in FIG. You may form so that it may enter.

  Furthermore, it goes without saying that SiC, sapphire, etc. can be used for the substrate in addition to silicon. The modifications described above can be applied to other embodiments described below.

<Second Embodiment>
FIG. 5 is a schematic cross-sectional view showing another preferred example of the field effect transistor of the present invention. The high electron mobility transistor (HFET) shown in FIG. 5 includes an Al _x Ga _1-x multilayer structure 55 in which an electron supply layer is formed by alternately laminating AlN layers and GaN layers similar to those in the first embodiment. The structure is the same as that of the HFET of the first embodiment except that it is composed of N layers (0 ≦ x ≦ 1) 59. With such a configuration, a mixed crystal of AlN and GaN is formed, and a uniform band gap is formed in the film thickness direction. Therefore, the polarization of the electron supply layer becomes a more appropriate value, and normally-off characteristics are obtained. There is an advantage that it is easy to be.

In the present embodiment, the thickness of the Al _x Ga _1-x N layer (0 ≦ x ≦ 1) 59 that is a part of the electron supply layer is 7.5 nm. Further, the thicknesses of the GaN layer and the AlN layer constituting the multilayer structure 55 which is a part of the electron supply layer are 2.5 nm and 1.25 nm, respectively, that is, a thickness of 10 atomic layers and 5 atomic layers, respectively. is there. The multilayer structure 55 has a structure in which one set of one AlN layer and one GaN layer are stacked, and the multilayer structure 55 as a whole has a thickness of 20 nm. Therefore, the thickness of the entire electron supply layer is 30 nm.

Next, an example of a method for manufacturing the HFET of FIG. 5 will be described with reference to FIG. FIG. 6 is a schematic process diagram showing an example of a method for manufacturing the HFET of FIG. 5, and is a schematic cross-sectional view of the HFET in the middle of manufacturing. First, a buffer layer 52 made of AlN and GaN and an electron transit layer 53 made of undoped GaN are sequentially stacked on a silicon substrate 51 using a conventionally known method. Next, an Al _x Ga _1-x N layer (0 ≦ x ≦ 1) 59 is formed thereon, and then a GaN layer and an AlN layer are alternately stacked to form a multilayer structure 55 (FIG. 6A). ).

Next, after forming the source electrode 56 and the drain electrode 57 on the multi-layer structure 55 (not shown in FIG. 6), the multi-layer structure is formed on the portion where the gate electrode is formed in the same manner as in the first embodiment. All the 55 AlN layers and GaN layers are dry-etched to form the recesses 60 to expose the Al _x Ga _1-x N layer (0 ≦ x ≦ 1) 59 (FIG. 6B). Finally, a gate electrode 58 is formed in the recess 60 to obtain the HFET shown in FIG.

The HFET of this embodiment performs a good normally-off operation with good reproducibility. Further, it had a low ON resistance of ² mΩcm ² . Furthermore, the threshold ON voltage of the HFET of this embodiment is 0.3 ± 0.01 V, and the variation of the threshold ON voltage is very small.

Here, the second embodiment described above can be modified as follows, for example, within a range that does not impair the object of the present invention. First, the thickness of the Al _x Ga _1-x N layer (0 ≦ x ≦ 1) 59 is not limited to the above value, and can be about 5 to 15 nm. When the thickness of the Al _x Ga _1-x N layer (0 ≦ x ≦ 1) 59 is within this range, normally-off is possible. Further, the threshold value can be changed by adjusting the thickness of the Al _x Ga _1-x N layer (0 ≦ x ≦ 1) 59.

Each layer of the GaN layer and the AlN layer constituting the multilayer structure 55 can be about 1 to 10 atomic layers as in the first embodiment. Further, 2 to 40 pairs of one GaN layer and one AlN layer can be laminated, and the total thickness of the multilayer structure 55 can be about 10 to 20 nm. The thickness of the entire electron supply layer is not limited to 30 nm in the second embodiment, and can be changed as appropriate. If the total thickness is about 20 to 40 nm, a good ON resistance of about 1 to 3 mΩcm ² can be obtained.

The number of remaining sets of the AlN layer and GaN layer constituting the electron supply layer after dry etching is not particularly limited, but the number of remaining sets is set to 0 with respect to the number of stacked sets of 2 to 40 in the multilayer structure 55. ~ 39 sets. That is, as in the second embodiment, all of the AlN layer and the GaN layer in the gate electrode formation portion may be etched or may be etched so that a multilayer structure remains. Further, a structure in which the Al _x Ga _1-x N layer (0 ≦ x ≦ 1) 59 is further etched after the AlN layer and the GaN layer are all etched may be employed.

The stacking order of the multilayer structure 55 and the Al _x Ga _1-x N layer (0 ≦ x ≦ 1) 59 can also be reversed. That is, the electron supply layer may be configured so that the multilayer structure 55 is in contact with the electron transit layer 53. Even with such a configuration, it is possible to precisely control the thickness variation of the electron supply layer remaining after the recess etching.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

It is a schematic sectional drawing which shows a preferable example of the field effect transistor of this invention. It is a schematic sectional drawing which shows the electron supply layer in HFET of FIG. It is a schematic diagram which shows the crystal structure of a GaN layer and an AlN layer, (a) shows the crystal structure of a GaN layer, (b) shows the crystal structure of an AlN layer. It is a schematic process drawing which shows an example of the manufacturing method of HFET of FIG. It is a schematic sectional drawing which shows another preferable example of the field effect transistor of this invention. FIG. 6 is a schematic process diagram illustrating an example of a method for manufacturing the field effect transistor of FIG. 5. It is a schematic sectional drawing which shows the structure of FET formed using the heterojunction of the conventional GaN-type compound semiconductor and forming a high mobility electron layer. It is a graph which shows typically the relation between the thickness of an electron supply layer, and two-dimensional electron concentration.

Explanation of symbols

11, 51 Silicon substrate, 12, 52 Buffer layer, 13, 53 Electron travel layer, 14, 54 Two-dimensional electron gas (2DEG) layer, 15 Electron supply layer, 16, 56 Source electrode, 17, 57 Drain electrode, 18, 58 gate electrode, 19, 60 recess, 21 GaN layer, 22 AlN layer, 31 Ga atom, 32 N atom, 33 GaN (for one layer), 34 Al atom, 35 AlN (for one layer), 55 multilayer structure, 59 Al _x Ga _1-x N layer (0 ≦ x ≦ 1).

Claims (4)

A field effect transistor having an electron transit layer made of GaN and an electron supply layer having a substantially larger band gap than the electron transit layer,
The thickness of the electron supply layer immediately below the gate electrode is less than the thickness of the electron supply layer in the other part, and
At least a part of the electron supply layer has a multilayer structure in which at least two layers selected from the group consisting of a BN layer, an InN layer, a GaN layer, and an AlN layer are alternately stacked. The field effect transistor according to claim 1, wherein the electron supply layer further includes an Al _x Ga _1-x N layer (0 ≦ x ≦ 1). The field effect transistor according to claim 2, wherein the Al _x Ga _1-x N layer is formed in contact with the electron transit layer.   The field effect transistor according to claim 1, wherein the layer immediately below the gate electrode is a layer that does not substantially contain Al.

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