JP2008193191A - Amplifier circuit, AGC circuit, and RF receiver - Google Patents

Abstract

An amplifier circuit that has a wide gain control range and can be applied to a high-frequency signal, an AGC circuit including the amplifier circuit, and an RF receiver including the AGC circuit are provided.
A variable resistor (41) is formed by combining a variable resistance element (410, 411, 412) using a MOS transistor capable of continuously changing a resistance value and a resistance element (413, 414) having a fixed resistance value. create. The variable resistor (41) is used as the resistance of the input section of the inverting amplifier circuit by the operational amplifier (23), the resistance of the negative feedback section, or the resistance of both the input section and the negative feedback section. In addition, an AGC circuit and an RF receiver are configured using the inverting amplifier circuit (40).
[Selection] Figure 5

Description

  The present invention relates to an amplifier circuit, an AGC (Automatic Gain Control) circuit, and an RF receiver. Specifically, for example, the present invention relates to an amplifier circuit used in an AGC circuit that adjusts the level of a signal received by an antenna, an AGC circuit including the amplifier circuit, and an RF receiver including the AGC circuit.

  In the RF receiver, when the radio wave received by the antenna is strong or weak, the level of the received signal varies. At this time, if this signal is reproduced as it is, noise is generated in the sound and the image. In order to avoid this, an AGC circuit that adjusts the received signal to a predetermined level is used.

  The AGC circuit can be realized by an inverting amplifier circuit using an operational amplifier (hereinafter referred to as an operational amplifier). For example, a variable resistor is used in a portion where the output voltage of the operational amplifier is negatively fed back to the inverting input terminal, and the gain of the output voltage is controlled by controlling the resistance value of the variable resistor. In this AGC circuit, the gain is controlled by changing the resistance value of the variable resistor in accordance with the voltage level of the received signal, and a signal having a voltage level suitable for the subsequent processing circuit is output.

  The variable resistor can be realized, for example, by operating an NMOS transistor or a PMOS transistor in a linear region. The resistance between the source and the drain is controlled by applying a control voltage to the gate and controlling the control voltage according to the voltage level of the received signal.

  However, when the voltage level of the received signal varies, the current flowing between the source and drain of the NMOS transistor or PMOS transistor varies. Along with this, the resistance between the source and the drain varies. For this reason, when an NMOS transistor or a PMOS transistor is used in the negative feedback portion of the inverting amplifier circuit, output distortion occurs in an AGC circuit that requires a wide dynamic range and gain control.

  Further, an inverting amplifier circuit using a resistor bank as a resistance of a signal input portion or a negative feedback portion is known (see, for example, paragraphs [0049] to [0051] of FIG. 5 and FIG. 5). In this inverting amplifier circuit, a resistor bank is configured using a plurality of resistors having different resistance values, and a resistor corresponding to the gain is selected by a switch. For example, an NMOS transistor or a PMOS transistor is used as the switch.

However, if a resistor bank is used, the gain cannot be changed continuously. For this reason, in order to enable a wide dynamic range and gain control, it is necessary to increase the number of resistors constituting the resistor bank. At this time, the sources or drains of a number of NMOS transistors and PMOS transistors are connected to the inverting input terminal of the operational amplifier. Therefore, a capacitor having a large capacity is connected to the inverting input terminal of the operational amplifier, which is equivalent to applying a low-pass filter to the input voltage. For this reason, the inverting amplifier circuit using a resistor bank is not suitable as an AGC circuit for high-frequency signals.
JP-A-10-336547

  As described above, when a variable resistor using an NMOS transistor or a PMOS transistor is used for the negative feedback portion of the inverting amplifier circuit, output distortion occurs in an AGC circuit that requires a wide dynamic range and gain control.

  An inverting amplifier circuit using a resistor bank as the resistance of the negative feedback portion is equivalent to applying a low-pass filter to the input voltage. For this reason, the high frequency component of the input signal is attenuated.

  From the above, there is a demand for an amplifier circuit that has a wide gain control range and can be applied to high-frequency signals, an AGC circuit that includes the amplifier circuit, and an RF receiver that includes the AGC circuit.

  In order to achieve the above object, an amplifier circuit according to the present invention includes a first input terminal connected to a reference potential, an output terminal connected to an external output terminal, and a first input connected to the external input terminal. A variable element including a resistance element, a second resistance element connected to the external output terminal, a variable resistance element whose resistance is controlled by a control signal, and a fixed resistance element whose resistance is fixed And the variable resistance portion is connected to the first resistance element and the second resistance element.

  Preferably, in the amplifying circuit of the present invention, the variable resistor section includes an input node connected to the first resistor element, an output node connected to the second resistor element, and a reference potential node connected to the first resistor element of the amplifier. 2 input terminals.

  In the amplifier circuit of the present invention, the first input terminal is connected to the reference potential, and the first output terminal and the second output terminal are connected to the first external output terminal and the second external output terminal, respectively. A fully differential amplifier, a first resistance element connected to a first external input terminal, a second resistance element connected to the first external output terminal, and the first resistance element, The same size as the third resistance element connected to the second external input terminal and the same size as the second resistance element, and connected to the second external output terminal Including a fourth resistance element, a variable resistance element whose resistance is controlled by a control signal, and a fixed resistance element whose resistance is fixed, and two variable resistance portions having the same configuration, And one of the variable resistance portions includes the first resistance element and the second resistance element. It is continued, one of the variable resistor is connected to said third resistance element and the fourth resistor element.

  Preferably, in the amplifier circuit according to the present invention, one of the variable resistor units includes an input node of the variable resistor unit connected to the first resistor element, and an output node of the variable resistor unit is the second resistor. And the reference potential node of the variable resistance unit is connected to the second input terminal of the amplifier. One of the variable resistance units is configured such that the input node of the variable resistance unit is connected to the third resistance element. Connected, the output node of the variable resistance section is connected to the fourth resistance element, and the reference potential node of the variable resistance section is connected to the third input terminal of the amplifier.

  Preferably, in the amplifier circuit according to the present invention, the variable resistance unit includes the fixed resistance element connected between the input node and the output node, and the output node and the reference potential node between the input node and the reference potential node. When two or more fixed resistance elements are included between reference potential nodes, the variable resistance elements are connected between a connection node between the fixed resistance elements and the reference potential node.

  Preferably, in the amplifier circuit according to the present invention, the variable resistance element is a field effect transistor, the control signal is input to a gate of the field effect transistor, and the source of the field effect transistor is set according to the voltage of the control signal. And the resistance between the drain and the drain is controlled.

  The AGC circuit of the present invention is an AGC circuit that adjusts a signal input to the external input terminal to a predetermined level and outputs the signal from the external output terminal, and the first input terminal is connected to a reference potential, The amplifier whose terminal is connected to the external output terminal, the first resistance element connected to the external input terminal, the second resistance element connected to the external output terminal, and the magnitude of the resistance by the control signal A variable resistance element including a variable resistance element whose resistance is controlled, a fixed resistance element whose resistance is fixed, and a control section that generates the control signal, wherein the variable resistance section includes the first resistance element. And the second resistance element.

  Preferably, in the AGC circuit according to the present invention, the variable resistor section has an input node connected to the first resistor element, an output node connected to the second resistor element, and a reference potential node connected to the first resistor element of the amplifier. 2 input terminals.

  In the AGC circuit of the present invention, the differential signal input to the first external input terminal and the second external input terminal is adjusted to a predetermined level, and the first external output terminal and the second external output terminal are adjusted. AGC circuit for outputting a differential signal from the first input terminal, the first input terminal is connected to a reference potential, the first output terminal and the second output terminal are the first external output terminal and the second output terminal, respectively. A fully differential amplifier connected to an external output terminal; a first resistance element connected to the first external input terminal; a second resistance element connected to the first external output terminal; A third resistance element connected to the second external input terminal and having the same size as the first resistance element, and the same size as the second resistance element; The resistance of the fourth resistance element connected to the external output terminal 2 and the control signal. A variable resistance element, a fixed resistance element having a fixed resistance, and two variable resistance sections having the same configuration, and a control section that generates the control signal, and the variable resistance section One of the parts is connected to the first resistance element and the second resistance element, and one of the variable resistance parts is connected to the third resistance element and the fourth resistance element.

  Preferably, in the AGC circuit of the present invention, one of the variable resistor units includes an input node of the variable resistor unit connected to the first resistor element, and an output node of the variable resistor unit is the second resistor. And the reference potential node of the variable resistance unit is connected to the second input terminal of the amplifier. One of the variable resistance units is configured such that the input node of the variable resistance unit is connected to the third resistance element. Connected, the output node of the variable resistance section is connected to the fourth resistance element, and the reference potential node of the variable resistance section is connected to the third input terminal of the amplifier.

  Preferably, in the AGC circuit of the present invention, in the variable resistance unit, the fixed resistance element is connected between the input node and the output node, and between the input node and the reference potential node, the output node and the When two or more fixed resistance elements are included between reference potential nodes, the variable resistance elements are connected between a connection node between the fixed resistance elements and the reference potential node.

  Preferably, in the AGC circuit of the present invention, the variable resistance element is a field effect transistor, and the control signal is input to a gate of the field effect transistor, and the source of the field effect transistor is set according to the voltage of the control signal. And the resistance between the drain and the drain is controlled.

  The RF receiver of the present invention is an RF receiver used for receiving a radio signal, and an amplifier having a first input terminal connected to a reference potential and an output terminal connected to an external output terminal. A first resistance element connected to the external input terminal, a second resistance element connected to the external output terminal, a variable resistance element whose magnitude is controlled by a control signal, and a magnitude of the resistance Including a variable resistance section including a fixed resistance element to which the first and second resistance elements are fixed, and a control section that generates the control signal. The variable resistance section is connected to the first resistance element and the second resistance element. An AGC circuit is included, and the AGC circuit adjusts a signal input to the external input terminal to a predetermined level and outputs the signal from the external output terminal.

  Preferably, in the RF receiver according to the present invention, the variable resistor unit includes an input node connected to the first resistor element, an output node connected to the second resistor element, and a reference potential node connected to the amplifier. Connected to the second input terminal.

  The RF receiver of the present invention is an RF receiver used for receiving a radio signal, wherein the first input terminal is connected to a reference potential, and the first output terminal and the second output terminal are connected to each other. A fully differential amplifier connected to each of the first external output terminal and the second external output terminal, a first resistance element connected to the first external input terminal, and the first external output terminal The second resistance element to be connected and the same size as the first resistance element, the third resistance element connected to the second external input terminal, and the same as the second resistance element A fourth resistance element connected to the second external output terminal, a variable resistance element whose resistance is controlled by a control signal, and a fixed resistance whose magnitude is fixed Two variable resistance parts having the same configuration, including a resistance element, and the control signal One of the variable resistor units is connected to the first resistor element and the second resistor element, and one of the variable resistor units is connected to the third resistor element and the second resistor element. The AGC circuit connected to the four resistance elements, the AGC circuit adjusts a differential signal input to the first external input terminal and the second external input terminal to a predetermined level, and A differential signal is output from the first external output terminal and the second external output terminal.

  Preferably, in the RF receiver of the present invention, one of the variable resistor units includes an input node of the variable resistor unit connected to the first resistor element, and an output node of the variable resistor unit of the second resistor unit. Connected to a resistance element, a reference potential node of the variable resistance section is connected to a second input terminal of the amplifier, and one of the variable resistance sections is configured such that an input node of the variable resistance section is the third resistance element. , The output node of the variable resistance unit is connected to the fourth resistance element, and the reference potential node of the variable resistance unit is connected to the third input terminal of the amplifier.

  Preferably, in the RF receiver according to the present invention, the variable resistance unit includes the fixed resistance element connected between the input node and the output node, and the output node between the input node and the reference potential node. The variable resistance element is connected between the reference potential nodes and between the connection node between the fixed resistance elements and the reference potential node when two or more fixed resistance elements are included.

  Preferably, in the RF receiver according to the present invention, the variable resistance unit includes the fixed resistance element connected between the input node and the output node, and the output node between the input node and the reference potential node. The variable resistance element is connected between the reference potential nodes and between the connection node between the fixed resistance elements and the reference potential node when two or more fixed resistance elements are included.

  As described above, according to the present invention, an amplifier circuit that has a wide gain control range and can be applied to a high-frequency signal, an AGC circuit including the amplifier circuit, and an RF receiver including the AGC circuit are realized. be able to.

  FIG. 1 is a block diagram illustrating an example of an RF receiver. The RF receiver 10 includes an antenna 100, an LNA (low noise amplifier) 101, an RF BPF (RF bandpass filter) 102, an RF AGC 103, a mixer 104, a frequency divider circuit 105, and a VCO (voltage control oscillator). ) 106, IF BPF (IF band-pass filter) 107, IF AGC 108, and A-D converter 109.

  The RF receiver 10 is an example of an RF receiver using a so-called low IF conversion method in which an intermediate frequency (hereinafter referred to as IF) is considerably lower than the reception frequency. In the low IF conversion method, since the disturbance due to the image signal is deteriorated, the IF signal of the I axis and the Q axis is usually formed, and the image signal is removed by using an image removal method such as a Hartley method.

  Specifically, the RF signal is received by the antenna 100, and the amplitude of the signal is increased by the LNA 101. The frequency of the RF signal is, for example, 401 to 887 MHz. After a predetermined bandwidth (band) is selected by the RF BPF 102, the signal amplitude is increased by the RF AGC 103.

  The VCO 106 outputs an oscillation signal having a predetermined frequency, and this oscillation signal is supplied to the frequency dividing circuit 105 and is divided into frequency-divided signals having a half frequency and orthogonal to each other as a local oscillation signal. It is supplied to the mixer 104. Based on this local oscillation signal, the mixer 104 forms an I-axis and Q-axis IF signal having a phase difference of 90 °. The frequency of the IF signal is, for example, 1 MHz to 7 MHz.

  The IF signal is converted into a digital signal by the AD converter 109 after a predetermined bandwidth (channel) is selected by the IF BPF 107 and gain control is performed by the IF AGC 108.

  The RF receiver 10 is an example of the RF receiver of the present invention.

  Hereinafter, an example of the configuration of an AGC circuit suitable for the IF AGC 108 will be described.

  FIG. 2 is a circuit diagram showing an example of the configuration of the amplifier circuit according to the first embodiment of the present invention. The amplifier circuit 20 includes a variable resistance unit 21, a resistor 22, an operational amplifier 23, and a resistor 24.

The variable resistance unit 21 includes an NMOS transistor 210, an NMOS transistor 211, a resistor 212, and a resistor 213. The NMOS transistor 210 and the resistor 212 are connected in series, and this series circuit is connected between the node N1 and the node N2. The NMOS transistor 211 and the resistor 213 are connected in series, and this series circuit is also connected between the node N1 and the node N2. A control voltage Vc1 and a control voltage Vc2 are input to the gates of the NMOS transistor 210 and the NMOS transistor 211, respectively. The resistance values of the resistor 212 and the resistor 213 are R ₃ and R ₄ , respectively.

The resistor 22 is connected between the external input terminal T1 and the node N1. The input voltage Vin is input from the external input terminal T1. The resistance of the resistor 22 is _{R 1.}

  The operational amplifier 23 has an output terminal 233 connected to the node N2. An external output terminal T2 is also connected to the node N2, and the voltage of the output terminal 233 of the operational amplifier 23 is output from the external output terminal T2 as the output voltage Vout. In the operational amplifier 23, the inverting input terminal 230 is connected to the node N1, and the non-inverting input terminal 231 is connected to the ground potential Gnd.

Resistor 24 is connected between nodes N1 and N2. Therefore, the resistor 24 and the variable resistance unit 21 are connected in parallel between the node N1 and the node N2. The resistance value of the resistor 24 is _{R 2.}

  The amplifier circuit 20 is an inverting amplifier circuit that negatively feeds back the voltage of the output terminal 233 of the operational amplifier 23 to the inverting input terminal 230 of the operational amplifier 23 via the variable resistor portion 21 and the resistor 24.

  FIG. 3 is a block diagram showing an example of the configuration of the AGC circuit according to the first embodiment of the present invention. The AGC circuit 30 includes an amplifier circuit 20 and a control unit 31. 2 and 3 indicate the same components. The control unit 31 generates the control voltage Vc1 and the control voltage Vc2, and controls the gain of the amplifier circuit 20.

4A and 4B are diagrams illustrating changes in the combined resistance value of the negative feedback portion of the amplifier circuit. FIG. 4A (a) shows a case where both the control voltage Vc1 and the control voltage Vc2 are at a low level (for example, the ground potential Gnd). At this time, both the NMOS transistor 210 and the NMOS transistor 211 are completely off, and their resistance values can be regarded as infinite. For this reason, the combined resistance value R of the negative feedback section is equal to the resistance value R ₂ of the resistor 24.

FIG. 4A (b) shows a case where the control voltage Vc1 is slightly higher than the low level and the control voltage Vc2 is at the low level. At this time, not a NMOS transistor 210 is turned off, the resistance value _{r 3} is very large, and very large combined resistance value of the resistance _{R 3} of the resistance value _{r 3} and the resistor 212 of the NMOS transistor 210. On the other hand, the NMOS transistor 211 is completely off and its resistance value can be regarded as infinite. For this reason, the combined resistance value R of the negative feedback section is substantially equal to the resistance value R ₂ of the resistor 24.

FIG. 4A (c) shows a case where the control voltage Vc1 is an intermediate voltage between the low level and the high level, and the control voltage Vc2 is at the low level. At this time, the NMOS transistor 210 is in an intermediate state between on and off, and its resistance value r ₃ is substantially equal to the resistance value R ₃ of the resistor 212. On the other hand, the NMOS transistor 211 is completely off and its resistance value can be regarded as infinite. For this reason, the negative feedback part of the amplifier circuit 20 can be regarded as the resistor 24 and the series circuit of the NMOS transistor 210 and the resistor 212 being connected in parallel.

FIG. 4A (d) shows a case where the control voltage Vc1 is at a high level (for example, the power supply potential Vdd) and the control voltage Vc2 is at a low level. At this time, the NMOS transistor 210 is completely on, and its resistance value r ₃ can be regarded as zero. On the other hand, the NMOS transistor 211 is completely off and its resistance value can be regarded as infinite. For this reason, the negative feedback part of the amplifier circuit 20 can be regarded as a circuit in which the resistor 24 and the resistor 212 are connected in parallel.

FIG. 4B (e) shows the case where the control voltage Vc1 is at a high level and the control voltage Vc2 is slightly higher than the low level. At this time, the NMOS transistor 210 is completely on, and its resistance value r ₃ can be regarded as zero. On the other hand, it is not a NMOS transistor 211 is turned off, the resistance value _{r 4} is quite large, very larger combined resistance value of the resistance _{R 4} of the resistance value _{r 4} and the resistor 213 of the NMOS transistor 211. For this reason, the negative feedback part of the amplifier circuit 20 can be considered that the resistor 24 and the resistor 212 are connected in parallel.

FIG. 4B (f) shows a case where the control voltage Vc1 is at a high level and the control voltage Vc2 is an intermediate voltage between the low level and the high level. At this time, the NMOS transistor 210 is completely on, and its resistance value r ₃ can be regarded as zero. On the other hand, the NMOS transistor 211 is in an intermediate state between on and off, and its resistance value r ₄ is substantially equal to the resistance value R ₄ of the resistor 213. For this reason, the negative feedback section of the amplifier circuit 20 can be regarded as the resistor 24, the resistor 212, and the series circuit of the NMOS transistor 211 and the resistor 213 being connected in parallel.

FIG. 4B (g) shows a case where both the control voltage Vc1 and the control voltage Vc2 are at a high level. At this time, the NMOS transistor 210 and the NMOS transistor 211 are completely on, and the resistance value r ₃ and the resistance value r ₄ can be regarded as zero. For this reason, the negative feedback part of the amplifier circuit 20 can be regarded as the resistor 24, the resistor 212, and the resistor 213 being connected in parallel.

  As described above, unlike the variable resistor using the conventional resistor bank, the combined resistance value of the negative feedback portion of the amplifier circuit 20 can be continuously changed.

Further, as shown in FIG. 4A (b), when the control voltage Vc1 is a voltage slightly higher than the low level, the resistance value r ₃ of the NMOS transistor 210 affect the combined resistance value of the negative feedback of the amplifier circuit 20 Does not affect. Resistance r ₄ of the same NMOS transistor 211 when the control voltage Vc2 is a voltage slightly higher than the low level does not affect the combined resistance value of the negative feedback of the amplifier circuit 20. Therefore, when the control voltage Vc1 and the control voltage Vc2 are small and the resistance value between the source and drain of the NMOS transistor 210 and the NMOS transistor 211 is extremely high, the NMOS transistor 210 and the NMOS transistor 211 affect the output distortion of the AGC circuit 30. Absent.

Further, as shown in FIG. 4A (c), when the control voltage Vc1 is an intermediate voltage between the low level and the high level, the combined resistance value of the circuit in which the NMOS transistor 210 and the resistor 212 are connected in series is r _3. a + _{R 3.} As the input voltage Vin varies, the resistance value r ₃ of the NMOS transistor 210 varies. However, the variation of the resistance value r ₃ of the NMOS transistor 210 is equivalent to that of the AGC circuit 30 as much as the resistance value R ₃ of the resistor 212 is added. The effect on output distortion is reduced. Similarly, the control voltage Vc2 is when an intermediate voltage of low level and the high level, also decreases the influence of variation in the resistance value r ₄ of the NMOS transistor 211 has on the output distortion of the AGC circuit 30.

  Therefore, the AGC circuit 30 has the problem of output distortion reduced as compared with the conventional AGC circuit using a variable resistor composed of a single NMOS transistor or PMOS transistor.

  In the above description, the number of pairs of NMOS transistors and resistors in the variable resistance unit 21 is two, but the number of pairs of NMOS transistors and resistors is not limited to this, and may be any number. Further, a PMOS transistor can be used instead of the NMOS transistor.

  The control unit 31 in the AGC circuit 30 shown in FIG. 3 is provided with a gain table that stores the relationship between the control voltage Vc1, the control voltage Vc2, and the gain of the amplifier circuit 20. When the gain of the amplifier circuit 20 is determined by a circuit (not shown) according to the level of the input voltage Vin input to the external input terminal T1, the control unit 31 refers to this gain table and controls the control voltage Vc1 and the control voltage Vc2. And the control voltage Vc1 and the control voltage Vc2 are supplied to the amplifier circuit 20. As a result, the gain of the amplifier circuit 20 is controlled, and the output voltage Vout at a level suitable for the subsequent processing circuit is output from the external output terminal T2.

  The operational amplifier 23 is an example of the amplifier of the present invention, the non-inverting input terminal 231 of the operational amplifier 23 is an example of the first input terminal of the present invention, and the output terminal 233 of the operational amplifier 23 is an example of the output terminal of the present invention. The external input terminal T1 is an example of the external input terminal of the present invention, the ground potential Gnd is an example of the reference potential of the present invention, the external output terminal T2 is an example of the external output terminal of the present invention, and the resistance 22 is an example of the first resistance element of the present invention, the resistor 24 is an example of the second resistance element of the present invention, the variable resistance section 21 is an example of the variable resistance section of the present invention, and the NMOS transistor 210 And the NMOS transistor 211 are examples of the variable resistance element and the field effect transistor of the present invention, the resistors 212 and 213 are examples of the fixed resistance element of the present invention, and the control voltage Vc1 The control voltage Vc2 is an example of the control signal of the present invention, the control unit 31 is an example of the control unit of the present invention, the amplifier circuit 20 is an example of the amplifier circuit of the present invention, and the AGC circuit 30 is the AGC circuit of the present invention. It is an example of a circuit.

  FIG. 5 is a circuit diagram showing an example of the configuration of an amplifier circuit according to the second embodiment of the present invention. The amplifier circuit 40 includes a resistor 22, a variable resistor 41, a resistor 24, and an operational amplifier 23. 2 and 5 indicate the same components. In the present embodiment, the variable resistor portion 21 of the first embodiment is replaced with a variable resistor portion 41, and in the first embodiment, the variable resistor portion 21 is connected in parallel with the resistor 24, whereas the present embodiment However, the variable resistor 41 is different in that it is connected in series between the resistor 22 and the resistor 24. The configurations of the resistor 22, the resistor 24, and the operational amplifier 23 are common to the amplifier circuit 40 of the present embodiment and the amplifier circuit 20 of the first embodiment.

The variable resistance unit 41 includes an NMOS transistor 410, an NMOS transistor 411, an NMOS transistor 412, a resistor 413, and a resistor 414. The resistor 413 and the resistor 414 are connected in series, and a series circuit including the resistor 413 and the resistor 414 is connected between the node N1 and the node N4. An NMOS transistor 410 is connected between the node N1 and a node N5 to which the inverting input terminal 230 of the operational amplifier 23 is connected. An NMOS transistor 411 is connected between the connection node N3 and the node N5 between the resistor 413 and the resistor 414, and an NMOS transistor 412 is connected between the node N4 and the node N5. Control voltage Vc3, control voltage Vc4, and control voltage Vc5 are input to the gates of NMOS transistor 410, NMOS transistor 411, and NMOS transistor 412, respectively. The resistance values of the resistors 413 and 414 are R ₅ and R ₆ , respectively.

  In the amplifier circuit 20 of the first embodiment, the inverting input terminal 230 of the operational amplifier 23 is connected to the node N1, and one end of the variable resistance unit 21, one end of the resistor 22, and one end of the resistor 24 are further connected to the node N1. However, in the amplifier circuit 40 of the present embodiment, the inverting input terminal 230 of the operational amplifier 23 is connected to the node N5, and only one end of the variable resistance unit 41 and one end of the resistor 22 are connected to the node N1.

  FIG. 6 is a block diagram showing an example of the configuration of the AGC circuit according to the second embodiment of the present invention. The AGC circuit 50 includes an amplifier circuit 40 and a control unit 51. 5 and 6 indicate the same components. The control unit 51 generates the control voltage Vc3, the control voltage Vc4, and the control voltage Vc5, and controls the gain of the amplifier circuit 40.

FIG. 7 is a diagram for explaining a change in the combined resistance value of the negative feedback portion of the amplifier circuit. FIG. 7A shows a case where the control voltage Vc3, the control voltage Vc4, and the control voltage Vc5 are all at a high level. At this time, the NMOS transistor 410, the NMOS transistor 411, and the NMOS transistor 412 are all turned on, and their resistance values can be regarded as zero. Therefore, the potentials of the nodes N1, N3, and N4 can be regarded as being equal to the potential of the node N5. On the other hand, the node N5 is connected to the inverting input terminal 230 of the operational amplifier 23, and the non-inverting input terminal 231 of the operational amplifier 23 is connected to the ground potential Gnd. That is, the nodes N1, N3, and N4 are all considered to be connected to the inverting input terminal 230 of the operational amplifier 23, and the potentials of the nodes N1, N3, and N4 are the same and equal to the ground potential Gnd. It can be considered. Therefore, as indicated by the arrows, current flows through the NMOS transistor 410 and the NMOS transistor 412, and no current flows through the resistor 413, the resistor 414, and the MOS transistor 411. For this reason, the resistance value R of the negative feedback part of the amplifier circuit 40 is equal to the resistance value R ₂ of the resistor 24.

FIG. 7B shows a case where the control voltage Vc3 and the control voltage Vc4 are at a high level, and the control voltage Vc5 is an intermediate voltage between the low level and the high level. At this time, the NMOS transistor 410 and the NMOS transistor 411 are completely on and their resistance values can be regarded as zero. Therefore, it can be considered that the node N1 and the node N3 are connected to the inverting input terminal 230 of the operational amplifier 23. On the other hand, the NMOS transistor 412 is in an intermediate state between on and off, and the resistance value R ₆ of the resistor 414 and the resistance value r ₆ of the NMOS transistor 412 are substantially equal. At this time, since a current flows between the source and drain of the NMOS transistor 412, a potential is generated at the node N4, and the potentials of the node N3 and the node N4 are different. For this reason, a current flows through the resistor 414 as indicated by an arrow. Therefore, the negative feedback portion of the amplifier circuit 40 can be regarded as a resistor 414 and an NMOS transistor 412 connected in parallel and a resistor 24 connected in series.

FIG. 7C shows a case where the control voltage Vc3 and the control voltage Vc4 are at a high level and the control voltage Vc5 is at a low level. At this time, it can be considered that the NMOS transistor 410 and the NMOS transistor 411 are completely on, and the node N1 and the node N3 are connected to the inverting input terminal 230 of the operational amplifier 23. On the other hand, NMOS transistor 412 is a completely off, the resistance value _{r 6} of the NMOS transistor 412 can be regarded as infinite. At this time, as indicated by an arrow, a current flows through the NMOS transistor 410, the NMOS transistor 411, and the resistor 414, and no current flows through the resistor 413 and the NMOS transistor 412. For this reason, the negative feedback part of the amplifier circuit 40 can be regarded as the resistor 414 and the resistor 24 being connected in series.

  FIG. 7D shows a case where the control voltage Vc3 is at a high level and the control voltage Vc4 and the control voltage Vc5 are at a low level. At this time, it can be considered that the NMOS transistor 410 is completely on and the node N1 is connected to the inverting input terminal 230 of the operational amplifier 23. On the other hand, the NMOS transistor 411 and the NMOS transistor 412 are completely off, and the resistance values of the NMOS transistor 411 and the NMOS transistor 412 can be regarded as infinite. At this time, currents flowing through the resistors 413 and 414 flow as indicated by arrows, and no current flows through the NMOS transistor 410, the NMOS transistor 411, and the NMOS transistor 412. For this reason, the negative feedback part of the amplifier circuit 40 can be regarded as the resistor 413, the resistor 414, and the resistor 24 being connected in series.

FIG. 8 is a diagram illustrating an example of a change in gain of the amplifier circuit. As described above, when the control voltage Vc3 and the control voltage Vc4 and the control voltage Vc5 is all high level (FIG. 7 (a)), the combined resistance value of the negative feedback of the amplifier circuit 40 is R _2. At this time, the gain of the amplifier circuit 40 is R ₂ / R ₁ .

When the control voltage Vc5 is gradually decreased, the gain gradually increases. When the control voltage Vc3 and the control voltage Vc4 are at the high level and the control voltage Vc5 is at the low level (FIG. 7C), the combined resistance value of the negative feedback section of the amplifier circuit 40 is R ₆ + R ₂ . At this time, the gain of the amplifier circuit 40 is (R ₆ + R ₂ ) / R ₁ .

When the control voltage Vc4 is gradually decreased, the gain further increases. When the control voltage Vc3 is at a high level and the control voltage Vc4 and the control voltage Vc5 are at a low level (FIG. 7D), the combined resistance value of the negative feedback portion of the amplifier circuit 40 is R ₅ + R ₆ + R ₂ . . At this time, the gain of the amplifier circuit 40 is (R ₅ + R ₆ + R ₂ ) / R ₁ .

FIG. 9 is a diagram for explaining a change in the combined resistance value of the input section of the amplifier circuit. FIG. 9A shows the case where the control voltage Vc3, the control voltage Vc4, and the control voltage Vc5 are all at the high level, as in FIG. 7A. At this time, the resistance value R ′ of the input part of the amplifier circuit 40 is equal to the resistance value R ₁ of the resistor 22.

  FIG. 9B shows a case where the control voltage Vc3 is at a low level and the control voltage Vc4 and the control voltage Vc5 are at a high level. At this time, the NMOS transistor 410 is completely off, and the resistance value of the NMOS transistor 410 can be regarded as infinite. On the other hand, it can be considered that the NMOS transistor 411 and the NMOS transistor 412 are completely on, and the node N3 and the node N4 are connected to the inverting input terminal 230 of the operational amplifier 23. At this time, current flows through the resistor 413, the NMOS transistor 411, and the NMOS transistor 412, and no current flows through the resistor 414 and the NMOS transistor 410. For this reason, the input part of the amplifier circuit 40 can be considered that the resistor 22 and the resistor 413 are connected in series.

  FIG. 9C shows a case where the control voltage Vc3 and the control voltage Vc4 are at a low level and the control voltage Vc5 is at a high level. At this time, the NMOS transistor 410 and the NMOS transistor 411 are completely off, and the resistance values of the NMOS transistor 410 and the NMOS transistor 411 can be regarded as infinite. On the other hand, it can be considered that the NMOS transistor 412 is completely on and the node N4 is connected to the inverting input terminal 230 of the operational amplifier 23. At this time, currents flowing through the resistors 413 and 414 flow as indicated by arrows, and no current flows through the NMOS transistor 410, the NMOS transistor 411, and the NMOS transistor 412. For this reason, it can be considered that the input part of the amplifier circuit 40 has the resistor 22, the resistor 413, and the resistor 414 connected in series.

FIG. 10 is a diagram illustrating different examples of changes in the gain of the amplifier circuit. As described above, when the control voltage Vc3 and the control voltage Vc4 and the control voltage Vc5 is all high level (FIG. 9 (a)), the combined resistance value of the input section of the amplifier circuit 40 is _{R 1.} At this time, the gain of the amplifier circuit 40 is R ₂ / R ₁ .

When the control voltage Vc3 is gradually decreased, the gain is gradually decreased. When the control voltage Vc3 is at a low level and the control voltage Vc4 and the control voltage Vc5 are at a high level (FIG. 9B), the combined resistance value of the input part of the amplifier circuit 40 is R ₁ + R ₅ . At this time, the gain of the amplifier circuit 40 is R ₂ / (R ₁ + R ₅ ).

When the control voltage Vc4 is gradually lowered, the gain further decreases. When the control voltage Vc3 and the control voltage Vc4 are at the low level and the control voltage Vc5 is at the high level (FIG. 9C), the combined resistance value of the input part of the amplifier circuit 40 is R ₁ + R ₅ + R ₆ . At this time, the gain of the amplifier circuit 40 is R ₂ / (R ₁ + R ₅ + R ₆ ).

FIG. 11 is a diagram illustrating still another example of a change in gain of the amplifier circuit. When the control voltage Vc3 and the control voltage Vc4 are at a low level and the control voltage Vc5 is at a high level, as shown in FIG. 9C, the combined resistance value of the input part of the amplifier circuit 40 is R ₁ + R ₅ + R _6. It is. On the other hand, the resistance value of the negative feedback section is R _2. At this time, the gain of the amplifier circuit 40 is R ₂ / (R ₁ + R ₅ + R ₆ ).

When the control voltage Vc4 is gradually increased and the control voltage Vc5 is gradually decreased while keeping the control voltage Vc3 at the low level, the gain of the amplifier circuit 40 gradually increases. When the control voltage Vc3 and the control voltage Vc5 are at low level and the control voltage Vc4 is at high level, the combined resistance value of the input part of the amplifier circuit 40 is R ₁ + R ₅ and the combined resistance value of the negative feedback part is R ₆ + R ₂ . At this time, the gain of the amplifier circuit 40 is (R ₆ + R ₂ ) / (R ₁ + R ₅ ).

When the control voltage Vc3 is gradually increased and the control voltage Vc4 is gradually decreased while keeping the control voltage Vc5 at the low level, the gain of the amplifier circuit 40 further increases. When the control voltage Vc3 is at a high level and the control voltage Vc4 and the control voltage Vc5 are at a low level, the combined resistance value of the negative feedback section of the amplifier circuit 40 is R ₅ + R ₆ + R as shown in FIG. ₂ . On the other hand, the resistance value of the input unit is R _1. At this time, the gain of the amplifier circuit 40 is (R ₅ + R ₆ + R ₂ ) / R ₁ .

  The relationship between the control voltage Vc3, the control voltage Vc4, the control voltage Vc5, and the gain of the amplifier circuit 40 is shown in Table 1 below.

  Here, H and L mean a high level and a low level, respectively.

  As described above, in the present embodiment, the combined resistance value of the negative feedback unit of the amplifier circuit 40 can be continuously changed by the variable resistor unit 41 as in the first embodiment. Furthermore, in the present embodiment, unlike the first embodiment, the combined resistance value of the input unit of the amplifier circuit 40 can be continuously changed by the variable resistor unit 41.

  Similarly to the first embodiment, when the control voltage Vc3, the control voltage Vc4, or the control voltage Vc5 is an intermediate voltage between the low level and the high level, the NMOS transistor 410, the NMOS transistor 411, or the NMOS transistor 412 The influence of the variation in the resistance value on the output distortion of the AGC circuit 50 is also reduced. For this reason, the AGC circuit 50 reduces the problem of output distortion as compared with the conventional AGC circuit using a variable resistor composed of a single NMOS transistor or PMOS transistor.

  In the above description, the variable resistance unit 41 is configured with three NMOS transistors and two resistors. However, the number of NMOS transistors and resistors is not limited to this, and the number of NMOS transistors is one more than the number of resistors. It can be any number under the conditions. Further, a PMOS transistor can be used instead of the NMOS transistor.

  The control unit 51 in the AGC circuit 50 is provided with a gain table that stores the relationship between the control voltage Vc3, the control voltage Vc4, the control voltage Vc5, and the gain of the amplifier circuit 40. When the gain of the amplifier circuit 40 is determined by a circuit (not shown) according to the level of the input voltage Vin input to the external input terminal T1, the control unit 51 refers to this gain table and the control voltage Vc3 and the control voltage Vc4. And the control voltage Vc5 is determined, and the control voltage Vc3, the control voltage Vc4, and the control voltage Vc5 are supplied to the amplifier circuit 40. As a result, the gain of the amplifier circuit 40 is controlled, and the output voltage Vout at a level suitable for the subsequent processing circuit is output from the external output terminal T2.

  Note that the node N1 is an example of the input node of the present invention, the node N3 is an example of a connection node between the fixed resistance elements of the present invention, the node N4 is an example of the output node of the present invention, and the node N5 is the present node. It is an example of the reference potential node of the present invention, the inverting input terminal 230 of the operational amplifier 23 is an example of the second input terminal of the amplifier of the present invention, and the NMOS transistor 410, the NMOS transistor 411, and the NMOS transistor 412 are the variable resistors of the present invention. The resistor 413 and the resistor 414 are examples of the fixed resistor element of the present invention, the variable resistor unit 41 is an example of the variable resistor unit of the present invention, and the control voltage Vc3 and the control voltage Vc4. And the control voltage Vc5 are examples of the control signal of the present invention, the control unit 51 is an example of the control unit of the present invention, and the amplifier circuit 40 is Is an example of an amplifier circuit of the light, the AGC circuit 50 is an example of the AGC circuit of the present invention.

  FIG. 12 is a circuit diagram showing an example of the configuration of an amplifier circuit according to the third embodiment of the present invention. The differential amplifier circuit 40D includes an amplifier circuit 40A, an amplifier circuit 40B, and a fully differential operational amplifier 23D. 5 and 12 denote the same components. The fully-differential operational amplifier 23D operates using the ground potential Gnd connected to the input terminal 231D as a common reference potential, and a differential signal is input from the input terminal 230A and the input terminal 230B, and the difference is output from the output terminal 233A and the output terminal 233B. A dynamic signal is output. The amplifier circuit 40A and the amplifier circuit 40B perform the same operation as the amplifier circuit 40 of FIG. That is, the amplifier circuit 40A and the amplifier circuit 40B amplify the differential signals VinA and VinB input from the external input terminal T1A and the external input terminal T1B according to the states of the control voltage Vc3, the control voltage Vc4, and the control voltage Vc5, The differential signals VoutA and VoutB are output from the external output terminal T2A and the external output terminal T2B.

  FIG. 13 is a block diagram showing an example of the configuration of the AGC circuit according to the third embodiment of the present invention. The AGC circuit 50D includes an amplifier circuit 40D and a control unit 51. 6 and 13 indicate the same components. The AGC circuit 50D receives the differential signals VinA and VinB from the external input terminal T1A and the external input terminal T1B and replaces the external output terminal T2A and the external output by replacing the amplifier circuit 40 of FIG. 6 with the amplifier circuit 40D of FIG. In this configuration, differential signals VoutA and VoutB are output from the terminal T2B.

  In the present embodiment, the second embodiment has an operation-type circuit configuration, and has higher noise resistance than the second embodiment having a single-ended circuit configuration.

  Also, the first embodiment can be similarly configured as an operation type.

  The fully differential operational amplifier 23D is an example of the fully differential amplifier of the present invention. The input terminals 231D, 230A, and 230B of the fully differential operational amplifier 23D are the first input terminal and the second input terminal of the present invention, respectively. The output terminal 233A and the output terminal 233B of the fully differential operational amplifier 23D are examples of the first output terminal and the second output terminal of the present invention, respectively. The external input terminal T1A of the amplifier circuit 40A is an example of the first external input terminal of the present invention, the external input terminal T1B of the amplifier circuit 40B is an example of the second external input terminal of the present invention, and the amplifier circuit 40A. The external output terminal T2A is an example of the first external output terminal of the present invention, the external output terminal T2B of the amplifier circuit 40B is an example of the second external output terminal of the present invention, and the resistor 22 of the amplifier circuit 40A. The resistor 24 of the amplifier circuit 40A is an example of the second resistor element of the present invention, and the resistor 22 of the amplifier circuit 40B is an example of the third resistor element of the present invention. The resistor 24 of the amplifier circuit 40B is an example of the fourth resistor element of the present invention, the variable resistor part 41 of the amplifier circuit 40A and the amplifier circuit 40B is an example of the variable resistor part of the present invention, and the amplifier circuit 40D. Is an example of the amplifier circuit of the present invention, and the AGC circuit 50D is an example of the AGC circuit of the present invention.

  As described above, according to the first embodiment, the second embodiment, and the third embodiment of the present invention, the combined resistance value of the negative feedback section of the amplifier circuit can be continuously changed. Therefore, unlike a conventional AGC circuit using a resistor bank, a wide dynamic range and gain control can be realized even if the number of resistors is small. Therefore, the number of NMOS transistors and PMOS transistors connected to the inverting input terminal of the operational amplifier can be reduced, and the capacitance of the capacitor connected to the inverting input terminal of the operational amplifier can be reduced.

  Furthermore, according to the second embodiment and the third embodiment of the present invention, the combined resistance value of the input section of the amplifier circuit can be continuously changed.

  In addition, the AGC circuit of the first embodiment, the second embodiment, and the third embodiment of the present invention has a higher output distortion than the conventional AGC circuit that uses a variable resistor with a single NMOS transistor or PMOS transistor. The problem is reduced.

  As described above, the first embodiment, the second embodiment, and the third embodiment of the present invention have a wide gain control range and can be applied to a signal having a high frequency, and an AGC circuit using the amplifier circuit. And an RF receiver using the AGC circuit can be realized.

It is a block diagram which shows an example of RF receiver. 1 is a circuit diagram illustrating an example of a configuration of an amplifier circuit according to a first embodiment of the present invention. 1 is a block diagram illustrating an example of a configuration of an AGC circuit according to a first embodiment of the present invention. It is a figure which shows the change of the combined resistance value of the negative feedback part of an amplifier circuit. It is a figure which shows the change of the combined resistance value of the negative feedback part of an amplifier circuit. It is a circuit diagram which shows an example of a structure of the amplifier circuit which concerns on the 2nd Embodiment of this invention. It is a block diagram which shows an example of a structure of the AGC circuit which concerns on the 2nd Embodiment of this invention. It is a figure for demonstrating the change of the synthetic | combination resistance value of the negative feedback part of an amplifier circuit. It is a figure which shows an example of the change of the gain of an amplifier circuit. It is a figure for demonstrating the change of the synthetic | combination resistance value of the input part of an amplifier circuit. It is a figure which shows the example from which the change of the gain of an amplifier circuit differs. It is a figure which shows another example of the change of the gain of an amplifier circuit. It is a circuit diagram which shows an example of a structure of the amplifier circuit which concerns on the 3rd Embodiment of this invention. It is a block diagram which shows an example of a structure of the AGC circuit which concerns on the 3rd Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... RF receiver, 20, 40, 40A, 40B, 40D ... Amplifier circuit, 21, 41 ... Variable resistance part, 22, 24, 212, 213, 413, 414, ... Resistance, 210, 211, 410, 411, 412 ... NMOS transistor, 23 ... operational amplifier, 23D ... fully differential operational amplifier, 30, 50, 50D ... AGC circuit, 31, 51 ... control unit, 108 ... IF AGC

Claims (18)

An amplifier having a first input terminal connected to a reference potential and an output terminal connected to an external output terminal;
A first resistance element connected to the external input terminal;
A second resistance element connected to the external output terminal;
A variable resistance element including a variable resistance element whose resistance is controlled by a control signal and a fixed resistance element whose resistance is fixed;
An amplifying circuit in which the variable resistance section is connected to the first resistance element and the second resistance element. The variable resistance section has an input node connected to the first resistance element, an output node connected to the second resistance element, and a reference potential node connected to a second input terminal of the amplifier. The amplifier circuit according to 1. A fully-differential amplifier having a first input terminal connected to a reference potential, a first output terminal and a second output terminal connected to the first external output terminal and the second external output terminal, respectively;
A first resistance element connected to the first external input terminal;
A second resistance element connected to the first external output terminal;
A third resistive element having the same size as the first resistive element and connected to the second external input terminal;
A fourth resistor element having the same size as the second resistor element and connected to the second external output terminal;
A variable resistance element whose resistance is controlled by a control signal; and a fixed resistance element whose resistance is fixed; and two variable resistance portions having the same configuration
One of the variable resistance portions is connected to the first resistance element and the second resistance element;
An amplifier circuit in which one of the variable resistance units is connected to the third resistance element and the fourth resistance element. One of the variable resistance units has an input node of the variable resistance unit connected to the first resistance element, an output node of the variable resistance unit connected to the second resistance element, A reference potential node is connected to the second input terminal of the amplifier;
One of the variable resistor units has an input node of the variable resistor unit connected to the third resistor element, an output node of the variable resistor unit connected to the fourth resistor element, The amplifier circuit according to claim 3, wherein a reference potential node is connected to a third input terminal of the amplifier. The variable resistance unit includes the fixed resistance element connected between the input node and the output node, between the input node and the reference potential node, between the output node and the reference potential node, and the fixed resistance. The amplifier circuit according to claim 2 or 4, wherein when two or more elements are included, the variable resistance element is connected between a connection node between the fixed resistance elements and the reference potential node. The variable resistance element is a field effect transistor, and the control signal is input to the gate of the field effect transistor, and the magnitude of the resistance between the source and drain of the field effect transistor is controlled according to the voltage of the control signal. The amplifier circuit according to claim 5. An AGC circuit that adjusts a signal input to an external input terminal to a predetermined level and outputs the signal from an external output terminal,
An amplifier having a first input terminal connected to a reference potential and an output terminal connected to the external output terminal;
A first resistance element connected to the external input terminal;
A second resistance element connected to the external output terminal;
A variable resistance unit including a variable resistance element whose resistance is controlled by a control signal, and a fixed resistance element whose resistance is fixed;
A control unit for generating the control signal,
An AGC circuit in which the variable resistance section is connected to the first resistance element and the second resistance element. The variable resistance section has an input node connected to the first resistance element, an output node connected to the second resistance element, and a reference potential node connected to a second input terminal of the amplifier. 8. The AGC circuit according to 7. An AGC circuit that adjusts differential signals input to the first external input terminal and the second external input terminal to a predetermined level and outputs differential signals from the first external output terminal and the second external output terminal. Because
A fully differential amplifier having a first input terminal connected to a reference potential, a first output terminal and a second output terminal connected to the first external output terminal and the second external output terminal, respectively; ,
A first resistance element connected to the first external input terminal;
A second resistance element connected to the first external output terminal;
A third resistance element having the same size as the first resistance element and connected to the second external input terminal;
A fourth resistance element having the same size as the second resistance element and connected to the second external output terminal;
Two variable resistance units having the same configuration, including a variable resistance element whose magnitude is controlled by a control signal, and a fixed resistance element whose magnitude is fixed,
A control unit for generating the control signal,
One of the variable resistance portions is connected to the first resistance element and the second resistance element;
An AGC circuit in which one of the variable resistance units is connected to the third resistance element and the fourth resistance element. One of the variable resistance units has an input node of the variable resistance unit connected to the first resistance element, an output node of the variable resistance unit connected to the second resistance element, A reference potential node is connected to the second input terminal of the amplifier;
One of the variable resistor units has an input node of the variable resistor unit connected to the third resistor element, an output node of the variable resistor unit connected to the fourth resistor element, The AGC circuit according to claim 9, wherein a reference potential node is connected to a third input terminal of the amplifier. The variable resistance unit includes the fixed resistance element connected between the input node and the output node, between the input node and the reference potential node, between the output node and the reference potential node, and the fixed resistance. 11. The AGC circuit according to claim 8, wherein when two or more elements are included, the variable resistance element is connected between a connection node between the fixed resistance elements and the reference potential node. The variable resistance element is a field effect transistor, and the control signal is input to the gate of the field effect transistor, and the magnitude of the resistance between the source and drain of the field effect transistor is controlled according to the voltage of the control signal. The AGC circuit according to claim 11. An RF receiver used to receive a radio signal,
An amplifier having a first input terminal connected to the reference potential and an output terminal connected to the external output terminal, a first resistance element connected to the external input terminal, and a second connected to the external output terminal A resistance element; a variable resistance element whose resistance is controlled by a control signal; a variable resistance section including a fixed resistance element whose resistance is fixed; and a control section that generates the control signal. The variable resistance unit includes an AGC circuit connected to the first resistance element and the second resistance element,
An RF receiver in which the AGC circuit adjusts a signal input to the external input terminal to a predetermined level and outputs the signal from the external output terminal. The variable resistance section has an input node connected to the first resistance element, an output node connected to the second resistance element, and a reference potential node connected to a second input terminal of the amplifier. 14. An RF receiver according to item 13. An RF receiver used to receive a radio signal,
A fully-differential amplifier having a first input terminal connected to the reference potential, a first output terminal and a second output terminal connected to the first external output terminal and the second external output terminal, respectively; A first resistive element connected to one external input terminal, a second resistive element connected to the first external output terminal, and the same size as the first resistive element, A third resistance element connected to the second external input terminal, a fourth resistance element having the same size as the second resistance element and connected to the second external output terminal, and a control A variable resistance element whose magnitude is controlled by a signal and a fixed resistance element whose resistance magnitude is fixed, two variable resistance sections having the same configuration, and a control section for generating the control signal And one of the variable resistance portions includes the first resistance element and the second resistance. Is connected to the child, one of the variable resistor has an AGC circuit connected with the third resistive element and the fourth resistor element,
The AGC circuit adjusts a differential signal input to the first external input terminal and the second external input terminal to a predetermined level, and the first external output terminal and the second external output terminal RF receiver that outputs differential signals from One of the variable resistance units has an input node of the variable resistance unit connected to the first resistance element, an output node of the variable resistance unit connected to the second resistance element, A reference potential node is connected to the second input terminal of the amplifier;
One of the variable resistor units has an input node of the variable resistor unit connected to the third resistor element, an output node of the variable resistor unit connected to the fourth resistor element, The RF receiver according to claim 15, wherein a reference potential node is connected to a third input terminal of the amplifier. The variable resistance unit includes the fixed resistance element connected between the input node and the output node, between the input node and the reference potential node, between the output node and the reference potential node, and the fixed resistance. The RF receiving device according to claim 14 or 16, wherein when two or more elements are included, the variable resistance element is connected between a connection node between the fixed resistance elements and the reference potential node. The variable resistance element is a field effect transistor, and the control signal is input to the gate of the field effect transistor, and the magnitude of the resistance between the source and drain of the field effect transistor is controlled according to the voltage of the control signal. The RF receiver according to claim 17.

Images