JP2008192837A - Lead frame for semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a lead frame for a semiconductor device capable of suppressing occurrence of unevenness in a silver plating film and preventing occurrence of erroneous recognition at the time of image recognition in a manufacturing process, and a manufacturing method thereof.
SOLUTION: An inner lead portion 2 including a mounting region 2a on which a semiconductor element 23 is mounted and a bonding region 2b, an outer lead 3 extending from the inner lead portion 2, and a rail portion connecting the outer lead 3. 4, a silver plating film 15 as the outermost layer is formed as an upper layer of the palladium plating film 13 in the mounting region 2 a and the bonding region 2 b, and a gold plating film 14 as the outermost layer is formed in the outer lead 3. It is formed as an upper layer of the palladium plating film 13.
[Selection] Figure 2

Description

  The present invention relates to a lead frame for a semiconductor device having an inner lead portion, and more particularly to a lead frame for a semiconductor device in which a silver plating film is applied as a partial plating to an inner lead portion and a manufacturing method thereof.

  As a lead frame for a conventional semiconductor device, for example, a lead frame used in a semiconductor device equipped with a light emitting diode element (hereinafter referred to as LED) as a semiconductor element adopts a lead-free technology in consideration of environmental problems. In order to improve the luminous efficiency, the coating composition applied to the surface has been studied. As a lead frame used for a surface-mounted white LED that corresponds to lead-free and does not affect the brightness and whiteness of white light emission of the LED, Pd-P. P. A lead frame called F (Palladium Pre Plated Lead Frame) that is partially silver-plated has been proposed (see, for example, Patent Document 1).

  FIG. 6 is a cross-sectional view of a main part of a conventional lead frame for a semiconductor device described in Patent Document 1. In FIG.

As shown in FIG. 6, this conventional lead frame 101 has a nickel plating film 105 formed on a metal substrate 104 of a lead frame made of copper, and a palladium plating film 106 formed on the nickel plating film 105. . A gold plating film 107 is formed on the palladium plating film 106. Further, in the inner lead portion 102, a silver plating film 108 is applied to a mounting region 102a where an LED (not shown) is mounted and a bonding region 102b where wire bonding is performed between the LED and the LED. A resin envelope 121 is mounted around the inner lead portion 102.
JP 2006-66504 A

  In the conventional lead frame 101 for a semiconductor device, the silver plating film 108 is formed on the gold plating film 107 to keep the light emission color of the LED white. This is necessary when the silver plating film 108 is formed. There is a problem that the gold plating film 106 is partially eroded by the cyan component of the silver plating solution, resulting in a non-uniform surface state.

  When the silver plating film 108 is formed on the gold plating film 107 having such a non-uniform surface state, the non-uniformity of the surface state of the base becomes unevenness on the surface of the silver plating film 108. The glossiness of the lead frame decreases. As a result, the luminous efficiency of the LED is reduced.

  In addition, there is a problem that unevenness of the surface of the silver plating film 108 causes erroneous recognition in the process of mounting a semiconductor element such as an LED element on a lead frame or in image recognition in a wire bonding process. there were.

  The present invention solves the above-described problems of the conventional lead frame for a semiconductor device, a semiconductor capable of suppressing the occurrence of unevenness in the silver plating film and preventing the occurrence of erroneous recognition during image recognition in the manufacturing process. An object is to provide an apparatus lead frame and a method of manufacturing the same.

  In order to solve the above problems, a lead frame for a semiconductor device according to the present invention includes an inner lead portion including a mounting region on which a semiconductor element is mounted and a bonding region, an outer lead extending from the inner lead portion, A rail portion for connecting an outer lead, and a silver plating film as an outermost layer is formed as an upper layer of a palladium plating film in the mounting region and the bonding region, and a gold plating film as an outermost layer is formed in the outer lead. It is formed as an upper layer of the palladium plating film.

  The method for manufacturing a lead frame for a semiconductor device according to the present invention includes a step of sequentially forming a nickel plating film and a palladium plating film on the surface of a metal substrate, and a step of forming a gold plating film on the surface of the palladium plating film. And removing the gold plating film in the mounting region and the bonding region where the semiconductor element is mounted to expose the palladium plating film, and forming a silver plating film on the exposed palladium plating film; It is provided with.

  The lead frame for a semiconductor device according to the present invention having the above-described structure has a good bondability between the outer lead and the lead-free solder and the unevenness of the silver plating film on the outermost surface of the mounting region and the bonding region. Is eliminated, and it is possible to achieve excellent image recognition when a semiconductor element is mounted or when wire bonding is performed on the semiconductor element.

  Further, according to the above-described method for manufacturing a lead frame for a semiconductor device of the present invention, a lead frame in which the outermost surface of the mounting region and the bonding region is a silver plating film and the outermost surface of the outer lead is a gold plating film is good and It can be manufactured easily.

  In a preferred embodiment of the lead frame for a semiconductor device according to the present invention, the palladium film has a thickness of 0.01 to 0.15 μm, and the silver plating film has a thickness of 0.2 to 8 μm. The gold plating film has a thickness of 0.003 to 0.1 μm. By doing so, the film configuration of the lead frame can be made strong and optimal.

  In the lead frame for a semiconductor device of the present invention, it is more preferable that the semiconductor element to be mounted is a light emitting diode element. This is because a suitable silver plating film on the outermost surface of the inner lead portion is used as a mirror surface for the light emission of the light emitting diode element, and exhibits the effect of improving the light utilization rate and maintaining the color of the emitted color.

Embodiments of a lead frame for a semiconductor device and a method for manufacturing the same according to the present invention will be described below with reference to the drawings.
(Embodiment 1)
FIG. 1 is a front view showing a lead frame for a semiconductor device according to a first embodiment of the present invention.

  As shown in FIG. 1, a lead frame 1 for a semiconductor device according to the present embodiment is made of a metal sheet in which strip-like leads are formed as a repeated pattern, and includes a semiconductor element mounting area 2a and a bonding area in the central portion. The outer lead 3 is connected to the inner lead portion 2 having 2b. The end of the outer lead 3 opposite to the inner lead portion 2 is connected to the adjacent outer leads 3 by the rail portion 4, and a resin envelope or a semiconductor element is mounted and subjected to wire bonding or the like. After this, the rail portion 4 is cut into individual semiconductor devices. In FIG. 1, a dotted line is used to indicate the position of the resin envelope 21 mounted on the inner lead portion 2. The resin envelope 21 also serves as a lens holder when the mounted semiconductor element is an LED, for example.

  FIG. 2 is a diagram showing a cross-sectional configuration of the lead frame for a semiconductor device according to the first embodiment of the present invention along the line AA in FIG. FIG. 2 shows a state where an LED is mounted as a semiconductor element. In addition, in order to make the laminated structure of the formed films easy to understand, in FIGS. 2, 3, and 4, the size in the thickness direction of each film is appropriately enlarged and displayed.

  As shown in FIG. 2, the lead frame 1 for a semiconductor device according to the present embodiment has a nickel plating film 12 formed on almost the entire surface of a metal base 11 of the lead frame. In the following description, “substantially the entire surface” refers to all the surfaces of the upper surface, the lower surface, and the side surfaces of the lead frame 1 except for the portions necessary for holding the lead frame in the plating process.

  As an upper layer of the nickel plating film 12, a palladium plating film 13 is formed on almost the entire surface thereof. Further, a gold plating film 14 is formed on the outer lead 3 portion on the palladium plating film 13, and the mounting region 2 a of the semiconductor element 23 exemplified by the LED and the bonding wire 24 to the semiconductor element 23 are connected. A silver plating film 15 is formed on the bonding region 2b.

  A resin envelope 21 is mounted around the semiconductor element 23 mounted in the mounting region 2a and the bonding region 2b to which the bonding wire 24 is connected. The resin envelope 21 has a surface opposite to the surface (the upper surface in FIG. 2) on which the mounting region 2a and the bonding region 2b on which the semiconductor element 23 of the lead frame 1 is mounted (FIG. 2). 2 is formed in the same size, and is also filled and formed in the gap portion between the mounting region 2a and the wire bonding region 2b of the inner lead portion 2 as shown in FIG. Yes. In addition, the resin envelope 21 is a rectangular bowl whose inner surface expands toward the upper side on the side where the mounting area 2a and the bonding area 2b are formed on the side where the semiconductor element 23 is mounted. The opening is filled with a transparent resin 22 for potting. When the semiconductor element 23 is an LED, a lens may be formed.

  Next, the film structure of the lead frame 1 according to the present embodiment will be described with reference to FIG. FIG. 3A is an enlarged cross-sectional view of the outer lead 3, and FIG. 3B is an enlarged cross-sectional view of the inner lead portion 2.

  The film structure of the outer lead 3 portion of the lead frame 1 for a semiconductor device according to the present embodiment whose cross section is shown in FIG. 3A is made of copper, an alloy containing copper, etc. A nickel plating film 12 having a film thickness of 0.5 to 3.5 μm is formed on almost the entire surface of the metal substrate 11, and a film thickness of 0.01 to 0.15 μm is formed on almost the entire surface of the nickel plating film 12. A palladium plating film 13 is formed. The palladium plating film 13 may be formed not only of palladium itself but also of an alloy containing palladium. Here, when the film thickness of the nickel plating film 12 is thinner than 0.5 μm, the solder wettability deteriorates. Moreover, when the thickness of the palladium plating film 13 is thinner than 0.01 μm, the oxidation resistance is lowered, which is not preferable. In addition, since palladium is a noble metal, if it becomes too thick, it will be a factor of high cost.

  3A, a gold plating film 14 having a film thickness of 0.003 to 1 μm is formed as an upper layer of the palladium plating film 13. As described above, by using the gold plating film 14 as the outermost layer, oxidation of the lead frame for a semiconductor device can be prevented. Since the surface of the outer lead 3 is not oxidized, the solder connection between the outer lead 3 and the peripheral circuit portion becomes good when wiring mounting is performed as a semiconductor device. In particular, good bondability with so-called lead-free solder can be secured. In addition, when the thickness of the gold plating film 14 becomes thinner than the range of 0.003 to 1 μm, the oxidation resistance is deteriorated, and when the thickness is increased, the solder wettability is deteriorated.

  Next, of the inner lead portion 2 of the lead frame 1 for a semiconductor device according to the present embodiment whose cross section is shown in FIG. 3B, at least the film structure of the mounting region 2a and the bonding region 2b is copper or an alloy containing copper. A nickel plating film 12 having a thickness of 0.5 to 3.5 μm is formed on almost the entire surface of the lead frame material 11 having a thickness of 0.05 to 1.0 mm, and the almost entire surface of the nickel plating film 12. Further, a palladium plating film 13 having a film thickness of 0.01 to 0.15 μm is formed. The palladium plating film 13 may be formed not only of palladium itself but also of an alloy containing palladium. Up to this point, the laminated structure is the same as that of the outer lead 3 shown in FIG. And in the inner lead part 2 shown in FIG.3 (b), the point by which the silver plating film 15 with a film thickness of 0.2-8 micrometers is formed as an upper layer of the palladium plating film 13 in FIG.3 (a). It is different from the film structure of the outer lead 3 shown. Here, the silver plating film 15 may be not only a silver simple substance but also an alloy containing silver. In addition, since the reflectance of a membrane | film | coat will fall when the thickness of the silver plating membrane | film | coat 15 becomes thinner than the range of 0.2-8 micrometers, it is unpreferable. Moreover, since silver is a noble metal, making it thicker than necessary causes a cost increase.

  Thus, by forming the outermost layer as a film of silver or an alloy containing silver, the semiconductor element 23 mounted in the mounting region 2a of the inner lead portion 2 and the bonding wire 24 bonded to the wire bonding region 2b Good bondability can be obtained. Since the outermost surface layer of the mounting region 2a and the bonding region 2b is a silver plating film 15 made of silver or a silver alloy, and the lower layer of the silver plating film 15 is a palladium plating film 13, when mounting the semiconductor element 23, and Image recognition can be performed satisfactorily when wire bonding is performed between the mounted semiconductor element and the bonding region.

  Furthermore, when the semiconductor element to be mounted is an LED, the silver plating film 15 acts as a highly efficient reflector, so that the light emission efficiency of the LED can be improved. In addition, the effect of ensuring the whiteness of the emitted light can be achieved.

  As described above, in the lead frame for a semiconductor device according to the present embodiment, the gold plating film 14 is formed on the outer lead 3 as the outermost film of the palladium plating film 13, and the inner lead 2 A silver plating film 15 is formed at least in the mounting region 2a and the bonding region 2b. For this reason, in the inner lead part 2 where surface gloss is required, the surface of the silver plating film 15 is prevented from becoming uneven due to the influence of the lower layer film, and good connectivity between the semiconductor device and the circuit board is required. In the outer lead 3 to be manufactured, it is possible to ensure particularly good connectivity to lead-free solder.

(Embodiment 2)
Next, a method for manufacturing a lead frame for a semiconductor device according to the present invention will be described as a second embodiment with reference to FIGS. FIGS. 4A to 4C are cross-sectional configuration diagrams along a process flow of a lead frame for a semiconductor device according to a second embodiment of the present invention.

  First, as shown in FIG. 4 (a), as a first step, a nickel plating film 12 is formed on the substantially entire surface of the lead frame material 11 made of copper or copper alloy by a thickness of 0.5 to 3.5 μm by electrolytic plating. Apply to become. Thereafter, the palladium plating film 13 is applied to almost the entire surface of the nickel plating film 12 by electrolytic plating so as to have a film thickness of 0.01 to 0.15 μm. The palladium plating film 13 may be plating of palladium alone or alloy plating containing palladium. As the next step, the gold plating film 14 is applied to almost the entire surface of the palladium plating film 13 by electrolytic plating so that the film thickness becomes 0.003 to 1 μm. In the process up to this point, it is only necessary to sequentially form a film on almost the entire surface of the lead frame 1 for a semiconductor. Therefore, by simply changing the plating material, as a technique, a laminated film structure is formed by the same electrolytic plating method. be able to.

  As the next step, as shown in FIG. 4B, the gold plating film 14 applied to the inner lead portion 2 is partially removed to expose the palladium plating film 13. FIG. 5 shows a method for removing the gold plating film 14 used at this time.

  FIG. 5 is a conceptual diagram showing a method for selectively removing the gold plating film 14. As shown in FIG. 5, the portion of the lead frame 1 where the gold plating film 14 is not removed is masked with a mechanical mask 31 made of heat-resistant fluororesin or the like, and an etching solution 33 is sprayed from the opening 31 b of the mechanical mask 31. 32 is used for injection. In this way, the gold plating film 14 can be easily and selectively etched away selectively by using a sparger method in which a reverse electric field is applied while spraying the etching solution 33 onto the gold plating film 14 to be removed. .

  As the etching solution 33 used when the gold plating film 14 is removed by etching, a carboxylic acid-based low-concentration cyan gold plating solution may be used. Specific examples of the gold plating solution composition include those having a carboxylate concentration of 80 g / L, a gold concentration of 0.8 g / L, and a cyan concentration of 0.21 g / L. By using such a carboxylic acid-based low-concentration cyan gold plating solution, it is possible to selectively remove only the gold plating film 14 that is desired to be etched away without eroding the palladium plating film 13 as a base. It becomes possible.

  In addition, although the mechanical mask 31 shown in FIG. 5 is integrated as a mask and the thing which injects the etching liquid 33 from the opening part 31b was shown, it is limited to the thing of such a form as a mechanical mask. Not done. For example, it is also possible to remove the portion of the gold plating film 14 exposed from the mask using a mechanical mask divided into a plurality of parts that covers only the portion of the outer lead 3 where the gold plating film 14 is not removed.

  As the next step, as shown in FIG. 4C, at least a portion corresponding to the mounting region 2a and the bonding region 2b of the inner lead portion 2 where the gold plating film 14 is removed and the palladium plating film 13 is exposed. Applies the silver plating film 15 to a film thickness of 0.2 to 8 μm. At this time, in order to selectively form the silver plating film 15, the region where the silver plating film 15 is not formed is masked with the mechanical mask 31 described with reference to FIG. A sparger method in which an electric field is applied while spraying may be used.

  The silver plating film 15 may be a film of a single silver film or an alloy film containing silver. Further, since the silver plating film 15 is only required as the outermost film in the mounting region 2a or the wire bonding region 2b of the inner lead part 2, as shown in FIG. It suffices to be formed only on the mounting side of the semiconductor element 23, that is, the upper part in FIG. 4C and the side part thereof, and on the side where the semiconductor element 23 is not mounted, that is, the lower part in FIG. Is finally covered with the resin envelope 21, so there is no problem even if the palladium plating film 13 is exposed.

  By using such a manufacturing method, the outer lead 3 has a gold plating film 14 as the outermost layer of the laminated film layer formed on the lead frame material 11, and the inner lead portion 2 has a silver plating film 15 as the outermost layer. It can be formed selectively. In particular, by using an appropriate etching solution, it is possible to cleanly remove the gold plating film 14 without eroding the surface of the palladium film 13 serving as a base layer. As a result, the surface of the silver plating film 15 formed as the uppermost layer of the inner lead portion 2 is not uneven, and the surface glossiness is not lost. For semiconductor devices having good image recognition Lead frames can be manufactured.

  In the present embodiment, the sparger method formed using the mechanical mask 31 is exemplified as a method for selectively forming the silver plating film 15, but as a method for manufacturing a lead frame for a semiconductor device according to the present invention. Is not limited to this. For example, a method can be used in which a silver plating film 15 is selectively formed in a fine region by printing a mask on the surface of the lead frame using a screen printing method and removing the mask printed after plating. In this case, the silver plating film 15 can be partially selectively formed with a precision of about ± 20 μm as the positional accuracy for a very small region of about 0.5 mmφ.

  The present invention is suitable as a lead frame for a semiconductor device in which the mounted semiconductor element is connected by wire bonding, and in particular, a lead frame for a semiconductor device that automatically performs mounting of a semiconductor element and a wire bonding process by image recognition, Moreover, it is useful as the manufacturing method.

The top view of the lead frame for semiconductor devices concerning this invention The cross-sectional block diagram which expanded the principal part of the lead frame for semiconductor devices concerning this invention Sectional structure figure which shows the membrane | film | coat structure of the lead frame for semiconductor devices concerning this invention Sectional configuration diagram showing a manufacturing process of a lead frame for a semiconductor device according to the present invention Schematic showing how to remove the film by masking Cross-sectional configuration diagram enlarging the main part of a conventional lead frame for semiconductor devices

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Lead frame 2 Inner lead part 2a Mounting area 2b Bonding area 3 Outer lead 4 Rail part 11 Metal base material 12 Nickel plating film 13 Palladium plating film 14 Gold plating film 15 Silver plating film 21 Resin envelope 22 Potting transparent resin DESCRIPTION OF SYMBOLS 23 Semiconductor element 24 Bonding wire 31 Mechanical mask 31b Opening part 32 Injection nozzle 33 Etching liquid 101 Lead frame 102 Inner lead part 102a Mounting area 102b Bonding area 104 Metal substrate 105 Nickel plating film 106 Palladium plating film 107 Gold plating film 108 Silver plating Film

Claims (4)

  An inner lead portion including a mounting region on which a semiconductor element is mounted and a bonding region, an outer lead extending from the inner lead portion, and a rail portion connecting the outer lead, the mounting region and the bonding region Then, the silver plating film as the outermost layer is formed as an upper layer of the palladium plating film, and in the outer lead, the gold plating film as the outermost layer is formed as the upper layer of the palladium plating film. Lead frame.   The palladium film has a thickness of 0.01 to 0.15 μm, the silver plating film has a thickness of 0.2 to 8 μm, and the gold plating film has a thickness of 0.003 to 0.1 μm. The lead frame for a semiconductor device according to claim 1.   The lead frame for a semiconductor device according to claim 1, wherein the semiconductor element to be mounted is a light emitting diode element. A step of sequentially forming a nickel plating film and a palladium plating film on the surface of the metal substrate;
Forming a gold plating film on the surface of the palladium plating film;
Removing the gold plating film in the mounting region and the bonding region where the semiconductor element is mounted to expose the palladium plating film;
And a step of forming a silver plating film on the exposed palladium plating film. A method for manufacturing a lead frame for a semiconductor device.

Images