JP2008192054A - Semiconductor memory system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technique for enabling a semiconductor memory system, to output a correct data while a status of written data is changed unintensionally by repeating readout of the data from a non-volatile semiconductor memory. <P>SOLUTION: A first ECC51 is added to data of each page of a memory at an initial stage. An error detection is performed by using the first ECC51 when a memory controller has started to read data. If an error is detected, the error is corrected by utilizing a first error correction algorithm and a corrected data is sent to a host system. The memory controller, then, generates a second ECC52 for the corrected data by utilizing a second error correction algorithm with a higher error correction performance than that of the first error correction algorithm. The controller stores the second ECC52 in the memory by replacing the first ECC51. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a technique for acquiring correct data from a rewritable nonvolatile semiconductor memory such as a flash memory. More specifically, the present invention relates to a technique for correctly supplying data against a phenomenon that data is unintentionally rewritten by repeatedly reading data from a flash memory.

  Among non-volatile memories, NAND flash memories are used in large quantities in SD memory cards and the like in order to enable high integration, simple manufacturing cost reduction, and easy writing by users. .

  Recently, NAND flash memory has been adopted in game machines and the like. When the NAND flash memory is used in a game machine or the like, writing does not occur and continuous reading occurs. That is, a NAND flash memory is increasingly used as a ROM.

  However, in game machines and the like, since a specific program is often read repeatedly, it has begun to be pointed out that the program may be rewritten unintentionally. Such a phenomenon is called a “Read Disturb” phenomenon, and a mechanism in which this phenomenon occurs will be briefly described below.

  FIG. 11 is a schematic diagram of a NAND flash memory. The NAND flash memory includes bit lines 41 and word lines 42, 43, 44, memory cells 52, 53, selection transistors 54, and the like wired in a lattice pattern.

  Consider a case where binary data (“0” or “1”) stored in the memory cell 52 is read. In this case, the memory cell 52 is called a selected cell 52 and the memory cell 53 is called a non-selected cell 53. First, the bit line 41 to which the selected cell 52 belongs is specified by the selection transistor 54. Next, a low gate voltage V (Low) = 0 V is applied to the word line 42 to which the selected cell 52 belongs. Then, a high gate voltage V (High) to 5 V is applied to the word line 43 to which the non-selected cell 53 belongs. At this time, since the non-selected cell 53 is in a weak write state, electrons are trapped and accumulated in the floating gate of the non-selected cell 53. That is, when the binary data stored in the selected cell 52 is repeatedly read, the threshold voltage of the non-selected cell 53 shifts, and the binary data stored in the non-selected cell 53 changes from “1” to “0”. May be rewritten unintentionally.

  However, even if the binary data stored in the non-selected cell 53 is unintentionally rewritten, the function of the non-selected cell 53 is restored when the data is erased collectively before being newly written. be able to. However, when writing does not occur and continuous reading occurs, the function of the non-selected cell 53 cannot be recovered.

  The following patent documents can be cited as documents providing means for avoiding the “Read Disturb” phenomenon described above.

US Patent Application Publication No. 2005/0210184

  The above-mentioned patent document provides means for avoiding the “Read Disturb” phenomenon by a control method inside a memory cell. However, the method disclosed herein is a method applicable to a memory having a specific cell structure, and is not applicable to other cell structures. That is, it is not a measure that can avoid the “Read Disturb” phenomenon without depending on the cell structure of the memory.

  Therefore, in view of the above problems, the present invention reads out correct data from a memory in which a “Read Disturb” phenomenon may occur even in various types of non-volatile memories without being restricted by the cell structure of the memory. It aims at providing the technique for.

  In order to solve the above-mentioned problem, the invention according to claim 1 is characterized in that the first error correction code or the data to which the second error correction code having a higher correction capability than the first error correction code is stored is rewritten. And a memory controller that controls access to the nonvolatile semiconductor memory, the memory controller performing error correction processing using the first error correction code and the second error correction code The memory controller can execute the error correction process on the data read from the nonvolatile semiconductor memory by using the first error correction code or the second error correction code. It is characterized by providing.

  The invention described in claim 2 is a rewritable nonvolatile semiconductor memory in which data is stored, and a first error correction code or a first error correction for correcting the data stored in the nonvolatile semiconductor memory. Correction code storage means for storing a second error correction code having a higher correction capability than the code, and a memory controller for controlling access to the nonvolatile semiconductor memory, wherein the memory controller includes the first error correction code. And the error correction process using the second error correction code can be executed, and the memory controller performs the first error correction code or the second error correction on the data read from the nonvolatile semiconductor memory. Means for executing an error correction process using an error correction code.

  According to a third aspect of the present invention, in the semiconductor memory system according to the first aspect, the memory controller further performs error correction on the data using the first error correction code, and then converts the data into read data. An error correction code storage unit that generates the second error correction code and stores the generated second error correction code in the nonvolatile semiconductor memory is provided.

  According to a fourth aspect of the present invention, in the semiconductor memory system according to the second aspect, the memory controller further performs error correction on the data using the first error correction code, and then converts the data into read data. An error correction code storage unit that generates the second error correction code and stores the generated second error correction code in the correction code storage unit is provided.

  According to a fifth aspect of the present invention, in the semiconductor memory system according to the third or fourth aspect, when the error relating to the read data is generated, the correction code storage means has a number of error bits exceeding a predetermined threshold value. The second error correction code is stored.

  According to a sixth aspect of the present invention, in the semiconductor memory system according to the third or fourth aspect, the correction code storage means is configured so that when an error occurs with respect to read data, the second code is stored regardless of the number of error bits. An error correction code is stored.

  According to a seventh aspect of the present invention, in the semiconductor memory system according to the first aspect, when the memory controller further reads data from the non-volatile semiconductor memory, the number of times of reading the area is a predetermined number of times. A second error correction code related to the read data is generated when the error is exceeded, and error correction code storage means for storing the generated second error correction code in the nonvolatile semiconductor memory is provided. To do.

  According to an eighth aspect of the present invention, in the semiconductor memory system according to the second aspect, when the memory controller further reads data from the non-volatile semiconductor memory, the number of times the area is read is a predetermined number of times. If it exceeds, an error correction code storage means for generating a second error correction code related to the read data and storing the generated second error correction code in the correction code storage means, To do.

  According to a ninth aspect of the present invention, in the semiconductor memory system according to the first aspect, the first error correction code is used for the data in each storage area in the nonvolatile semiconductor memory, or the second error correction code is used. It is characterized in that designation information for designating whether to use is stored.

  According to a tenth aspect of the present invention, in the semiconductor memory system according to the second aspect, the correction code storage means uses a first error correction code for data in each storage area, or a second error correction code. It is characterized in that designation information for designating whether to use is stored.

  According to an eleventh aspect of the present invention, in the semiconductor memory system according to the ninth or tenth aspect of the present invention, the correction code storage means stores the second error correction code, and then stores the specified information with respect to the second information. It is characterized by rewriting the information to specify an error correction code.

  The invention according to claim 12 is the rewritable nonvolatile semiconductor memory in which the first error correction code and the data to which the second error correction code having higher correction capability than the first error correction code is added are stored. And a memory controller that controls access to the non-volatile semiconductor memory, wherein the first error correction code is applied to the data in each storage area in the non-volatile semiconductor memory, or a second error Specification information for specifying whether a correction code is applied is stored, and the memory controller can execute an error correction process using the first error correction code and the second error correction code. The memory controller uses the designation information for data read from the nonvolatile semiconductor memory. Utilizing the first error correction code or the second error correction code that is a constant, characterized in that it comprises, means for performing an error correction process.

  The invention according to claim 13 is a rewritable nonvolatile semiconductor memory in which data is stored, a first error correction code and a first error correction for correcting the data stored in the nonvolatile semiconductor memory. A correction code storage means for storing a second error correction code having a higher correction capability than the code; and a memory controller for controlling access to the nonvolatile semiconductor memory. Specification information for specifying whether the first error correction code or the second error correction code is applied to the data is stored, and the memory controller stores the first error correction code. And an error correction process using the second error correction code, and the memory controller Comprises means for executing an error correction process on the data read from the nonvolatile semiconductor memory using the first error correction code or the second error correction code specified by the specification information. It is characterized by that.

  According to the fourteenth aspect of the present invention, in the semiconductor memory system according to the twelfth or thirteenth aspect, after the error correction is further performed on the read data using the first error correction code, the read data And a designated information changing means for rewriting the designated information so that the second error correction code is applied.

  According to a fifteenth aspect of the present invention, in the semiconductor memory system according to the fourteenth aspect, the designation information changing means is a case where an error occurs with respect to read data, and the number of error bits exceeds a predetermined threshold value. In this case, the designation information is rewritten.

  According to a sixteenth aspect of the present invention, in the semiconductor memory system according to the fourteenth aspect, the designation information changing means rewrites the designation information regardless of the number of error bits when an error occurs in the read data. Features.

  According to a seventeenth aspect of the present invention, in the semiconductor memory system according to the twelfth or thirteenth aspect, when the memory controller further reads data from the non-volatile semiconductor memory, the number of times the area is read is predetermined. When the number of times exceeds the specified number of times, there is provided specification information changing means for rewriting the specification information so that the second error correction code is applied to the read data.

  The invention according to claim 18 is the semiconductor memory system according to any one of claims 1, 2, 12, and 13, wherein read access is performed among data stored in the nonvolatile semiconductor memory. For data that is assumed to occur in large numbers, the second error correction code is used.

  According to a nineteenth aspect of the present invention, in the semiconductor memory system according to any one of the first, second, twelfth and thirteenth aspects, a read error occurs in the storage area of the nonvolatile semiconductor memory. The second error correction code is used for the data stored in the assumed storage area.

  According to a twentieth aspect of the present invention, in the semiconductor memory system according to any one of the first, second, twelfth, and thirteenth aspects, the importance degree among the data stored in the nonvolatile semiconductor memory For high data, the second error correction code is used.

  The memory system of the present invention includes a rewritable nonvolatile semiconductor memory. The data stored in the nonvolatile semiconductor memory is added with the first error correction code or the second error correction code having a higher correction capability than the first error correction code. Thus, depending on conditions, it is possible to selectively use error correction with low processing capability but low processing load and error correction with high correction capability but high processing load.

  According to the present invention, the second error correction code is stored after error correction using the first error correction code. Thus, in the initial stage, error correction with a small processing load is performed and high-speed reading is performed, and when the “Read Disturb” phenomenon occurs, the data is corrected to the correct data by the second error correction code having higher correction capability. Can be output.

  In addition, the first error correction code and the second error correction code having a higher correction capability than the first error correction code are added to the data stored in the nonvolatile semiconductor memory. Thereby, according to conditions, it is possible to selectively use error correction with a low processing load and error correction with a high correction capability.

{First embodiment}
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a functional block diagram of the information processing system according to the present embodiment. This information processing system includes a host system 1 and a memory module (memory system) 2. The memory module 2 includes a memory controller 3 and a memory 4.

  In the present embodiment, the memory 4 employs a NAND flash memory that is a rewritable nonvolatile semiconductor memory. The memory controller 3 controls reading and writing of data with respect to the memory 4. For example, this information processing system functions as a game device. In this case, the host system 1 constitutes a game apparatus body, and the memory module 2 constitutes a game cartridge. The memory module 2 may be a type that is detachable from the host system 1 or may be a type that is built in an apparatus that constitutes the host system 1.

  As shown in the figure, the memory controller 3 includes an interface 31, an address decoder unit 32, and an error correction unit 33. The interface 31 functions as an input interface for inputting read and write commands output from the host system 1 and as an output interface for outputting read data output from the memory 4 to the host system 1. Alternatively, the interface 31 functions as an input interface for inputting write data output from the host system 1.

  The address decoder unit 32 acquires a read address and a write address from a read command and a write command input via the interface 31. When a read address is output to the memory 4, the memory data corresponding to the read address is read from the memory 4. When a write address and data are given to the memory 4, a data write process for the memory 4 is executed.

  Here, the memory module 2 in the present embodiment employs a writable NAND flash memory. However, as described above, the memory module 2 is used as a memory mainly for reading, such as a game cartridge. That is, in response to the read commands sequentially output from the host system 1, the process of reading the data at the designated read address is repeatedly executed. The host system 1 inputs data read from the memory 4 and executes various processes.

  As described above, in the present embodiment, there is a possibility that many reading processes of data stored in the memory 4 are repeatedly performed. In such a case, as described above, there is a possibility that a phenomenon in which stored data is rewritten unintentionally, that is, a “Read Disturb” phenomenon occurs. The memory module 2 according to the present embodiment has a function for enabling correct data to be supplied to the host system 1 by error correction even when the “Read Disturb” phenomenon occurs.

  FIG. 2 is a diagram showing a storage area of the memory 4. As shown in the figure, the memory 4 is managed by a plurality of pages. In the present embodiment, each page of the memory 4 corresponds to a read / write unit in the NAND flash memory. That is, the memory 4 can read and write data in units of pages. On the other hand, the memory 4 can be erased in units of blocks composed of a plurality of pages.

  As shown in the figure, each page of the memory 4 includes a data area 41 in which substantial data is stored, and a redundant area 42 in which information associated with the substantial data is stored. Yes. In the data area 41, for example, a game program is stored.

  3 and 4 are diagrams showing a part of the information stored in the redundant area 42. FIG. In the redundant area 42, information related to an error correcting code (ECC) is recorded. In the present embodiment, the error correction code of either the first ECC 51 or the second ECC 52 is added to the data stored in each page. At the initial stage when the memory module 2 is supplied, the first ECC 51 is added to the data stored in each page. Then, the first ECC 51 is rewritten to the second ECC 52 under conditions and processing described later.

  The second ECC 52 is a code having a higher error correction capability than the first ECC 51. In other words, the error correction algorithm using the second ECC 52 (referred to as the second error correction algorithm) is an algorithm having a higher error correction capability than the error correction algorithm using the first ECC 51 (referred to as the first error correction algorithm). is there. For example, the error correction algorithm using the first ECC 51 is an error correction algorithm capable of detecting an error of up to 4 bits and correcting an error of up to 2 bits. On the other hand, the error correction algorithm using the second ECC 52 is an algorithm capable of detecting an error of up to 8 bits and correcting an error of up to 6 bits, for example. For this reason, generally, the bit length of the second ECC 52 is larger than the bit length of the first ECC 51. Further, the first error correction algorithm is an algorithm with a smaller processing load than the second error correction algorithm.

  The ECC designation information 50 is information for designating the type of error correction code stored in the redundant area 42. That is, this is information for designating whether the first ECC 51 or the second ECC 52 is stored in the redundant area 42. FIG. 3 shows the redundant area 42 when the first ECC 51 is added to the data stored in the data area 41. In this case, in the ECC designation information 50, information indicating that the first ECC 51 is stored in the redundant area 42 is recorded. FIG. 4 shows the redundant area 42 when the second ECC 52 is added to the data stored in the data area 41. In this case, information indicating that the second ECC 52 is stored in the redundant area 42 is recorded in the ECC designation information 50.

  In the present embodiment, the error correction code and the ECC designation information 50 are stored in the redundant area 42, but these data may be stored in the data area 41. Alternatively, the error correction code and the ECC designation information 50 may be stored in a storage unit other than the memory 4.

  The error correction unit 33 reads data stored in each page and performs error detection. If a data error is detected, error correction is performed. Specifically, when the first ECC 51 is designated in the ECC designation information 50, the error correction unit 33 reads the first ECC 51 from the redundant area 42, and uses the first error correction algorithm to correct the data error. Perform detection. When a data error is detected, data error correction is performed using the first error correction algorithm. Further, when the second ECC 52 is designated in the ECC designation information 50, the error correction unit 33 reads the second ECC 52 from the redundant area 42 and performs data error detection using the second error correction algorithm. . When a data error is detected, data error correction is performed using the second error correction algorithm. Then, the data corrected by the first or second error correction algorithm is output to the host system 1 via the interface 31.

  The contents of the error correction processing in the present embodiment executed based on the above configuration will be described with reference to the flowchart of FIG.

  First, the memory controller 3 reads data of a specified page in the memory 4 (step S11). At this time, together with the data stored in the data area 41, the ECC designation information 50 and the error correction code (first ECC 51 or second ECC 52) stored in the redundant area 42 are also read.

  The error correction unit 33 refers to the ECC designation information 50 (step S12). When the first ECC 51 is designated in the ECC designation information 50, an error in the read data is detected using the read first ECC 51 according to the first error correction algorithm, and when an error is detected, Error correction is performed (step S13). Then, the data after error correction is output to the host system 1. If no error is detected by the first error correction algorithm, the read data is output to the host system 1 as it is, but this process is omitted in the flowchart.

  Next, the error correction unit 33 determines whether or not the number of error bits exceeds the threshold (step S14). The error correction unit 33 stores threshold data of the number of error bits in a storage unit (not shown). For example, when the first error correction algorithm can correct an error of up to 2 bits, an example in which the threshold is set to 1 bit or the like can be considered.

  When the detected number of error bits exceeds the threshold (for example, when the threshold is set to 1 bit and the number of error bits is 2 bits), the error correction unit 33 Then, the second ECC 52 for the corrected data is generated using the second error correction algorithm (step S15). Next, the generated second ECC 52 is recorded in the redundant area 42 of the read data (step S16). At this time, the first ECC 51 that has already been stored is deleted, and the newly generated second ECC 52 is stored. Further, the error correction unit 33 rewrites the ECC designation information 50 (step S17). That is, the information is updated so that the ECC type designated by the ECC designation information 50 becomes the second ECC 52. In this manner, the redundant area 42 shown in FIG. 3 is rewritten to the redundant area 42 shown in FIG.

  In this embodiment, the case where the first ECC 51 is replaced with the second ECC 52 has been described. However, the first ECC 51 is stored as it is, and the second ECC 52 is stored in another area in the redundant area 42 (the error correction code is stored in the data area). 41 or other storage means, it may be stored in another area in the storage means). In this case, it is specified which error correction code is applied by rewriting the ECC designation information 50 so that the second ECC 52 is designated.

  If it is determined in step S14 that the number of error bits does not exceed the threshold value, the process ends as it is. That is, as the error correction algorithm for the read data, the first error correction algorithm is used as it is.

  On the other hand, if it is determined in step S12 that the second ECC 52 is designated, an error in the read data is detected using the read second ECC 52 according to the second error correction algorithm, and if an error is detected, Error correction is performed (step S18). Then, the data after error correction is output to the host system 1. If no error is detected by the second error correction algorithm, the read data is output to the host system 1 as it is, but this process is omitted in the flowchart.

  Thus, according to the present embodiment, one of the first ECC 51 and the second ECC 52 is stored in the redundant area 42 of the memory 4. In the initial stage, the first ECC 51 is stored for the data of each page. If the detected number of error bits exceeds a predetermined threshold, a second ECC having a higher error correction capability than the first ECC 51 is generated, and the second ECC 52 is stored in the redundant area 42 instead of the first ECC 51. .

  Thereby, in the initial stage, it is possible to use the first error correction algorithm with a low processing load and use the second error correction algorithm having a high error correction capability from the time when the error exceeds a predetermined threshold. Therefore, in the initial stage, high-speed reading is performed by error correction with a small processing load, and even when the “Read Disturb” phenomenon occurs and an error occurs in the read data, an error correction algorithm with higher error correction capability is used. It can be used to supply correct corrected data to the host system.

  In this embodiment, two types of error correction algorithms having different correction capabilities are used. However, three or more types of error correction algorithms having different correction capabilities may be used. Then, it is possible to compare the number of error bits with a threshold value and switch to an error correction algorithm having a higher correction capability one after another when the threshold value is exceeded.

{Second Embodiment}
Next, a second embodiment of the present invention will be described. FIG. 6 is a flowchart of error correction processing according to the second embodiment. Note that the configuration of the information processing system in the second embodiment is the same as that shown in FIG. The information stored in the redundant area 42 is the same as that shown in FIGS.

  Steps S21 to S23 are the same as steps S11 to S13 in the first embodiment. That is, when an error is detected for the read data, error correction processing is performed using the first error correction algorithm. If no error is detected by the first error correction algorithm, the read data is output to the host system 1 as it is, but this process is omitted in the flowchart.

  In the first embodiment, in step S14, the number of error bits is compared with a threshold value. On the other hand, in the second embodiment, the shift process to the second error correction algorithm is performed without comparing with the threshold value. That is, when an error occurs even with one bit in a state where the first error correction algorithm is set, the transition to the second error correction algorithm is performed.

  Steps S24 to S26 are the same as steps S15 to S17 in the first embodiment. The second ECC 52 is generated based on the second error correction algorithm, and the second ECC 52 is stored in the redundant area 42 instead of the first ECC 51. Further, the information is rewritten so that the second ECC 52 is designated by the ECC designation information 50.

  As in the first embodiment, the first ECC 51 is stored as it is, and the second ECC 52 is stored in another area in the redundant area 42 (when the error correction code is stored in the data area 41 or another storage means). In this case, it may be stored in another area in the storage means. In this case, it is specified which error correction code is applied by rewriting the ECC designation information 50 so that the second ECC 52 is designated.

  Step S27 after the transition to the second error correction algorithm is the same as step S18 in the first embodiment. That is, when an error occurs, error correction is performed using a second error correction algorithm having a high error correction capability. If no error is detected by the second error correction algorithm, the read data is output to the host system 1 as it is, but this process is omitted in the flowchart.

  As a result, even when the “Read Disturb” phenomenon occurs and an error occurs in the read data, it is possible to use the error correction algorithm with higher error correction capability to supply the corrected data to the host system.

  In this embodiment, the error correction code and the ECC designation information 50 may be stored in the data area 41. Alternatively, the error correction code and the ECC designation information 50 may be stored in a storage unit other than the memory 4.

{Third embodiment}
Next, a third embodiment of the present invention will be described. FIG. 7 is a diagram showing the redundant area 42 in the memory 4 according to the third embodiment. FIG. 8 is a flowchart of error correction processing according to the third embodiment. The configuration of the information processing system is the same as that shown in FIG.

  As shown in FIG. 7, both the first ECC 51 and the second ECC 52 are stored in the redundant area 42. That is, from the initial stage, the first ECC 51 and the second ECC 52 are prepared for the data of each page, and both ECCs are stored in the redundant area 42. However, in the ECC designation information 50, the first ECC 51 is designated at the initial stage. Then, the ECC designation information 50 is rewritten by conditions and processing described later, and the second ECC 52 is designated by the ECC designation information 50.

  Therefore, the error correction unit 33 refers to the ECC designation information 50, and when the first ECC 51 is designated, the error correction unit 33 performs error correction using the first ECC 51 read from the redundant area 42, and the ECC designation information 50 uses the first ECC 51. When 2ECC 52 is designated, error correction is performed using the second ECC 52 read from the redundant area 42.

  In this embodiment, the error correction code and the ECC designation information 50 are stored in the redundant area 42. However, these data may be stored in the data area 41. Alternatively, the error correction code and the ECC designation information 50 may be stored in a storage unit other than the memory 4.

  Please refer to FIG. First, the memory controller 3 reads the data of the designated page in the memory 4 (step S31). At this time, together with the data stored in the data area 41, the ECC designation information 50 and the error correction code (first ECC 51 and second ECC 52) stored in the redundant area 42 are also read. Note that only necessary information may be read out from the first ECC 51 and the second ECC 52 based on the information designated in the ECC designation information 50.

  Next, the error correction unit 33 refers to the ECC designation information 50 (step S32). When the first ECC 51 is designated in the ECC designation information 50, an error in the read data is detected using the read first ECC 51 according to the first error correction algorithm, and when an error is detected, Error correction is performed (step S33). Then, the data after error correction is output to the host system 1. If no error is detected by the first error correction algorithm, the read data is output to the host system 1 as it is, but this process is omitted in the flowchart.

  Next, the error correction unit 33 determines whether or not the number of error bits exceeds the threshold (step S34). The error correction unit 33 stores threshold data of the number of error bits in a storage unit (not shown). Similar to the case illustrated in the first embodiment, for example, when the first error correction algorithm can correct an error of up to 2 bits, an example in which the threshold is set to 1 bit can be considered.

  If the number of detected error bits exceeds the threshold value, the error correction unit 33 rewrites the ECC designation information 50 (step S35). That is, the information is updated so that the second ECC 52 is designated by the ECC designation information 50.

  If it is determined in step S34 that the number of error bits does not exceed the threshold value, the process ends as it is. That is, as the error correction algorithm for the read data, the first error correction algorithm is used as it is.

  On the other hand, if it is determined in step S32 that the second ECC 52 is designated, an error in the read data is detected using the read second ECC 52 according to the second error correction algorithm, and if an error is detected, Error correction is performed (step S36). Then, the data after error correction is output to the host system 1. If no error is detected by the second error correction algorithm, the read data is output to the host system 1 as it is, but this process is omitted in the flowchart.

  Thus, according to the present embodiment, the redundant area 42 of the memory 4 stores information on both the first ECC 51 and the second ECC 52. In the initial stage, the ECC designation information 50 is set so that the first ECC 51 is used for the data of each page. When the number of detected error bits exceeds a predetermined threshold, the ECC designation information 50 is rewritten so as to use the second ECC 52 having a higher error correction capability than the first ECC 51.

  Thereby, in the initial stage, it is possible to use the first error correction algorithm with a low processing load and use the second error correction algorithm having a high error correction capability from the time when the error exceeds a predetermined threshold. Therefore, in the initial stage, high-speed reading is performed by error correction with a small processing load, and even when the “Read Disturb” phenomenon occurs and an error occurs in the read data, an error correction algorithm with higher error correction capability is used. It is possible to supply the host system 1 with correctly corrected data. Further, in this embodiment, since the first ECC 51 and the second ECC 52 are generated and stored in the memory 4 in advance, the process of generating the second ECC 52 is performed even when shifting to the second error correction algorithm. There is no need.

  In this embodiment, two types of error correction algorithms having different correction capabilities are used. However, three or more types of error correction algorithms having different correction capabilities may be used. Then, the number of error bits and the threshold value are compared, and when the threshold value is exceeded, it is possible to switch to an error correction algorithm having a higher correction capability one after another.

{Fourth embodiment}
Next, a fourth embodiment of the present invention will be described. FIG. 9 is a flowchart of error correction processing according to the fourth embodiment. The configuration of the information processing system in the fourth embodiment is the same as that shown in FIG. Further, the information stored in the redundant area 42 is the same as that shown in FIG. 7 in the third embodiment.

  Steps S41 to S43 are the same as steps S31 to S33 in the third embodiment. That is, when an error is detected for the read data, error correction processing is performed using the first error correction algorithm. If no error is detected by the first error correction algorithm, the read data is output to the host system 1 as it is, but this process is omitted in the flowchart.

  In the third embodiment, the number of error bits is compared with a threshold value in step S34. On the other hand, in the fourth embodiment, the transition process to the second error correction algorithm is performed without comparing with the threshold value. That is, when an error occurs even with one bit in a state where the first error correction algorithm is set, the transition to the second error correction algorithm is performed.

  Step S44 is the same as step S35 in the third embodiment. The error correction unit 33 rewrites the information so that the ECC designation information 50 designates the second ECC 52.

  Step S45 after the transition to the second error correction algorithm is the same as step S36 in the third embodiment. That is, when an error occurs, error correction is performed using a second error correction algorithm having a high error correction capability. If no error is detected by the second error correction algorithm, the read data is output to the host system 1 as it is, but this process is omitted in the flowchart.

  As a result, even when the “Read Disturb” phenomenon occurs and an error occurs in the read data, it is possible to use the error correction algorithm with higher error correction capability to supply the corrected data to the host system 1. .

  In this embodiment, the error correction code and the ECC designation information 50 may be stored in the data area 41. Alternatively, the error correction code and the ECC designation information 50 may be stored in a storage unit other than the memory 4.

{Fifth embodiment}
In the first to fourth embodiments, in the initial stage, the first error correction algorithm is used, and after an error occurs, the second error correction algorithm having a higher correction capability is used. .

  On the other hand, in the fifth embodiment, the second error correction algorithm having a high correction capability is used for specific data or a specific area in a fixed manner.

  FIG. 10 is a diagram illustrating the memory 4 according to the fifth embodiment. The redundant area 42 stores the first ECC 51 or the second ECC 52 as in FIGS. 3 and 4 in the first embodiment. FIG. 10 shows which ECC is stored in the redundant area 42.

  In the example of this figure, the first ECC 51 is stored in the redundant area 42 for areas such as page 0, page 1, and page 2. For the page 50 and the page 51, the second ECC 52 is stored in the redundant area. For page 0, page 1, page 2, etc., the first error correction algorithm is used fixed from the initial stage, and for page 50, page 51, the second error correction algorithm is fixed from the initial stage. Is used.

  For example, it is effective to add the second ECC 52 for data that is likely to be read repeatedly in advance due to the characteristics of the program and data. Alternatively, for the page area where the “Read Disturb” phenomenon is likely to occur due to the physical structure of the memory 4, it is effective to store the second ECC 52 in the redundant area 42.

  For data with high importance, it is effective to add the second ECC. High importance data is data that hinders the execution of an application or the like when an error occurs. Alternatively, highly important data is data that greatly affects the execution of an application when an error occurs. For example, the program main body is applicable. For example, depending on the application program, even if an error occurs in image data or audio data, the execution of the application is not greatly affected. In such a case, the program body is handled as highly important data.

  As described above, an area where the “Read Disturb” phenomenon is likely to occur or an area where highly important data is stored is specified, and an ECC having a high error correction capability is used only for the area, so that the redundant code can be generated. Waste can be eliminated. For other areas, an error correction algorithm with a small processing load is fixedly used, so that high-speed reading can be performed.

  Alternatively, both the first ECC 51 and the second ECC 52 may be stored in the redundant area 42. Also in this case, for example, for data that is highly likely to be repeatedly read in advance due to the characteristics of the program and data, the second ECC 52 is set by the ECC designation information 50. Alternatively, the page area where the “Read Disturb” phenomenon is likely to occur due to the physical structure of the memory 4 is set so that the second ECC 52 is designated by the ECC designation information 50. Similarly, for data with high importance, setting is made so that the second ECC 52 is designated by the ECC designation information 50.

  Also in this embodiment, the error correction code and the ECC designation information 50 are stored in the redundant area 42, but these data may be stored in the data area 41. Alternatively, the error correction code and the ECC designation information 50 may be stored in a storage unit other than the memory 4.

  Further, the error correction methods described in the above embodiments may be used in combination. For example, a method of using the first embodiment and the fifth embodiment in combination is conceivable. Specifically, the fifth embodiment in which the second ECC 52 is stored from the initial stage is applied to a specific area, and rewriting from the first ECC 51 to the second ECC 52 is performed for other areas in response to the occurrence of an error. The first embodiment to be performed is applied.

{Sixth embodiment}
In the first embodiment and the second embodiment, when the number of error bits exceeds a predetermined threshold value or when an error occurs, the second ECC 52 is generated and stored in the redundancy area 42 or the like. I did it. As another embodiment, the second ECC 52 may be generated according to the number of times of reading.

  That is, the memory controller 3 counts the number of readings of each storage area (for example, page unit) of the memory 4. For data stored in an area where the number of readings exceeds a predetermined threshold, the second ECC 52 is generated and stored in the redundant area 42 or the like. Then, the ECC designation information 50 is rewritten so that the second ECC 52 is applied.

{Seventh embodiment}
In the third embodiment and the fourth embodiment, the ECC designation information 50 is rewritten so as to designate the second ECC 52 when the number of error bits exceeds a predetermined threshold or when an error occurs. I made it. As another embodiment, the ECC designation information 50 may be rewritten according to the number of times of reading.

  That is, the memory controller 3 counts the number of readings of each storage area (for example, page unit) of the memory 4. The ECC designation information 50 is rewritten so that the second ECC 52 is designated for data stored in an area where the number of readings exceeds a predetermined threshold.

{Modifications}
In the first, second, and sixth embodiments, the ECC designation information 50 is rewritten when the second ECC 52 is generated and stored. However, immediately after the second ECC 52 is generated, the ECC designation information 50 may be rewritten at another timing in addition to rewriting.

  For example, the ECC designation information 50 is not rewritten during execution of the application, but is rewritten during backup related to the application when the power is turned off. Alternatively, rewriting may be performed during a certain period, idle (timing when there is no memory access by an application), during sleep, during charging, or when the power is turned on.

  However, when the ECC designation information 50 is rewritten when the power is turned on or during charging, the power is turned off once, so that information related to the ECC designation information 50 to be rewritten is temporarily stored in another nonvolatile memory. do it.

  In the third, fourth, and seventh embodiments, when the number of error bits exceeds a threshold, when an error occurs, or when the number of readings exceeds a predetermined threshold, The ECC designation information 50 was rewritten. However, the ECC designation information 50 may be rewritten at another timing instead of immediately after it is determined that these conditions are met.

  For example, rewriting may be performed during backup related to an application when the power is turned off, during a certain period, during idling, during sleep, during charging, or when the power is turned on.

  However, when the ECC designation information 50 is rewritten when the power is turned on or during charging, the power is turned off once, so that information related to the ECC designation information 50 to be rewritten is temporarily stored in another nonvolatile memory. do it.

1 is a block diagram of an information processing system according to an embodiment. It is a figure which shows the storage area of memory. It is a figure which shows a redundant area. It is a figure which shows a redundant area. It is a flowchart of the error correction process which concerns on 1st Embodiment. It is a flowchart of the error correction process which concerns on 2nd Embodiment. It is a figure which shows a redundant area. It is a flowchart of the error correction process which concerns on 3rd Embodiment. It is a flowchart of the error correction process which concerns on 4th Embodiment. It is a figure which shows ECC stored in the memory which concerns on 5th Embodiment. It is a figure which shows generation | occurrence | production operation | movement of a "Read Disturb" phenomenon.

Explanation of symbols

1 Host system 2 Memory module 3 Memory controller 4 Memory 41 Data area 42 Redundant area 50 ECC designation information 51 First ECC
52 2nd ECC

Claims (20)

A rewritable nonvolatile semiconductor memory storing data to which the first error correction code or the second error correction code having higher correction capability than the first error correction code is stored;
A memory controller for controlling access to the nonvolatile semiconductor memory;
With
The memory controller can execute an error correction process using the first error correction code and the second error correction code,
The memory controller is
Means for performing error correction processing on the data read from the nonvolatile semiconductor memory using the first error correction code or the second error correction code;
A semiconductor memory system comprising: A rewritable nonvolatile semiconductor memory in which data is stored;
Correction code storage means for storing a first error correction code for correcting data stored in the nonvolatile semiconductor memory or a second error correction code having a higher correction capability than the first error correction code;
A memory controller for controlling access to the nonvolatile semiconductor memory;
With
The memory controller can execute an error correction process using the first error correction code and the second error correction code,
The memory controller is
Means for performing error correction processing on the data read from the nonvolatile semiconductor memory using the first error correction code or the second error correction code;
A semiconductor memory system comprising: The semiconductor memory system according to claim 1,
The memory controller further includes:
After performing error correction on the data using the first error correction code, a second error correction code related to the read data is generated, and the generated second error correction code is stored in the nonvolatile semiconductor memory. Error correction code storage means for storing,
A semiconductor memory system comprising: The semiconductor memory system according to claim 2.
The memory controller further includes:
After error correction is performed on the data using the first error correction code, a second error correction code related to the read data is generated, and the generated second error correction code is stored in the correction code storage means. Error correction code storage means for storing
A semiconductor memory system comprising: The semiconductor memory system according to claim 3 or 4,
The correction code storage means stores a second error correction code when an error occurs in the read data and the number of error bits exceeds a predetermined threshold. The semiconductor memory system according to claim 3 or 4,
The correction code storage means stores a second error correction code regardless of the number of error bits when an error occurs in the read data. The semiconductor memory system according to claim 1,
The memory controller further includes:
When data is read from the nonvolatile semiconductor memory, if the number of times the area has been read exceeds a predetermined number, a second error correction code related to the read data is generated, and the nonvolatile semiconductor memory Error correction code storage means for storing the generated second error correction code,
A semiconductor memory system comprising: The semiconductor memory system according to claim 2.
The memory controller further includes:
When data is read from the nonvolatile semiconductor memory, if the number of times the area has been read exceeds a predetermined number, a second error correction code related to the read data is generated and stored in the correction code storage means Error correction code storage means for storing the generated second error correction code,
A semiconductor memory system comprising: The semiconductor memory system according to claim 1,
The nonvolatile semiconductor memory stores designation information for designating whether to use a first error correction code or a second error correction code for data in each storage area. Semiconductor memory system. The semiconductor memory system according to claim 2.
The correction code storage means stores designation information for designating whether to use a first error correction code or a second error correction code for data in each storage area. Semiconductor memory system. The semiconductor memory system according to claim 9 or 10,
The correction code storage means stores the second error correction code, and then rewrites the designation information to information designating the second error correction code. The rewritable nonvolatile semiconductor memory in which data to which a first error correction code and a second error correction code having a higher correction capability than the first error correction code are added is stored;
A memory controller for controlling access to the nonvolatile semiconductor memory;
With
In the nonvolatile semiconductor memory, designation information for designating whether the first error correction code is applied to the data in each storage area or the second error correction code is applied is stored.
The memory controller can execute an error correction process using the first error correction code and the second error correction code,
The memory controller is
Means for executing an error correction process on the data read from the nonvolatile semiconductor memory using the first error correction code or the second error correction code specified by the specification information;
A semiconductor memory system comprising: A rewritable nonvolatile semiconductor memory in which data is stored;
Correction code storage means for storing a first error correction code for correcting data stored in the nonvolatile semiconductor memory and a second error correction code having a higher correction capability than the first error correction code;
A memory controller for controlling access to the nonvolatile semiconductor memory;
With
The correction code storage means stores designation information for designating whether the first error correction code or the second error correction code is applied to the data in each storage area,
The memory controller can execute an error correction process using the first error correction code and the second error correction code,
The memory controller is
Means for executing an error correction process on the data read from the nonvolatile semiconductor memory using the first error correction code or the second error correction code specified by the specification information;
A semiconductor memory system comprising: 14. The semiconductor memory system according to claim 12, further comprising:
Designation information changing means for rewriting the designation information so that the second error correction code is applied to the read data after performing error correction on the read data using the first error correction code;
A semiconductor memory system comprising: 15. The semiconductor memory system according to claim 14, wherein
The specified information changing means rewrites the specified information when an error occurs with respect to read data and the number of error bits exceeds a predetermined threshold. 15. The semiconductor memory system according to claim 14, wherein
The specified information changing means rewrites the specified information regardless of the number of error bits when an error occurs in the read data. The semiconductor memory system according to claim 12 or 13,
The memory controller further includes:
When the data is read from the non-volatile semiconductor memory, if the number of times the area has been read exceeds a predetermined number, the designation information is rewritten so that the second error correction code is applied to the read data. Information change means,
A semiconductor memory system comprising: The semiconductor memory system according to any one of claims 1, 2, 12, and 13,
2. A semiconductor memory system, wherein a second error correction code is used for data that is assumed to have a large number of read accesses among data stored in the nonvolatile semiconductor memory. The semiconductor memory system according to any one of claims 1, 2, 12, and 13,
A semiconductor memory system, wherein a second error correction code is used for data stored in a storage area in which a read error is assumed to occur in the storage area of the nonvolatile semiconductor memory. The semiconductor memory system according to any one of claims 1, 2, 12, and 13,
A semiconductor memory system characterized in that a second error correction code is used for data of high importance among data stored in the nonvolatile semiconductor memory.

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