JP2008187375A - Analog/digital converter, and electronic apparatus employing it - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an analog/digital converter for prolonging the driving time of an electronic apparatus and reducing power consumption while attaining good audio reproduction, and to provide an electronic apparatus employing it. <P>SOLUTION: A digital audio processing circuit 100 and an analog low-pass filter 110 constitute an analog/digital converter. An interpolation filter 20 filters digital audio signals S4 of different sampling frequency fs. A ΔΣ modulator 40 performs ΔΣ modulation of the output from the interpolation filter 20 before it is delivered to a class D amplifier 50 and the analog low-pass filter 110 on the post-stage. The ΔΣ modulator 40 is arranged such that the degree and the over sampling rate can be switched. A control section 30 includes an ROM 36 holding the degree and the over sampling rate to be set in the ΔΣ modulator 40 for every sampling frequency fs of the audio signal S4. A sampling control section 34 receives the value of sampling frequency fs of the audio signal S4, reads out the degree and the over sampling rate to be set depending on that value and sets them in the ΔΣ modulator 40. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to audio signal processing, and more particularly to a 1-bit digital-to-analog converter using a ΔΣ modulator.

  With the development of semiconductor integrated technology in recent years, 1-bit digital-analog conversion using high-speed digital signal processing is used in electronic devices having audio playback functions such as silicon audio players, CD (Compact Disc) players, and mobile phone terminals. Is done. In the 1-bit digital-analog conversion, first, an audio signal is oversampled using a digital filter to remove unnecessary bands. Subsequently, the filtered audio signal is converted into a 1-bit pulse signal that is pulse-modulated using a ΔΣ modulator or the like. Subsequently, the pulse signal is amplified using a class D amplifier, and high frequency components are removed by an analog filter. The resulting analog filter output signal is the audio signal to be reproduced.

JP 63-160406 A JP 2004-080152 A JP 2003-283338 A

  In a silicon audio player using a hard disk or a flash memory or a mobile phone terminal, the sampling frequency of an audio signal to be reproduced may vary. For example, in the case of a compressed digital audio signal typified by MP3 (MPEG AUDIO LAYER-3), the sampling frequency changes according to the compression rate. Further, when a call voice is output from a mobile phone terminal or the like, the sampling frequency is lower than that of music data.

  When the sampling frequency of the audio signal to be played changes, if the same processing is performed at different sampling frequencies, good sound quality may be obtained at a certain sampling frequency, but the sound quality may deteriorate at other sampling frequencies. .

  The present invention has been made in view of these problems, and its comprehensive purpose is to improve the sound quality of digital audio equipment.

  A 1-bit analog-digital converter according to an aspect of the present invention includes a digital filter that filters digital audio signals having different sampling frequencies, and ΔΣ-modulates the output of the digital filter, and outputs it to a subsequent class D amplifier and analog filter. A modulator comprising a ΔΣ modulator whose order and oversampling rate can be switched, and a memory that holds values of the order and oversampling rate to be set in the ΔΣ modulator for each sampling frequency of the audio signal. A control unit which receives the value of the sampling frequency of the signal, reads out the order and oversampling rate to be set according to the value from the memory, and sets them in the ΔΣ modulator.

  At the design stage of the ΔΣ modulator, the order and oversampling rate are changed to various values for audio signals with different sampling frequencies, and characteristics such as S / N ratio and THD (total harmonic distortion) are measured. Thus, it is possible to estimate an appropriate order and oversampling rate for each sampling frequency. By writing the result in the memory of the control unit, it is possible to set an appropriate order and oversampling rate for each sampling frequency of the audio signal in a state where it is mounted in a set, and it has good characteristics (sound quality ) Can be obtained. Furthermore, there is a case where power consumption can be reduced by reducing the order within a range that does not impair the characteristics of the audio signal.

  The control unit may set the order of the ΔΣ modulator lower and set the oversampling rate higher as the sampling frequency is lower.

  The control unit may set the order to the 4th order when the sampling frequency is less than 24 kHz, and set the order to the 5th order when the sampling frequency is 24 kHz or more.

  The control unit may set the oversampling rate to 128 times when the sampling frequency is less than 24 kHz, and set the oversampling rate to 64 times or less when the sampling frequency is 24 kHz or more.

  The digital / analog converter may be integrated on a single semiconductor substrate. “Integrated integration” includes the case where all of the circuit components are formed on a semiconductor substrate and the case where the main components of the circuit are integrated. A resistor, a capacitor, or the like may be provided outside the semiconductor substrate. By integrating the circuit as one IC, the area can be reduced.

  Another embodiment of the present invention is an electronic device. The electronic device includes a battery, a signal generation unit that generates a digital audio signal, the above-described analog-digital converter that operates using the battery as a power source and receives an audio signal as an input, and a ΔΣ modulator of the analog-digital converter. The D signal amplifier that amplifies the pulse signal of the signal, the analog filter that filters the output signal of the D signal amplifier, the audio output unit provided after the analog filter, and the analog / digital converter are notified of the sampling frequency of the audio signal. A host processor.

  According to this aspect, since the appropriate ΔΣ modulator order and oversampling rate are set for each sampling frequency, it is possible to reduce power consumption and extend the driving time of the electronic device while realizing good audio reproduction. it can.

  It should be noted that any combination of the above-described constituent elements and a representation obtained by converting the expression of the present invention between methods, apparatuses, and the like are also effective as an aspect of the present invention.

  The digital-analog converter according to the present invention can reduce power consumption.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

  FIG. 1 is a block diagram showing a configuration of an electronic device 200 equipped with a digital audio processing circuit 100 according to an embodiment of the present invention. The electronic device 200 is a device that can output sound from a speaker, a headphone, an earphone, or the like such as a mobile phone terminal, a silicon audio player, or a CD player. The electronic device 200 includes a digital audio processing circuit 100, an analog low-pass filter 110, an audio output unit 120, an audio signal generation unit 130, and a battery 140.

  The battery 140 is used as a main power source of the electronic device 200, and is, for example, a lithium ion battery or a nickel metal hydride battery. The digital audio processing circuit 100 and the audio signal generator 130 are supplied with a battery voltage Vbat output from the battery 140 or a voltage obtained by stabilizing the battery voltage Vbat with a switching regulator or the like as a power supply voltage. The audio output unit 120 is a device that converts an electrical signal into an acoustic wave, such as a speaker, headphones, or earphones, and is built in or externally attached to the electronic apparatus 200.

  The audio signal generation unit 130 generates a digital audio signal S1. The audio signal S1 is a PCM (Pulse Code Modulation) format signal obtained by decoding an audio signal that is encoded and recorded in a voice or ringing tone uttered by a communication partner or a memory (not shown). The audio signal S1 is sampled at different sampling frequencies depending on the type. For example, if the voice is a call voice, the sampling frequency is about 8 kHz.

  The audio signal generation unit 130 and the digital audio processing circuit 100 are connected via a signal line 132. For example, the signal line 132 is an I2S standard bus, and the audio signal S1 is transmitted to the digital audio processing circuit 100 as serial data. Note that I2S is merely an example, and other serial buses or parallel buses may be used. The present invention is not limited to a situation where a specific bus is used.

  The digital audio processing circuit 100 receives the audio signal S1, converts it into a pulse-modulated 1-bit pulse signal, amplifies it, and outputs it to the analog low-pass filter 110 at the subsequent stage. The analog low-pass filter 110 removes the high frequency component of the pulse signal S2 and converts it to an analog audio signal S3. The audio output unit 120 is driven by the analog audio signal S3 from the analog low-pass filter 110. The digital audio processing circuit 100 and the analog low-pass filter 110 constitute a 1-bit digital-analog converter.

  The digital audio processing circuit 100 includes an input terminal 102, an output terminal 104, and a power supply terminal 106. The audio signal S1 from the audio signal generator 130 is input to the input terminal 102, and the output terminal 104 is connected to the analog low-pass filter 110. A power supply voltage based on the battery voltage Vbat is supplied to the power supply terminal 106. Each block in the digital audio processing circuit 100 operates using a power supply voltage.

  The digital audio processing circuit 100 includes an input interface unit 10, a digital interpolation filter (hereinafter simply referred to as an interpolation filter) 20, a control unit 30, a ΔΣ modulator 40, and a class D amplifier 50, and is integrated on a single semiconductor substrate. Has been.

  The input interface unit 10 receives the audio signal S1 input via the signal line 132, and serial-parallel converts this to generate an audio signal S4. The audio signal S4 is input to the interpolation filter 20 at the subsequent stage.

  The interpolation filter 20 is an FIR filter that interpolates by oversampling the audio signal S4 having the sampling frequency fs by 8 times. The filtered audio signal S5 is input to the subsequent ΔΣ modulator 40.

  The ΔΣ modulator 40 ΔΣ modulates the audio signal S5 output from the interpolation filter 20 and outputs the pulse signal S6 as a pulse-modulated pulse signal S6. The coarseness of the pulse train included in the pulse signal S6 or the width (duty ratio) of each pulse corresponds to the amplitude of the audio signal to be reproduced. An analog audio signal is generated by removing the high-frequency component of the pulse signal S6 by the analog low-pass filter 110 at the subsequent stage.

  In the present embodiment, the ΔΣ modulator 40 is configured such that the order of the ΔΣ modulation and the oversampling rate are variable. For switching the order of the ΔΣ modulator, the technique described in Patent Document 2 already filed by the present applicant may be used.

  The class D amplifier 50 amplifies the pulse-modulated pulse signal S6 output from the ΔΣ modulator 40. The class D amplifier 50 is a CMOS (Complementary Metal Oxide Semiconductor) inverter type switching amplifier. The 1-bit pulse signal S2 amplified by the class D amplifier 50 is output via the output terminal 104.

  The control unit 30 includes a clock control unit 32, a sampling control unit 34, and a ROM (Read Only Memory) 36. The control unit 30 controls the state of the ΔΣ modulator 40 in accordance with the sampling frequency fs of the audio signal S1 input to the digital audio processing circuit 100.

  A master clock signal CK is input to the clock control unit 32 from the outside. The clock control unit 32 multiplies the master clock signal CK and supplies an appropriate clock signal to the ΔΣ modulator 40. For example, the clock control unit 32 includes a PLL (Phase Locked Loop) circuit.

  The sampling control unit 34 receives the sampling frequency fs of the audio signal S1 currently input to the digital audio processing circuit 100 as data. The ROM 36 holds the order and oversampling rate values to be set in the ΔΣ modulator 40 for each sampling frequency fs of the audio signal S1 to be reproduced. For example, the sampling frequency fs takes any value of 8, 11, 12, 16, 22, 24, 32, 44, and 48 kHz. In this case, the order and the oversampling rate are set for each value of the sampling frequency fs.

  The sampling control unit 34 receives the value of the sampling frequency fs of the audio signal S1, decodes it, and reads out the order and oversampling rate to be set according to the value from the ROM 36. The sampling control unit 34 sets the read order and oversampling rate in the ΔΣ modulator 40.

Next, the relationship between the sampling frequency fs, the order of the ΔΣ modulator 40, and the oversampling rate will be described.
The order and oversampling rate are optimized through simulations and experiments in the design stage of the ΔΣ modulator 40 and the digital audio processing circuit 100 as a whole. That is, for the audio signal S1 having a different sampling frequency fs, the order and oversampling rate are changed to various values, and characteristics such as S / N ratio and THD (total harmonic distortion) are measured. As a result, an appropriate order and oversampling rate can be estimated for each sampling frequency fs.

2A and 2B are tables showing the relationship between the sampling frequency, the order of the ΔΣ modulator 40, and the oversampling rate.
FIG. 2A shows an example of THD measurement results for various combinations of sampling frequency fs, order, and oversampling rate. The S / N ratio shows the same tendency as THD.

  FIG. 2B is a diagram showing a set of orders and oversampling rates corresponding to each sampling frequency fs determined based on the measurement result of FIG. Basically, a combination of an oversampling rate and an order that minimizes the THD may be selected for each sampling frequency fs. Even if the oversampling rate or the order is changed, if the THD value is substantially the same value (for example, ± 1 dB), any of them may be selected.

  2A and 2B, preferably, the sampling control unit 34 may set the order of the ΔΣ modulator 40 to be lower as the sampling frequency fs is lower. More preferably, the oversampling rate is set higher as the sampling frequency fs is lower.

  Here, from the viewpoint of the capacity of the ROM 36 and the simplification of the circuit, it is desirable that the combination of the oversampling rate and the order to be selected is as small as possible. Therefore, in this embodiment, the oversampling rate is set to 128 times and the order is set to the fourth order with respect to fs <24 kHz. For 24 kHz ≦ fs <44 kHz, the oversampling rate is set to 64 times and the order is set to the fifth order. For 44 kHz ≦ fs, the oversampling rate is set to 32 times and the order is set to the fifth order. The ROM 36 holds the oversampling rate and order selected in this way. As a result, since the ΔΣ modulator 40 may be configured to be switched between the 4th order and the 5th order, the circuit can be simplified. In addition, since only three sets of orders and oversampling rates need to be held, memory capacity can be saved.

  According to the digital audio processing circuit 100 according to the present embodiment, the combination of the order of ΔΣ modulation and the oversampling rate is recorded in the ROM 36 for each sampling frequency, so that the optimum order and oversampling rate are Can be automatically set without receiving an instruction from the host processor. That is, only the sampling frequency of the audio signal S1 needs to be input from the outside, and the load on the host processor can be reduced.

Even if the sampling frequency of the audio signal S1 changes, the following two methods are also conceivable as methods for obtaining good characteristics. The first is a method in which ΔΣ modulation is performed after the audio signal S1 is sampled and converted by a sampling converter to unify the sampling frequency. In this method, in order to obtain high sound quality, it is necessary to unify the sampling frequency to 32 kHz or higher. However, with this method, an audio signal of about 8 kHz, which does not require high sound quality, is sampled and converted to 32 kHz or higher, so that the power consumption of the circuit increases.
In the digital audio processing circuit 100 according to the present embodiment, power consumption can be reduced as compared with the first method.

  Secondly, a method is also conceivable in which the sampling conversion is not performed and the order and oversampling rate of the ΔΣ modulator 40 are optimized to the sampling frequency that requires the most characteristics. However, this method does not provide satisfactory characteristics for other sampling frequencies that are not optimized. In the digital audio processing circuit 100 according to the present embodiment, this problem can be solved.

  In addition, when either one of the order or the oversampling rate is fixed and the other is changed, from FIG. 2A, even if good characteristics are obtained at a certain sampling frequency, the characteristics deteriorate at other sampling frequencies. I understand that. According to the digital audio processing circuit 100 according to the present embodiment, good characteristics can be obtained at any sampling frequency by changing both the order of the ΔΣ modulator 40 and the oversampling rate.

  Furthermore, since the order and oversampling rate of the ΔΣ modulator 40 can be set low as necessary, for example, the power consumption of the circuit can be reduced compared to the case where the fifth order and 128 times are fixed. it can.

  In the embodiment, the case where the value of the order and the oversampling rate is switched in three ways according to the sampling frequency fs has been described. However, the present invention is not limited to this, and the measurement result as shown in FIG. Alternatively, from the simulation results, a set that gives good characteristics to each sampling frequency may be selected and recorded in the ROM 36.

  Although the present invention has been described based on the embodiments, the embodiments merely illustrate the principle and application of the present invention, and the embodiments are intended to include the idea of the present invention defined in the claims. Many modifications and changes in arrangement are possible within the range not leaving.

It is a block diagram which shows the structure of the electronic device carrying the digital audio processing circuit which concerns on embodiment of this invention. FIGS. 2A and 2B are tables showing the relationship between the sampling frequency, the order of the ΔΣ modulator, and the oversampling rate.

Explanation of symbols

  10 input interface section, 20 interpolation filter, 30 control section, 32 clock control section, 34 sampling control section, 36 ROM, 40 ΔΣ modulator, 50 class D amplifier, 100 digital audio processing circuit, 102 input terminal, 104 output terminal, 106 power supply terminal, 110 analog low-pass filter, 120 audio output unit, 130 audio signal generation unit, 140 battery, 200 electronic device, S1 audio signal, S2 pulse signal, S3 analog audio signal.

Claims (3)

A digital filter for filtering digital audio signals having different sampling frequencies;
A ΔΣ modulator that ΔΣ-modulates the output of the digital filter and outputs it to a subsequent class D amplifier and an analog filter, the order and oversampling rate being switchable;
For each sampling frequency of the audio signal, a memory that holds the value of the order and oversampling rate to be set in the ΔΣ modulator, receives the value of the sampling frequency of the audio signal, and should be set according to the value A controller that reads the order and oversampling rate from the memory and sets the ΔΣ modulator;
An analog-digital converter characterized by comprising:   2. The analog-digital converter according to claim 1, wherein the controller sets the order of the ΔΣ modulator lower and sets the oversampling rate higher as the sampling frequency is lower. Battery,
A signal generator for generating a digital audio signal;
The analog-digital converter according to claim 1 or 2, wherein the battery operates as a power source and receives the audio signal as an input.
A class D amplifier for amplifying a pulse signal from the ΔΣ modulator of the analog-digital converter;
An analog filter for filtering the output signal of the class D amplifier;
An audio output unit provided in a subsequent stage of the analog filter;
A host processor for notifying the analog-digital converter of the sampling frequency of the audio signal;
An electronic device comprising:

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