JP2008186894A - Solid-state image sensor - Google Patents

Abstract

Provided is a solid-state imaging device capable of improving the S / N ratio of an output signal and obtaining a high-quality image in a solid-state imaging device having a large pixel size used for applications such as HD movies and single-lens reflex DSCs. To do.
A pixel configuration of a solid-state imaging device according to the present invention is as follows. A photodiode 10, a floating diffusion 20, a transfer transistor 100, a reset transistor 110, and an amplifying source follower transistor 120 are formed on the same active region. Between the photodiode 10 adjacent in the horizontal direction, A source follower transistor 120 is disposed. At this time, the gate length of the source follower transistor 120 is configured to be longer than the gate length of the transfer transistor 100.
[Selection] Figure 2

Description

  The present invention relates to a MOS type solid-state imaging device having an amplification transistor in a pixel.

  In recent years, MOS solid-state imaging devices have been used as image information acquisition means for mobile phones, digital still cameras, and movie cameras. In applications such as mobile phone cameras, there is a strong demand for smaller and higher pixel camera modules, and pixel size reduction using a fine silicon process has been promoted. Pixel sizes are as fine as 2.0 μm or less. It has become.

  Examples of a pixel circuit configuration and a cell layout of a solid-state imaging device having such fine pixels are shown in FIGS. 6 and 7 (see Patent Document 1). 6A and 6B are so-called three-transistor pixels, and FIGS. 7A and 7B are four-transistor pixels in which row selection transistors are added to the three-transistor pixels. As shown in FIGS. 6B and 7B, a photodiode 10, a floating diffusion 20, a transfer transistor 100, a reset transistor 110, and a source follower transistor 120 for amplification are configured on the same active region. A reset transistor 110 and a source follower transistor 120 are arranged between the photodiodes 10 adjacent in the horizontal direction. In FIG. 7B, a row selection transistor 130 is provided adjacent to the source follower transistor 120. All the transistors in the pixel are composed of MOS transistors.

On the other hand, for HD (High Definition) movies and single-lens reflex DSC (Digital Still Camera), the pixel size is generally determined by the product specifications of optical inch size and number of pixels. For example, in the case of a solid-state image sensor for DSC of 10 million pixel class, the pixel size is generally about 5 μm. Further, there is a high demand in terms of imaging characteristics, and in order to improve the S / N ratio, it is necessary to increase the basic characteristics such as sensitivity and saturation by increasing the area of a photoelectric conversion element typified by a photodiode. Further, in these solid-state imaging devices for these applications, transistor design based on a microfabrication process is often used even if the pixel size is relatively large for portable applications.
JP-A-10-150182

  In general, in the solid-state imaging device as shown in Patent Document 1, it is preferable that the gate length of the source follower transistor is longer than the minimum gate size allowed by the design rule. When the gate length of the transistor is shortened, the effective gate length varies due to the short channel effect, and the gain of the transistor varies accordingly. This is because the gain variation causes sensitivity variations and causes noise.

  However, in the configuration of the conventional solid-state imaging device, the gate length of the source follower transistor is generally set to be shorter than the gate length of the transfer transistor. The reason is as follows.

  First, it results from the device structure of the transfer transistor. The transfer transistor has a function of transferring charges accumulated in the photodiode to the floating diffusion, and a source and a drain in a general transistor correspond to the photodiode and the floating diffusion in the transfer transistor, respectively. However, in order to improve the sensitivity on the long wavelength side, it is necessary to form the photodiode up to a deep portion (˜3 μm) of the silicon substrate, and the photodiode and the floating diffusion are likely to punch through deep in the substrate. In order to prevent this, the gate length of the transfer transistor needs to be sufficiently larger than the minimum gate size allowed by the design rule. When the pixel size is about 2 to 3 μm, the gate length of the transfer transistor is generally about 0.6 to 0.7 μm.

  The second is a reduction in conversion gain accompanying an increase in the gate length of the source follower transistor, and a suppression of a noise reduction effect accompanying the reduction in conversion gain. The signal charge accumulated in the photodiode is modulated with a gain corresponding to the reciprocal of the total capacitance Ctotal of the floating diffusion and output as a signal from the source follower transistor. Here, a voltage signal output from the source follower transistor for one electron carried to the floating diffusion is defined as “conversion gain”.

The floating diffusion has various capacitances in addition to its own diffusion capacitance CS. The total capacitance Ctotal of the floating diffusion when the source follower transistor is operating is
Ctotal = CS + CL + CG + (1-α) × CSF (Formula 1)
It is represented by

  Here, CL is the sum of the parasitic capacitances between the floating diffusion including the wiring for electrically connecting the floating diffusion and the source follower transistor, and the equipotential region between the wiring constituting the pixel, and CG is the transfer transistor and the transfer transistor. , CSF is the gate capacitance of the source follower transistor, and α is the modulation degree of the source follower transistor. α generally has a value of about 0.7 to 0.8.

  As can be seen from (Equation 1), when the gate length of the source follower transistor is increased and the gate capacitance CSF is increased, Ctotal is increased and the conversion gain is decreased. On the other hand, as described above, when the gate length of the source follower transistor is increased, noise is reduced. When these are estimated in a cell having a pixel size of about 2 to 3 μm, as will be described later, for example, even if the gate length is increased from 0.6 μm to 1.0 μm, the noise is reduced only by about 15%. It was found that the conversion gain is reduced by about 10%. In this case, the effect of reducing the noise generated in the pixel portion by increasing the gate length of the source follower transistor is low. Further, since the conversion gain is reduced by 10%, the noise generated in the subsequent circuit is increased by 10% when converted by the input of the floating diffusion. Therefore, the total noise reduction effect is low, and the merit of increasing the gate length of the source follower transistor is small.

  Third, there is a relationship between cell area and transistor size. In order to ensure a predetermined sensitivity, it is necessary to make the area of the photodiode equal to or larger than a certain level. However, with a pixel size of about 2 μm, there is no area margin to increase the transistor size by increasing the gate length of the source follower transistor.

  From the above, the gate length of the source follower transistor has been set to be shorter than the gate length of the transfer transistor. In general, the gate length of the transfer transistor is designed to be longer than that of the other transistors in the pixel.

  However, as described above, higher quality images have been required for applications such as HD movies and single-lens reflex DSCs, and the need to reduce noise and improve the S / N ratio is increasing. .

  Therefore, an object of the present invention is to improve the S / N ratio of an output signal and obtain a high-quality image in a solid-state imaging device having a large pixel size.

  In order to solve the above problems, a solid-state imaging device of the present invention holds a transferred charge, a photoelectric conversion element that converts incident light into charges, a transfer transistor that transfers charges accumulated in the photoelectric conversion elements, and the like. A pixel having at least a charge holding unit including a floating diffusion capacitor, an amplification transistor having a gate electrode electrically connected to the charge holding unit, and a reset transistor for resetting the photoelectric conversion element and the charge holding unit In the solid-state imaging device, the amplification transistor includes: a plurality of light receiving portions arranged; a signal processing circuit for outputting a signal from the pixel to the outside; and a driving circuit for driving the pixel and the signal processing circuit Is longer than the gate lengths of the other transistors constituting the pixel.

  A selection transistor for selecting a readout row is preferably provided in the pixel.

  It is preferable that the thickness of the gate insulating film of the amplification transistor is the smallest as compared with the thickness of the gate insulating film of another transistor constituting the pixel.

  According to the present invention, by setting the gate length of the source follower transistor to be longer than the gate length of the transfer transistor, 1 / f noise caused by the source follower transistor can be reduced, and a high-quality image can be obtained. .

(Embodiment)
FIG. 1 is a schematic configuration diagram of a solid-state imaging device according to the present embodiment. The light receiving unit 1 in which the pixel cells are arranged in a matrix is reset, stored, and read out in units of rows by the vertical shift register 2. The signal read in units of rows is amplified by the column amplifier 3, and a value obtained by canceling the offset variation of the amplifier is held by the noise cancellation circuit 4. The pixel signals for one row held in the noise cancellation circuit 4 are selected by the horizontal shift register 6 and sequentially output via the multiplexer 5 and the output amplifier 7. Signals for operating the vertical shift register 2, the noise cancellation circuit 4, the multiplexer 5 and the output amplifier 7 are supplied from the timing generator 8.

  FIG. 2 shows a pixel cell layout of the solid-state imaging device in the present embodiment. In the present embodiment, the pixel size is about 5 to 6 μm. Note that the circuit configuration in the pixel is the same as that shown in FIG.

  As apparent from FIG. 2, the difference from the conventional layout is that the gate length of the source follower transistor 120 is longer than the gate length of the transfer transistor 100. With such a layout, 1 / f noise due to the source follower transistor 120 can be reduced, and a high-quality image can be obtained. This effect will be described in detail below.

  First, we estimated the conversion gain and noise change with respect to the gate length change of the source follower transistor. FIG. 3 shows the correlation between the gate length of the transistor and the 1 / f noise amplitude. The noise amplitude is a value obtained by normalizing an actual measurement value at each gate length with an actual measurement value at a gate length of 0.35 μm. In addition, the transistor was evaluated using a 0.3 μm rule manufacturing process. As can be seen from FIG. 5, it was found that the degree of change of 1 / f noise with respect to the gate length changes at the boundary of the gate length of 0.6 μm. When the gate length is 0.6 μm or less, 1 / f noise is significantly reduced as the gate length is increased. However, when the gate length exceeds 0.6 μm, the noise reduction rate decreases and tends to saturate. It was. In this case, if the amplitude of 1 / f noise in a transistor having a gate length of 0.6 μm is 1, the amplitude of 1 / f noise in a transistor having a gate length of 1.0 μm is 0.77.

  Next, the total capacity Ctotal of the floating diffusion 20 was estimated using the conventional pixel cell configuration.

When the pixel size is 2.8 μm and the capacity is estimated with the configuration shown in FIG.
(CL + CG + CS): CSF-3: 3.3 (Gate length: 0.6 μm) (Formula 2)
(CL + CG + CS): CSF to 3: 2 (Gate length: 1.0 μm) (Formula 3)
It became. Further, if α = 0.7, the ratio of Ctotal when the gate length is 0.6 μm and Ctotal when the gate length is 1.0 μm is:
Ctotal (L = 0.6) / Ctotal (L = 1.0)
= (3+ (1-0.7) × 3.3) / (3+ (1-0.7) × 2)
= 3.99 / 3.6-1.1 (Formula 4)
It became.

  From these values, the reduction of the conversion gain and the noise reduction effect when the gate length is increased are estimated.

  First, as is clear from (Equation 2), when the gate length is changed from 0.6 μm to 1.0 μm, the conversion gain decreases by about 10%. On the other hand, the noise reduction effect is as follows.

  First, since the conversion gain is reduced by 10%, when the gate length is increased, the noise reduction effect in terms of input of the source follower transistor is 0.77 / 0.9 to 0.86, that is, about 14%. On the other hand, since the output signal decreases by about 10%, the noise generated in the subsequent circuit increases by about 10% in terms of the input of the source follower transistor.

On the other hand, if the pixel size is 5.6 μm in the present embodiment, (CL + CG + CS) increases about 2.5 times. This is because the parasitic wiring length, the area of the floating diffusion 20, and the overlap between the floating diffusion 20 and the transfer transistor increase. So the capacity estimate is
(CL + CG + CS): CSF to 7.5: 3.3 (gate length: 0.6 μm) (Formula 5)
(CL + CG + CS): CSF to 7.5: 2 (Gate length: 1.0 μm) (Formula 6)
The ratio between Ctotal when the gate length is 0.6 μm and Ctotal when the gate length is 1.0 μm is
Ctotal (L = 0.6) / Ctotal (L = 1.0)
= (7.5+ (1-0.7) × 3.3) / (7.5+ (1-0.7) × 2)
= 8.49 / 8.1 to 1.05 (Formula 7)
It became.

  Therefore, in this embodiment, when the gate length is changed from 0.6 μm to 1.0 μm, the conversion gain is reduced by about 5%. On the other hand, the noise reduction effect is as follows.

  First, since the conversion gain is reduced by about 5%, when the gate length is increased, the noise reduction effect in terms of input of the source follower transistor is 0.77 / 0.95 to 0.81, that is, about 19%. . The noise is reduced to 0.77 / 0.95 to 0.81, that is, about 19%. On the other hand, since the output signal decreases by about 5%, the noise generated in the subsequent circuit increases by about 5% in terms of the input of the source follower transistor.

  Here, when the gate length of the source follower transistor is 0.6 μm, the number of noise electrons generated in the pixel portion and the number of noise electrons generated in the subsequent circuit are defined as A and B, respectively. Since A and B are independent, the amounts of noise generated at pixel pitches of 2.8 μm and 5.6 μm are shown below.

2.8 μm pixel: ((0.86 × A) ² + (1.1 × B) ² ) ^0.5 (Formula 8)
5.6 μm pixel: ((0.81 × A) ² + (1.05 × B) ² ) ^0.5 (Formula 9)
If A = B, the noise is 1.40 A for a 2.8 μm pixel and 1.33 A for a 5.6 μm pixel. When the gate length of the source follower transistor is 0.6 μm, the amount of noise is √2A. Therefore, the amount of noise improvement of the 2.8 μm pixel is only about 1%, whereas that of the 5.6 μm pixel is about 6%. The noise is greatly improved.

  Further, in this embodiment, since the pixel size is increased, there is room in the space between the photodiodes 10, and the gate length of the source follower transistor 120 can be made longer than the gate length of the transfer transistor 100. It is.

  As described above, according to the present embodiment, the gate length of the source follower transistor 120 is made longer than the gate length of the transfer transistor 100 to reduce 1 / f noise caused by the source follower transistor 120, and to achieve high image quality. Images can be obtained.

(First Modification of Embodiment)
FIG. 4 shows a pixel cell layout of the solid-state imaging device in the first modification of the present embodiment. The circuit configuration in the pixel is the same as that shown in FIG. The difference from the layout shown in FIG. 2 is that a row selection transistor 130 is arranged adjacent to the source follower transistor 120. The above-described effect of the present invention is the same as that of the first embodiment. is there.

(Second Modification of Embodiment)
FIG. 5 shows a pixel cell layout of the solid-state imaging device in the second modification of the present embodiment. The circuit configuration in the pixel is the same as that shown in FIG. The difference from the layout shown in FIG. 4 is that the transfer transistor 100 is arranged at the corner of the photodiode and is arranged obliquely with respect to the side of the photodiode 10. By doing so, the size of the transfer transistor 100 can be reduced, the cell area can be reduced, the overlap with the floating diffusion 20 can be reduced, and Ctotal can be reduced, that is, the conversion gain can be increased. The effects of the present invention described above are the same as in the case of the first embodiment.

  In addition, in the first embodiment including the modification example, noise is further increased by making the thickness of the gate insulating film of the source follower transistor 120 the smallest with respect to the thickness of the gate insulating film of other transistors in the pixel. Can be reduced. This is because the 1 / f noise caused by the source follower transistor 120 is inversely proportional to the gate capacitance.

  In addition, the circuit block configuration in the element and the circuit configuration in the pixel shown in FIG. 1 can be freely modified within the scope of the effects of the present invention.

  In this embodiment, a solid-state imaging device having a pixel size of 5.6 μm has been described as an example. However, if there is an area margin for increasing the gate length of the transfer transistor in the pixel, the pixel size can be reduced to a smaller pixel size. The invention is applicable.

  The solid-state imaging device according to the present invention can obtain a high-quality image and is useful for use in applications such as HD movies and single-lens reflex DSCs.

1 is a schematic configuration diagram of a solid-state imaging device according to a first embodiment of the present invention. The figure which shows the pixel cell layout of the solid-state image sensor in the 1st Embodiment of this invention. The figure which shows the correlation with the gate length of the transistor of the solid-state image sensor in the 1st Embodiment of this invention, and 1 / f noise amplitude The figure which shows the pixel cell layout of the solid-state image sensor in the 1st modification of embodiment of this invention. The figure which shows the pixel cell layout of the solid-state image sensor in the 2nd modification of embodiment of this invention. It is an example of the pixel circuit structure and cell layout of the conventional solid-state image sensor, (a), (b) is a figure regarding the pixel of 3 transistor structure. (A), (b) is a diagram regarding a pixel having a four-transistor configuration

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Light-receiving part 2 Vertical shift register 3 Column amplifier 4 Noise cancellation circuit 5 Multiplexer 6 Horizontal shift register 7 Output amplifier 8 Timing generator 10 Photodiode 20 Floating diffusion 100 Transfer transistor 110 Reset transistor 120 Source follower transistor 130 Row selection transistor

Claims (3)

A photoelectric conversion element for converting incident light into electric charge, a transfer transistor for transferring electric charge accumulated in the photoelectric conversion element, charge holding means including a floating diffusion capacitor for holding the transferred electric charge, and a gate electrode An amplifying transistor electrically connected to the charge holding unit; a light receiving unit in which a plurality of pixels having at least a reset transistor for resetting the photoelectric conversion element and the charge holding unit are arranged;
A signal processing circuit for outputting a signal from the pixel to the outside;
In a solid-state imaging device including a driving circuit for driving the pixel and the signal processing circuit,
A solid-state imaging device, wherein the gate length of the amplification transistor is the longest compared to gate lengths of other transistors constituting the pixel. The solid-state imaging device according to claim 1, wherein a selection transistor for selecting a readout row is provided in the pixel. 3. The solid-state imaging device according to claim 1, wherein a thickness of the gate insulating film of the amplification transistor is the smallest compared with a thickness of a gate insulating film of another transistor constituting the pixel.

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