JP2008182014A - Package substrate and manufacturing method thereof - Google Patents

Abstract

Provided is a package substrate which is excellent in airtight reliability, has no characteristic deterioration of functional elements, and can easily be sealed at a wafer level.
A package substrate of the present invention includes a first substrate having a functional element on one surface, and a second substrate having a first surface disposed so as to overlap the functional element of the first substrate. , And at least a sealing portion 15 sandwiched between the first substrate and the second substrate to form a space 51 at a position corresponding to the functional element and to surround the space. The first substrate includes a first conductive portion 13 that is electrically connected to the functional element. The second substrate includes a second conductive portion 23 disposed on one surface, a third conductive portion 25 disposed on the other surface, and a fourth conductive member that electrically connects the second conductive portion and the third conductive portion. A through electrode 26 is provided. The sealing portion is at a position enclosed in one surface of the second substrate when viewed from the direction in which the first substrate and the second substrate overlap, and the first conductive portion and the second conductive portion are formed by the solder bumps 16. Electrically connected.
[Selection] Figure 1

Description

  The present invention relates to a package substrate in which functional elements are sealed with two substrates and a method for manufacturing the same, and more particularly, to an improvement in the structure of a hermetically sealed package having a through wiring, and in particular, improving hermetic reliability. It has been made.

  2. Description of the Related Art In recent years, an electronic component in which a very small electromechanical mechanism, so-called MEMS (Micro Electromechanical System), is formed by applying a processing technology for forming fine wiring such as a semiconductor integrated circuit element on a main surface of a semiconductor substrate such as a silicon wafer. Is attracting attention and is being developed.

  Such microelectromechanical mechanisms include sensors such as accelerometers, pressure sensors, and actuators, micromirror devices with movable microscopic mirrors, optical devices, microchemical systems incorporating micropumps, etc. Prototypes and developments have been made that span a very wide range of fields.

  Further, as a structure of a semiconductor package in which functional elements such as a pressure sensor and an acceleration sensor are mounted, an airtight sealed package structure in which the functional elements are sealed with two substrates is widely used. For example, as shown in FIG. As described above, a wire bonding type semiconductor package is known. This hermetic package has a functional element 112 arranged on one surface, a surface wiring 113 for outputting a signal from the functional element 112, a wire bond 115 as a means for connecting the surface wiring 113 to another substrate, and A sealing material 116 is disposed around the functional element 112 of the functional element substrate 111 including the surface protective film 114 covering the surface wiring 113 so as to provide a gap, and the upper opening of the gap is closed with a cap substrate 121. Then, the functional element substrate 111 and the cap substrate 121 are joined by the sealing material 116 by heating to melt the sealing material 116, and the gap surrounding the functional element 112 is sealed. Is.

However, in the above hermetically sealed package structure, when two substrates are sealed, the sealing portion is located on the outer periphery of the substrate, and the cap substrate 121 is sealed on the functional element substrate 111 including the functional elements 112. When stopping, gas emitted from the cap substrate 121 or the like during heat treatment may enter the functional element portion in the gap, and the characteristics of the functional element 112 may be deteriorated.
In addition, in such a package structure, the surface wiring 113 that outputs a signal from the functional element 112 and the other substrate are connected by the wire bond 115. Therefore, the functional element substrate 111 on which the functional element 112 is mounted is a cap substrate. It is necessary to expand in the surface direction from 121. For this reason, it is difficult to reduce the size and stacking due to the problem of physical space. Further, since the wiring length of the wire bond 115 is long, it is not suitable for high-speed transmission.

In addition, a sealing material for joining the functional element substrate and the cap substrate is exposed on the side surface around the semiconductor package thus obtained, and the airtightness, moisture resistance, chemical resistance, etc. are not necessarily sufficient. However, there is a risk that stable operation and long life of the functional element cannot be obtained, and stacking is difficult in terms of reliability.
Furthermore, since the two substrates to be sealed are different in size, it is difficult to perform wafer-level sealing in which a large number of semiconductor packages are obtained by dicing to a predetermined size.

  Therefore, as means for solving the problems of miniaturization and lamination of semiconductor packages using wire bonds, a wiring metal film formed on the front surface side of the substrate and a metal film covering the inner surface of the recess opening on the back surface side of the substrate Is electrically connected through the contact hole portion, so that input / output of a sensor as a functional element is taken from the back side of the substrate, thereby eliminating the need for wire bonding on the front side ( Patent Document 1).

  Similarly, the first semiconductor chip and the second semiconductor chip disposed above the first semiconductor chip are electrically connected to extend from the end of the first semiconductor chip toward the end of the second semiconductor chip. There has been proposed a structure in which a space required for wire bonding is not required by being electrically connected by a conductive connecting portion, and the semiconductor package is miniaturized and densified (see Patent Document 2).

  Further, as means for reducing the size of the package in which the light receiving element is sealed, only the light receiving element formed on the semiconductor substrate is sealed with a light-transmitting member, and the light receiving element and the light receiving element on the semiconductor substrate are formed. There has been proposed a wiring portion that electrically connects an external connection terminal formed on a surface opposite to the surface (see Patent Document 3).

  Further, as means for reducing the thickness of a package such as a MEMS device, a thinning support plate is provided on the surface of the mounting substrate on which the device is mounted, and is fixed to the mounting substrate. Has been proposed (see Patent Document 4).

  In addition, as an example of a wafer level package structure in which a MEMS element or the like is packaged at a wafer level, a first substrate provided with a functional element having an input / output electrode, and a through-hole facing the input / output electrode of the functional element The input / output electrode and the first conductor are joined by the second conductor to the second substrate provided with the input / output terminal including the first conductor filled in the through hole. Further, the first conductor and the second substrate are bonded by a third conductor so as to surround the joint position of the input / output electrode and the first conductor, and the functional element is bonded. A hermetically sealed one has been proposed (see Patent Document 5).

  In addition, as an example of a wafer level package structure in which MEMS elements and the like are packaged at a wafer level, a first substrate and a second substrate are arranged so as to sandwich a functional element, and a seal glass is used between the two. There has been proposed a method in which solder is injected into a through hole provided in the second substrate (cap) (see Non-Patent Document 1).

  Furthermore, as an example of a wafer level package structure in which a MEMS element or the like is packaged at a wafer level, a first substrate and a second substrate are arranged so as to sandwich a functional element, and a seal ring (AuSn) is provided between the two. And a paste formed by filling a through hole provided in the second substrate (cap) with a paste (see Non-Patent Document 2).

However, in any of the above-described means, when a functional substrate is sealed by stacking another substrate on a substrate provided with a functional element, gas or the like emitted from the other substrate during heat treatment enters the sealed area of the functional element. In addition, there is a possibility that the characteristics of the functional element may be deteriorated, and sealing at the wafer level is difficult.
JP 09-116173 A JP 2004-296922 A JP 2004-335794 A JP 2005-166909 A JP 2005-251898 A Wafer-Level Packaging of MEMS Accelerometers with Through- Wafer Interconnections (2005 Electronic Components and Technology Conference) Wafer-Level Bonding of MEMS devices using ceramic LIDS (IPAC2005)

The present invention has been made in view of the above circumstances, and a first object thereof is to obtain a package substrate that is excellent in airtight reliability and has no deterioration in characteristics of functional elements.
A second object of the present invention is to provide a method of manufacturing a package substrate that facilitates hermetic sealing of functional elements at the wafer level.

  A package substrate according to claim 1 of the present invention includes a first substrate having a functional element on one surface, a second substrate having one surface disposed so as to overlap the functional element of the first substrate, And at least a sealing portion that is sandwiched between the first substrate and the second substrate and forms a space at a position corresponding to the functional element and surrounds the space. The sealing portion is located at a position included in one surface of the second substrate when viewed from the direction in which the first substrate and the second substrate overlap.

  A package substrate according to claim 2 of the present invention is the package substrate according to claim 1, wherein the first substrate is disposed on one surface of the package substrate and electrically connected to the functional element. The second substrate is electrically connected to the second conductive portion disposed on one surface thereof, the third conductive portion disposed on the other surface, and the second conductive portion and the third conductive portion. The first conductive portion and the second conductive portion are electrically connected to each other by solder bumps.

  A package substrate according to claim 3 of the present invention is the package substrate according to claim 2, wherein the sealing portion is made of a material having a melting point lower than that of the fourth conductive portion.

  The package substrate according to claim 4 of the present invention is the package substrate according to claim 2, wherein the sealing portion is made of the same material as the second conductive portion and the fourth conductive portion. To do.

  Moreover, in the manufacturing method of the package substrate according to claim 5 of the present invention, the first substrate provided with the functional element on one surface, and the one surface is arranged so as to overlap the functional element of the first substrate. A sealing portion disposed between the second substrate and the first substrate and the second substrate so as to form a space at a position corresponding to the functional element and to surround the space. And the sealing part is a method for manufacturing a package substrate in a position enclosed within one surface of the second substrate when viewed from the direction in which the first substrate and the second substrate overlap. Then, by forming the sealing portion, the space A is isolated from the outside, and at least the step A of joining the first substrate and the second substrate is provided.

  According to a sixth aspect of the present invention, there is provided a method for manufacturing a package substrate, the solder bump for electrically connecting the first conductive portion of the first substrate and the second conductive portion of the second substrate together with the step A. Step B is provided.

In the package substrate according to claim 1 of the present invention, when viewed from the direction in which the first substrate and the second substrate overlap, the sealing portion is arranged at a position included in one surface of the second substrate. Therefore, the sealing portion can prevent gas and the like from entering the sealing area of the functional element, and can improve the hermetic sealing performance of the package substrate. Moreover, since the sealing portion is not exposed on the peripheral side surface of the package substrate, it is excellent in airtightness, moisture resistance, chemical resistance, etc., and stable operation and long life of the functional element shall be obtained. Can do. Therefore, it is possible to obtain a package substrate that is excellent in airtight reliability and has no characteristic deterioration of the functional element.
Furthermore, it is possible to provide a package substrate that can be reduced in size and stacked with a reduced physical space without requiring spread in the surface direction.

  In the method for manufacturing a package substrate according to claim 5 of the present invention, by forming a sealing portion, a space serving as a sealing region for the functional element is isolated from the outside, and the first substrate and the second substrate are separated. Joining is also performed. Therefore, it is possible to prevent gas or the like emitted from another substrate during heat treatment from entering the sealing area of the functional element, improve the hermetic sealing performance of the package substrate, and bond the first substrate to the second substrate. It is possible to easily provide a sealing portion that can be used. Therefore, it is possible to simplify the method for manufacturing a package substrate in which functional elements are easily sealed at the wafer level and the characteristics of the functional elements are good.

The present invention will be described below with reference to the drawings based on the best mode.
FIG. 1 is a cross-sectional view schematically showing an example of a package substrate according to the present invention. In other embodiments to be described later, the same reference numerals are used for the same components as in the present embodiment, and the description thereof will be omitted.

  As shown in FIG. 1, the package substrate 10 in this embodiment has a first substrate 11 provided with a functional element 12 on one surface, and one surface arranged so as to overlap the functional element 12 of the first substrate 11. The second substrate 21 is sandwiched between the first substrate 11 and the second substrate 21 so as to form a space 51 at a position corresponding to the functional element 12 and surround the space 51. And at least a sealing portion 15 arranged as described above.

In addition, the package substrate 10 in the present embodiment includes the first conductive portion 13 that is disposed on one surface of the first substrate 11 and is electrically connected to the functional element 12. The substrate 21 electrically connects the second conductive portion 23 disposed on one surface thereof, the third conductive portion 25 disposed on the other surface, and the second conductive portion 23 and the third conductive portion 25. Each of the through electrodes 26 is formed of a fourth conductive portion connected to the.
Further, the first conductive portion 13 and the second conductive portion 23 are electrically connected by solder bumps 16.

  In the package substrate 10 according to this embodiment, the sealing portion 15 is included in one surface of the second substrate 21 when viewed from the direction in which the first substrate 11 and the second substrate 21 overlap. It is in position.

By joining the first substrate 11 and the second substrate 21 by the sealing portion 15, the hermetic sealing property in the space 51 can be improved. In addition, when the sealing portion 15 is located in one surface of the second substrate 21 when viewed from the direction in which the first substrate 11 and the second substrate 21 overlap, the first conductive portion 13 is provided. The solder bumps 16 that electrically connect the second conductive portion 23 and the second conductive portion 23 are positioned outside the sealing portion 15, and the first substrate 11 and the second substrate 21 are connected to the functional element 12 by the sealing portion 15. The surrounding space 15 is joined in a state of being isolated from other regions.
Therefore, it is possible to suppress the gas generated during the hot press processing for joining the first substrate 11 and the second substrate 21 from entering the space 51, and to have a package structure with no characteristic deterioration. Moreover, since the sealing portion is not exposed on the peripheral side surface of the package substrate, it is excellent in airtightness, moisture resistance, chemical resistance, etc., and stable operation and long life of the functional element shall be obtained. Can do.

The first substrate 11 is formed by forming a passivation film (not shown) and a functional element 12 requiring hermetic sealing on the surface of a base material made of a semiconductor material such as Si or GaAs. The passivation film is an insulating film formed by passivation made of SiN, SiO ₂ or the like. This passivation film can be formed by, for example, the LP-CVD method, and the film thickness is, for example, 0.1 to 0.5 μm.

  The functional element 12 is a place responsible for the central function of the device. For example, in a MEMS device such as a pressure sensor or an acceleration sensor, the functional element 12 is an area for converting a physical change applied to the first substrate 11 into an electrical signal. It is the three-dimensional structure part of the MEMS sensor corresponding to.

  The first conductive portion 13 is a surface wiring layer for transmitting an electrical signal from the functional element 12, and for example, a conductive material such as Al is preferably used. The first conductive portion 13 is covered with a surface protective film 14. Examples of the material forming the surface protective film 14 include SiN.

  The sealing portion 15 is a member arranged to form a space 51 at a position corresponding to the functional element 12 and to surround the space 51. The sealing portion 15 can be formed by a known method such as solder printing. For example, a material such as Au—Sn solder or low-melting glass is preferably used. Moreover, the sealing part 15 joins the 1st board | substrate 11 and the 2nd board | substrate 21 at a wafer level.

  Further, the sealing portion 15 may be made of a material having a melting point lower than that of the through electrode 26. Thereby, the remelting of the through electrode 26 can be prevented when the first conductive portion 13 and the second conductive portion 23 are connected with the hot press process for joining the first substrate 11 and the second substrate 21.

  Furthermore, the sealing portion 15 may be made of the same material as the second conductive portion 23 and the through electrode 26. Thereby, since the flow of the member in a connection part can be made the same at the time of the connection of the 1st electroconductive part 13 and the 2nd electroconductive part 23 accompanying the hot press process which joins the 1st board | substrate 11 and the 2nd board | substrate 21. In addition, no bridge or the like occurs, and the connection reliability can be improved.

The solder bump 16 electrically connects the first conductive portion 13 and the second conductive portion 23 and can be formed by a known method such as solder printing or paste printing. A metal thin film (not shown) formed by sputtering or the like for the purpose of improving adhesion and preventing metal diffusion at the interface between the solder bump 16 and the first conductive portion 13 and the solder bump 16 and the second conductive portion 23, respectively. ) May be inserted. Examples of the material forming the metal thin film include Ti, Ni, Au, and the like.
In addition, when the sealing part 15 has electroconductivity, the solder bump 16 can also be formed in a lump by the same material and forming method as the sealing part 15.

The second substrate 21 may be made of an insulating material such as glass in addition to a substrate formed of a semiconductor material such as Si or GaAs on a surface of a passivation film (not shown).
The second substrate 21 may have a cavity 21 </ b> A that forms part of the space 51. By having the cavity 21A, the height can be reduced, and a reduction in height can be achieved.
The second substrate 21 may include a circuit unit 24 for the purpose of driving or controlling the first substrate 11.

The second substrate 21 is a member for protecting the functional element 12 provided on the first substrate 11, supported by the first substrate 11 through the sealing portion 15, and above the functional element 12. The space 51 is arranged. The first substrate 11 and the second substrate 21 are bonded via the sealing portion 15, so that the space 51 including the functional element 12 is hermetically sealed.
Note that an underfill may be provided between the first substrate 11 and the second substrate 21 with a resin or the like for the purpose of improving reliability.

The space 51 is an area surrounded by the first substrate 11, the sealing portion 15, and the second substrate 21 so as to form a space at a position corresponding to the functional element 12, and secures an operation area of the functional element 12. It is. Therefore, this space 51 is isolated from the external space.
The space 51 can be obtained by forming the cavity 21A in the second substrate 21 by a method such as dry etching or wet etching.

  The second conductive portion 23 is a rewiring layer disposed on one surface of the second substrate 21, and solder bumps 16 are provided to electrically connect the first conductive portion 13 and the second conductive portion 23. Outside the position where the second substrate 21 is located, the second substrate 21 is electrically connected to the through electrode 26 formed in the hole 22 penetrating from one surface to the other surface. For the second conductive portion 23, a conductive material such as Cu, Al, AuSn, or the like is preferably used. Further, the second conductive portion 23 is covered with a surface protective film 27. Examples of the material forming the surface protective film 27 include SiN and epoxy resin.

  The through electrode 26 is a wiring penetrating the second substrate 21, and similarly to the second conductive portion 23, for example, a conductive material such as Cu, Al, AuSn is preferably used. For example, the through electrode 26 is formed by filling the hole 22 formed through one surface of the second substrate 21 with the other surface by the molten metal suction method or the printing method. (See JP 2004-95849 A).

  The third conductive portion 25 is a rewiring layer disposed on the other surface of the second substrate 21. For example, a conductive material such as Al is preferably used.

  Here, the second conductive portion 23 is disposed outside the sealing portion 15, that is, outside the hermetically sealed space 51, so that the first conductive member 23 is attached to the first substrate 11 and the second substrate 21. When the one conductive portion 13 and the second conductive portion 23 are connected, the degas generated from the surface protective film 27 covering the second conductive portion 23 and the conductivity at the connection portion between the through electrode 26 and the third conductive portion 25 are reduced. Since there is no concern about the leaking damage, the airtightness in the space 51 and the connection reliability of the wiring part can be greatly improved.

  Therefore, the package substrate 10 in the present embodiment is emitted from the functional element 12 through the first conductive portion 13, the solder bump 16, the second conductive portion 23, the through electrode 26, and the third conductive portion 25. An electric signal can be transmitted to the circuit unit 24 or taken out to an external substrate, and the signal can be transmitted at high speed.

In addition, the package substrate 10 having the above-described configuration prepares the first substrate 11 and the second substrate 21 as described above, as shown in FIG.
Next, as shown in FIG. 2B, the space 51 is sandwiched between the first substrate 11 and the second substrate 21, and a space 51 is formed at a position corresponding to the functional element 12. 51 is disposed so as to surround 51, and a solder bump material 16a is disposed between the first conductive portion 13 of the first substrate 11 and the second conductive portion 23 of the second substrate 21, The first substrate 11 is disposed so as to overlap with the functional element 12 with a certain distance and facing the one surface of the second substrate 21.
Then, the first substrate 11 and the second substrate 21 in a superposed state are subjected to a hot press process to melt the sealing member 15a, thereby isolating the space 51 from the outside, and the first substrate and the first substrate By forming the sealing portion 15 for joining the two substrates, and forming the solder bump 16 that electrically connects the first conductive portion and the second conductive portion by melting the solder bump material 16a The package substrate 10 shown in FIG. 1 can be obtained.

  Thereby, in the manufacturing method according to the present invention, the bonding of the first substrate 11 and the second substrate 21 and the electrical connection of the first conductive portion 13 and the second conductive portion 23 can be performed collectively, The manufacturing process can be simplified. Moreover, in the manufacturing method according to the present invention, a plurality of semiconductor packages can be collectively manufactured at the wafer level and then separated into individual semiconductor packages.

Moreover, as shown in FIG. 2, this invention can also be set as the package substrate which takes out an electrical signal by a wire bond.
FIG. 2 is a plan view schematically showing a second structure of the package substrate according to the present invention.
As shown in FIG. 2, the package substrate 20 in the present embodiment has a first substrate 11 provided with a functional element 12 on one surface, and one surface arranged so as to overlap the functional device 12 of the first substrate 11. The second substrate 21 is sandwiched between the first substrate 11 and the second substrate 21 so as to form a space 51 at a position corresponding to the functional element 12 and surround the space 51. And at least a sealing portion 15 arranged as described above.

Further, the package substrate 20 in the present embodiment includes the first conductive portion 13 that is disposed on one surface of the first substrate 11 and is electrically connected to the functional element 12. The substrate 21 electrically connects the second conductive portion 23 disposed on one surface thereof, the third conductive portion 25 disposed on the other surface, and the second conductive portion 23 and the third conductive portion 25. Each of the through electrodes 26 is formed of a fourth conductive portion connected to the.
Further, the first conductive portion 13 and the second conductive portion 23 are electrically connected by solder bumps 16.
The first conductive portion 13 is covered with a surface protective film 14. Examples of the material forming the surface protective film 14 include SiN. Further, the second conductive portion 23 is covered with a surface protective film 27. Examples of the material forming the surface protective film 27 include SiN and epoxy resin.

The package substrate 20 according to the present embodiment includes a wire bond 52 that extracts an electrical signal from the third conductive portion 25.
As a result, the electrical signal emitted from the functional element 12 disposed on the first substrate 11 is extracted from the other surface of the second substrate 21 by the wire bond 52 in a state where the area of the package substrate is reduced. Can do.

Moreover, as shown in FIG. 3, this invention can also be used as a package substrate which enables solder bump mounting.
FIG. 3 is a plan view schematically showing a third structure of the package substrate according to the present invention.
As shown in FIG. 3, the package substrate 30 according to the present embodiment has a first substrate 11 provided with a functional element 12 on one surface, and one surface arranged so as to overlap the functional device 12 of the first substrate 11. The second substrate 21 is sandwiched between the first substrate 11 and the second substrate 21 so as to form a space 51 at a position corresponding to the functional element 12 and surround the space 51. And at least a sealing portion 15 arranged as described above.

In addition, the package substrate 30 in the present embodiment includes the first conductive portion 13 that is disposed on one surface of the first substrate 11 and is electrically connected to the functional element 12. The substrate 21 electrically connects the second conductive portion 23 disposed on one surface thereof, the third conductive portion 25 disposed on the other surface, and the second conductive portion 23 and the third conductive portion 25. Each of the through electrodes 26 is formed of a fourth conductive portion connected to the.
Further, the first conductive portion 13 and the second conductive portion 23 are electrically connected by solder bumps 16.
The first conductive portion 13 is covered with a surface protective film 14. Examples of the material forming the surface protective film 14 include SiN. Further, the second conductive portion 23 is covered with a surface protective film 27. Examples of the material forming the surface protective film 27 include SiN and epoxy resin.

In the package substrate 30 according to this embodiment, the third conductive portion 25 is covered, and the surface protective layer 28 having an opening 28a exposing a part of the third conductive portion 25 and the surface protective layer 28 are covered. And a surface protective layer 50 having a fifth conductive part 29 electrically connected to the third conductive part 25 through the opening 28a, an opening 50a exposing a part of the fifth conductive part 29, and the opening. A solder bump 53 electrically connected to the fifth conductive portion 29 through the portion 50a is provided.
Moreover, as a material which makes the surface protective layer 28 and the surface protective layer 50, SiN, an epoxy resin, etc. can be mentioned, for example.

  As a result, in a state where the area of the package substrate is reduced, an electrical signal emitted from the functional element 12 disposed on the first substrate 11 is taken out by the solder bump 16 and electrically connected to an external substrate (not shown). Can be connected.

In addition, as shown in FIG. 4, the present invention can be a package substrate that realizes stacking of ICs.
FIG. 4 is a plan view schematically showing a fourth structure of the package substrate according to the present invention.
As shown in FIG. 4, the package substrate 40 according to the present embodiment has a first substrate 11 provided with a functional element 12 on one surface, and one surface arranged so as to overlap the functional device 12 of the first substrate 11. The second substrate 21, the third substrate 31 provided on one surface of the second substrate 21 so as to overlap the circuit portion 24, the first substrate 11, and the second substrate 21. A first sealing portion 15A sandwiched between the substrate 21 and disposed so as to form the first space 51A at a position corresponding to the functional element 12 and surround the first space 51A; It is sandwiched between the second substrate 21 and the third substrate 31, and is arranged so as to form the second space 51B at a position corresponding to the circuit portion 24 and so as to surround the second space 51B. And a second sealing portion 15B.

In addition, the package substrate 40 in the present embodiment includes the first conductive portion 13 that is disposed on one surface of the first substrate 11 and is electrically connected to the functional element 12. The substrate 21 electrically connects the second conductive portion 23 disposed on one surface thereof, the third conductive portion 25 disposed on the other surface, and the second conductive portion 23 and the third conductive portion 25. Each of the through electrodes 26 is formed of a fourth conductive portion connected to the.
Further, the first conductive portion 13 and the second conductive portion 23 are electrically connected by a first solder bump 16A.
The first conductive portion 13 is covered with a surface protective film 14. Examples of the material forming the surface protective film 14 include SiN. Further, the second conductive portion 23 is covered with a surface protective film 27. Examples of the material forming the surface protective film 27 include SiN and epoxy resin.

The third substrate 31 has a fifth conductive portion 33 disposed on one surface thereof, a circuit portion 34 disposed on the other surface, and a sixth conductive portion 35 electrically connected to the circuit portion 34. And a through electrode 36 composed of a seventh conductive portion for electrically connecting the fifth conductive portion 33 and the sixth conductive portion 35 to each other.
Further, the third conductive portion 23 and the fifth conductive portion 33 are electrically connected by a second solder bump 16B.
The fifth conductive portion 33 is covered with a surface protective film 37. Examples of the material forming the surface protective film 37 include SiN and epoxy resin.

  As a result, in a state where the area of the package substrate is reduced, the functional element 12 (MEMS sensor) is hermetically sealed at the wafer level, an electrical signal is extracted from the functional element 12, and further to the functional element 12. The stacking of ICs can also be realized.

  The present invention can be applied to a semiconductor package in which functional elements are hermetically sealed with two substrates such as a micro electro mechanical mechanism (MEMS) that functions as a sensor such as an acceleration sensor, a pressure sensor, and an actuator.

It is a figure which shows an example of the package board | substrate which concerns on this invention. It is a figure which shows an example of the manufacturing method of the package board | substrate which concerns on this invention. It is a figure which shows another example of the package board | substrate which concerns on this invention. It is a figure which shows another example of the package board | substrate which concerns on this invention. It is a figure which shows another example of the package board | substrate which concerns on this invention. It is a figure which shows an example of the conventional package substrate.

Explanation of symbols

  10, 20, 30, 40 Package substrate, 11 First substrate, 12 Functional element, 13 First conductive portion, 14 Surface protective film, 15 Sealing portion, 16 Solder bump, 21 Second substrate, 21A Cavity, 22 Hole , 23 Second conductive portion, 24 Circuit portion, 25 Third conductive portion, 26 Through electrode (fourth conductive portion), 27 Surface protective film.

Claims (6)

A first substrate with functional elements on one side;
A second substrate on which one surface is arranged so as to overlap the functional element of the first substrate;
A sealing portion that is sandwiched between the first substrate and the second substrate, forms a space at a position corresponding to the functional element, and is disposed so as to surround the space;
Comprising at least
The package substrate, wherein the sealing portion is in a position enclosed within one surface of the second substrate when viewed from the direction in which the first substrate and the second substrate overlap. The first substrate is disposed on one surface of the first conductive portion electrically connected to the functional element, the second substrate is disposed on one surface of the second conductive portion, and the like. A through-electrode comprising a third conductive part disposed on the other surface and a fourth conductive part for electrically connecting the second conductive part and the third conductive part,
The package substrate according to claim 1, wherein the first conductive portion and the second conductive portion are electrically connected by solder bumps.   The package substrate according to claim 2, wherein the sealing portion is made of a material having a melting point lower than that of the fourth conductive portion.   The package substrate according to claim 2, wherein the sealing portion is made of the same material as the second conductive portion and the fourth conductive portion. A first substrate having a functional element on one surface, a second substrate having one surface disposed so as to overlap the functional element of the first substrate, and between the first substrate and the second substrate And a sealing portion disposed so as to form a space at a position corresponding to the functional element and to surround the space, the sealing portion including the first substrate A method of manufacturing a package substrate at a position enclosed in one surface of the second substrate as seen from the direction in which the second substrate overlaps,
A method of manufacturing a package substrate, comprising at least a step A of isolating the space from the outside by forming the sealing portion and also joining the first substrate and the second substrate.   The step B of providing a solder bump for electrically connecting the first conductive portion of the first substrate and the second conductive portion of the second substrate together with the step A is performed. Package substrate manufacturing method.

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