JP2008181936A - Method for detecting junction position - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for detecting the position of a metallurgical PN junction in the semiconductor substrate of a micro semiconductor device by predicting and controlling the device characteristics of a transistor precisely and performing failure analysis of a specific part. <P>SOLUTION: The method for detecting the junction position of a P-type impurity region doped with P-type impurities and an N-type impurity region doped with N-type impurities on a semiconductor substrate comprises a step for exposing the cross-section becoming an observation object from the semiconductor substrate, a step for cleaning the cross-section, a step for depositing a silicide on the cross-section, and a step for detecting the junction interface by observing the grain size of the silicide. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for detecting a metallurgical PN junction position in a minute region in a semiconductor device.

In recent years, with the development of semiconductor microfabrication technology, the size of elements such as transistors used in ICs (Integrated Circuits) has been further miniaturized.
The gate length of the transistor is manufactured using advanced process technology and is already 50 nm or less, and it is certain that it will be further reduced in the future.
In this way, in order to fabricate minute devices including transistors constituting an IC and operate them normally, the profile of impurities doped on the semiconductor substrate on which the device is formed and the metallurgical PN junction It is necessary to know the position accurately.

That is, when the impurity doped in the semiconductor substrate is distributed deeper than intended because the transistor is formed, the short channel effect becomes remarkable, and a problem that desired electrical characteristics cannot be obtained occurs. Therefore, it is necessary to grasp the impurity profile of the semiconductor substrate in the process step.
Also, when a defect occurs in a semiconductor device, the cause of the defect and the defective part are identified and fed back to the process process by knowing the impurity profile and metallurgical bonding position of the specific part in performing the defect analysis. It becomes possible.

Furthermore, when the design impurity profile and electrical characteristics of next-generation transistors are predicted using process / device simulation, the impurity profile and metallurgical junction position in the semiconductor substrate used in existing processes It becomes important data to obtain a highly accurate simulation result.
The reason for this is that the impurity profile of the next-generation transistor cannot be determined unless the extent to which the impurity doped into the semiconductor substrate by ion implantation technology is diffused into the semiconductor substrate by a subsequent heat treatment heated at a predetermined temperature. It is not possible to correctly select the diffusion model to be used when simulating.

That is, unless the simulation result and the measured data in the experimental result can be accurately combined, the accuracy of the simulation model cannot be increased, and as a result, the electrical characteristics of the transistor cannot be accurately predicted.
From the above, detecting the metallurgical PN junction position in the semiconductor substrate of fine semiconductor devices with high accuracy predicts device characteristics such as transistors such as bipolar and MOS (Metal-Oxide-Semiconductor). It is an important process in controlling and analyzing defects.

When a semiconductor device is formed on a semiconductor substrate, a process of injecting and diffusing impurities is performed. There are several elemental analysis methods for knowing the distribution of doped impurity elements in the semiconductor substrate.
Hereinafter, a metallurgical PN junction position detection method according to a conventional method will be described with reference to the drawings. As the detection method, the table in FIG. 4 summarizes analysis methods often used for elemental analysis of semiconductor devices.
As shown in the table of FIG. 4, elemental analysis methods are roughly classified into three types depending on the probe used.

Here, representative examples of methods using electrons as probes include AES (Auger Electron Spectroscopy) and EPMA (Electron Probe MicroAnalysis).
The AES detects Auger electrons generated by the interaction between the incident electron beam and the sample, and the EPMA detects characteristic X-rays emitted from the sample by the incident electron beam, thereby detecting the element existing on the sample surface. Perform analysis.
When detecting an impurity profile in a semiconductor substrate or a metallurgical PN junction position in a semiconductor device, it is possible to obtain a one-dimensional or two-dimensional element distribution by scanning an incident electron beam.

A typical method using photons as probes is XPS (X-ray Photoelectron Spectroscopy).
This XPS analysis method irradiates a sample surface placed in an ultra-high vacuum with X-rays, causes electrons existing on the sample surface to jump out of the sample, and determines the kinetic energy and intensity of the emitted electrons. By measuring the electron binding energy and energy level specific to the X-ray irradiated part and analyzing the element, the element distribution of the doped impurity is detected, and the impurity profile and metallurgical characteristics are measured. This is a method for detecting the PN junction position.

Typical techniques using ions as probes include SIMS (Secondary Ion Mass Spectroscopy) and RBS (Rutherford Back Scattering).
By irradiating the sample surface with ions, some of the ions are backscattered by atoms on the sample surface, and the remaining ions lose energy while repeating collisions inside the sample. At this time, atoms on the sample surface are sputtered and jump out of the sample in a neutral or ionic state. SIMS is a method for performing elemental analysis of the sample surface by analyzing the mass of ions that have jumped out of the sample.
RBS is a technique for analyzing the mass, density, and the like of nuclei on the sample surface by measuring the energy of ions that have been backscattered (Rutherford scattering) very slightly among the incident ions.

  When using SIMS or XPS to inspect the impurity profile or metallurgical PN junction position in the semiconductor substrate of a semiconductor device, the object to be inspected is sputter-etched by ion milling or the like from the front or back surface of the sample. By detecting the number of atoms present in the predetermined region and the bonding state of electrons, the impurity profile and the metallurgical PN junction position can be obtained.

As another method for obtaining an impurity profile in a semiconductor substrate, there is a method in which after cleaving a sample, wet etching is performed and the surface is observed with an electron microscope.
FIG. 5A is a cross-sectional SEM (Scanning Electron Microscopy) image when a sample in which an N-channel MOS (Metal Oxide Semiconductor) transistor is formed on a silicon substrate is cleaved and then wet-etched with a chemical solution containing hydrofluoric acid. FIG. 5B is a schematic diagram showing a cross-sectional structure of a cleaved portion obtained by deforming the SEM image of FIG. 6A is a cross-sectional SEM image when the sample in which the P-channel MOS transistor is formed is cleaved and then wet-etched with a chemical solution containing hydrofluoric acid. FIG. 6B is a cross-sectional SEM image. It is a schematic diagram which shows the cross-section of the cleavage part which deform | transformed SEM image of this.
FIG. 5A is an N-channel MOS transistor, and FIG. 6A is a cross-sectional SEM image of a P-channel MOS transistor. Since the etching rate of the region doped with arsenic (As) or boron (B) at a high concentration is high, the high concentration region is selectively removed. As a result, the metallurgical junction position of the diffusion layer portion of the transistor can be roughly grasped.

There is also a technique for obtaining an impurity profile and a metallurgical PN junction position by utilizing the fact that the structural stability of an electric field assisted oxide film formed by a scanning probe microscope strongly depends on the conductivity type of the substrate (for example, Patent Document 1).
That is, the electric field assisted oxide film formed on the P-type conductive region and the electric field assisted oxide film formed on the N-type conductive region differ in the structural stability of the film with respect to heat. A difference occurs in the amount of change, and unevenness occurs at the PN junction. For this reason, it is possible to easily specify the PN junction position with high accuracy by measuring the surface irregularities using a scanning probe microscope after the heat treatment.
JP 2001-237290 A

However, in the method described above, each method has the following problems when detecting the metallurgical PN junction position.
When obtaining a one-dimensional or two-dimensional impurity profile using elemental analysis such as SIMS or XPS, the number of atoms existing in a certain region, the number of electrons, Detect the binding state.
For this reason, it is very difficult in principle to analyze a specific layout pattern (for example, a specific transistor) or a minute region (for example, an impurity profile at the drain end).
That is, the impurity profile and the metallurgical PN junction position are obtained in a pseudo manner by performing measurement using a sample that has not been patterned.
Therefore, there is a high possibility that the actual pattern has a different profile, and it has been difficult to obtain an accurate impurity profile and metallurgical bonding position.

  In EPMA using an electron beam as a probe, it is possible to analyze an element existing in a minute region. However, in order to measure the distribution, it is necessary to perform multipoint measurement. When performing a general evaluation, it is necessary to increase the number of measurement points, which is not suitable for obtaining an impurity profile and a metallurgical PN junction position.

Moreover, when using the above-described wet etching as a method for obtaining the metallurgical PN junction position in the semiconductor substrate, it is difficult to control the etching amount of the silicon substrate, and the etching is performed more than the actual doping profile. There are many.
As shown in the SEM image shown in FIG. 6B, since the wet etching rate of the diffusion layer portion of the P-channel MOS transistor is high, it is very difficult to specify the metallurgical PN junction position.
In addition, if there is a crystal defect, the region is also etched, so it is often etched more than the impurity profile that is actually doped with impurities, and the correct impurity profile and metallurgical PN junction position must be obtained. Is difficult.

  Also, in the method using a scanning probe microscope, it is possible to analyze an element present in a minute region, but in order to measure its distribution, since multipoint measurement must be performed, two-dimensional measurement is performed. When performing a general evaluation, it is necessary to increase the number of measurement points, which is not suitable for obtaining an impurity profile and a metallurgical PN junction position.

As described above, in the conventional example, since an accurate actual impurity profile in the semiconductor substrate cannot be grasped, the actual measurement value and the simulation result cannot be compared, and as a result, an accurate simulation model cannot be obtained.
Therefore, the conventional example has a problem that the accuracy of the simulation result of the device structure cannot correspond to the process used for device creation, and only low-accuracy simulation can be performed.
Further, in the conventional example, when performing defect analysis, an accurate impurity profile of a specific part cannot be obtained. Therefore, the accuracy of defect analysis is low and it is difficult to identify the cause of the defect.

  The present invention has been made in view of such circumstances, and accurately predicts and controls device characteristics of transistors and the like in a semiconductor substrate in a fine semiconductor device capable of performing failure analysis of a specific portion. It is an object of the present invention to provide a method for detecting the metallurgical PN junction position.

  The method for detecting a junction position according to the present invention is a method for detecting a junction position between a P-type impurity region doped with a P-type impurity and an N-type impurity region doped with an N-type impurity in a semiconductor substrate. A cross-section exposure process for exposing a cross-section to be observed from, a cross-section processing process for cleaning the cross-section, a deposition process for depositing silicide on the cross-section, and observing the grain size of the silicide, And a detecting step for detecting.

  The junction position detection method of the present invention is characterized in that, in the detection step, the junction interface is detected based on a difference in silicide grain size between the P-type impurity region and the N-type impurity region.

  The bonding position detection method of the present invention is characterized in that the semiconductor substrate is a silicon substrate.

  The junction position detection method of the present invention is characterized in that the silicide is tungsten silicide.

  The method for detecting a junction position according to the present invention is characterized in that, in the deposition step, a chemical vapor deposition method is used for the silicide.

  In the method for detecting a bonding position according to the present invention, tungsten hexafluoride and silane or cyclosilane are used as the gas used when depositing the silicide in the deposition step.

  The junction position detection method of the present invention is characterized in that, in the deposition step, the silicide is deposited with a thickness of 7 nm or less.

As described above, according to the present invention, the metallurgical PN junction position of a specific portion of a fine semiconductor device is scanned by the difference in the grain size of silicide in the P-type impurity region and the N-type impurity region. By observation with a scanning electron microscope (hereinafter abbreviated as SEM), it can be easily identified two-dimensionally and visually.
Therefore, according to the present invention, it is possible to fit the impurity diffusion amount (and profile) in the semiconductor substrate on which the diffusion layer is actually patterned and the device, and the simulation result, and obtain the fitting result. Accurate and accurate diffusion model (diffusion model consisting of parameters such as ion type, ion implantation amount, implantation energy, diffusion temperature, diffusion time, etc.) to accurately predict and control device characteristics of next-generation transistors It becomes possible.
In addition, according to the present invention, since the metallurgical bonding position of a minute region in a semiconductor substrate of a device can be grasped two-dimensionally with high accuracy, a defect that has occurred at a specific part of the device inside the IC. It is also possible to analyze the cause.

  Hereinafter, a method for detecting a joining position according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a conceptual diagram showing the order of steps in a method for detecting a joining position according to the embodiment. FIG. 2 is a planar SEM image of a tungsten silicide film formed by CVD (Chemical Vapor Deposition) on a cross section of an N-type and P-type doped silicon substrate, and the cross section observed in plan view. . FIG. 3 is a schematic diagram of a sample cross-sectional structure after the sample is processed according to the process flow of FIG. In FIG. 3, an N-channel MOS transistor 17 and a P-channel MOS transistor 18 are shown side by side for convenience. The SEM image inserted in FIG. 3 observes the surface states of the N type diffusion layer 5, the P type diffusion layer 9, the N well 3, and the P well 2 after processing the sample according to the flow of FIG. 1 of the present embodiment. It is a thing.

Hereinafter, according to the flow of FIG. 1, the process of detecting the joining position of the present embodiment will be described.
In step S1, in order to produce the sample 12 to be observed, a region to be analyzed for impurity profiling or metallurgical PN junction position from the semiconductor substrate, in this embodiment, the silicon substrate 1, is used using a diamond cutter or the like. By slicing, cleaving, or using focused ion beam (FIB), the observation surface (hereinafter referred to as a cross section) 13 is exposed.

Next, in step S2, a chemical solution having a high selectivity between the silicon substrate 1 and the oxide film, for example, hydrogen fluoride (hereinafter referred to as hydrofluoric acid) is used to selectively remove the natural oxide film formed on the cross section 13. And water are removed by washing the sample 12 with a diluted hydrofluoric acid (DHF) solution diluted to 1: 100 (HF: H ₂ O) at a solution temperature of 20 ° C. and a treatment time of 30 seconds. .
Further, the surface of the cross section 13 may be polished and planarized by CMP (Chemical Mechanical Planarization) with respect to the cross section 13 of the sample 12, and then the above-described chemical polishing for removing the natural oxide film may be performed.

Next, in step S3, a tungsten silicide film 14 is deposited on the cross section 13 by a chemical vapor deposition (CVD) method.
Here, tungsten hexafluoride (WF ₆ ) and silane (SiH ₄ ) or dichlorosilane (SiH ₂ Cl ₂ ) are used as a material for forming the tungsten silicide film 14. In the present embodiment, as the film conditions, for example, the substrate temperature is 560 ° C., the degree of vacuum is 33.3 Pa, the flow rate of WF ₆ is 2.5 SCCM, the flow rate of SiH ₂ Cl ₂ is 900 SCCM, and the tungsten silicide film 14 is formed. Deposit to a thickness of 5 nm.

  At this time, if the tungsten silicide film 14 is too thick, the difference in grain size cannot be clearly observed. From the experiment, if the thickness is 7 nm or less, the type of impurities and the concentration of impurities are reflected in the grain size by the underlying impurities to be deposited. That is, when the above-described film formation conditions are used, the base dependency appears in the growth method of the tungsten silicide film 14. As described above, in this embodiment, the ion species doped in the base (cross section 13) is either an N-type impurity (P: phosphorus, As: arsenic) or a P-type impurity (B: boron). Therefore, by utilizing the difference in the formation of nuclei (nuclei for growing as grains) at the time of film formation of the tungsten silicide 14, the P-type impurity region and the N-type impurity region (or non-doped region) are formed. Detect the bonding interface.

Next, in step S4, the cross section 13 is observed with an SEM. An observation example is shown in FIG. FIG. 2 shows a tungsten silicide film 14 formed on the cross section 13 of the N-type and P-type doped silicon substrate 1 by the CVD method, and this cross section is observed by SEM.
In the cross section 13, in the silicon region doped with the N-type impurity, it can be confirmed that the formed tungsten silicide film 15 has a small grain size and a high density of grain formation, and is a continuous film.

On the other hand, in the cross section 13, the grain size of the tungsten silicide film 14 formed in the silicon region doped with the P-type impurity is larger than that in the silicon region doped with the N-type impurity. Further, the density at which the grains of the tungsten silicide film 14 are formed is sparse compared to the silicon region doped with N-type impurities. In the silicon region doped with the P-type impurity, the tungsten silicide film 16 becomes an independent discontinuous film in which each grain is separated from other grains.
That is, as described above, by determining the boundary between regions having different grain sizes from the difference in grain size and density of tungsten silicide formed on the P-type impurity region and the N-type impurity region, The junction interface between the impurity region and the N-type impurity region is detected, and the position of the PN junction is detected from the interface.

As described above, after the tungsten silicide film 14 is formed on the cross section 13 and the film quality of the formed tungsten silicide film 14 is observed by SEM, as shown in the schematic cross section of FIG. It can be visually confirmed that the film quality state (grain growth state) of the tungsten silicide film 14 is greatly different between the doped region and the region doped with the P-type impurity, and that there is a difference in grain size.
In FIG. 3, the grains of the tungsten silicide film of each impurity layer when the cross sections of the N-channel MOS transistor 17 and the P-channel MOS transistor 18 are observed with an SEM are shown as SEM images.

An N-channel MOS transistor 17 includes an N-type diffusion layer 5 of an N-type impurity serving as a source and a drain, a gate mask nitride film 8, a gate tungsten 7 and a gate polysilicon in a P well 2 formed in a silicon substrate 1. 6 and the like, and is separated from other adjacent transistors by STI (Shallow Trench Isolation) 4.
Here, the grain size of the tungsten silicide film 14 (tungsten silicide film 15 deposited in the N-type impurity region) formed on the surface of the N-type impurity layer 5 is the same as that of the tungsten silicide film 14 ( The tungsten silicide film 16) deposited in the P-type impurity region is smaller than the grain size and densely formed. As a result, the metallurgical PN junction position between the P well 2 and the N-type impurity layer 5 can be accurately recognized by the SEM image.

Similarly, a P-channel MOS transistor 18 includes a P-type diffusion layer 9 of P-type impurities serving as a source and a drain, a gate mask nitride film 8, a gate tungsten 7 and an N well 3 formed in the silicon substrate 1. It is formed of gate polysilicon 6 or the like and is separated from other adjacent transistors by STI4.
Here, the grain size of the tungsten silicide film 14 (tungsten silicide film 16 deposited in the P-type impurity region) formed on the surface of the P-type impurity layer 9 is the same as that of the tungsten silicide film 14 ( The tungsten silicide film 15) deposited in the N-type impurity region is larger than the grain size and is formed sparsely. As a result, the metallurgical PN junction position between the N well 3 and the P-type impurity layer 9 can be accurately recognized by the SEM image.

Accordingly, the boundary between the P-type impurity and the N-type impurity, that is, the metallurgical PN junction position can be clearly observed.
That is, according to the present invention, when a tungsten silicide film is formed by the CVD method, the impurity profile is accurately reflected in the cross section of the sample by utilizing the grain size of the growing grain and the base dependency of the density to be formed. The boundary of the tungsten silicide film can be made visually.

  As described above, it is possible to detect a profile including the impurity concentration of the diffusion layer diffused by ion implantation into the metallurgical PN junction position and the semiconductor substrate at a specific minute portion. From this observation result, the failure cause of the semiconductor device and the position of the defective portion can be specified in the failure analysis. In addition, the diffusion model used for the simulation can be adjusted with high accuracy, the simulation accuracy of the impurity profile can be improved, and an accurate impurity profile can be estimated.

It is a conceptual diagram which shows the flow of a process in the detection method of the joining position by one Embodiment of this invention. It is a SEM image of section 13 of sample 12 which formed tungsten silicide by CVD method. It is a schematic diagram of the SEM observation of the cross section 13 of the sample 12 (N channel type MOS transistor and P channel type MOS transistor) in which tungsten silicide is formed by the CVD method. It is a table which shows the main analysis methods. It is a SEM image of the cross section of the sample (N channel type MOS transistor) processed with hydrofluoric acid. It is a SEM image of the cross section of the sample (P channel type MOS transistor) processed with hydrofluoric acid.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate 2 ... P well 3 ... N well 4 ... STI
DESCRIPTION OF SYMBOLS 5 ... N type diffused layer 6 ... Gate polysilicon 7 ... Gate tungsten 8 ... Gate mask nitride film 9 ... P type diffused layer 12 ... Sample 13 ... Section 14 ... Tungsten silicide film 15 ... Tungsten silicide film (deposited in N type impurity region) Have been)
16 ... Tungsten silicide film (deposited in P-type impurity region)
17 ... N-channel MOS transistor 18 ... P-channel MOS transistor

Claims (7)

A method of detecting a junction position between a P-type impurity region doped with a P-type impurity and an N-type impurity region doped with an N-type impurity in a semiconductor substrate;
A cross-section exposure step of exposing a cross-section to be observed from the semiconductor substrate;
A cross-section processing step for performing a cleaning process on the cross-section;
A deposition step of depositing silicide on the cross section;
A detection step of detecting a bonding interface by observing the grain size of the silicide.   2. The method for detecting a junction position according to claim 1, wherein in the detection step, the junction interface is detected based on a difference in a grain size of silicide between the P-type impurity region and the N-type impurity region.   The method for detecting a bonding position according to claim 1, wherein the semiconductor substrate is a silicon substrate.   The method for detecting a junction position according to any one of claims 1 to 3, wherein the silicide is tungsten silicide.   5. The method for detecting a junction position according to claim 1, wherein a chemical vapor deposition method is used for the silicide in the deposition step. 6.   6. The method for detecting a junction position according to claim 5, wherein tungsten hexafluoride and silane or cyclohexylsilane are used as the gas used when depositing the silicide in the deposition step.   7. The method for detecting a joint according to claim 1, wherein in the deposition step, the silicide is deposited with a thickness of 7 nm or less.

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