JP2008177483A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress interferences among adjacent memory cells. <P>SOLUTION: A dummy contact UC is provided between drain contacts DC adjacent in X direction. Then, the data-holding characteristics of memory cell transistors Tm1 and Tm2 mutually adjacent and interposing the drain contacts DC in Y direction can be maintained, thereby interference between the memory cell transistors Tm1 and Tm2 can be suppressed. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device including a pair of memory cell transistors and a method for manufacturing the same.

For example, a NOR-type flash memory device forms a cell array by arranging memory cell transistors in a matrix. An example of such a semiconductor device is disclosed in Patent Document 1. As disclosed in Patent Document 1, the cell array of the NOR type flash memory device has two adjacent memory cells that share a drain region and two adjacent memory cells. Each source area is shared. However, the structure disclosed in Patent Document 1 has a problem in that interference between adjacent memory cells increases.
JP 2005-79282 A

  An object of the present invention is to provide a semiconductor device capable of suppressing interference between adjacent memory cells and a method for manufacturing the same.

  The present invention provides a semiconductor substrate, a stacked gate electrode formed on the semiconductor substrate via a gate insulating film, and a first layer formed on one side of the stacked gate electrode and on a surface layer of the semiconductor substrate. A pair of memory cell transistors each having a source region of the first gate region and a first drain region formed on a surface layer of the semiconductor substrate located on the other side of the stacked gate electrode, A pair of memory cell transistors configured to share a first drain region between transistors; a second drain region formed in a surface layer of the semiconductor substrate in parallel with the first drain region; A drain contact plug formed on the first drain region and a dummy contact plug formed on the second drain region. To provide the body system.

  According to one embodiment of the present invention, a semiconductor substrate, a stacked gate electrode formed over the semiconductor substrate with a gate insulating film interposed therebetween, and formed on a surface layer of the semiconductor substrate, located on one side of the stacked gate electrode A pair of memory cell transistors each having a first source region and a first drain region located on the other side of the stacked gate electrode and formed in a surface layer of the semiconductor substrate, A pair of memory cell transistors configured to share a first drain region between the memory cell transistors, a dummy gate electrode formed on the semiconductor substrate via a gate insulating film, and one of the dummy gate electrodes A second source region formed on the surface layer of the semiconductor substrate on the side of the semiconductor substrate and a surface layer of the semiconductor substrate on the other side of the dummy gate electrode. A pair of dummy transistors each having a second drain region, the second drain region being shared between the pair of dummy transistors, the dummy gate electrode, the second source region, The second drain region includes a pair of dummy transistors arranged in parallel with the stacked gate electrode, the first source region, and the first drain region of the pair of memory cell transistors, and the first source of the memory cell transistor. A local source line formed on the semiconductor substrate across the region and the second source region of the dummy transistor, and a drain contact formed on the first drain region shared by the pair of memory cell transistors The pair of dummy transistors shared by the plug and the drain contact plug are shared. To provide a semiconductor device which is characterized in that a dummy contact plug formed in the second drain region.

  According to one embodiment of the present invention, a semiconductor substrate, a stacked gate electrode formed over the semiconductor substrate with a gate insulating film interposed therebetween, and one of the stacked gate electrodes is formed on a surface layer of the semiconductor substrate. A plurality of columns in which a plurality of columns of a pair of memory cell transistors each having a first source region and a first drain region located on the other side of the stacked gate electrode and formed on the surface layer of the semiconductor substrate are arranged A plurality of memory cell transistors arranged in parallel by sharing a first drain region between the pair of memory cell transistors, and a stacked gate electrode of the plurality of memory cell transistors Dummy gate electrodes arranged in parallel in the arrangement direction of the first drain regions of the plurality of columns of memory cell transistors and arranged in the arrangement direction of the first drain regions of the memory cell transistors in the plurality of columns. A pair of dummy transistors, and a second source region arranged in parallel in the arrangement direction of the first source regions of the memory cell transistors in the plurality of columns, wherein the second drain region is A pair of dummy transistors configured in common; a plurality of drain contact plugs respectively formed on a first drain region of the plurality of columns of memory cell transistors; and a pair of the plurality of columns of memory cell transistors A local source line formed so as to connect the first source region on one side or the other side of the memory cell transistor and the second source region of the dummy transistor, and the second drain of the dummy transistor Provided is a semiconductor device comprising a dummy contact plug formed on a region.

  According to the present invention, interference between adjacent memory cells can be suppressed.

  Hereinafter, an embodiment in which a semiconductor device of the present invention is applied to a NOR type flash memory device will be described with reference to the drawings. In the description of the drawings referred to below, the same or similar parts are denoted by the same or similar reference numerals. However, the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones.

  FIG. 1 shows an equivalent circuit diagram of a part of the electrical configuration of a cell array of a NOR type flash memory device, and FIGS. 2A and 2B are plan views of portions corresponding to the electrical configuration shown in FIG. Is shown. 2A shows a plan view mainly depicting the upper layer portion, and FIG. 2B shows a plan view mainly depicting the lower layer portion.

  The NOR type flash memory device 1 is divided into a memory cell region M and a peripheral circuit region (not shown), and a peripheral circuit (a cell array Ar formed in the memory cell region M is formed in the peripheral circuit region). (Not shown).

  As shown in FIG. 1, in the cell array Ar, memory cell transistors Tm1 and Tm2 (hereinafter abbreviated as transistors Tm1 and Tm2 respectively) are arranged in a matrix with respect to the XY direction (in-surface direction of the silicon substrate 2). Is made up of. The X direction and the Y direction are directions orthogonal to each other within the surface of the silicon substrate 2 (see FIGS. 2A and 2B).

  As shown in FIG. 1, two (a pair) of transistors Tm1 and Tm2 adjacent in the Y direction are arranged symmetrically with respect to the Y direction, and the pair of transistors Tm1 and Tm2 share a drain region. At the same time, the drain region is connected to a bit line BL extending in the Y direction.

  A plurality of pairs of these transistors Tm1 and Tm2 are arranged in the Y direction. The drain regions of the plurality of pairs of transistors Tm1 and Tm2 arranged in the Y direction are commonly connected to one bit line BL. Note that two pairs of transistors Tm1 and Tm2 adjacent in the Y direction are arranged symmetrically with respect to the local source line LSL1 or LSL2.

  A plurality of pairs of transistors Tm1 and Tm2 arranged in the Y direction are arranged in a plurality of rows with a separation in the X direction. Thus, the transistors Tm1 and Tm2 are arranged in a matrix with respect to the XY directions, thereby forming a cell array Ar.

  A plurality of bit lines BL are juxtaposed in correspondence with the transistors Tm1 and Tm2 arranged in a plurality of columns separated in the X direction. The plurality of bit lines BL are formed at the same interval in the X direction, and a main source line MSL is disposed between two (plural) bit lines BL. The main source line MSL is a line that becomes a source potential.

  Transistors Tm1 arranged in the X direction have their gates (control gate electrode CG (see FIGS. 4 and 6)) commonly connected by a word line WL1. Transistors Tm2 arranged in the X direction have their gates (control gate electrode CG (see FIGS. 4 and 6)) commonly connected by a word line WL2. The word lines WL1 and WL2 extend in the X direction in parallel with each other.

  The transistors Tm1 arranged in the X direction have their sources commonly connected to a local source line LSL1 (corresponding to a local source line contact plug) extending in the X direction, and the transistors Tm2 arranged in the X direction The sources are commonly connected to a local source line LSL2 (corresponding to a local source line contact plug) extending in the X direction. The plurality of local source lines LSL1 and LSL2 are spaced apart from each other in the Y direction, extend in the X direction, and are commonly connected to the main source line MSL extending in the Y direction.

  As shown in FIGS. 2A and 2B, the gate electrode MG1 of the transistor Tm1 is formed in the intersection region between the word line WL1 and the bit line BL, and the intersection region between the word line WL2 and the bit line BL is A gate electrode MG2 of the transistor Tm2 is configured. The gate electrodes MG1 and MG2 of these transistors Tm1 and Tm2 are juxtaposed in the XY direction.

  Transistors Tm1 and Tm1 adjacent in the Y direction share one local source line LSL1 disposed at the center in the Y direction between the gate electrodes MG1 and MG1. Similarly, the transistors Tm2 and Tm2 adjacent in the Y direction share one local source line LSL2 disposed at the center in the Y direction between the gate electrodes MG2 and MG2.

  A dummy gate electrode DG1 is provided in an intersection region between the main source line MSL and the word line WL1. As shown in FIG. 2A, the dummy gate electrode DG1 is provided in a region where the gate electrodes MG1 and MG2 of the memory cell transistors Tm1 and Tm2 cannot be disposed substantially because the main source line MSL is disposed in the upper layer thereof. It is configured. A second drain region 2aa (see FIGS. 5 and 6 to be described later) and a second source region 2bb (see FIGS. 6 and 7 to be described later) located on the surface layer of the silicon substrate 2 on both sides in the Y direction of the dummy gate electrode DG1. Reference) is formed. A dummy transistor (dummy cell transistor) TD1 is composed of a dummy gate electrode DG1, a second drain region 2aa, and a second source region 2bb.

  A dummy gate electrode DG2 is provided in an intersection region between the main source line MSL and the word line WL2. As shown in FIG. 2A, the dummy gate electrode DG2 is provided in a region where the gate electrodes MG1 and MG2 of the memory cell transistors Tm1 and Tm2 cannot substantially be provided because the main source line MSL is provided in an upper layer thereof. It is configured. A second drain region 2aa and a second source region 2bb are formed on the surface layer of the silicon substrate 2 on both sides of the dummy gate electrode DG2 in the Y direction. The dummy transistor TD2 includes a dummy gate electrode DG2, a second drain region 2aa, and a second source region 2bb.

  The dummy gate electrodes DG1 and DG2 constitute an overerased memory cell, and cannot be normally written and are not normally used. The reason why the dummy gate electrodes DG1 and DG2 are provided is to maintain the arrangement regularity and arrangement periodicity of the gate electrode with respect to the X direction, and the effect of improving the dimensional controllability of the gate electrode during manufacturing. Play.

  As shown in FIGS. 2A and 2B, a drain via plug DV and a drain contact plug (hereinafter referred to as a drain contact) DC are located between, for example, the center between adjacent word lines WL1 and WL2 and immediately below the bit line BL. Is provided. The drain via plug DV and the drain contact DC are configured to extend from the silicon substrate 2 in the vertical direction (Z direction orthogonal to the XY plane), and the first drain region 2a of the transistors Tm1 and Tm2 ( 4 and 5) and a bit line BL disposed in the upper layer in the vertical direction are provided for electrical connection.

  A source via plug SV1 is provided in an intersecting region of the main source line MSL and the local source line LSL1. The source via plug SV1 is disposed so as to be sandwiched between a part of the local source line LSL1 and a part of the main source line MSL, and electrically connects the local source line LSL1 and the main source line MSL. Is provided to do.

  The word line WL1 is a wiring that commonly connects the control gate electrodes CG (see FIGS. 4 and 6) of the transistors Tm1 arranged in the X direction, and the word line WL2 is the wiring of the transistors Tm2 arranged in the X direction. This is a wiring for commonly connecting the control gate electrodes CG (see FIGS. 4 and 6).

  A source via plug SV2 is provided in an intersecting region of the main source line MSL and the local source line LSL2. The source via plug SV2 is disposed on a part of the local source line LSL2, and is provided to electrically connect the local source line LSL2 and the main source line MSL.

  A dummy contact plug UC located, for example, in the center between the word lines WL1 and WL2 adjacent to a part of the main source line MSL and adjacent in the Y direction (between the local source lines LSL1 and LSL2 adjacent in the Y direction). (Hereinafter referred to as a dummy contact UC) is provided. The dummy contact UC is juxtaposed with the drain contact DC in the X direction.

  The dummy contact UC is provided in order to prevent interference between the gate electrodes MG1 and MG2 of the transistors Tm1 and Tm2 adjacent in the Y direction in terms of electrical structure, for example.

  Hereinafter, the dummy contact UC according to the feature of the present embodiment and the longitudinal sectional structure around the dummy contact UC will be described. 3 shows a longitudinal sectional view taken along line EE in the X direction of FIGS. 2A and 2B, and FIG. 4 shows a longitudinal sectional view taken along line AA in the Y direction of FIGS. 2A and 2B. Show. 5 shows a longitudinal sectional view taken along line BB in FIGS. 2A and 2B, and FIG. 6 shows a longitudinal sectional view taken along line CC in FIGS. 2A and 2B. FIG. 7 is a longitudinal sectional view taken along the line DD in FIGS. 2A and 2B.

  Hereinafter, details of the cross-sectional structure of the transistors Tm1, Tm2, TD1, and TD2 will be described. As shown in FIG. 4, the transistor Tm2 has a symmetrical structure in the Y direction across the transistor Tm1 and the drain contact DC, and the transistor Tm2 is almost the same as the structure of the transistor Tm1, and therefore the structure of the transistor Tm1. This will be described, and a specific structural description of the transistor Tm2 will be omitted.

  Further, since the stacked structure of the dummy gate electrodes DG1 and DG2 of the transistors TD1 and TD2 is the same as the stacked gate electrode structure of the gate electrodes MG1 and MG2 of the transistors Tm1 and Tm2, a specific structural description of the gate electrode MG1 of the transistor Tm1 is given. The description of the structure of the gate electrode MG2 and the dummy gate electrode DG of the transistor Tm2 is omitted.

  As shown in FIGS. 3, 5, and 7, a p-type silicon substrate 2 as a semiconductor substrate is formed with a plurality of element isolation trenches 3 spaced apart in the X direction. A plurality of these element isolation grooves 3 are arranged in parallel along the Y direction and spaced apart in the X direction, thereby dividing the element region Sa of the silicon substrate 2 into a plurality in the X direction. As shown in FIG. 4, these element regions Sa are regions including the first drain region 2a and the first source region 2b of the transistors Tm1 and Tm2, and the channel region sandwiched between them, It is formed directly below. Further, as shown in FIG. 6, the element region Sa also shows a region including the second drain region 2aa and the second source region 2bb constituting the dummy transistors TD1 and TD2 and a channel region sandwiched therebetween. The element region Sa is formed to be located immediately below the main source line MSL.

  As shown in FIGS. 3, 5, and 7, the element isolation insulating film 4 is embedded in each of the plurality of element isolation trenches 3 to form an element isolation region Sb. These element isolation insulating films 4 are formed in a laminated structure by a silicon oxide film 4a formed along the inner surface of the element isolation trench 3 and a silicon oxide film 4b embedded inside the silicon oxide film 4a. It is configured to protrude upward from the surface of the silicon substrate 2.

  A silicon oxide film 5 is formed on the element region Sa of the silicon substrate 2 defined by the element isolation trench 3. The silicon oxide film 5 is a film that functions as a first gate insulating film and a tunnel insulating film.

  On this silicon oxide film 5, a polycrystalline silicon layer 6 is formed between the element isolation insulating films 4 adjacent in the X direction. The polycrystalline silicon layer 6 is configured by polycrystallizing amorphous silicon doped with an impurity such as phosphorus, and the upper surface thereof is formed so as to substantially coincide with the upper surface of the element isolation insulating film 4. Yes.

  A polycrystalline silicon layer 7 is formed on the polycrystalline silicon layer 6. The polycrystalline silicon layer 7 is formed by polycrystallizing amorphous silicon doped with an impurity such as phosphorus, and is formed so as to protrude on the adjacent element isolation insulating film 4. These polycrystalline silicon layers 6 and 7 are formed in a so-called T shape in the cross section in the X direction, and are configured as a floating gate electrode FG (see FIGS. 4 and 6) of the transistor Tm1. As shown in FIGS. 3, 5, and 7, the polycrystalline silicon layer 7 is divided on the element isolation insulating film 4 between the floating gate electrodes FG adjacent in the X direction.

  An ONO film (silicon oxide film-silicon nitride film-silicon oxide film) 8 is formed along the X direction on the polycrystalline silicon layer 7 and the element isolation insulating film 4 from which the polycrystalline silicon layer 7 is divided. Yes. The ONO film 8 functions as a second gate insulating film, an inter-gate insulating film, an interpoly insulating film, and a conductive interlayer insulating film.

  A polycrystalline silicon layer 9 is formed on the ONO film 8. The polycrystalline silicon layer 9 is a layer formed by polycrystallizing amorphous silicon doped with impurities such as phosphorus. A tungsten silicide (WSi) layer 10 is formed on the polycrystalline silicon layer 9, and a silicon oxide film 11 is formed on the tungsten silicide layer 10 as a cap film.

  As shown in FIGS. 4 and 6, the control gate electrode CG is composed of a polycrystalline silicon layer 9 and a tungsten silicide layer 10. The gate electrode MG1 of the transistor Tm1 and the gate electrode MG2 (corresponding to a stacked gate electrode) of the transistor Tm2 are formed of layers 6 to 10 on the silicon substrate 2 with the silicon oxide film 5 interposed therebetween.

  As shown in FIG. 4, the side surfaces of the layers 6 to 11 are flush with each other in the cross section in the Y direction. In the surface layer of the silicon substrate 2, on both sides of the gate electrodes MG1 and MG2 in the Y direction, a first drain region 2a is formed on one side, and a first source region 2b is formed on the other side. On these first drain / source regions 2a and 2b, a silicon oxide film 12 and a silicon nitride film 13 are sequentially formed with a silicon oxide film 5 interposed therebetween, on which gate electrode MG1 and MG2 sides are formed. A BPSG (Boro-phospho silicate glass) film 14 is embedded at the position.

  More specifically, as shown in FIGS. 3 and 4, a thin silicon oxide film 12 is formed on the side wall surfaces of the polycrystalline silicon layers 6 and 7, the ONO film 8, the polycrystalline silicon layer 9, and the tungsten silicide film 10. Has been. A silicon nitride film 13 is formed as a barrier film so as to cover the silicon oxide films 11 and 12. A BPSG film 14 is formed on the side of the silicon nitride film 13 in the Y direction.

  The BPSG film 14 is embedded in the periphery (outer periphery) of the drain contact DC and the dummy contact UC. The BPSG film 14 is formed so that the upper surface thereof is flush with the upper surface of the silicon nitride film 13.

  A silicon oxide film 15 is formed on the silicon nitride film 13 and the BPSG film 14. A silicon oxide film 16 is laminated on the silicon oxide film 15 (upper layer). These silicon oxide films 15 and 16 constitute an interlayer insulating film in the upper layer of gate electrodes MG1 and MG2.

  A drain contact DC is formed on each first drain region 2 a of the silicon substrate 2. The drain contact DC extends in the Z direction from directly above the first drain region 2 a and is connected to the silicon oxide film 15, the BPSG film 14, the silicon nitride film 13, the silicon oxide film 12, and the silicon oxide film 5. Are formed through. As shown in FIG. 5, these drain contacts DC are arranged in parallel in the X direction with the same interval and the same width.

  As shown in FIG. 5, the first drain regions 2 a are arranged in parallel in the X direction and are electrically insulated from each other by the element isolation insulating film 4. On the surface layer of the silicon substrate 2, a second drain region 2aa is formed in parallel with the first drain region 2a. The second drain region 2aa is juxtaposed in the X direction with respect to the first drain region 2a at the same interval as the interval between the adjacent first drain regions 2a and 2a. The plurality of first drain regions 2 a and second drain regions 2 aa are electrically insulated from each other by the element isolation insulating film 4.

  A dummy contact UC is formed on the second drain region 2aa. The drain contacts DC are juxtaposed in the X direction, but the dummy contacts UC are juxtaposed to the drain contacts DC at the same interval as the X direction interval between adjacent drain contacts DC, and It is formed with the same width as the width in the X direction. The dummy contact UC and the drain contact DC are electrically separated from each other in the X direction by the layers 12 to 14.

  The drain contact DC and the dummy contact UC are made of the same material. The drain contact DC and the dummy contact DC are configured as a metal wiring layer by the tungsten layer 17 and the barrier metal film 18 formed so as to cover the lower surface and the side surface of the tungsten layer 17.

  On the other hand, as shown in FIG. 7, first source regions 2 b are arranged in parallel in the X direction on the surface layer of the silicon substrate 2. The plurality of first source regions 2 b are electrically insulated from each other in the X direction by the element isolation insulating film 4. Further, a second source region 2bb is formed on the surface layer of the silicon substrate 2 in parallel with the first source region 2b. The second source region 2bb is juxtaposed in the X direction with respect to the first source region 2b at the same interval as the interval between the adjacent first source regions 2b and 2b. The plurality of first source regions 2 b and second source regions 2 bb are electrically insulated from each other by the element isolation insulating film 4.

  A local source line LSL1 is formed on the first and second source regions 2b and 2bb. The local source line LSL1 is connected across the first and second source regions 2b and 2bb (element region Sa) provided in the X direction, and the plurality of first and second source regions 2b and 2bb. Are structurally and electrically connected to each other. The local source line LSL1 is formed along the X direction across the plurality of element regions Sa and element isolation regions Sb. Although not shown in the structure cross section, the local source line LSL2 has the same structure as the local source line LSL1.

  As shown in FIGS. 4 to 6, the drain contact DC, the dummy contact UC, the silicon oxide film 15, and the upper surfaces of the local source lines LSL1 and LSL2 are formed in a planar shape. As shown in FIGS. 4 and 7, an interlayer insulating film 16 is formed on the silicon oxide film 15, the dummy contact UC, and the local source lines LSL1 and LSL2.

  As shown in FIGS. 4 and 5, a drain via plug DV is formed on a part of the drain contact DC. The drain via plug DV is formed on each drain contact DC.

  On the other hand, as shown in FIGS. 6 and 7, a source via plug SV1 is formed in a part on the local source line LSL1, and a source via plug SV2 is formed in a part on the local source line LSL2. Yes.

  The drain via plug DV and the source via plugs SV1 and SV2 have the same laminated structure, and each includes a tungsten layer 19 and a barrier metal film 20 formed so as to cover the lower surface and side surfaces of the tungsten layer 19. Thus, a metal wiring layer is formed. As shown in FIGS. 4 to 7, the upper surfaces of the interlayer insulating film 16, the drain via plug DV, and the source via plugs SV1 and SV2 are formed in a planar shape.

  As shown in FIGS. 4 and 5, the bit line BL is formed on the interlayer insulating film 16 and the drain via plug DV, and as shown in FIG. 2A, a plurality of drain vias formed apart from each other in the Y direction. Plug DV is connected and connected.

  As shown in FIGS. 6 and 7, the main source line MSL is formed on the interlayer insulating film 16 and the source via plugs SV1 and SV2, and is formed apart in the Y direction as shown in FIGS. 2A and 6. The plurality of source via plugs SV1 and SV2 are connected and coupled. A dummy contact UC is also formed below the main source line MSL, but the main source line MSL is not electrically connected to the dummy contact UC.

  As shown in FIGS. 3 to 7, the memory cell region M has a multilayer structure on the silicon substrate 2. From the lower layer side to the upper layer side, (1) the surface layers LY1, (2 The contact plug forming layer LY2, (3) the via plug forming layer LY3, and (4) the wiring layer LY4 are formed in a multilayer structure. Note that (2) the stacked gate electrode layer LY2a is provided in a part of the same layer as the (2) contact plug formation layer LY2. The height of the contact plug formation layer LY2 is higher than the height of the constituent layer LY2a of the stacked gate electrode.

In these layers (1) to (4), the following electrically conductive elements are formed.
(1) Surface layer LY1
Drain region 2a, 2aa, source region 2b, 2bb
(2) Contact plug formation layer LY2
Drain contact DC, dummy contact UC, local source lines LSL1, LSL2
(2a) Stacked gate electrode layer LY2a
The stacked gate electrode MG1 (floating gate electrode FG, control gate electrode CG) of the memory cell transistor Tm1, the stacked gate electrode MG2 (floating gate electrode FG, control gate electrode CG) of the memory cell transistor Tm2, the gate electrode DG1 of the dummy transistor TD1, Gate electrode DG2 of dummy transistor TD2
(3) Via plug formation layer LY3
Drain via plug DV, Source via plug SV1, SV2
(4) Wiring layer LY4
Bit line BL, main source line MSL
Although details will be described later, each electrically conductive element in the same layer of these layers (1) to (4) is formed in the same process in the manufacturing process.

  In the present embodiment, the dummy contact UC is provided in parallel with the drain contact DC in the X direction. The dummy contacts UC are arranged at the same interval as the interval in the X direction between the drain contacts DC with respect to the adjacent drain contacts DC. In addition, the dummy contact UC is disposed substantially at the center between the word lines WL1 and WL2 adjacent in the Y direction.

  The inventors have obtained the characteristic results of the case where the dummy contact UC is provided in the arrangement relationship as described above and the conventional structure in which the dummy contact UC is not provided and the interlayer insulating film is embedded in the constituent region of the dummy contact UC. Comparing.

For example, as shown in FIG. 2B, a drain contact DC is formed on both sides of the dummy contact UC in the X direction, and between the gate electrodes MG1 and MG2 of the transistors Tm1 and Tm2 sandwiching the drain contact DC in the Y direction. The interference (see interference path K shown in FIGS. 2A and 2B) is:
(A) When dummy contact UC is not provided 5mV
(B) When dummy contact UC is provided 0.5 mV
As measured. That is, according to this experimental result, the interference voltage is detected as a large difference of about 10 times, and it is confirmed that the interference can be suppressed by providing the dummy contact UC.

  As shown in FIGS. 2A and 2B, a dummy gate electrode DG1 is provided between the gate electrodes MG1 of the transistors Tm1 adjacent in the X direction and immediately below the main source line MSL, and the transistors Tm2 adjacent in the X direction A dummy gate electrode DG2 is provided between the gate electrodes MG2. When a voltage is applied to the dummy gate electrode DG1 or DG2 from the word line WL1 or WL2 to turn on the dummy transistor TD1 or TD2, the dummy transistor TD1 is turned on. Alternatively, an on-current flows through TD2, and leakage occurs from the source contact LSL1 or LSL2 to the dummy contact UC.

  However, since the on-resistances of the dummy transistors TD1 and TD2 are high at this time, it is also confirmed that the voltage drop between the source contact LSL1 and the dummy contact UC and between the source contact LSL2 and the dummy contact UC is large. It has been confirmed that the influence of the above does not affect the data retention characteristics of the memory cell transistors Tm1 and Tm2.

  According to the structure of the present embodiment, the dummy contact UC is provided in parallel with the drain contact DC, so that the drain contact DC is sandwiched in the Y direction while maintaining the data retention characteristics of the memory cell transistors Tm1 and Tm2. Interference between adjacent gate electrodes MG1 and MG2 can be suppressed.

  Since the dummy contact UC is provided between the plurality of drain contacts DC in the X direction, the interference between the adjacent gate electrodes MG1 and MG2 sandwiching the plurality of drain contacts DC on both sides in the X direction of the dummy contact UC in the Y direction. Can be suppressed.

<About manufacturing method>
Hereinafter, a manufacturing method of the above-described structure will be described with reference to FIGS. 8 to 20D.
8 to 13 show cross-sectional views along the Y direction in the course of manufacture corresponding to FIG. 3 described above.

  As shown in FIG. 8, the silicon substrate 2 is heated in an oxygen atmosphere at 800 ° C. to form a silicon oxide film 5 of 10 [nm] on the surface of the silicon substrate 2, and then low pressure chemical vapor deposition (Low Pressure Chemical Vapor). Amorphous silicon doped with impurities such as phosphorus is deposited by about 60 [nm] by the Deposition method, and then a silicon nitride film 21 is deposited by about 100 [nm] by the low pressure CVD method, and the silicon oxide film 22 is deposited. About 150 nm. Since amorphous silicon is polycrystallized by heat treatment later, the reference numeral 6 is assigned as the polycrystalline silicon layer 6 in the drawings subsequent to FIG.

Next, as shown in FIG. 9, a photoresist (not shown) is applied, patterned by a normal photolithography technique, and silicon oxide is oxidized by RIE (Reactive Ion Etching) using the photoresist mask pattern as a mask. The film 22 is removed and the silicon nitride film 21 is removed. Next, the photoresist is removed by exposure to O ₂ plasma, and the polycrystalline silicon layer 6 is removed using the silicon oxide film 22 as a mask.

  Next, as shown in FIG. 10, the silicon oxide film 5 is processed using the silicon oxide film 22 as a mask, the element isolation groove 3 is formed in the surface layer of the silicon substrate 2, and heated to 1000 ° C. in an oxygen atmosphere. A 6 nm thick silicon oxide film 4 a is formed along the inner surface of the element isolation trench 3.

  Next, as shown in FIG. 11, a silicon oxide film 4b is deposited on the inner side of the silicon oxide film 4a in the element isolation trench 3 by HDP (High Density Plasma) -CVD method, and silicon by CMP (Chemical Mechanical Polishing) method. The silicon oxide film 4b is planarized using the nitride film 21 as a stopper and heated in a nitrogen atmosphere at 900.degree.

  Next, as shown in FIG. 12, the silicon nitride film 21 is removed by immersing in a buffered hydrofluoric acid solution (BHF) for about 10 seconds and by performing a phosphoric acid treatment at 150 ° C. to obtain a dilute hydrofluoric acid (DHF) solution. The silicon oxide film 4b is etched by about 20 [nm], and amorphous silicon doped with impurities such as phosphorus is deposited by low pressure CVD, and a photoresist (not shown) is deposited on the amorphous silicon. The photoresist is patterned by a normal photolithography technique, and the amorphous silicon is divided on the silicon oxide film 4b by a RIE (Reactive Ion Etching) method using the mask pattern of the photoresist as a mask. Since this amorphous silicon is polycrystallized by a subsequent heat treatment, the reference numeral 7 is assigned as the polycrystal silicon layer 7 in the drawings subsequent to FIG.

  Next, as shown in FIG. 13, an ONO film 8 (5 [nm] for the silicon oxide film, 5 [nm] for the silicon nitride film, and 5 [nm] for the silicon oxide film) is formed by the low pressure CVD method. Amorphous silicon doped with an impurity such as phosphorus (polycrystalline silicon layer 9) is deposited to 100 [nm], a tungsten silicide film 10 is formed thereon to 100 [nm], and then a silicon oxide film 11 is formed to 200 [nm]. nm] to deposit.

  FIG. 14A to FIG. 20A show longitudinal sectional views along the line AA in FIG. 2A and FIG. FIGS. 14B to 19B show longitudinal sectional views along the line BB in FIGS. 2A and 2B in the course of manufacture, corresponding to FIG. FIG. 14C to FIG. 20C show longitudinal sectional views along the line CC in FIG. 2A and FIG. FIGS. 14D to 19D show longitudinal sectional views along the line DD in FIGS. 2A and 2B in the middle of manufacture, corresponding to FIG.

  14A to 14D respectively show vertical cross-sectional structures along the cross-sectional lines AA, BB, CC, and DD when the manufacturing process of FIG. 13 is completed. . As shown in FIGS. 14A to 14D, at this time, the above-described stacked structure shown in FIG. 13 is formed in the same structure along the X direction.

  Next, as shown in FIGS. 15A to 15D, a photoresist (not shown) is applied on the silicon oxide film 11, the photoresist is patterned, and silicon oxide is masked using the mask pattern of the photoresist as a mask. The film 11 is removed by RIE to remove the mask pattern.

  Next, as shown in FIGS. 16A to 16D, the tungsten silicide film 10, the polycrystalline silicon layer 9, the ONO film 8, and the polycrystalline silicon layers 7 and 6 are sequentially removed by the RIE method using the silicon oxide film 11 as a mask. After processing, impurities are ion-implanted to form source / drain regions 2a, 2b, 2aa and 2bb. If necessary, a high concentration drain region may be formed particularly in the drain regions 2a and 2aa by forming spacers in the subsequent steps and ion-implanting high concentration impurities.

  Next, as shown in FIGS. 17A to 17D, heating is performed in an oxygen atmosphere set at 1000 ° C., and the side walls of the polycrystalline silicon layer 9, ONO film 8, polycrystalline silicon layers 7 and 6, and the silicon oxide film 5 are heated. A silicon oxide film 12 is formed along the upper surface.

  Next, as shown in FIGS. 18A to 18D, a silicon oxide film (not shown) of about 20 [nm] is formed so as to cover the layers 5 to 11 by the low pressure CVD method, and 30 so as to cover the silicon oxide film. A silicon nitride film 13 of about [nm] is deposited.

Next, as shown in FIGS. 19A to 19D, a BPSG film 14 having a thickness of about 700 [nm] is deposited by atmospheric pressure CVD, and heated in an N ₂ atmosphere at 850 ° C. to reflow the BPSG film 14. To do. Next, a silicon oxide film 15 is deposited with a film thickness of about 200 [nm] by plasma CVD.

Next, as shown in FIGS. 20A to 20D, a resist (not shown) is applied on the silicon oxide film 15, the resist is patterned, and the silicon oxide film 15 and the BPSG film are formed using the mask pattern as a mask. 14 is removed and processed by the RIE method. Next, O ₂ plasma treatment is performed to remove the photoresist. Next, the silicon nitride film 13 and the silicon oxide films 12 and 5 are removed and processed. Next, the barrier metal film 18 is sputtered, tungsten 17 is deposited by CVD, and the tungsten 17 and barrier metal film 18 are planarized by CMP using the silicon oxide film 15 as a stopper.

  Next, as shown in FIGS. 3 to 7, a silicon oxide film 16 is deposited on the drain contact DC, the local source line contacts LSL 1, LSL 2, the dummy contact DC, and the silicon oxide film 15, and on the silicon oxide film 16. A resist is applied and patterned, and the silicon oxide film 16 is removed by RIE. Next, the barrier metal film 20 is sputtered, and tungsten 19 is buried inside the barrier metal film 20 and flattened by CMP. Thus, the source via plugs SV1 and SV2 and the drain via plug DV can be formed in the same process. Further, the bit line BL is formed on the drain via plug DV along the Y direction, and at the same time, the main source line MSL is formed along the Y direction so as to cross over the source via plugs SV1 and SV2. Further, the NOR type flash memory device 1 can be configured through a process of forming an upper layer wiring, a post process, and the like.

  According to the manufacturing method according to the present embodiment, since the dummy contacts UC and the plurality of drain contacts DC are periodically and regularly formed in the X direction, the contacts DC and UC are formed. It is sufficient to form the necessary mask pattern at the same interval in the X direction, and the dimension control of the drain contact DC is facilitated. In addition, the design speed of the photomask can be improved and the productivity can be improved.

  In addition, since the bit line BL and the main source line MSL are arranged in parallel in the X direction at the same interval, a mask pattern necessary for forming the bit line BL and the main source line MSL is represented by X. It is sufficient to form them at the same interval in the direction, and dimensional control becomes easy. In addition, the photomask design speed can be improved and the productivity can be improved.

(Other embodiments)
The present invention is not limited to the above embodiment, and for example, the following modifications or expansions are possible.
Although the embodiment has been described in which the main source line MSL and the plurality of bit lines BL are formed with the same width and the same interval in the X direction, the present invention may be formed with different widths and / or different intervals.

Although the embodiment in which the plurality of drain contacts DC are formed in the X direction with the same width and the same interval has been described, the present invention may be formed with different widths and / or different intervals.
Although the embodiment in which the dummy contact UC is provided between the plurality of drain contacts DC has been shown, if the plurality of drain contacts DC and the dummy contact UC are juxtaposed and there is an effect of suppressing interference between the transistors Tm1 and Tm2, an end portion is provided. The present invention can also be applied to a structure provided with dummy contacts UC.

  Although the embodiment in which the polycrystalline silicon layer 7 is formed so as to project on the adjacent element isolation insulating film 4 is shown, in the present invention, the polycrystalline silicon layer 7 does not project on the adjacent element isolation insulating film 4. It can also be applied to structures.

1 is an electrical configuration diagram showing a part of a memory cell region of a flash memory device according to an embodiment of the present invention. Plan view showing the structure of the region corresponding to FIG. 1 (including the upper layer region and the lower layer region) Plan view showing the structure of the region corresponding to FIG. 1 (only the lower layer region) 2A and 2B schematically showing a longitudinal section along the line EE in FIG. 2B 2A and 2B are schematic longitudinal sectional views taken along line AA in FIG. 2A and 2B schematically showing a longitudinal section along the line BB in FIG. 2B FIG. 2A and FIG. 2B schematically show a longitudinal section along the line CC 2A and 2B are schematic longitudinal sectional views taken along the line DD in FIG. 2B. FIG. 2A and FIG. 2B are longitudinal sectional views (part 1) schematically shown along the line EE in the course of manufacturing. 2 is a longitudinal sectional view schematically showing along the line EE in FIGS. 2A and 2B during the production (part 2). 2A and 2B schematically showing a longitudinal section taken along the line E-E in FIG. 2A (Part 3) FIG. 2A and FIG. 2B are longitudinal sectional views (part 4) schematically shown along the line EE in the course of manufacture. FIG. 2A and FIG. 2B are longitudinal sectional views (part 5) schematically shown along the line EE in the course of manufacture. FIG. 2A and FIG. 2B are longitudinal sectional views schematically showing along the line E-E in the course of manufacturing (No. 6). FIG. 2A and FIG. 2B are longitudinal sectional views schematically showing along the line AA in the course of manufacturing (part 1). FIG. 2A and FIG. 2B are longitudinal sectional views (part 1) schematically shown along the line BB in the course of manufacture. FIG. 2A and FIG. 2B are longitudinal sectional views (part 1) schematically shown along the line CC in FIG. 2A and 2B schematically showing a longitudinal section taken along the line DD in FIG. 2A and FIG. 2B (part 1) 2A and 2B are schematic longitudinal sectional views taken along the line A-A in FIG. 2A and FIG. 2B (part 2). 2 is a longitudinal cross-sectional view schematically shown along the line B-B in FIGS. 2A and 2B (part 2). 2A and 2B are schematic longitudinal sectional views taken along the line CC in FIGS. 2A and 2B (part 2). 2A and 2B are longitudinal sectional views schematically showing along the line DD in FIGS. 2A and 2B (part 2). 2A and 2B schematically showing a longitudinal section taken along the line AA in FIG. 2A and FIG. 2B (part 3) FIG. 2A and FIG. 2B are longitudinal sectional views (part 3) schematically shown along line BB in the course of manufacture. FIG. 2A and FIG. 2B are longitudinal sectional views (part 3) schematically shown along the line CC in FIG. 2A and 2B schematically showing a longitudinal section taken along the line DD in FIG. 2A and FIG. 2B (part 3) FIG. 2A and FIG. 2B are longitudinal sectional views schematically showing along the line AA in the course of manufacturing (part 4). FIG. 2A and FIG. 2B schematically show a vertical cross-sectional view along the line BB in the course of manufacturing (part 4). FIG. 2A and FIG. 2B are longitudinal sectional views (part 4) schematically shown along the line CC in FIG. FIG. 2A and FIG. 2B are longitudinal sectional views schematically showing along the line DD in FIG. 2A during production (part 4). 2A and 2B schematically showing a longitudinal section taken along the line AA in FIG. 2A and FIG. 2B (part 5) FIG. 2A and FIG. 2B are longitudinal sectional views schematically showing along the line BB in FIG. FIG. 2A and FIG. 2B are longitudinal sectional views schematically taken along the line CC in FIG. FIG. 2A and FIG. 2B are longitudinal sectional views schematically showing along the line DD in FIG. FIG. 2A and FIG. 2B are longitudinal sectional views schematically showing along the line AA in the middle of the manufacture (No. 6). FIG. 2A and FIG. 2B are longitudinal sectional views schematically showing along the line BB in the course of manufacturing (No. 6). FIG. 2A and FIG. 2B are longitudinal cross-sectional views schematically shown along the line CC in FIG. FIG. 2A and FIG. 2B are longitudinal sectional views schematically showing along the line DD in FIG. FIG. 2A and FIG. 2B are longitudinal sectional views schematically showing along the line AA in the course of manufacturing (No. 7). FIG. 2A and FIG. 2B schematically show a vertical cross-sectional view along the line BB in the course of manufacture (No. 7). FIG. 2A and FIG. 2B are longitudinal cross-sectional views schematically shown along the line CC in FIG. FIG. 2A and FIG. 2B are longitudinal cross-sectional views schematically shown along the line DD in FIG.

Explanation of symbols

  In the drawings, 1 is a flash memory device (semiconductor device), 2a is a first drain region of a memory cell transistor, 2b is a first source region of a memory cell transistor, 2aa is a second drain region of a dummy transistor, and 2bb is The second source region of the dummy transistor, Tm1 and Tm2 are memory cell transistors, DC is a drain contact plug, TD1 and TD2 are dummy transistors, UC is a dummy contact plug, LSL1 and LSL2 are local source line contact plugs, SV1 and SV2 are A source via plug, MSL is a main source line, and BL is a bit line.

Claims (5)

A semiconductor substrate;
A stacked gate electrode formed on the semiconductor substrate via a gate insulating film; a first source region formed on a surface layer of the semiconductor substrate located on one side of the stacked gate electrode; and the stacked gate A pair of memory cell transistors each having a first drain region formed on a surface layer of the semiconductor substrate located on the other side of the electrode, the first drain region between the pair of memory cell transistors A pair of memory cell transistors configured in common, and
A second drain region formed in a surface layer of the semiconductor substrate in parallel with the first drain region;
A drain contact plug formed on the first drain region;
A semiconductor device comprising: a dummy contact plug formed on the second drain region. A semiconductor substrate;
A stacked gate electrode formed on the semiconductor substrate via a gate insulating film; a first source region formed on a surface layer of the semiconductor substrate located on one side of the stacked gate electrode; and the stacked gate A pair of memory cell transistors each having a first drain region formed on a surface layer of the semiconductor substrate located on the other side of the electrode, the first drain region between the pair of memory cell transistors A pair of memory cell transistors configured in common, and
A dummy gate electrode formed on the semiconductor substrate via a gate insulating film; a second source region formed on a surface layer of the semiconductor substrate on one side of the dummy gate electrode; and the dummy gate A pair of dummy transistors each having a second drain region formed on a surface layer of the semiconductor substrate on the other side of the electrode, wherein the second drain region is shared between the pair of dummy transistors. The dummy gate electrode, the second source region, and the second drain region are arranged in parallel with the stacked gate electrode, the first source region, and the first drain region of the pair of memory cell transistors, respectively. A pair of dummy transistors,
A local source line configured on the semiconductor substrate across the first source region of the memory cell transistor and the second source region of the dummy transistor;
A drain contact plug formed on a first drain region shared by the pair of memory cell transistors;
A semiconductor device comprising: a dummy contact plug formed in parallel with the drain contact plug and formed on a second drain region shared by the pair of dummy transistors. A semiconductor substrate;
A stacked gate electrode formed on the semiconductor substrate through a gate insulating film; a first source region formed on a surface layer of the semiconductor substrate located on one side of the stacked gate electrode; and the stacked gate electrode A plurality of columns of memory cell transistors each including a pair of memory cell transistors each having a first drain region formed on a surface layer of the semiconductor substrate located on the other side of the semiconductor substrate, A plurality of memory cell transistors arranged in parallel by sharing a first drain region between the memory cell transistors;
Dummy gate electrodes arranged in parallel in the arrangement direction of the stacked gate electrodes of the plurality of columns of memory cell transistors, and second drain regions arranged in parallel in the arrangement direction of the first drain regions of the plurality of columns of memory cell transistors And a second source region arranged in parallel in the arrangement direction of the first source regions of the plurality of columns of memory cell transistors, the second drain region being shared A pair of configured dummy transistors;
A plurality of drain contact plugs respectively formed on a first drain region of the plurality of columns of memory cell transistors;
A local region formed by connecting the first source region on one side or the other side of the pair of memory cell transistors of the plurality of columns of memory cell transistors and the second source region of the dummy transistors. Source line,
A semiconductor device comprising: a dummy contact plug formed on the second drain region of the dummy transistor. A manufacturing method for manufacturing the semiconductor device according to claim 3,
A method of manufacturing a semiconductor device, wherein the dummy contact plug and the plurality of drain contact plugs are formed at the same interval. A manufacturing method for manufacturing the semiconductor device according to claim 3,
A plurality of bit lines are formed along a crossing direction that is disposed on each of the plurality of drain contact plugs and arranged in the predetermined direction and intersects the predetermined direction, and the bit lines are formed on the dummy transistor. A plurality of bit lines are arranged in parallel in the arrangement direction of the plurality of bit lines, and a main source line electrically connected to the second source region of the dummy transistor is electrically disconnected from the dummy contact plug and the plurality of bit lines. A method of manufacturing a semiconductor device, wherein the semiconductor device is formed at the same interval.

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