JP2008176910A - Semiconductor memory device - Google Patents

Abstract

An object of the present invention is to prevent erroneous reading of a semiconductor memory device or to easily reduce power consumption.
P-channel transistors 106 and 107 are formed in an N well region 151 on a semiconductor substrate. In P well regions 152 and 153 arranged on both sides of N well region 151, N channel transistors 108 and 109 are formed. The gate lengths (gate electrode widths) A, B, and C of the N-channel transistor 108, the read drive transistor 120, and the read access transistor 122 are set so that A <B, A <C, and C <B. ing.
[Selection] Figure 2

Description

  The present invention is a so-called multiport SRAM (Static Random Access Memory) having a holding circuit (flip-flop circuit) and a read output circuit that outputs a signal corresponding to data held in the holding circuit. The present invention relates to a semiconductor memory device.

  An SRAM is configured by vertically and horizontally arranging memory cells each having a holding circuit that holds stored data. A memory cell that constitutes a multi-port SRAM has, for example, a read-only output circuit, and can read from and read from a plurality of memory cells at the same time. In FIGS. 8 and 9 of Patent Document 1, as an example of the SRAM as described above, in addition to the write access transistors (N3, N4), a read drive transistor (N8) and an access transistor (N9) A circuit configuration of a memory cell including the above and a layout of a transistor or the like are disclosed. The gate length of each of the transistors is the same as that of the transistors constituting the holding circuit.

Furthermore, an SRAM having a hierarchical bit line structure is known in order to increase the access speed. Patent Documents 2 and 3 disclose SRAMs having a plurality of local read bit lines and one global read bit line, and each memory cell being connected to one of the local read bit lines. . In such an SRAM, the length of the local read bit line can be kept short, and thus the parasitic capacitance can be kept small, so that high-speed access is facilitated.
JP 2002-43441 A JP 2004-47003 A US Pat. No. 6,014,338

  In the multiport SRAM as described above, erroneous reading tends to occur when a plurality of columns of memory cells arranged in the bit line direction are provided in a direction perpendicular to the bit line. For example, in the SRAM as described above, two memory cells belonging to the same row may be simultaneously selected for writing and reading. In that case, in the read memory cell, since the write access transistor is turned on, the potential of the input / output node of the holding circuit varies depending on the potential of the write bit line. Therefore, since the potential of the read bit line is also affected, erroneous reading is likely to occur.

  In an SRAM having a hierarchical bit line structure, a global read bit line is provided for each column, and when these potentials change according to a signal read from a memory cell in each column, Electric power corresponding to each potential change is consumed.

  The present invention has been made in view of this point, and an object of the present invention is to make it difficult for erroneous reading to occur or to easily reduce power consumption.

To solve the above problem,
The semiconductor memory device of the example of the first invention is
A holding circuit for holding stored data;
A read-only output circuit that outputs a signal corresponding to the data held in the holding circuit;
A semiconductor memory device comprising a plurality of memory cells having
The read-only output circuit has a read drive transistor that is controlled according to a signal held in the holding circuit,
The gate length of the read drive transistor is longer than the gate length of the transistor constituting the holding circuit.

A semiconductor memory device according to an example of the second invention is
A holding circuit for holding stored data;
A read-only output circuit that outputs a signal corresponding to the data held in the holding circuit;
A semiconductor memory device comprising a plurality of memory cells having
The read-only output circuit is
A read drive transistor controlled according to a signal held in the holding circuit, and a read access transistor controlled by a read word selection signal;
The gate length of the read access transistor is longer than the gate length of the transistor constituting the holding circuit.

  As a result, the threshold voltage Vt is less likely to be lowered due to the short channel effect, and the uniformity of the semiconductor is increased and the variation in the threshold voltage is reduced. Therefore, the minimum threshold voltage of the read drive transistor and the read access transistor can be reduced. Can be easily kept higher than the transistor constituting the transistor. Therefore, the read drive transistor and the read access transistor can easily suppress erroneous reading by suppressing the decrease in the threshold voltage while suppressing the size of the transistors and the like constituting the holding circuit to be small.

The semiconductor memory device of the example of the third invention is
A bit line for reading stored data is a semiconductor memory device having a hierarchical bit line structure,
A plurality of local blocks each having a plurality of memory cells and a local read bit line to which the memory cells are connected include a plurality of columns arranged in the direction of the local read bit line,
A global read bit line provided in common corresponding to a plurality of columns;
A local amplifier that drives the global read bit line according to the signal output from each local block,
With
Each of the above memory cells
A holding circuit for holding stored data;
A read output circuit for outputting a signal corresponding to the data held in the holding circuit to one local read bit line;
Have
At the time of reading the retained data, only one memory cell in one local block is activated for each column,
The local amplifier is
A drive transistor for controlling the presence or absence of application of a predetermined potential according to an input signal;
A column selection transistor that controls the presence or absence of conduction between the input and output terminals in accordance with a column selection signal;
It is characterized by comprising.

Thereby, compared with the case where a global bit line is provided in each column and these are charged / discharged at the same time, the power consumption can be reduced. In addition, it is not necessary to provide a global read bit line, a precharge (discharge) circuit, a global bit line driver, etc. for each column, and it is not necessary to provide each element or an element isolation region. It becomes easy.

A semiconductor memory device of an example of the fourth invention is
A bit line for reading stored data is a semiconductor memory device having a hierarchical bit line structure,
A plurality of local blocks each having a plurality of memory cells and a local read bit line to which the memory cells are connected;
A global read bit line,
A local amplifier that drives the global read bit line according to the signal output from each local block;
A read output holding circuit that holds and outputs a signal of the global read bit line at a predetermined timing;
A row decoder for generating a read word selection signal for selecting any of the plurality of memory cells;
With
Each of the above memory cells
A holding circuit for holding stored data;
A read output circuit for outputting a signal corresponding to the data held in the holding circuit to one local read bit line;
And having
further,
And a timing control circuit that has a dummy global read bit line and controls a signal holding timing by the read output holding circuit based on a delay time of the dummy global read bit line.

  This makes it easy to control the data read operation at an appropriate timing according to fluctuations in power supply voltage, environmental temperature, and variations in device characteristics during the manufacturing process, and to ensure accurate operation with an operating margin. Can be. In addition, the timing control according to the length of the local read bit line and the global read bit line and the parasitic capacitance is automatically performed, so the number of memory cells in the local block and the number of local blocks in the column are various. Even when the semiconductor memory device is manufactured, it becomes easy to save or reduce the design and adjustment.

A semiconductor memory device of an example of the fifth invention is
A bit line for reading stored data is a semiconductor memory device having a hierarchical bit line structure,
A plurality of local blocks each having a plurality of memory cells and a local read bit line to which the memory cells are connected;
A global read bit line,
A local amplifier that drives the global read bit line according to the signal output from each local block;
With
Each of the above memory cells
A holding circuit for holding stored data;
A read output circuit for outputting a signal corresponding to the data held in the holding circuit to one local read bit line;
Have
The plurality of local blocks include a small number of local blocks having a smaller number of memory cells than the other local blocks,
A capacitor element is connected to the local read bit line of the small number of local blocks.

  Thereby, even if the local read bit line is short, it can be easily set to the same parasitic capacitance as other local read bit lines. Therefore, it is particularly useful for accurate reading.

A semiconductor memory device according to an example of the sixth invention is
A bit line for reading stored data is a semiconductor memory device having a hierarchical bit line structure,
A plurality of local blocks each having a plurality of memory cells and a local read bit line to which the memory cells are connected include a plurality of columns arranged in the direction of the local read bit line,
One or a plurality of global read bit lines corresponding to the plurality of local blocks,
A local amplifier that drives the global read bit line according to the signal output from each local block;
With
Each of the above memory cells
A holding circuit for holding stored data;
A read output circuit for outputting a signal corresponding to the data held in the holding circuit to one local read bit line;
And having
further,
While storing data for maintaining the potential of the precharged local read bit line in the memory cell to be inspected,
In another memory cell connected to the same local read bit line as the memory cell to be inspected, data for discharging the potential of the precharged local read bit line is stored, and
While the memory cell to be inspected is in a read state,
Put other memory cells selected by the same write word selection signal as the memory cell to be inspected into the write state,
An inspection circuit for determining whether or not the data read from the inspection target memory cell is correct is provided.

A semiconductor memory device of an example of a seventh invention is
A bit line for reading stored data is a semiconductor memory device having a hierarchical bit line structure,
A plurality of local blocks each having a plurality of memory cells and a local read bit line to which the memory cells are connected;
A global read bit line,
A local amplifier that drives the global read bit line according to the signal output from each local block;
With
Each of the above memory cells
A holding circuit for holding stored data;
A read output circuit for outputting a signal corresponding to the data held in the holding circuit to one local read bit line;
And having
The read output circuit includes a read access transistor controlled by a read word selection signal and a read drive transistor controlled according to a signal held in the holding circuit, or the read access transistor,
The read access transistor and the read drive transistor, or the read access transistor are configured such that a source potential and a substrate potential can be applied independently.

  By these, it is possible to facilitate accurate inspection of good and bad.

  According to the present invention, erroneous reading is less likely to occur or power consumption can be easily reduced.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following embodiments and modifications, components having the same functions as those of the other embodiments and modifications are denoted by the same reference numerals and description thereof is omitted.

Embodiment 1 of the Invention
The memory cell provided in the semiconductor memory device of Embodiment 1 has a circuit configuration as shown in FIG. This memory cell 130 is a so-called 2-port 8-transistor cell. The P-channel transistors 106 and 107 (PMOS transistors), the N-channel transistors 108 and 109 (NMOS transistors), the write access transistors 116 and 117, the read A drive transistor 120 and a read access transistor 122 are included.

  P-channel transistor 106 and N-channel transistor 108, and P-channel transistor 107 and N-channel transistor 109 constitute a CMOS inverter, respectively. In these CMOS inverters, input / output terminals are connected to each other to form a holding circuit 103 (flip-flop circuit). The write access transistors 116 and 117 conduct a pair of write bit lines 112 and 113 (NWBL and WBL) to the holding circuit 103, respectively, when the write word line 110 (WWL) becomes “H (High level)”. It works as an access gate (transfer gate). In addition, the read drive transistor 120 and the read access transistor 122 are configured so that the read bit line 114 (RBL) is output when the read word line 111 (RWL) is “H” and the input / output node 103a of the holding circuit 103 is “H”. "L (Low level)" is set.

  Each of the transistors is laid out on a semiconductor substrate, for example, as shown in FIG. P-channel transistors 106 and 107 are formed in N well region 151. The N channel transistors 108 and 109 are formed in the P well regions 152 and 153 disposed on both sides of the N well region 151. The gate lengths (gate electrode widths) A, B, and C of the N-channel transistor 108, the read drive transistor 120, and the read access transistor 122 are set so that A <B, A <C, and C <B. ing.

  By setting as described above, the gate length of a very small transistor is long, and as the transistor area increases, the threshold voltage Vt is less likely to decrease due to the short channel effect, and the homogeneity of the semiconductor increases. Therefore, the threshold voltage variation is reduced, so that the minimum threshold voltage of the read drive transistor 120 and the read access transistor 122 can be easily maintained higher than that of the N-channel transistor 109. Here, since the signal held in the holding circuit 103 is determined by the balance of the characteristics of the N-channel transistors 108 and 109 and the P-channel transistors 106 and 107, the influence of the variation in threshold voltage of the N-channel transistor 109 is relatively small. On the other hand, a reduction in threshold voltages of the read drive transistor 120 and the read access transistor 122 has a relatively large influence on erroneous reading. Therefore, the read drive transistor 120 and the read access transistor 122 can suppress the decrease in the threshold voltage and suppress erroneous reading while suppressing the size of the N-channel transistor 109 and the like.

  More specifically, by setting A <B, the amount of random variation determined by the device size of the read drive transistor 120 can be suppressed, and the short channel effect can be achieved even when the gate length is short within an allowable range. The threshold voltage drop due to can be suppressed (reduced). As a result, in the multi-port memory to which the single-ended read structure is applied, the holding circuit when the write word line 110 and the read word line 111 in the same row are turned on at the same time, for example, in the read-only port whose internal node is gated. Even if the potential of the 103 input / output node 103a rises slightly due to the potential of the write bit lines 112 and 113, the read drive transistor 120 is difficult to turn on. Therefore, erroneous reading due to a potential drop of the read bit line 114 (or a local read bit line in the case of a memory having a hierarchical bit line structure) can be easily suppressed. Therefore, since the read timing setting range is widened, the design of the read timing signal generation circuit becomes easy, and the design man-hours can be easily reduced.

  Also, by setting A <C, the threshold voltage drop due to the short channel effect of the read access transistor 122 is suppressed, and the random variation determined by the device size is also suppressed by increasing the transistor size. Is done. Therefore, the worst transistor threshold voltage drop is suppressed, and the potential drop of the read bit line 114 due to the off-leak current of the read access transistor 122 of the row where the read word line 111 is turned off is suppressed, and erroneous reading is still performed. It can be easily suppressed.

  Further, by setting C <B, the off-leakage current of the read access transistor 122 and the simultaneous write / write to the memory cell 130 in the same row while the read access transistor 122 is on and the read drive transistor 120 is off. When compared with the erroneous read current that flows due to the floating of the internal node at the time of reading, if the latter is large, the influence on the erroneous read to the read bit line 114 can be reduced.

  The read access transistor 122 is more dominant with respect to the cell current because the substrate bias effect is generally applied to the read access transistor 122 side where the read word line 111 is connected to the gate. In addition, the erroneous read current can be suppressed while suppressing the decrease of the normal read cell current.

  A limited memory cell when the erroneous read current at the time of simultaneous read / write when the write word line 110 and the read word line 111 of the same row are simultaneously turned on is more dominant than the off-leak current of the read access transistor 122 An erroneous read current suppression effect can be obtained effectively within the area.

  The setting is not limited to C <B, but may be set to satisfy B <C as shown in FIG. 3, for example. In this case, an off-leakage current of the read access transistor 122 and an error caused by floating of an internal node at the time of simultaneous writing / reading to the memory cell 130 in the same row while the read access transistor 122 is on and the read drive transistor 120 is off. When compared with the read current, if the former is large, the influence on erroneous read to the read bit line 114 can be reduced.

  When the gate width of the N-channel transistor 108 constituting the holding circuit 103 of the memory cell 130 is very wide, the floating of the internal node during the simultaneous read / write operation can be suppressed. In such a case, the off-leakage current of the read access transistor 122 becomes more dominant than the erroneous read current during simultaneous read / write when the write word line 110 and the read word line 111 in the same row are simultaneously turned on. In such a case, by suppressing the off-leak current side preferentially, it is possible to effectively suppress the erroneous reading within a limited memory cell area.

  In addition, it is not necessarily set so that A <B and A <C as described above, and for example, as shown in FIG.

  Furthermore, the configuration as described above is not limited to a memory cell having a single-ended read structure, and may be applied to a complementary bit line read type memory cell, for example, as shown in FIGS. Even in this case, it is possible to easily suppress a decrease in the potential difference between the complementary bit lines when the sense amplifier is activated due to a decrease in the potential of the bit line on the side where the “H” state should be maintained.

<< Embodiment 2 of the Invention >>
As a second embodiment of the present invention, a semiconductor memory device having a hierarchical bit line structure, for example, as shown in FIG. 7, one global read bit line 137 is provided for a plurality of columns (for example, four columns). A semiconductor memory device will be described. In this semiconductor memory device, power consumption required for charging / discharging the global read bit line 137 is only required for one column, regardless of which column is to be read. This will be described in more detail below.

  This semiconductor memory device is provided with a plurality of memory cell groups 131 (local blocks) in which a plurality of (for example, 16) memory cells 130 as described in the first embodiment are combined. A plurality of the memory cell groups 131 are arranged in the direction of the global read bit line 137 to constitute one column, and four columns are arranged in the direction of the word lines 110 and 111. The memory cells 130 in each memory cell group 131 are connected to the individual local read bit lines 114 ′ for each memory cell group 131 and to the common write bit lines 112 and 113 in the column.

  A local amplifier 136 is provided between each pair of four memory cell groups 131 adjacent in the direction of the global read bit line 137. The local amplifier 136 includes P-channel transistors P1 to P20 and N-channel transistors N1 and N2. The P channel transistors P1 to P8 form a precharge circuit, and precharge the local read bit line 114 'in response to a precharge signal LBPCG. The P-channel transistors P9 to P16 are configured to raise the node I1 to “H” when the local read bit line 114 ′ is “L”. The P channel transistors P17 to P20 select a column in response to a 4-bit column selection signal NCAD10-13. The N channel transistor N1 keeps the node I2 at "L" during standby. The N-channel transistor N2 is a global bit line driver, and when the node I2 is “H”, the global read bit line 137 is set to “L”.

  The layout of each transistor and wiring constituting the memory cell 130 is not particularly limited, but can be arranged in a so-called horizontal topology as shown in FIGS. FIG. 8 shows a layout of each transistor including a gate electrode pattern. FIG. 9 shows a wiring pattern in the direction of the word lines 110 and 111 in the memory cell in the first metal wiring layer. FIG. 10 shows a wiring pattern in the second metal wiring layer in the direction of the global read bit line 137 (local read bit line 114 ′, write bit lines 112 and 113, power supply lines VDD and VSS, etc.). FIG. 11 shows a wiring pattern of the word lines 110 and 111 in the third metal wiring layer. FIG. 12 shows a wiring pattern of the power supply lines VDD and VSS and one global read bit line 137 per four columns in the fourth metal wiring layer. The power supply wirings VDD and VSS of the fourth metal wiring layer serve both as a shield to the lower layer and power supply reinforcement. When such a layout is used, the use of the hierarchical bit line structure facilitates mitigation of the wiring congestion of the second metal wiring layer, and the global read bit line 137 also in the fourth metal wiring layer. Can be provided only for a plurality of columns, the wiring density is reduced, the wiring interval is secured widely, the coupling capacity between the global read bit line 137 and the same layer wiring is reduced, and the low It is possible to easily achieve power consumption and high-speed operation. In addition, the wiring width of the global read bit line 137 can be increased to reduce the wiring resistance, and the probability of a wiring short can be reduced to improve the yield. Further, it is possible to easily form a strong power supply system by increasing the width of the power supply wiring.

  Also, the layout including the peripheral circuits is not particularly limited. For example, the layout can be configured as schematically shown in FIG. The example shown in the figure includes 4 × 8 memory cell groups 131 and has a configuration called 1W-1R type dual port SRAM. That is, separate clock signals CLKW and CLKR and address signals ADW and ADR are input to the write port side and the read port side, respectively, and basically write and read are performed separately for separate addresses. It can be done in clock cycles and clock timing.

  In the semiconductor memory device as described above, the power consumption can be reduced compared to the case where global bit lines are provided in each column and these are charged / discharged simultaneously. Further, the global read bit line 137, the precharge (discharge) circuit of the node I2, the global bit line driver and the like do not need to be provided for each column, and it is not necessary to provide each element or element isolation region. The area can be easily reduced.

  Note that the number of memory cells in each memory cell group, the number of memory cell groups in a column, the number of columns per global read bit line, and the like are not particularly limited and can be variously set. Specifically, for example, as shown in FIG. 14, one global read bit line 137 is provided corresponding to two columns, or the number of local blocks at the end of the column is within other local blocks. The number of memory cells may be smaller than that of the memory cell. The number of memory cell ports is not limited to a dual port, and may include more read and / or write ports such as a triple port.

  Further, the local amplifier 136 is not limited to the above configuration. For example, as shown in FIG. 15, the N channel transistor N2 is controlled by the signal of the node I1, and the output of the N channel transistor N2 is the column selection signal NCAD10-11. May be selected by P-channel transistors P17 and P18 controlled by.

  Further, the column selection signal is not limited to be input to each local amplifier 136 in common, but only the column selection signal corresponding to the memory cell group 131 including the memory cell 130 selected by the read word line 111 is “L”. In other words, a row address signal or a signal logically operated with the decode signal may be used so as to be "." As a result, the column selection signal can only undergo a minimum level transition, so that the power consumption can be further reduced.

  In addition, the write bit lines 112 and 113 may be hierarchized as shown in, for example, ISSCC 2007 “A 45 nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations” (Renesas / Matsushita). In addition, the power consumption may be further reduced. Specifically, as shown in FIG. 16, for example, local write bit lines 112 ′ and 113 ′, global write bit lines 141 and 142, a precharge transistor 143, and a selection transistor 144 are provided, and a memory cell 130 in which writing is performed. Only the levels of the local write bit lines 112 ′ and 113 ′ corresponding to may be changed according to the data to be written.

  The local write bit lines 112 ′ and 113 ′ may be provided so as to correspond to the same number of memory cells 130 as the local read bit lines 114 ′ correspond to, but correspond to an integer multiple of the memory cells 130. It may be provided as follows. In this case, the local write bit lines 112 ′ and 113 ′ are longer than the local read bit line 114 ′ (parasitic capacitance is increased), but the data I / O unit (not shown) is compared with the drive capability of the memory cell 130. Since the write buffer disposed in the memory has a large driving capability, the number of precharge transistors 143 and selection transistors 144 can be reduced while the area of the semiconductor memory device can be reduced while relatively high speed of writing can be achieved. It becomes easy.

  The precharge transistor 143 and the selection transistor 144 may be disposed in the same region where the local amplifier 136 is disposed. This makes it easier to reduce the dead space provided at the boundary between the logic circuit region and the memory cell region and further reduce the area of the semiconductor memory device.

<< Embodiment 3 of the Invention >>
Instead of the local amplifier 136 of the second embodiment, a local amplifier 146 may be provided as shown in FIG. The local amplifier 146 is provided with a NOR circuit 147 that receives the signal of the local read bit line 114 ′ and the column selection signal NCAD10-11 and drives the N-channel transistor N2. Even in such a configuration, only the signal corresponding to the data held in the memory cell 130 of the column selected by the column selection signal is transmitted to one global read bit line 137. It is possible to easily reduce the wiring area while keeping the power small.

  When the local amplifier 146 as described above is used, a global read bit line 137 may be provided for each column. Even in that case, since the potential of the global read bit line 137 of the column not selected by the column selection signal does not transit regardless of the stored contents of the memory cell 130, the power consumption can be reduced. In addition, since the wiring connecting each N-channel transistor N2 and the global read bit line 137 can be shortened, the delay due to the parasitic capacitance of the wiring can be suppressed small.

  Also in the third embodiment, various modifications as described in the second embodiment may be applied.

<< Embodiment 4 of the Invention >>
An example of a semiconductor memory device having a hierarchical bit line structure and capable of more accurate reading will be described.

  First, read timing of stored data will be described with reference to FIG. When the data stored in the memory cell is data for discharging the local bit line (discharge data), the potential of the local bit line is indicated by symbol P when a row is selected by the read word line. So as to decline rapidly. On the other hand, when the data stored in the memory cell is data (maintenance data) for maintaining the potential of the local bit line, it is ideal that the potential of the local bit line does not change as indicated by the symbol Q. In practice, however, it gradually decreases as indicated by the symbol R due to the influence of off-leakage of the read access transistor. Therefore, in order to perform appropriate reading, the read signal corresponding to the potential of the global bit line is latched at the timing within the period t1 (more precisely, the timing according to the transition of the potential of the corresponding global bit line). There is a need to. Further, the period t1 varies depending on the power supply voltage, the environmental temperature, etc., as shown in FIG.

  Therefore, as shown in FIG. 20, the semiconductor memory device of the fourth embodiment controls the latch timing of the read signal by using the replica memory cell 167 (dummy memory cell) and the replica control circuit 168 (dummy read output circuit). It is supposed to be.

  More specifically, for example, as shown in FIG. 21, an RS flip-flop 311 is provided in the read control area.

  In the read row decoder area, a replica dummy row decoder 164 (dummy row decoder) is provided in addition to a normal row decoder 301 similar to that of a normal semiconductor memory device.

  The replica memory cell area includes the replica memory cell 167, the unused memory cell 169, the replica local read bit line 312 (dummy local read bit line), the replica local amplifier 313 (dummy local amplifier), and the replica global read bit line 314. (Dummy global read bit line) is provided.

  In the column I / O region, the replica control circuit 168 is provided in addition to the output circuit 302 having a latch function similar to a normal semiconductor memory device.

  The RS flip-flop 311 is set at the rising edge of the read clock signal CLKR, and is reset by the timing signal output from the replica control circuit 168.

  The replica dummy row decoder 164 outputs a read word signal for all read addresses at the same timing as that of the normal row decoder 301 while the RS flip-flop 311 is set.

  The replica memory cell 167 has a circuit configuration and an element layout as shown in FIGS. 22 and 23, for example. The N channel transistors N11 and N12 always discharge the replica local read bit line 312 in accordance with the read word signal output from the replica dummy row decoder 164. N channel transistors N13 to N16 are not functionally required, but N channel transistors N13 and N14 are gate wirings connected to the normal read word line 111 at the boundary with the normal memory cell 130 in the layout pattern. Is provided to exist. The N channel transistors N15 and N16 are provided as optical dummies. Note that a latch circuit may be provided similarly to the normal memory cell 130, but the area can be reduced by omitting the latch circuit.

  The replica local amplifiers 313 are provided in the same number as the normal local amplifiers 136 and, like the local amplifiers 136, the replica global read bit lines 314 are discharged according to the signal of the replica local read bit lines 312. Note that at least one of the replica local amplifiers 313 is configured to operate according to the signal of the replica local read bit line 312, and the other is an N channel for driving the replica global read bit line 314 in the normal local amplifier 136. Only transistor N2 may be provided with its gate connected to VSS.

  The replica control circuit 168 outputs a timing signal at a predetermined timing according to the delay amount of the output circuit 302 according to the potential of the replica global read bit line 314.

  With the above configuration, the output circuit 302 is controlled at an appropriate timing according to fluctuations in the power supply voltage, environmental temperature, device characteristics in the manufacturing process, etc., and an operation margin is ensured and accurate reading is performed. Can be easily performed. In addition, since the timing control according to the length and parasitic capacitance of the local read bit line 114 ′ and the global read bit line 137 is automatically performed, the number of memory cells 130 in the memory cell group 131, Even in the case of manufacturing semiconductor memory devices having various numbers of memory cell groups 131, it is easy to save or reduce design and adjustment work.

  More specifically, since a replica circuit that generates a read timing using a circuit used for an actual read operation is configured, for example, the gate electrode is thinned, the impurity implantation variation into the diffusion region of the memory cell, or With respect to variations in the wiring capacity due to the finish of the wiring layer, the inter-wiring film thickness, the Via diameter, etc., an accurate replica operation can be performed with respect to the actual reading operation, and a stable countermeasure against erroneous reading can be realized. Therefore, for example, in a semiconductor memory device including a leak current of an access transistor of a read port, and in particular a memory cell having a read drive transistor 120, it is caused by simultaneous write / read operations in the same row. It is possible to easily prevent erroneous reading that occurs when the local bit line potential that is expected to hold the “H” state decreases to the “L” state. As a result, the read timing is optimally set between the normal read operation and the erroneous read current, so that a non-defective product can be obtained.

  In addition, many miniaturized SRAMs in recent years have a redundant relief function. However, as described above, a cell with extremely low cell current in normal reading or a cell that causes erroneous reading has a defective bit number even when the cell characteristics fluctuate from a predetermined value due to process finishing variation factors. Since an increase in exponential function is avoided, a large number of redundant spare cells to be mounted can be used for defectively processed memory cells and the like, so that a higher yield can be obtained.

  It is to be noted that not only all the replica circuits and wirings as described above are provided, but, for example, instead of the replica memory cell 167, the replica local read bit line 312 and the replica control circuit 168 as shown in FIG. A delay adjustment circuit 163 having a delay time corresponding to the time may be used. Even in this case, timing control according to the delay time mainly by the replica local amplifier 313 and the replica global read bit line 314 can be appropriately performed. In addition, since the delay adjustment circuit 163 can be easily configured with transistors in the peripheral circuit logic unit that is not the memory array unit, the delay adjustment circuit 163 is arranged in a layout-like manner due to the size relationship between the data input / output unit and the row decoder unit. When there is a large blank space, the above effect can be obtained with a smaller area than when a replica memory cell is provided in the memory array by arranging a replica layout composed of an inverter delay or the like in that portion. Can do.

  Further, as shown in FIG. 25, the delay adjusting circuit 163 may have a delay time corresponding to the delay time by the replica local read bit line 312 or the replica local amplifier 313, and further, as shown in FIG. A one-shot pulse generation circuit 160 using the element 161 may be provided, and the output pulse may be supplied to the output circuit 302 via the replica global read bit line 314 as a timing signal. As a result, the timing control according to the length of the replica global read bit line 314 and the parasitic capacitance can be performed with a simple circuit configuration. Therefore, a special replica memory as shown in FIG. 22, for example, does not hold write data, but always operates at a fixed “H” or “L” potential, which is different from a normal memory cell. This can reduce development man-hours for additional cell development.

  Further, when using the replica memory cell 167 and / or the replica local amplifier 313 as a drive circuit, as shown in FIGS. 27 and 28, a plurality of or a plurality of sets of these are used (in the example of FIG. Are provided in parallel, and the replica local read bit line 312 and / or the replica global read bit line 314 as a driven circuit, such as the number or length corresponding to each, are provided in parallel or linearly. May be. That is, by providing a plurality of driving circuits and driven circuits, the influence of variation in characteristics can be averaged and reduced, and by increasing the driving capability of the driving circuit and increasing the parasitic capacitance of the driven circuit, 1 A delay time equivalent to the case where they are provided one by one can be generated.

  In the above case, only one replica local amplifier 313 having a circuit to which the signal of the replica local read bit line 312 is input is provided so that two N-channel transistors N2 are controlled by the output of the circuit. Also good.

<< Embodiment 5 of the Invention >>
An example of a semiconductor memory device in which reliable reading can be easily performed even when the number of memory cells in the memory cell group is different from other memory cell groups will be described.

  In the semiconductor memory device of the fifth embodiment, for example, as shown in FIG. 29, three memory cell groups 131A to 131C are provided. The memory cell groups 131A and 131B are each provided with 16 memory cells 130, while the memory cell group 131C is provided with two memory cells 130. Therefore, the local read bit line 114 'of the memory cell group 131C is formed shorter than the local read bit line 114' of the memory cell groups 131A and 131B, and the wiring capacitance is also reduced. However, a dummy capacitor 181 is connected to the local read bit line 114 ′ of the memory cell group 131C, and the total of the wiring capacitance is equal to the local read bit line 114 ′ of the memory cell groups 131A and 131B. .

  The adjustment as described above is particularly useful for accurate reading because a slight difference in bit line capacitance has a great influence on the read timing in a semiconductor memory device having a hierarchical bit line structure having a relatively small bit line capacitance. .

  Specifically, as the dummy capacitor 181, an inter-wiring capacitor formed by a wiring pattern may be used. For example, as shown in FIG. 30, the source electrode and the drain electrode of the MOS transistor 190 are connected to each other. Thus, the gate capacitance between these and the gate electrode can be used. Further, as shown in FIG. 31, the source electrode and the gate electrode may be connected to each other, and the diffusion capacitance between these and the drain electrode may be used. According to these, a special manufacturing process is not required, and the gate oxide film is generally thinner than the inter-wiring film thickness, etc., so that a large capacitance is formed in a small area, and the area efficiency of the semiconductor substrate is increased. Can be easily done.

  Further, as shown in FIG. 32, a plurality of types of capacitors such as an interwiring capacitor and a diffusion capacitor may be combined. More specifically, as shown in FIGS. 33 to 35, diffusion layers 204 and 205 are formed on the semiconductor substrate, wiring patterns 202 and 203 are formed on the first wiring layer, and the second wiring layer is formed on the second wiring layer. The wiring patterns 200 and 201 are formed. The wiring pattern 200 is connected to the local read bit line 114 ′ of the memory cell group 131 </ b> C, and is connected to the wiring pattern 202 and the diffusion layer 204 through vias. Further, the wiring pattern 201, the wiring pattern 203, and the diffusion layer 205 are connected to each other through a via and are grounded.

  As described above, when the dummy capacitor is formed by the diffusion layer or the wiring layer in the same manner as the bit line capacitance is formed, the variation of the diffusion capacitance due to the impurity implantation variation, the wiring width, the wiring film thickness, It is possible to easily form a highly accurate dummy capacitor according to variations caused in a manufacturing process such as a wiring interlayer film and a via diameter. Therefore, even a memory cell group with an odd number of words can be easily read with high accuracy, and the yield of the semiconductor memory device can be easily increased. Note that a wiring pattern or a diffusion region having a shape or configuration more similar to the memory cell shape may be formed.

Embodiment 6 of the Invention
As shown in FIG. 36, the semiconductor storage device 401 according to the sixth embodiment includes, for example, a 2-port SRAM 402, a BIST circuit 403 (Built In Self Test circuit), and selectors 404 and 405.

  The selectors 404 and 405 are configured to switch the input / output signals of the 2-port SRAM 402 from the other circuits in the semiconductor memory device 401 to the BIST circuit 403 when testing the 2-port SRAM 402. In the 2-port SRAM 402, various signals other than those shown in the figure are input / output, but the description thereof is omitted for simplification.

  For example, as shown in FIG. 37, the 2-port SRAM 402 includes a memory cell 130 having a holding circuit 103, write access transistors 116 and 117, a read drive transistor 120, and a read access transistor 122. As shown in FIG. 38, the read drive transistor 120 and the read access transistor 122 can apply a predetermined forward bias by separating the substrate potential from the source potential. As the forward bias, for example, the threshold voltages of the read drive transistor 120 and the read access transistor 122 are set to be equal to the threshold voltage at the highest ambient temperature allowed in the specification.

  When testing, for example, the memory cell 130A of the 2-port SRAM 402, the BIST circuit 403 first writes data that turns off the read drive transistor 120 to the memory cell 130A, while writing to all other memory cells 130. The data for turning on the read drive transistor 120 is written. The predetermined forward bias is applied to the read drive transistor 120 and the read access transistor 122. In this state, while the write bit lines 112 and 113 are kept at “H”, both the write word line 110 and the read word line 111 connected to the memory cell 130A are turned on. That is, while memory cell 130A is selected as a cell from which stored data is read, in the case of a multi-column configuration, memory cell 130A is brought into the same state as when data is written to a memory cell in another column of the same row as memory cell 130A. Data stored in 130A is read.

  In the state as described above, the potential of the global read bit line 137 decreases most rapidly with respect to reading of data to be maintained. Even in this case, the potential of the “global read bit line 137 is maintained. If it is determined that the “data to be read” has been read, erroneous reading due to the read timing being too late will not occur. On the other hand, if it is determined that erroneous reading has occurred, it may be a defective product or may be replaced with a redundant memory cell provided in advance. In addition, it may be tested again as a device with a more lenient specification condition.

  As described above, the influence when data is written to the memory cell in the same row as the memory cell from which the stored data is read, the influence of the off-leak current of the read access transistor in other memory cells in the same column, and the high ambient temperature Since it is possible to perform a test in which the influence of (corresponding to the substrate voltage) is taken into account, accurate determination of good / bad is performed accurately. Moreover, the test cost can be greatly reduced as compared with the case where the test is actually performed at a high environmental temperature.

  In addition to the above-described test, under the reverse condition, the potential of the global read bit line 137 is made to decrease most slowly with respect to data reading, and in that case A test may be performed to determine whether or not the “data whose potential of the global read bit line 137 should be lowered” has been read.

  Further, the transistor that applies the substrate voltage separated from the source voltage is not limited to the above, and the transistor of the holding circuit 103 and the write access transistors 116 and 117 are also tested under more severe conditions by applying a predetermined substrate voltage. You may be able to do it. Further, for example, when a memory having the local amplifier 136 as described in the second embodiment (FIG. 7) is tested, a predetermined forward bias is also applied to the substrates of the P-channel transistors P9 to P16 constituting the local amplifier 136. It is also possible to test under more severe conditions.

  The test method as described above may also be applied to a memory having a memory cell that does not have a read drive transistor. In that case, the influence of simultaneous read / write on the memory cells in the same row as described above does not originally occur, so it is not an object of consideration for the test conditions. Can do.

  In addition, each memory cell may be inspected individually or automatically or continuously.

  Further, it is not always necessary to apply the substrate voltage as described above, but it is possible to perform a quality test due to other factors. On the other hand, the BIST circuit 403 may not be provided, and only the substrate voltage may be applied so that it can be used for manual inspection.

  Note that the components described in the above embodiments and modifications may be combined in various ways within a logically possible range. Specifically, for example, a memory cell having a gate length as described in the first embodiment may be used in each of the other embodiments, and the local amplifier 146 as described in the third embodiment (FIG. 17) is provided. The configuration is applied to the configuration having the replica circuit as described in the fourth embodiment, or the configuration including the dummy capacitor 181 and the BIST circuit 403 as described in the fifth and sixth embodiments is different from the configuration of the other embodiments. You may combine.

  The semiconductor storage device to which the present invention is applied is not limited to a single element, but may be incorporated in a so-called system LSI or used as a register file.

  In addition, the present invention is particularly effective for a single-ended read type memory cell and a memory cell having a read drive transistor. However, the present invention is not limited to this. Some effects peculiar to the present invention can be obtained even for memory cells that do not have memory cells, memory cells that do not have read-only output circuits, and the like. The configurations of the first and sixth embodiments may be applied to a semiconductor memory device that does not have a hierarchical bit line structure.

  Further, the number of read / write ports is not limited to the above, and the present invention may be applied to a semiconductor memory device having a combination of two or more read / write ports.

  The semiconductor memory device according to the present invention has an effect of making it difficult to cause erroneous reading or easily reducing power consumption, and outputs a holding circuit and a signal corresponding to data held in the holding circuit. The semiconductor memory device is a so-called multiport SRAM (Static Random Access Memory) having a read output circuit.

1 is a circuit diagram showing a configuration of a memory cell provided in a semiconductor memory device according to a first embodiment of the present invention. It is a top view which shows the layout of the memory cell. It is a top view which shows the modification of the layout of a memory cell. It is a top view which shows the other modification of the layout of a memory cell. It is a circuit diagram which shows the structure of the other modification of a memory cell. It is a top view which shows the layout of the memory cell. It is a circuit diagram which shows the structure of the principal part of the semiconductor memory device of Embodiment 2 of this invention. It is a top view which shows the layout of the transistor of the memory cell of the same apparatus. It is a top view which shows the wiring pattern of the 1st metal wiring layer of the same apparatus. It is a top view which shows the wiring pattern of the 2nd metal wiring layer of the same apparatus. It is a top view which shows the wiring pattern of the 3rd metal wiring layer of the same apparatus. It is a top view which shows the wiring pattern of the 4th metal wiring layer of the same apparatus. It is a top view which shows the layout of the memory cell and peripheral circuit of the apparatus. It is a circuit diagram which shows the structure of the principal part of the modification of the same apparatus. It is a circuit diagram which shows the structure of the local amplifier of the other modification of the apparatus. It is a circuit diagram which shows the structure of the principal part of the further another modification of the apparatus. It is a circuit diagram which shows the structure of the principal part of the semiconductor memory device of Embodiment 3 of this invention. It is explanatory drawing which shows the example of the reading timing of stored data. It is explanatory drawing which shows the example of the fluctuation | variation of the reading timing of stored data. It is explanatory drawing which shows schematic structure of the semiconductor memory device of Embodiment 4 of this invention. It is a block diagram which shows the detailed structure of the same apparatus. It is a circuit diagram which shows the structure of the replica memory cell of the same apparatus. It is a top view which shows the layout of the replica memory cell of the same apparatus. It is a block diagram which shows the structure of the modification of the apparatus. It is a block diagram which shows the structure of the other modification of the apparatus. It is a block diagram which shows the structure of the other modification of the same apparatus. It is a block diagram which shows the structure of the further another modified example of the same apparatus. It is a circuit diagram which shows the structure of the principal part of the modification. It is a circuit diagram which shows the structure of the principal part of the semiconductor memory device of Embodiment 5 of this invention. It is a circuit diagram which shows the specific structure of the dummy capacity | capacitance of the apparatus. It is a circuit diagram which shows the other specific structure of the dummy capacity | capacitance of the apparatus. It is a circuit diagram which shows the other specific structure of the dummy capacity | capacitance of the apparatus. It is a top view which shows the pattern of the diffusion layer of the dummy capacity | capacitance of the apparatus. It is a top view which shows the pattern of the wiring of the 1st wiring layer of the dummy capacity | capacitance of the same apparatus. It is a top view which shows the pattern of the wiring of the 2nd wiring layer of the dummy capacity | capacitance of the apparatus. It is a block diagram which shows schematic structure of the semiconductor memory device of Embodiment 6 of this invention. It is a circuit diagram which shows the structure of the principal part of the apparatus. It is a circuit diagram which shows the structure of the memory cell of the same apparatus.

Explanation of symbols

103 Holding circuit 103a Input / output node 106 P channel transistor 107 P channel transistor 108 N channel transistor 109 N channel transistor 110 Write word line 111 Read word line 112, 113 Write bit line 112 ', 113' Local write bit line 114 Read bit line 114 'Local read bit line 116,117 Write access transistor 120.121 Read drive transistor 122,123 Read access transistor 130 Memory cell 131 Memory cell group 136 Local amplifier 137 Global read bit line 141, 142 Global write bit line 143 Precharge transistor 144 Selection transistor 146 Local amplifier 147 NOR circuit 15 N well region 152, 153 P well region 160 One shot pulse generation circuit 161 Delay element 163 Delay adjustment circuit 164 Replica dummy row decoder 167 Replica memory cell 168 Replica control circuit 169 Unused memory cell 181 Dummy capacity 190 MOS transistor 200 Wiring pattern 201 Wiring pattern 202 Wiring pattern 203 Wiring pattern 204 Diffusion layer 205 Diffusion layer 301 Normal row decoder 302 Output circuit 311 RS flip-flop 312 Replica local read bit line 313 Replica local amplifier 314 Replica global read bit line 401 Semiconductor memory device 402 Port SRAM
403 BIST circuit 404, 405 selector
I1 node
I2 node
N1 N-channel transistor
N2 N-channel transistors N11 and N12 N-channel transistors N13 and N14 N-channel transistors N15 and N16 N-channel transistors P1 to P20 P-channel transistors

Claims (35)

A holding circuit for holding stored data;
A read-only output circuit that outputs a signal corresponding to the data held in the holding circuit;
A semiconductor memory device comprising a plurality of memory cells having
The read-only output circuit has a read drive transistor that is controlled according to a signal held in the holding circuit,
2. The semiconductor memory device according to claim 1, wherein a gate length of the read drive transistor is longer than a gate length of a transistor constituting the holding circuit. A holding circuit for holding stored data;
A read-only output circuit that outputs a signal corresponding to the data held in the holding circuit;
A semiconductor memory device comprising a plurality of memory cells having
The read-only output circuit is
A read drive transistor controlled according to a signal held in the holding circuit, and a read access transistor controlled by a read word selection signal;
2. The semiconductor memory device according to claim 1, wherein the read access transistor has a gate length longer than a gate length of the transistor constituting the holding circuit. A bit line for reading stored data is a semiconductor memory device having a hierarchical bit line structure,
A plurality of local blocks each having a plurality of memory cells and a local read bit line to which the memory cells are connected include a plurality of columns arranged in the direction of the local read bit line,
A global read bit line provided in common corresponding to a plurality of columns;
A local amplifier that drives the global read bit line according to the signal output from each local block,
With
Each of the above memory cells
A holding circuit for holding stored data;
A read output circuit for outputting a signal corresponding to the data held in the holding circuit to one local read bit line;
Have
At the time of reading the retained data, only one memory cell in one local block is activated for each column,
The local amplifier is
A drive transistor for controlling the presence or absence of application of a predetermined potential according to an input signal;
A column selection transistor that controls the presence or absence of conduction between the input and output terminals in accordance with a column selection signal;
A semiconductor memory device comprising: The semiconductor memory device according to claim 3,
One local amplifier is provided for every two local blocks in each column.
The drive transistor includes two first drive transistors and one second drive transistor,
Each of the first drive transistors controls whether or not a predetermined potential is applied according to the potential of the local read bit line, and the output terminals of the two first drive transistors are connected to each other.
The column selection transistor is provided between the first drive transistor and the global read bit line, and controls the presence or absence of conduction between the input and output terminals according to the column selection signal.
The second drive transistor is provided between the column selection transistor and the global read bit line or between the first drive transistor and the column selection transistor, and is connected to the column selection transistor or the first drive transistor. Depending on the applied potential, the presence or absence of application of a predetermined potential is controlled,
A semiconductor memory device, wherein a second drive transistor or a column selection transistor of each local amplifier is connected to one global read bit line. The semiconductor memory device according to claim 3,
The semiconductor memory device, wherein the local read bit line and the global read bit line are formed in different wiring layers. The semiconductor memory device according to claim 3, further comprising:
A pair of global write bit lines to which signals according to stored data are applied;
A plurality of pairs of local write bit lines each having a plurality of memory cells connected thereto;
A local write control circuit for controlling whether or not a predetermined potential is applied to the local write bit line in accordance with the potential of the global write bit line;
With
The semiconductor memory device, wherein the local write control circuit is arranged in a region where the local amplifier is arranged. The semiconductor memory device according to claim 6,
A pair of the local write bit lines are provided corresponding to a plurality of local blocks. A bit line for reading stored data is a semiconductor memory device having a hierarchical bit line structure,
A plurality of local blocks each having a plurality of memory cells and a local read bit line to which the memory cells are connected include a plurality of columns arranged in the direction of the local read bit line,
One global read bit line corresponding to at least one column;
A local amplifier that drives the global read bit line according to the signal output from each local block,
With
Each of the above memory cells
A holding circuit for holding stored data;
A read output circuit for outputting a signal corresponding to the data held in the holding circuit to one local read bit line;
Have
At the time of reading the retained data, only one memory cell in one local block is activated for each column,
The local amplifier is
A logic element that outputs a signal corresponding to the potential of the local read bit line when selected by a column selection signal;
A drive transistor having an output terminal connected to the global read bit line and controlling the presence or absence of application of a predetermined potential according to the output signal of the logic element;
A semiconductor memory device comprising: 9. The semiconductor memory device according to claim 8, wherein
One global read bit line is provided corresponding to a plurality of columns,
A semiconductor memory device, wherein a drive transistor of each local amplifier is connected to the one global read bit line. 9. The semiconductor memory device according to claim 8, wherein
The semiconductor memory device, wherein the local read bit line and the global read bit line are formed in different wiring layers. 9. The semiconductor memory device according to claim 8, further comprising:
A pair of global write bit lines to which signals according to stored data are applied;
A plurality of pairs of local write bit lines each having a plurality of memory cells connected thereto;
A local write control circuit for selecting one of the plurality of pairs of local write bit lines and connecting to the global write bit line;
Prepared,
The semiconductor memory device, wherein the local write control circuit is arranged in a region where the local amplifier is arranged. The semiconductor memory device according to claim 11, comprising:
A pair of the local write bit lines are provided corresponding to a plurality of local blocks. A bit line for reading stored data is a semiconductor memory device having a hierarchical bit line structure,
A plurality of local blocks each having a plurality of memory cells and a local read bit line to which the memory cells are connected;
A global read bit line,
A local amplifier that drives the global read bit line according to the signal output from each local block;
A read output holding circuit that holds and outputs a signal of the global read bit line at a predetermined timing;
A row decoder for generating a read word selection signal for selecting any of the plurality of memory cells;
With
Each of the above memory cells
A holding circuit for holding stored data;
A read output circuit for outputting a signal corresponding to the data held in the holding circuit to one local read bit line;
And having
further,
A semiconductor memory device comprising a dummy global read bit line, and a timing control circuit for controlling a signal holding timing by the read output holding circuit based on a delay time of the dummy global read bit line. 14. The semiconductor memory device according to claim 13, wherein
In addition to the delay time of the dummy global read bit line, the timing control circuit has a total time corresponding to the delay time of the row decoder, memory cell, local read bit line, local amplifier, and read output holding circuit. Based on the above, a semiconductor memory device is characterized in that the holding timing of the signal by the read output holding circuit is controlled. 15. The semiconductor memory device according to claim 14, wherein
The timing control circuit further includes a delay circuit,
A semiconductor memory device configured to set the total time based on the dummy global read bit line and a delay time of a delay circuit. 15. The semiconductor memory device according to claim 14, wherein
The timing control circuit further includes all or any one of a dummy row decoder, a dummy memory cell, a dummy local read bit line, a dummy local amplifier, and a dummy read output holding circuit,
The total time is set based on the delay time of the dummy global read bit line, dummy row decoder, dummy memory cell, dummy local read bit line, dummy local amplifier, and dummy read output holding circuit. A semiconductor memory device. 15. The semiconductor memory device according to claim 14, wherein
The timing control circuit further includes a dummy memory cell, a dummy local read bit line, and a dummy local amplifier,
A semiconductor memory device, wherein the total time is set based on delay times of the dummy global read bit line, dummy memory cell, dummy local read bit line, and dummy local amplifier. The semiconductor memory device according to claim 17, comprising:
The semiconductor memory device, wherein the dummy memory cell and the dummy local amplifier are arranged in a region where the memory cell and the local amplifier are arranged. The semiconductor memory device according to claim 17, comprising:
The number of the dummy local amplifiers is the same as the number of local amplifiers connected to one global read bit line. One dummy local amplifier has the same configuration as the local amplifier, and the other dummy local amplifiers are local. A semiconductor memory device comprising an amplifier and the same transistor as a drive transistor connected to a global read bit line. The semiconductor memory device according to claim 17, comprising:
2. The semiconductor memory device according to claim 1, wherein the dummy memory cell includes the same circuit as a read output circuit included in the memory cell. The semiconductor memory device according to claim 17, comprising:
Two or more predetermined numbers of the dummy memory cells are provided, and the dummy local read bit line is configured to have a parasitic capacitance that is the predetermined number times the local read bit line. Storage device. The semiconductor memory device according to claim 21,
The dummy local read bit line is formed by the predetermined number of wiring patterns arranged in parallel with the same length as the local read bit line, or a wiring pattern of the predetermined number times as long as the local read bit line. A semiconductor memory device. The semiconductor memory device according to claim 17, comprising:
The dummy local amplifiers are provided by a predetermined multiple of two or more of the number of local amplifiers connected to one global read bit line, and the dummy global read bit lines are parallel with the same length as the global read bit line. A semiconductor memory device characterized by being formed by the predetermined number of wiring patterns arranged on the substrate. A bit line for reading stored data is a semiconductor memory device having a hierarchical bit line structure,
A plurality of local blocks each having a plurality of memory cells and a local read bit line to which the memory cells are connected;
A global read bit line,
A local amplifier that drives the global read bit line according to the signal output from each local block;
With
Each of the above memory cells
A holding circuit for holding stored data;
A read output circuit for outputting a signal corresponding to the data held in the holding circuit to one local read bit line;
Have
The plurality of local blocks include a small number of local blocks having a smaller number of memory cells than the other local blocks,
A semiconductor memory device, wherein a capacitive element is connected to a local read bit line of the minority local block. 25. The semiconductor memory device according to claim 24, wherein
2. The semiconductor memory device according to claim 1, wherein the capacitor element is formed using at least one of a gate capacitor, a diffusion capacitor, and an interwiring capacitor of a MIS transistor. A bit line for reading stored data is a semiconductor memory device having a hierarchical bit line structure,
A plurality of local blocks each having a plurality of memory cells and a local read bit line to which the memory cells are connected include a plurality of columns arranged in the direction of the local read bit line,
One or a plurality of global read bit lines corresponding to the plurality of local blocks,
A local amplifier that drives the global read bit line according to the signal output from each local block;
With
Each of the above memory cells
A holding circuit for holding stored data;
A read output circuit for outputting a signal corresponding to the data held in the holding circuit to one local read bit line;
And having
further,
In the memory cell to be inspected, data for maintaining the potential of the precharged local read bit line is stored,
In another memory cell connected to the same local read bit line as the memory cell to be inspected, data for discharging the potential of the precharged local read bit line is stored, and
While the memory cell to be inspected is in a read state,
Put other memory cells selected by the same write word selection signal as the memory cell to be inspected into the write state,
A semiconductor memory device comprising: an inspection circuit that determines whether data read from a memory cell to be inspected is correct. 27. The semiconductor memory device according to claim 26, comprising:
further,
Having redundant memory cells;
The semiconductor memory device, wherein the inspection circuit is set so that a redundant memory cell is used instead of the memory cell in which the read data is determined to be erroneous. 27. The semiconductor memory device according to claim 26, comprising:
The read output circuit includes a read access transistor controlled by a read word selection signal and a read drive transistor controlled according to a signal held in the holding circuit, or the read access transistor,
A semiconductor memory device, wherein the read access transistor and the read drive transistor, or the read access transistor, are configured such that a source potential and a substrate potential can be applied independently. The semiconductor memory device according to claim 28, wherein
The semiconductor memory device, wherein the inspection circuit is configured to apply a forward bias to the read access transistor and the read drive transistor or a substrate of the read access transistor to perform the inspection. 27. The semiconductor memory device according to claim 26, comprising:
A transistor constituting the local amplifier is configured so that a source potential and a substrate potential can be applied independently. The semiconductor memory device according to claim 30, wherein
The semiconductor memory device, wherein the inspection circuit is configured to apply a forward bias to the substrate of the transistor to perform the inspection. A bit line for reading stored data is a semiconductor memory device having a hierarchical bit line structure,
A plurality of local blocks each having a plurality of memory cells and a local read bit line to which the memory cells are connected;
A global read bit line,
A local amplifier that drives the global read bit line according to the signal output from each local block;
With
Each of the above memory cells
A holding circuit for holding stored data;
A read output circuit for outputting a signal corresponding to the data held in the holding circuit to one local read bit line;
And having
The read output circuit includes a read access transistor controlled by a read word selection signal and a read drive transistor controlled according to a signal held in the holding circuit, or the read access transistor,
A semiconductor memory device, wherein the read access transistor and the read drive transistor, or the read access transistor, are configured such that a source potential and a substrate potential can be applied independently. A semiconductor memory device according to claim 32, comprising:
A semiconductor memory device configured to be able to apply a forward bias to the read access transistor and the read drive transistor or the substrate of the read access transistor at the time of inspection. A bit line for reading stored data is a semiconductor memory device having a hierarchical bit line structure,
A plurality of local blocks each having a plurality of memory cells and a local read bit line to which the memory cells are connected;
A global read bit line,
A local amplifier that drives the global read bit line according to the signal output from each local block;
With
Each of the above memory cells
A holding circuit for holding stored data;
A read output circuit for outputting a signal corresponding to the data held in the holding circuit to one local read bit line;
And having
A transistor constituting the local amplifier is configured so that a source potential and a substrate potential can be applied independently. A semiconductor memory device according to claim 34,
A semiconductor memory device characterized in that a forward bias can be applied to the substrate of the transistor during inspection.

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