JP2008172470A - Voltage controlled oscillator and method for controlling oscillation frequency of voltage controlled oscillator - Google Patents

Abstract

In a variable capacitor used in a voltage controlled oscillator, a voltage controlled oscillator capable of using a linear region of a variable capacitor wider than a ground potential of a circuit to a power supply potential or more is provided.
An oscillating unit including inductors 2a and 2b, variable capacitors 10a, 10b, 11a, 11b, 12a and 12b constituting a resonance circuit, and a frequency control terminal 5 for controlling the resonance frequency of the resonance circuit. In addition, a bias circuit 201 that applies a bias voltage to the resonance circuit and a bias control circuit 202 that switches and controls the bias voltage of the bias circuit 201 according to the frequency control voltage are provided. When the frequency control voltage changes and exceeds a threshold value, the bias control circuit 202 switches the bias voltage in a direction to bring the frequency control voltage closer to the target control voltage.
[Selection] Figure 1

Description

  The present invention relates to a voltage controlled oscillator used in a radio communication transceiver and an oscillation frequency control method of the voltage controlled oscillator.

  A voltage controlled oscillator is widely used as a means for generating a local oscillation signal of a wireless communication device. An example of the configuration of such a conventional voltage controlled oscillator is shown in FIG.

  In the figure, reference numerals 1a and 1b indicate oscillation transistors which are negative resistance elements, reference numerals 2a and 2b indicate inductors, and reference numerals 3a and 3b correspond to the magnitude of a DC voltage applied between both terminals. Indicates a variable capacitor whose capacitance value changes. Reference numeral 4 represents a power supply terminal, reference numeral 5 represents a frequency control terminal, and reference numeral 6 represents a current source.

  The operation of the conventional voltage controlled oscillator will be described below with reference to FIG. In FIG. 11, inductors 2a and 2b and variable capacitors 3a and 3b constitute a parallel resonance circuit. The capacitance values of the variable capacitance elements 3a and 3b vary depending on the potential difference between the two terminals. Therefore, the capacitance values of the variable capacitors 3a and 3b change depending on the frequency control voltage applied to the frequency control terminal 5, and as a result, the resonance frequency of the parallel resonance circuit changes.

  Since the oscillation frequency of the voltage controlled oscillator oscillates in the vicinity of the resonance frequency of the resonance circuit, the oscillation frequency of the voltage controlled oscillator can be controlled to a desired frequency by adjusting the control voltage. The oscillation transistors 1a and 1b generate a negative resistance to cancel the loss due to the parasitic resistance component of the resonance circuit and satisfy the oscillation condition.

  Here, the relationship between the control voltage and the oscillation frequency of the voltage controlled oscillator is substantially determined by the characteristics of the variable capacitors 3a and 3b. Therefore, it is desirable for the variable capacitors 3a and 3b to be used to change their capacitance gradually over a wide control voltage range. This is because, when a PLL (Phase Locked Loop) circuit is configured using a voltage controlled oscillator, the transient response characteristics and noise band characteristics of the PLL circuit depend on the frequency sensitivity with respect to the control voltage. This is because the characteristics of the circuit itself vary with frequency. Further, in a region where the frequency sensitivity with respect to the frequency control voltage is high, there is a problem that the phase noise characteristic is deteriorated because the frequency fluctuates even by a slight noise applied to the frequency control terminal.

  However, when a voltage-controlled oscillator is realized on a semiconductor substrate, introducing a special process to form the variable capacitance element leads to an increase in cost, so it is actually difficult to use a highly linear variable capacitance element. .

  FIG. 12A shows a variable capacitance element using the gate capacitance of a MOS transistor widely used in the CMOS process. FIG. 12B shows changes in the gate capacitance value when a reference voltage (reference potential) is applied to the gate of the MOS transistor and a frequency control voltage is applied to the drain / source side. In FIG. 12B, the horizontal axis represents the voltage difference between the voltage applied to the gate of the MOS transistor and the voltage applied to the drain / source side, and the vertical axis represents the capacitance value of the gate capacitance of the MOS transistor. .

  As described above, in a variable capacitance element using a gate capacitance of a MOS transistor that is generally used, the capacitance changes steeply in the vicinity of the threshold voltage, so the oscillation frequency also changes sharply in the region near the threshold voltage. As a result, there arises a problem that the transient response characteristic and noise band characteristic of the PLL circuit using the voltage controlled oscillator greatly vary depending on the frequency.

  In order to solve such a problem, a circuit described below has already been proposed.

  FIG. 13 shows a circuit example for improving the linearity of a conventional variable capacitor (see Patent Document 1). In this figure, the same parts as those in FIG. In FIG. 13, reference numerals 10a, 10b, 11a, 11b, 12a, 12b indicate variable capacitance elements, reference numerals 13a, 13b, 14a, 14b, 15a, 15b indicate DC blocking capacitors that block DC components, and reference numerals 16a, Reference numerals 16b, 17a, 17b, 18a and 18b denote resistors, and reference numeral 50 denotes a reference voltage generation circuit.

  In this circuit, inductors 2a and 2b are connected in series, and a series circuit of DC blocking capacitor 13a, variable capacitance element 10a, variable capacitance element 10b and DC blocking capacitor 13b is connected in parallel to the series circuit of inductors 2a and 2b. Similarly, a series circuit of a DC blocking capacitor 14a, a variable capacitance element 11a, a variable capacitance element 11b, and a DC blocking capacitor 14b is connected in parallel, and further, a DC blocking capacitor 15a, a variable capacitance element 12a, a variable capacitance element 12b, and a DC blocking A series circuit of capacitors 15b is connected in parallel.

  A series circuit of resistors 16a and 16b is connected between a connection point between the DC blocking capacitor 13a and the variable capacitance element 10a and a connection point between the variable capacitance element 10b and the DC blocking capacitor 13b. Similarly, a series circuit of resistors 17a and 17b is connected between a connection point between the DC blocking capacitor 14a and the variable capacitance element 11a and a connection point between the variable capacitance element 11b and the DC blocking capacitor 14b. Furthermore, a series circuit of resistors 18a and 18b is connected between a connection point between the DC blocking capacitor 15a and the variable capacitance element 12a and a connection point between the variable capacitance element 12b and the DC blocking capacitor 15b.

  Further, the frequency control terminal 5 is commonly connected to the connection point of the variable capacitance elements 10a and 10b, the connection point of the variable capacitance elements 11a and 11b, and the connection point of the variable capacitance elements 12a and 12b. The output terminal 50a of the reference voltage generation circuit 50 is connected to the connection point of the resistors 16a and 16b. Similarly, the output terminal 50b of the reference voltage generation circuit 50 is connected to the connection point of the resistors 17a and 17b. Further, the output terminal 50c of the reference voltage generation circuit 50 is connected to the connection point of the resistors 18a and 18b.

  From the three output terminals 50a, 50b and 50c of the reference voltage generation circuit 50 which is a bias circuit, voltages shifted by the voltage Vd such as Vb, Vb−Vd and Vb−2Vd are output. The frequency control terminal 5 is supplied with a frequency control voltage Vc. Therefore, the potential difference between both terminals of the variable capacitance elements 10a and 10b is a difference voltage between the frequency control voltage Vc and the voltage Vb, respectively. Similarly, the potential difference between both terminals of the variable capacitance elements 11a and 11b is a difference voltage between the frequency control voltage Vc and the voltage Vb−Vd, respectively. Furthermore, the potential difference between both terminals of the variable capacitance elements 12a and 12b is a difference voltage between the frequency control voltage Vc and the voltage Vb-2Vd.

  FIG. 14 shows the characteristics of the capacitance values of the variable capacitance elements 10a, 10b, 11a, 11b, 12a and 12b and the total characteristics of the variable capacitance elements 10a, 10b, 11a, 11b, 12a and 12b with respect to the frequency control voltage. ing. In FIG. 14, a curve X1 indicates the capacitance value characteristics of the variable capacitance elements 10a and 10b, a curve X2 indicates the capacitance value characteristics of the variable capacitance elements 11a and 11b, and a curve X3 indicates the capacitance value of the variable capacitance elements 12a and 12b. The curve X4 shows the total characteristic of the variable capacitance element. In FIG. 14, the horizontal axis represents the frequency control voltage Vc, and the vertical axis represents each variable capacitance element or the total capacitance value thereof.

Therefore, as shown in FIG. 14, the characteristics of the variable capacitance elements can be shifted by the voltage Vd, and they can be synthesized. For this reason, the change in capacitance with respect to the frequency control voltage can be moderated. As a result, the frequency dependence of the transient response characteristic and noise band characteristic of the PLL circuit can be eliminated.
JP 2004-147310 A

  However, when the voltage controlled oscillator is incorporated in a PLL circuit, the range of the frequency control voltage is limited even if there is a linear region of variable capacitance that exceeds the voltage range from the ground potential of the circuit to the power supply potential of the circuit. For this reason, there is a problem that it is not possible to use all of the variable capacitance linear region. The reason is as follows.

  As shown in FIG. 15, the PLL circuit generally includes a voltage controlled oscillator (VCO) 100, a frequency divider (DIV) 101 that divides the output of the voltage controlled oscillator 100, an output of the frequency divider 101, and a reference. A phase comparator (PD) 102 that compares frequency signals, a charge pump (CP) 103 that inputs and outputs current according to the output of the phase comparator 102, and a low-pass filter (LPF) that averages the output of the charge pump 103 And a closed-loop circuit that feeds back the output of the low-pass filter 104 to the voltage control terminal of the voltage-controlled oscillator 100 as a frequency control voltage.

  When the output of the charge pump 103 approaches the ground potential or power supply potential of its own circuit, the output current value approaches 0 and the characteristics of the PLL circuit become unstable. The output voltage of the charge pump 103 is equal to the output voltage of the low-pass filter 104. Therefore, the voltage of the frequency control terminal is near the ground potential or the power supply potential. This means that the output voltage of the charge pump 103 is also near the ground potential or the power supply potential. Since the characteristics of the PLL circuit become unstable, a voltage near the ground potential or the power supply potential cannot be used as the frequency control voltage.

  The voltage controlled oscillator does not consider the temperature characteristics of the variable capacitor at all. If the variable capacitance value changes due to temperature change, the frequency at the time of communication is fixed, so the frequency control terminal holds the capacitance value constant. The voltage of fluctuates. At this time, if the voltage at the frequency control terminal is near the ground potential or the power supply potential, the characteristics of the PLL circuit become unstable.

  In addition, when the gate capacitance of a commonly used MOS transistor is used as a variable capacitor, it is necessary to consider a device-like drawback that it takes time to charge and discharge charges when the potential difference between both ends of the variable capacitor becomes large.

  In view of the above problems, the present invention provides a voltage-controlled oscillator capable of effectively using a variable capacitance linear region having a wide control voltage range exceeding the range from the ground potential of the circuit to the power supply potential, and the oscillation frequency of the voltage-controlled oscillator An object is to provide a control method.

  Another object of the present invention is to provide a voltage controlled oscillator in which the voltage at the frequency control terminal does not fluctuate even if the temperature characteristic of the variable capacitor is canceled and the temperature changes.

  In order to solve the above problems, a voltage controlled oscillator according to the present invention includes an inductor and a variable capacitor, and is provided with a frequency control voltage for controlling a resonance frequency and a bias voltage serving as a reference for controlling the resonance frequency. An oscillation unit having a resonance circuit in which the resonance frequency changes according to the frequency control voltage vs. resonance frequency characteristic curve by changing the frequency control voltage with reference to the bias voltage, and a negative resistance circuit connected to the resonance circuit; A bias circuit for applying a bias voltage to the resonance circuit, and a bias control circuit for switching the bias voltage output from the bias circuit in accordance with the frequency control voltage.

  Here, the bias control circuit can switch a plurality of frequency control voltages vs. resonant frequency characteristic curves in which the frequency control voltage is sequentially shifted by switching the bias voltage, and the frequency control voltage can be changed. By changing the bias voltage when the frequency control voltage reaches a predetermined threshold voltage in the process of changing the resonance frequency of the resonance circuit, the frequency control voltage vs. resonance frequency characteristic curve of the resonance circuit is changed to the current frequency. The control voltage vs. resonance frequency characteristic curve is switched to the frequency control voltage vs. resonance frequency characteristic curve shifted in the direction to bring the frequency control voltage closer to the target control voltage.

  According to this configuration, it is possible to use a variable capacitance linear region having a wide control voltage range exceeding the voltage range from the ground potential of the circuit to the power supply potential. In addition, the above-described wide variable capacitance linear region can be controlled by a frequency control voltage that changes in a narrower range than the voltage range from the circuit ground potential to the power supply potential.

  In the configuration of the present invention, the variable capacitor has a configuration in which a plurality of series circuits each including a DC blocking capacitance element and a variable capacitance element are connected in parallel. In each, a frequency control terminal is provided at one end of the variable capacitive element, a bias terminal is provided at the other end of the variable capacitive element, and the bias circuit is a plurality of series circuits each including a DC blocking capacitive element and a variable capacitive element. It is preferable to apply different bias voltages to the bias terminals.

  In the configuration of the present invention, the bias control circuit includes a comparator having hysteresis characteristics, the comparator compares the frequency control voltage with the threshold voltage, and switches the bias voltage output from the bias circuit according to the comparison result. It is preferable.

  In the configuration of the present invention described above, the bias control circuit includes a plurality of comparators having hysteresis characteristics and different threshold voltages, and the plurality of comparators compare the frequency control voltage with each threshold voltage. It is preferable to switch the bias voltage output from the bias circuit according to the comparison result.

  In the above configuration of the present invention, the bias circuit has a configuration in which a plurality of stages of diodes or series circuits of diodes and resistors are connected in cascade. It is preferable that the bias voltage is output from the interstage point.

  In the configuration of the present invention, it is preferable that the bias circuit has a temperature characteristic in the output bias voltage, and cancels the temperature characteristic of the variable capacitor by the temperature characteristic of the bias voltage. Note that the bias circuit can be provided with temperature characteristics by configuring the bias circuit with a diode and using the temperature characteristics of the diode, or by providing the bias circuit with an operational amplifier with temperature characteristics.

  According to this configuration, it is possible to provide a voltage controlled oscillator in which the frequency control voltage does not fluctuate even when the temperature characteristic of the variable capacitor is canceled and the temperature changes.

  In addition, in the configuration of the present invention, a timer circuit is provided, and a function for fixing an arbitrary time bias circuit after turning on the power supply voltage to any one of a plurality of bias states and then releasing the fixation of the bias state It is preferable to have.

  Further, in the configuration of the present invention, the bias control circuit includes a timer circuit, and fixes the first arbitrary time bias circuit after turning on the power supply voltage to any one of a plurality of bias states, and then It is preferable to have a function of releasing the fixation of the bias state in the second arbitrary time period and then fixing the bias state in the final state of the release period of the fixation of the bias state.

  When the voltage controlled oscillator is included in the PLL circuit, the bias control circuit receives a PLL lock detection signal for detecting the lock state of the PLL circuit, and the period during which the PLL lock detection signal indicates the PLL non-lock state (PLL lock detection). Period) The bias circuit is fixed to any one of a plurality of bias states, and the bias lock state is changed in response to the change of the PLL lock detection signal from the state indicating the PLL non-lock state to the state indicating the PLL lock state. It preferably has a function of releasing the fixation.

  A PLL circuit including the voltage controlled oscillator according to the present invention includes a voltage controlled oscillator according to the present invention, a frequency divider that divides the output of the voltage controlled oscillator, a signal of the frequency divider, and a reference frequency from the outside. A phase comparator that compares signals, a charge pump that receives the output of the phase comparator, a low-pass filter circuit that receives the output of the charge pump, and a PLL that provides the output of the low-pass filter circuit to the voltage control terminal of the voltage-controlled oscillator A PLL lock detection circuit that detects a PLL lock state using an output signal of the frequency divider circuit and a reference frequency signal is provided, and the bias state is changed from a fixed state according to the lock detection signal of the PLL lock detection circuit. By setting the unlocked state, the PLL can be stably operated after being locked.

  The diode is formed of a transistor in which a collector and a base are combined, for example. The variable capacitor is composed of a gate capacitor of a MOS transistor formed by, for example, a CMOS process.

An oscillation frequency control method for a voltage controlled oscillator according to the present invention includes a bias voltage serving as a reference for controlling a resonance frequency and a frequency control voltage for controlling the resonance frequency for a resonance circuit including an inductor and a variable capacitor. An oscillation frequency control method for a voltage controlled oscillator that changes the resonance frequency of the resonance circuit according to the frequency control voltage vs. resonance frequency characteristic curve by changing the frequency control voltage with reference to the bias voltage,
By making the bias voltage switchable, it is possible to switch a plurality of frequency control voltages vs. resonant frequency characteristic curves in which the frequency control voltage is sequentially shifted by the resonance circuit,
In the process of changing the resonant frequency of the resonant circuit by changing the frequency control voltage, switching the bias voltage when the frequency controlled voltage reaches a predetermined threshold voltage, the frequency control voltage of the resonant circuit vs. the resonant frequency The characteristic curve is switched from the current frequency control voltage versus resonance frequency characteristic curve to a frequency control voltage versus resonance frequency characteristic curve that is shifted in a direction that brings the frequency control voltage closer to the target control voltage.

  According to this method, it is possible to use a variable capacitance linear region having a wide control voltage range exceeding the voltage range from the ground potential of the circuit to the power supply potential. In addition, the above-described wide variable capacitance linear region can be controlled by a frequency control voltage that changes in a narrower range than the voltage range from the circuit ground potential to the power supply potential.

  According to the voltage controlled oscillator and the oscillation frequency control method of the present invention, it is possible to use a variable capacitance linear region having a wide control voltage range exceeding the voltage range from the ground potential of the circuit to the power supply potential. In addition, the above-described wide variable capacitance linear region can be controlled by a frequency control voltage that changes in a narrower range than the voltage range from the circuit ground potential to the power supply potential.

  Further, according to the voltage controlled oscillator of the present invention, it is possible to provide a voltage controlled oscillator characterized in that the frequency control voltage does not fluctuate even if the temperature characteristic of the variable capacitor is canceled and the temperature changes.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is a block diagram of a voltage controlled oscillator according to the first embodiment of the present invention. The voltage controlled oscillator includes an oscillation unit 200, a bias circuit 201 that applies a bias to the variable capacitor of the oscillation unit 200, and a bias control circuit 202 that controls the bias of the bias circuit 201. The oscillating unit 200 has the same configuration as that of the prior art shown in FIG.

  The frequency control terminal 5 is connected to the oscillation unit 200 and the bias control circuit 202. As an example, three bias voltages Vb1, Vb2, and Vb3 from the output terminals 201a, 201b, and 201c of the bias circuit 201 to the variable capacitor of the oscillating unit 200 are given, and the bias circuit 201 is output from the output terminals 202a and 202b of the bias control circuit 202. Assume that two output signals Vbc1 and Vbc2 are supplied to the input terminals 201d and 201e.

  A specific circuit diagram of the oscillation unit 200, the bias circuit 201, and the bias control circuit 202 in FIG. 1 is shown in FIG.

  As in the prior art, the oscillation unit 200 includes oscillation transistors 1a and 1b as negative resistance circuits, inductors 2a and 2b, variable capacitance elements 10a, 10b, 11a, 11b, 12a and 12b, and variable capacitance elements 10a, DC blocking capacitors 13a, 13b, 14a, 14b, 15a, 15b connected in series to 10b, 11a, 11b, 12a, 12b. One terminal of the variable capacitance elements 10a, 10b, 11a, 11b, 12a, and 12b is fixed to the bias voltages Vb1, Vb2, and Vb3, respectively, and the other terminal is connected to the resistors 16a, 16b, 17a, and 17b from the frequency control terminal 5, respectively. , 18a, 18b, the frequency control voltage Vc is applied.

  The bias circuit 201 is configured by connecting diodes D0, D1, D2, and D3 and a resistor Rx in series between a ground potential and a power supply potential. The bias voltage Vb1 is output from the anode of the diode D3. The bias voltage Vb2 is output from the anode of the diode D2 (the cathode of the diode D3). The bias voltage Vb3 is output from the anode of the diode D1 (the cathode of the diode D2). The bias voltage Vb2 is lower than the bias voltage Vb1 by the forward voltage Vd of the diode D3. The bias voltage Vb3 is lower than the bias voltage Vb2 by the forward voltage Vd of the diode D2. With this configuration, the characteristics are synthesized as shown in FIG.

  The bias control circuit 202 compares the frequency control voltage Vc applied to the frequency control terminal 5 with the reference voltages (threshold voltages) Vref1 and Vref2, respectively, according to the output states of the comparators Com1 and Com2, and the comparators Com1 and Com2. The switches S1 and S2 are turned on and off. The switches S1 and S2 have one end connected to the anodes of the diodes D1 and D0 and the other end connected to the ground. The comparators Com1 and Com2 each have hysteresis characteristics. The switches S1 and S2 are composed of, for example, MOS transistors.

  The outputs of the comparators Com1 and Com2 are connected to the control terminals of the switches S1 and S2, respectively. Depending on the state of the switches S1 and S2, the bias voltages Vb1, Vb2, and Vb3 applied to the variable capacitor of the oscillating unit 200 are shifted by the voltage Vd or the voltage 2Vd.

  Therefore, there are three types of characteristics of the variable capacitance of the oscillation unit 200 and the frequency control voltage in the circuit of FIG. 2. By switching the bias voltages Vb1, Vb2, and Vb3 by turning the switches S1 and S2 on and off, Any one of the three characteristics can be selected.

  Here, the three characteristics are represented as band1, band2, and band3. The state of the switches S1 and S2 is band1 when S1 = arbitrary (ON or OFF) and S2 = ON, the state of S1 = ON and S2 = OFF is band2, the state of S1 = OFF and S2 = OFF is band3 FIG. 3 shows a change in the capacitance value of the variable capacitor with respect to the frequency control voltage Vc. In FIG. 3, the horizontal axis represents the frequency control voltage and the vertical axis represents the variable capacitance value. In FIG. 3, reference voltages Vref1 and Vref2 given to the comparators Com1 and Com2 are shown together with the ground potential and the circuit power supply voltage. In the prior art, the voltage range of the frequency control terminal is a range from the ground potential to the circuit power supply voltage. However, in the first embodiment of the present invention, the voltage range of the frequency control terminal is a reference voltage narrower than that of the prior art. The range is from Vref1 to the reference voltage Vref2 (Vref1 <Vref2).

  As described above, even if the voltage range of the frequency control terminal is set narrower than that of the prior art, as described above, by selecting one of the three characteristics according to the change of the frequency control voltage, the prior art It is possible to change the capacitance value over a wide range equal to or greater than that of the case. Here, by making the reference voltage Vref1 sufficiently higher than the ground potential and making the reference voltage Vref2 sufficiently lower than the circuit power supply voltage, the problem of unstable operation of the PLL circuit described in the prior art can be solved. The reference voltages Vref1 and Vref2 can be arbitrarily set. As an example, a voltage about 0.5 V away from the ground potential and the circuit power supply voltage is preferable.

  Then, for example, in the prior art, the characteristic of the variable capacitor is only band2, but by using the first embodiment of the present invention, the three characteristics band1 to band3 can be selectively used, and conventionally, the ground is ground. A variable capacitance value that cannot be obtained without changing the frequency control voltage from the potential to the circuit power supply voltage (VCC potential) can be obtained within the range from the ground potential to the VCC potential. Therefore, as described above, the characteristics of the PLL circuit can be stabilized.

  When used as a PLL circuit, the frequency control terminal voltage is automatically adjusted to the target frequency. However, since the comparator has hysteresis, adjustment of the target frequency will not fail. That is, since the comparator has hysteresis, the operation does not become unstable near the threshold value.

  In FIG. 4, when the target frequency is changed from high to low, that is, when the variable capacitance value is changed from small to large, the change in frequency control voltage is indicated by a thick solid arrow. It shows with. In addition, when the target frequency is changed from low to high, that is, when the variable capacitance value is changed from large to small, the change in frequency control voltage is indicated by a thick broken arrow. Show.

  Here, the relationship between the hysteresis operation of the comparators Com1 and Com2 and the change in the frequency control voltage will be described below. Generally, after the power supply voltage is turned on, the frequency control voltage starts from the ground potential. Therefore, when the frequency control voltage is the ground potential, the switch S1 and the switch S2 are set so as to start from the characteristic band3. The frequency control voltage changes until the target frequency, that is, the target capacity is reached. At this time, if the frequency control voltage becomes close to the reference voltage Vref1 or Vref2, if there is no hysteresis, temperature fluctuation or power supply voltage A slight change in capacitance due to fluctuation causes characteristic switching, resulting in unstable operation. In this circuit, due to the hysteresis, the voltage Vref1 'exceeds the reference voltage Vref1, and the characteristic band3 is shifted to the characteristic band2. Since the comparator has hysteresis after the movement, the threshold value is the voltage Vref1. Further, the characteristic band2 moves to the characteristic band1 when the reference voltage Vref2 is exceeded, and after the movement, the comparator has hysteresis, so the threshold value becomes the voltage Vref2 ′.

  When the frequency control voltage starts from the circuit power supply voltage, the following occurs. When the frequency control voltage is the circuit power supply voltage, the switches S1 and S2 are set so as to start from the characteristic band1. The frequency control voltage changes until the target frequency, that is, the target capacity is reached. At this time, if the frequency control voltage becomes close to the reference voltage Vref1 or Vref2, if there is no hysteresis, temperature fluctuation or power supply voltage A slight change in capacitance due to fluctuation causes characteristic switching, resulting in unstable operation. In this circuit, due to the hysteresis, the characteristic band1 is shifted to the characteristic band2 at a voltage Vref2 ′ that is lower than the reference voltage Vref2. Since the comparator has hysteresis after the movement, the threshold value is the voltage Vref2. Further, the characteristic band2 moves to the characteristic band3 when it falls below the reference voltage Vref1, and after the movement, the comparator has hysteresis, so that the threshold value becomes the voltage Vref1 ′.

  In the above operation, the voltage Vref1'-Vref1 becomes the hysteresis amount of the comparator Com1, and similarly, Vref2-Vref2 'becomes the hysteresis amount of the comparator Com2.

  Here, in FIG. 4, the reason why the frequency control voltage is rapidly changed by switching the bias voltage will be described. The reason why the frequency control voltage changes suddenly by switching the bias voltage is that the PLL frequency synthesizer forms a closed loop circuit that achieves the target frequency. When the frequency control voltage vs. capacity curve changes, the frequency control voltage changes to restore the capacity. For example, when the capacitance curve is changed from the characteristic band 2 to the characteristic band 3 when the stable operation is performed at the target frequency, the capacitance is changed unless the frequency control voltage is changed, and the target frequency is not reached.

(Embodiment 2)
FIG. 5 shows a voltage controlled oscillator according to the second embodiment of the present invention, and FIG. 6 shows a specific circuit thereof. In this embodiment, in order to cancel the temperature fluctuation of the oscillation frequency due to the positive or negative temperature characteristic of the variable capacitor of the voltage control circuit 200, the bias circuit 301 that changes the bias voltage according to the temperature fluctuation, and the bias circuit 301 1 is provided in place of the bias circuit 201 and the bias control circuit 202 shown in FIGS. 1 and 2. The temperature characteristic correction signal 6 is supplied to the bias circuit 301, thereby enabling variable capacitor temperature compensation.

  6, the bias circuit 301 has a structure in which a series circuit of a diode and a resistor is vertically stacked, unlike FIG. 2, but may have a structure in which only the diode is vertically stacked as in FIG. In FIG. 6, symbols R0 to R3 each indicate a resistance.

  The bias voltage can be finely adjusted by flowing current from the current source to the bias circuit 301. When the bias voltage changes, the capacitance curve also changes and the control voltage also changes. The bias circuit 301 and the variable capacitor have temperature characteristics. That is, since the capacitance curve has temperature characteristics, the value of the control voltage also has temperature characteristics. In order to cancel the temperature characteristic of the variable capacitor, a temperature characteristic adjusting circuit 400 including a current source that supplies current to the bias circuit 301 is used, and the current supplied to the bias circuit 301 has temperature characteristics.

  In this temperature characteristic adjusting circuit 400, a current mirror is constituted by the NPN bipolar transistor 20 and the bipolar transistor 21 that is N times the parallel number of the NPN bipolar transistor 20, and a resistor Rv is connected to the emitter of the bipolar transistor 21. .

  Specifically, the base of the NPN bipolar transistor 20 and the base of the NPN bipolar transistor 21 are connected and shared, and the shared base is connected to the collector of the bipolar transistor 20 to form a current mirror. . In the PNP transistors 30, 31, and 32 that form another current mirror with a common base, the collectors of the PNP transistors 30 and 31 are connected to the collectors of the NPN transistors 20 and 21, respectively. The variable current Iv is output from the collector of the PNP transistor 32 and supplied to the bias circuit 301 via the switch S10.

Here, the operation of the temperature characteristic adjusting circuit 400 will be described. The correction signal 6, that is, the current supplied from the temperature characteristic adjustment circuit 400 to the bias circuit 301 assumes that the current gain h _{FE of the} transistor is infinite, and the mirror ratios of the PNP transistors 30, 31, and 32 are the same, If one to one to one, the current is
Iv = (Vt / Rv) × lnN
Vt = kT / q
Where k: Boltzmann constant
T: Temperature (K)
q: Elementary charge
Vb3-Vb2 = R3 × (Vt / Rv) × lnN + VD3
However, VD3 is the base-emitter voltage of the diode D3.

  At this time, the first term on the right side has a positive slope with respect to the temperature, and the second term has a negative slope. Therefore, by weighting with the coefficient (R3 / Rv) of the first term on the right side, Vb3-Vb2 can have a positive or negative slope with respect to temperature, and temperature dependence can be eliminated. That is, the temperature characteristic of the bias voltage may be set so as to cancel the temperature characteristic of the variable capacitor.

  As can be seen from the above equation, the bias voltage difference Vb3-Vb2 can have temperature characteristics, and the bias voltage also changes with temperature in accordance with the bias voltage difference Vb3-Vb2. Further, the temperature characteristic of the variable capacitor can be canceled by adjusting the bias voltage in the direction in which the temperature characteristic of the variable capacitor is canceled.

  Here, the compensation of the temperature characteristic of the MOS capacitor will be briefly described. Even if the bias voltage is constant, if the temperature changes due to the temperature characteristic of the MOS capacitor, the capacitance-control voltage characteristic shifts from the broken line characteristic to the solid line state as shown in FIG. Therefore, the temperature-compensating operation by the bias circuit 301 restores the capacitance-control voltage characteristics as shown in FIG. 7B. It is assumed that the MOS capacitor whose symbol is shown in FIG. 7C has a temperature characteristic as shown in FIG. FIG. 7D shows three characteristics of the capacitance-voltage Vgb when the voltage applied to both ends of the MOS capacitor is Vgb, using temperature as a parameter.

  According to this embodiment, since the temperature characteristic adjusting circuit 400 is provided and the current Iv having the temperature characteristic is supplied to the bias circuit 301, the bias voltage changes so as to cancel the temperature characteristic of the variable capacitor of the oscillation unit 200. To do. Therefore, fluctuations in the oscillation frequency of the oscillation unit 200 due to temperature fluctuations can be prevented, and therefore temperature fluctuations in the frequency control voltage can be prevented.

(Embodiment 3)
FIG. 8 shows a circuit diagram of a main part of the voltage controlled oscillator according to the third embodiment of the present invention. The illustration of the oscillation unit is omitted. As shown in FIG. 8, the voltage controlled oscillator includes an initial setting circuit 401, a timer circuit 402, and switches S11 to S14, and connects the bias control circuit 202 and the bias circuit 201 via the switches S11 and S12. The initial setting circuit 402 is connected to the bias circuit 201 via switches S13 and S14. The timer circuit 402 is provided for switching on and off the switches S11 to S14. Other configurations are the same as those in FIG.

  In this voltage-controlled oscillator, the switches S11 and S12 are off and the switches S13 and S14 are on for an arbitrary period after the power is turned on, that is, until the timer time of the timer circuit 402 elapses. At this time, the bias circuit 201 is fixed to any one of a plurality of bias states by the initial setting circuit 401. Specifically, the initial setting circuit 401 is set, for example, so that the anodes of the diodes D1 and D0 of the bias circuit 201 are grounded, for example, and works effectively when the switches S13 and S14 are turned on.

  After the timer time elapses, the switches S11 and S12 are turned on and the switches S13 and S14 are turned off. As a result, the timer circuit 402 releases the fixing of the bias state by the initial setting circuit 401, and the bias control circuit 202 controls the bias voltage of the bias circuit 201 in accordance with the frequency control voltage.

  According to this embodiment, when the voltage controlled oscillator is used in the PLL circuit (see FIG. 15), the band is switched once after the bias state is released. Uptime can be increased.

(Embodiment 4)
FIG. 9 shows a circuit diagram of a main part of the voltage controlled oscillator in the fourth embodiment of the present invention. The illustration of the oscillation unit is omitted. As shown in FIG. 9, the voltage controlled oscillator includes an initial setting circuit 401, a timer circuit 402 that sets a first timer time and a second timer time, and a latch circuit 404 that operates by an external reference frequency 403. , Switches S13 to S18 are provided, the bias control circuit 202 and the bias circuit 201 are connected via the switches S15 and S16, the latch circuit 404 and the switches S17 and S18, and the initial setting circuit 402 is connected to the bias circuit 201, the switches S13, Connected via S14. Further, the timer circuit 402 is provided for switching the switches S13 to S18 on and off. Other configurations are the same as those in FIG.

  In this voltage controlled oscillator, the switches S13 and S14 are on and the switches S15 to S18 are off for an arbitrary period (first timer time) after the power is turned on. At this time, the bias circuit 201 is fixed to any one of a plurality of bias states by the initial setting circuit 401. Specifically, the initial setting circuit 401 is set, for example, so that the anodes of the diodes D1 and D0 of the bias circuit 201 are grounded, for example, and works effectively when the switches S13 and S14 are turned on.

  After the elapse of the first timer time, the switches S13 and S14 are turned off and the switches S15 to S18 are turned on. As a result, the timer circuit 402 releases the fixing of the bias state by the initial setting circuit 401, and the bias control circuit 202 controls the bias voltage of the bias circuit 201 in accordance with the frequency control voltage. At this time, the latch circuit 404 provided between the bias control circuit 202 and the bias circuit 201 latches the output of the bias control circuit 202 at intervals of the period of the external reference frequency and supplies the latch circuit 201 with the latch circuit 404. This period continues for a second timer time.

  After the elapse of the second timer time, the switches S13, S14, S15, and S16 are turned off and the switches S17 to S18 are turned on. As a result, the bias state of the bias circuit 201 is again fixed by the timer circuit 402. That is, the bias state of the bias circuit 201 is fixed in the last latched bias state in the state where the bias state of the bias circuit 201 is released.

  According to this embodiment, when the voltage controlled oscillator is used in the PLL circuit (see FIG. 15), the bias circuit is fixed in the last latched bias state, so that the operation after locking of the PLL circuit is stabilized. Can be done automatically.

(Embodiment 5)
FIG. 10 shows a circuit diagram of a main part of the voltage controlled oscillator in the fifth embodiment of the present invention. The illustration of the oscillation unit is omitted. As shown in FIG. 10, the voltage controlled oscillator includes an initial setting circuit 401, a PLL lock detection circuit 405 that activates a PLL lock detection signal when lock of the PLL circuit is detected, and switches S11 to S14. The bias control circuit 202 and the bias circuit 201 are connected via the switches S11 and S12, and the initial setting circuit 402 is connected to the bias circuit 201 via the switches S13 and S14. The PLL lock detection circuit 405 is provided for switching on and off of the switches S11 to S14. Other configurations are the same as those in FIG.

  A PLL circuit including the voltage controlled oscillator includes an oscillation unit, a frequency divider that divides the output of the oscillation unit, a phase comparator that compares the output of the frequency divider and a reference frequency signal, and A charge pump that inputs and outputs current according to the output of the phase comparator, and a low-pass filter that averages the output of the charge pump, and a voltage-controlled oscillator and bias control from the frequency control terminal using the output of the low-pass filter as a frequency control voltage This configuration feeds back to the circuit. The PLL lock detection circuit is configured to detect the PLL lock based on the output of the frequency divider and the reference frequency signal.

  In this voltage-controlled oscillator, the switches S11 and S12 are off and the switches S13 and S14 are on during the lock detection period (non-lock detection state) of the lock detection circuit 405. At this time, the bias circuit 201 is fixed to any one of a plurality of bias states by the initial setting circuit 401. Specifically, the initial setting circuit 401 is set, for example, so that the anodes of the diodes D1 and D0 of the bias circuit 201 are grounded, for example, and works effectively when the switches S13 and S14 are turned on.

  When the PLL lock detection signal of the lock detection circuit 405 becomes active, the switches S11 and S12 are turned on and the switches S13 and 14 are turned off. As a result, the fixing of the bias state by the initial setting circuit 401 is released, and the bias voltage of the bias circuit 201 is controlled by the bias control circuit 202 according to the frequency control voltage.

  According to this embodiment, when the voltage-controlled oscillator is used in the PLL circuit (see FIG. 15), the bias state is released by the lock detection signal after the PLL circuit is locked. For this reason, the lock-up time for locking to the target frequency can be increased.

  The voltage controlled oscillator according to the present invention can use a variable capacitance linear region having a wide control voltage range exceeding the range from the ground potential of the circuit to the power supply potential, and is used particularly in a wireless communication device. Useful for voltage controlled oscillators.

It is a circuit diagram which shows the structure of the voltage controlled oscillator of Embodiment 1 of this invention. It is a circuit diagram which shows the more concrete circuit structure of the voltage controlled oscillator of Embodiment 1 of this invention. It is a characteristic view of the capacitance value with respect to the frequency control repression of the variable capacitance of the voltage controlled oscillator in Embodiment 1 of the present invention. It is a characteristic view which shows the change of the frequency control voltage in Embodiment 1 of this invention. It is a block diagram which shows the structure of the voltage controlled oscillator of Embodiment 2 of this invention. It is a circuit diagram which shows the more concrete structure of the voltage controlled oscillator of Embodiment 2 of this invention. It is a figure which shows the mode of the correction | amendment of the temperature characteristic of gate capacitance. It is a block diagram which shows the structure of the principal part of the voltage controlled oscillator of Embodiment 3 of this invention. It is a block diagram which shows the structure of the principal part of the voltage controlled oscillator of Embodiment 4 of this invention. It is a block diagram which shows the structure of the principal part of the voltage controlled oscillator of Embodiment 5 of this invention. It is a circuit diagram which shows the structure of the voltage control oscillator of a prior art. (A) is a figure which shows the symbol of a variable capacitance element, (b) is a characteristic view which shows the voltage difference between the both terminals of a variable capacitance element, and the relationship of a capacitance value. It is a circuit diagram which shows the structure of the voltage control oscillator of another prior art. It is a characteristic view of the capacitance value with respect to the frequency control voltage of the variable capacitor of the voltage controlled oscillator. It is a block diagram which shows the structure of a PLL circuit.

Explanation of symbols

1a, 1b Oscillation transistor 2a, 2b Inductor 4 Power supply terminal 5 Frequency control terminal 6 Current source 10a, 10b, 11a, 11b, 12a, 12b Variable capacitance element 13a, 13b, 14a, 14b, 15a, 15b DC blocking capacitor 16a, 16b , 17a, 17b, 18a, 18b Resistor D0 to D3 Diode Com1, Com2 Comparator S1, S2 Switch 101 Frequency divider 102 Phase comparator 103 Charge pump 104 Low pass filter 105 Lock detector 200 Oscillator 201 Bias circuit 202 Bias control circuit 301 Bias circuit 302 Bias control circuit 400 Temperature characteristic adjustment circuit

Claims (12)

A frequency control voltage for controlling the resonance frequency and a bias voltage serving as a reference for controlling the resonance frequency are provided, and the frequency control voltage changes based on the bias voltage. An oscillation unit having a resonance circuit whose resonance frequency changes according to a frequency control voltage vs. resonance frequency characteristic curve, and a negative resistance circuit connected to the resonance circuit;
A bias circuit for applying the bias voltage to the resonant circuit;
A bias control circuit that switches the bias voltage output from the bias circuit according to the frequency control voltage;
The bias control circuit can switch a plurality of frequency control voltages vs. resonance frequency characteristic curves in which the frequency control voltage is sequentially shifted by the resonance circuit by switching the bias voltage, and the frequency control voltage changes. By switching the bias voltage when the frequency control voltage reaches a predetermined threshold voltage in the process of changing the resonance frequency of the resonance circuit, the frequency control voltage vs. resonance frequency characteristic curve of the resonance circuit Is a voltage-controlled oscillator that switches from a current frequency control voltage versus resonance frequency characteristic curve to a frequency control voltage versus resonance frequency characteristic curve that is shifted in a direction that brings the frequency control voltage closer to the target control voltage. The variable capacitor has a configuration in which a plurality of series circuits each including a DC blocking capacitor and a variable capacitor are connected in parallel. In each of the plurality of series circuits including the DC blocking capacitor and the variable capacitor, A frequency control terminal is provided at one end of the variable capacitance element, and a bias terminal is provided at the other end of the variable capacitance element,
2. The voltage controlled oscillator according to claim 1, wherein the bias circuit applies different bias voltages to the bias terminals in each of a plurality of series circuits including the DC blocking capacitive element and the variable capacitive element.   The bias control circuit includes a comparator having hysteresis characteristics, the comparator compares the frequency control voltage with a threshold voltage, and switches a bias voltage output from the bias circuit according to the comparison result. The voltage controlled oscillator described.   The bias control circuit includes a plurality of comparators each having a hysteresis characteristic and having different threshold voltages, and the plurality of comparators compare the frequency control voltage with each threshold voltage, and the comparison result The voltage controlled oscillator according to claim 1, wherein the bias voltage output from the bias circuit is switched according to the frequency.   The bias circuit has a configuration in which a plurality of stages of diodes or series circuits of diodes and resistors are connected in cascade. The voltage controlled oscillator according to claim 1, having a configuration for outputting   2. The voltage controlled oscillator according to claim 1, wherein the bias circuit has a temperature characteristic in the output bias voltage, and cancels the temperature characteristic of the variable capacitor according to the temperature characteristic of the bias voltage.   The bias control circuit includes a timer circuit, and has a function of fixing the bias circuit to any one of a plurality of bias states for an arbitrary time after turning on a power supply voltage, and thereafter releasing the fixation of the bias state. The voltage controlled oscillator according to claim 1.   The bias control circuit includes a timer circuit, and fixes the bias circuit to any one of a plurality of bias states after a first arbitrary time after turning on a power supply voltage, and then a second arbitrary time thereafter 2. The voltage controlled oscillator according to claim 1, wherein the voltage controlled oscillator has a function of releasing the fixation of the bias state and then fixing the bias state in the last state of the release period of the fixation of the bias state. A voltage controlled oscillator included in a PLL circuit,
The bias control circuit receives a PLL lock detection signal for detecting a lock state of the PLL circuit as an input, and the bias control circuit is any one of a plurality of bias states during a period when the PLL lock detection signal indicates a PLL non-lock state. 2. The voltage control according to claim 1, wherein the voltage control has a function of releasing the fixation of the bias state in response to a change from a state indicating the PLL unlocked state to a state indicating the PLL locked state. Oscillator.   6. The voltage controlled oscillator according to claim 5, wherein said diode is formed of a transistor having a collector and a base combined.   2. The voltage controlled oscillator according to claim 1, wherein the variable capacitor is configured by a gate capacitor of a MOS transistor formed by a CMOS process. A bias voltage serving as a reference for controlling the resonance frequency and a frequency control voltage for controlling the resonance frequency are provided to a resonance circuit including an inductor and a variable capacitor, and the frequency control is performed based on the bias voltage. An oscillation frequency control method of a voltage controlled oscillator that changes a resonance frequency of the resonance circuit according to a frequency control voltage vs. resonance frequency characteristic curve by changing a voltage,
By making the bias voltage switchable, it is possible to switch a plurality of frequency control voltages versus resonance frequency characteristic curves in which the frequency control voltage is sequentially shifted in the resonance circuit,
In the process of changing the resonance frequency of the resonance circuit by changing the frequency control voltage, the frequency of the resonance circuit is switched by switching the bias voltage when the frequency control voltage reaches a predetermined threshold voltage. The control voltage vs. resonance frequency characteristic curve is switched from a current frequency control voltage vs. resonance frequency characteristic curve to a frequency control voltage vs. resonance frequency characteristic curve shifted in a direction to bring the frequency control voltage closer to the target control voltage. An oscillation frequency control method for a voltage controlled oscillator.

Images