JP2008172323A - Dead time control circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a dead time control circuit capable of highly accurately setting a dead time in a wide range by changing step intervals in accordance with the dead time with an IC chip of a small circuit scale without externally adding a delay element when setting the dead time in a wide range at a plurality of steps. <P>SOLUTION: A dead time control circuit 10 delays activation pulse edges of two pulse signals, adds the dead time between their non-activation pulse edges and activation pulse edges, and outputting them in parallel. The circuit 10 is provided with: delay circuit parts 101a and 101b for selecting any of a delay time at the plurality of steps with step intervals corresponding to the dead time on the basis of a control signal (DA) to delay both pulse edges of the input pulse signals; and a signal generation part (logical circuit parts 102a and 102b) for generating a signal whose activation pulse edge is delayed by performing logical processing to the input pulse signal and the pulse signal delayed by the delay circuit part. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a dead time control circuit, and more particularly to a dead time control circuit for controlling a time during which two switching elements having a push-pull configuration are simultaneously non-conductive (hereinafter referred to as a dead time).

  When two switching elements having a push-pull configuration perform switching operation, in order to prevent a through current from flowing through the two switching elements, the switching element drive circuit has a dead time so that the two switching elements do not turn on at the same time. Is provided. As two switching elements having a push-pull configuration, for example, a circuit using a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is used for various purposes. In particular, when used in a digital amplifier or the like that operates at high speed, the dead time is as short as several ns, and it is required to set and control the dead time with high accuracy. Also, when setting the dead time over a wide range in a plurality of steps, if the dead time is relatively long, the step interval (time interval between steps of a plurality of steps) can be set somewhat rough, but the dead time is several ns. When it becomes very short, it is necessary to set a fine step interval.

  A technique for setting a dead time is disclosed in Patent Document 1. FIG. 8 is a circuit diagram showing a drive circuit described in Patent Document 1. As shown in FIG. As shown in FIG. 8, the drive circuit 1 is connected to and driven by a drive unit such as a speaker or a motor as the load unit 8, and is a pre-driver that drives the power MOSFETs M1 and M2 as two switching elements. IC (Integrated Circuit). The drive circuit 1 includes external CR circuits 2 and 3 for setting a time constant, and a drive signal generation circuit 4, and the drive circuit 1 and MOSFETs M1 and M2 constitute, for example, a class D amplifier. The drive signals generated by the drive circuit 1 drive the gates of the MOSFETs M1 and M2.

The external CR circuit 2 is an integrating circuit that is connected to an input terminal 7a to which an input signal HI is input, and in which a resistor R1 and a capacitor C1 are connected in series. The external CR circuit 3 is an integrating circuit connected to an input terminal 7b to which an input signal LI whose logic level is inverted from the input signal HI is input, and a resistor R2 and a capacitor C2 are connected in series.
The drive signal generation circuit 4 includes AND gates 5a and 5b and high voltage drive circuits 6a and 6b, and generates a drive signal for driving the gates of the two power MOSFETs.

One input terminal of the AND gate 5a is connected to a connection point between the resistor R1 and the capacitor C1, and an output signal from the external CR circuit 2 is input thereto. The input signal HI is input to the other input terminal of the AND gate 5a through the input terminal 7a. The input signal LI is input to one input terminal of the AND gate 5b via the input terminal 7b. The other input terminal of the AND gate 5b is connected to a connection point between the resistor R2 and the capacitor C2, and an output signal of the external CR circuit 3 is input thereto.
High-voltage drive circuits 6a and 6b amplify the output signals of AND gates 5a and 5b, respectively, and output drive signals Hout and Lout. In the drive signal generation circuit 4, AND gates 5a and 5b and high-voltage drive circuits 6a and 6b are formed on the same IC chip through an element isolation oxide film by, for example, an SOI (Silicon On Insulator) process.

  FIG. 9 is a timing chart in the drive circuit. As shown in FIGS. 9A and 9B, the input signals HI and LI are pulse signals having logic levels that are inverted from each other. The input signal HI and the output of the input signal HI from the external CR circuit 2 are input to the AND gate 5a, and the rising time of the input signal HI is as shown in FIG. A signal HI2 delayed by a time dt determined by the time constant is output. Further, the input signal LI and the output of the input signal LI from the external CR circuit 3 are input to the AND gate 5b, and the rise time of the input signal LI is as shown in FIG. A signal LI2 delayed by a time dt determined by the time constant is output.

  The signals HI2 and LI2 are amplified by the high-voltage drive circuits 6a and 6b, respectively, and supplied to the gates of the MOSFETs M1 and M2 as drive signals Hout and Lout. Therefore, as shown in FIGS. 9E and 9F, the drive signals Hout and Lout have a dead time dt added as a delay time from the fall of one signal to the rise of the other signal. It is a signal. MOSFETs M1 and M2 are deactivated (turned off) at the fall of the drive signals Hout and Lout, and activated (turned on) at the rise. Therefore, in this case, the falling edges of the input signals HI and LI are inactivation pulse edges, and the rising edges are activation pulse edges. As described above, by controlling the gate of the MOSFET, it is possible to prevent a current from flowing between the two MOSFETs.

  When the technique for setting the dead time according to the above-mentioned Patent Document 1 is used, high-precision components are selected as the resistors R1, R2 and capacitors C1, C2 constituting the external CR circuits 2, 3 according to the dead time. , Get and use. As a result, when setting the dead time in a wide range of steps, when setting a relatively long dead time, the step interval is set to be somewhat rough, and when the dead time is very short, a few ns, the step interval is made finer. Can be set. When an IC using a technique for setting the dead time is used to set only one step, resistors R1 and R2 having resistance values corresponding to the dead time at that step, and capacitors C1 and C having capacitance values However, when setting is performed in a wide range of steps, the resistors R1, R2 having resistance values and the capacitors C1, C having capacitance values corresponding to the dead time in each step are selected. The number of parts must be obtained, and the number of parts increases, and the management man-hours such as selection, acquisition and storage also increase.

  Patent Document 2 discloses a delay circuit capable of finely setting the delay time in a wide range in a plurality of steps. FIG. 10 is a block diagram showing a configuration of the delay circuit described in Patent Document 2. In FIG. As shown in FIG. 10, for example, when two delay circuits 46a and 46b are connected in series, the second delay circuit 46b is delayed so that the first delay circuit 46a can set the delay time finely. It is configured so that the time can be roughly set. The delay times of the first and second delay circuits 46a and 46b are set by the lower bit and the upper bit of the register 19, respectively. For example, the lower bit and the upper bit of the register 19 are 2 bits and 1 bit, respectively, the delay time per two stages of the inverter 11 of the first delay circuit 46a is Δd = 2ns, and the inverter of the second delay circuit 46b 11 delay time per two stages is assumed to be ΔD = Δd × 4 = 8 ns. At this time, the delay time when the signal input to the first delay circuit 46a is output from the second delay circuit 46b is 8 steps of 0, 2, 4, 6, 8, 10, 12, 14 ns. It can be set.

  When the technique of Patent Document 2 described above is applied to a technique for setting a dead time, the dead time is set at the dead time interval as described above by setting the lower bit and the upper bit of the register 19 according to the dead time. It can be set in multiple steps over a wide range. For example, the dead time in a plurality of steps can be set to 0, 2, 4, 6, 10, 14 ns, and the step interval can be controlled from 0 to 6 ns with a fine step interval of 2 ns steps, and 6 to 14 ns with a coarse step interval of 4 ns. Consider the case of using an IC to which the dead time control that can be set in the above-mentioned 8 steps is applied when there is an IC request. In this case, 8 ns and 10 ns are not used and are wasted. In other words, there is a useless inverter 11 constituting a delay element. This means that the area of the IC chip becomes larger than necessary.

Further, the step interval is smaller than 0, 2, 4, 6, 10, 14 ns described above, for example, 0, 2, 4, 6, 8, 12, 16, 20 ns, and the step interval is 0 to 8 ns, and the fine step interval is 2 ns. Then, when there is a demand for an IC that can be controlled at a coarse step interval of 4 ns for 8 to 20 ns, a case where an IC to which dead time control applying the technique of Patent Document 2 is applied will be considered. In this case, the step interval needs to be set at 11 steps of at least 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20 ns at equal intervals. For this purpose, lower bits and upper bits require 3 bits and 1 bit instead of 2 bits and 1 bit, respectively. In this case, the number of input terminals increases when the lower bit + upper bit is changed from 3 bits to 4 bits and data is input to the register 19 in parallel or when a bit signal is directly input from the outside without using the register 19. There is a problem of doing. In this case, 10, 14, and 18 ns are not used and are wasted. Also in this case, there is a useless inverter 11 constituting the delay element, which means that the area of the IC chip becomes larger than necessary.
JP 2005-260773 A JP 2000-357951 A

  As described above, when the dead time is set in a plurality of steps over a wide range in the conventional technique, the step interval is changed according to the dead time, and an IC having a small circuit scale without an external delay element. It was difficult to implement with a chip.

  In one aspect of the dead time control circuit of the present invention, two pulse signals whose activation pulse edge and inactivation pulse edge substantially coincide with each other are input in parallel, and the activation pulse edge of the input pulse signal is delayed. A dead time control circuit 10 that outputs a dead time between a deactivation pulse edge and an activation pulse edge and outputs the dead time in parallel, and based on a control signal (for example, the control signal DA in FIG. 1) A delay circuit unit that delays both pulse edges of the input pulse signal by selecting one of a plurality of step delay times corresponding to a dead time, and the input pulse signal and the delay circuit unit delay A signal generator (for example, the logic circuit units 102a and 1a in FIG. Includes a 2b), the. A delay circuit unit that can set a plurality of delay times based on a plurality of step intervals is provided, and a dead time can be widened by controlling one of a plurality of delay times based on a control signal. The step interval at the time of setting in a plurality of steps can be controlled to be relatively fine for control with a relatively short dead time and relatively coarse for control with a relatively long dead time.

  According to the present invention, when setting the dead time in a plurality of steps over a wide range, changing the step interval according to the dead time is performed with an IC chip having a small circuit scale without adding a delay element. Can do. Thereby, the dead time can be accurately set over a wide range.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, components having the same configuration or function and corresponding parts are denoted by the same reference numerals and description thereof is omitted.
Also, in this specification, when there are a plurality of the same constituent elements and they are distinguished from each other, a suffix is added to the code to distinguish each of the plurality of constituent elements. For example, FIG. 1 shows a plurality of delay circuit units 101a and 101b. In the description with reference to FIG. 1, the delay circuit unit 101 represents one or more of the plurality of delay circuit units 101a and 101b, and is suffixed like the delay circuit unit 101a (or the delay circuit unit 101b). In the case of using a code to which a letter is added, each of the plurality of delay circuit units is shown.

  FIG. 1 is a block diagram showing an example of the configuration of the dead time control circuit of the present invention. In the following, the dead time control circuit 10 shown in FIG. 1 is described as being applied when two switching elements having a push-pull configuration are both constituted by N-channel MOSFETs, similarly to the circuit shown in FIG. To do. A dead time control circuit 10 shown in FIG. 1 includes a first pulse signal generation circuit 100a, a second pulse signal generation circuit 100b, delay circuit units (delay units) 101a and 101b, a logic circuit unit (signal generation unit) 102a, 102b. The dead time control circuit 10 inputs two pulse signals in which the activation pulse edge and the inactivation pulse edge substantially coincide with each other in parallel (HI and LI in FIG. 1), and among the input pulse signals, the activation pulse Output edges in parallel with delayed edges. In the present embodiment, the two pulse signals in which the activation pulse edge and the inactivation pulse edge substantially coincide with each other are two pulse signals having different logic levels.

  The delay circuit units 101a and 101b set a delay time that defines a dead time, and delay the pulse signal based on the set delay time. The logic circuit units 102a and 102b are AND gates (AND circuits), and output a logical product of the input pulse signals and the pulse signals delayed by the delay circuit units 101a and 101b. HI and LI indicate input signals (pulse signals), and HO and LO indicate output signals (pulse signals obtained by delaying activation pulse edges). DA is a control signal of a plurality of bits for controlling the delay time, and details will be described later with reference to FIG.

FIG. 2 is a block diagram showing an example of the configuration of the delay circuit unit of the present invention. The delay circuit unit 101 includes a first delay circuit 110A and a second delay circuit 110B. The first delay circuit 110A includes a first delay block (first delay unit) 120, and the second delay circuit 110B includes a second delay block (second delay unit) 130 and a third delay block (third delay block). Delay unit) 140. The first delay circuit 110A and the second delay circuit 110B, that is, the first, second, and third delay blocks are connected in series. Also, as a specific example of the control signal DA shown in FIG. 1, m = 3 bits D1 (upper 1 bit) to D3 (lower 1 bit) are shown. The delay circuit unit 101 is controlled by logic inputs from external terminals D1 to D3. Among the control signals DA of m = 3 bits, the higher-order m1 = 1-bit control signal D1 is input as the first control signal, and the lower-order m2 = m−m1 = 2-bit control signals D2 and D3 are second-controlled. Input as a signal. The dead time is set in 2 ^m = 8 steps based on the control signal DA of m = 3 bits. The step interval of the dead time set in 8 steps is controlled to n = 2 different step intervals by the control signal D1.

The first delay circuit 110A receives the high-order 1-bit control signal D1, selects one first delay time from n = 2 delay times based on the control signal D1, and delays the input pulse signal. n = 2 One of the two delay times is 0, the other is a predetermined minimum delay time (excluding 0), and in the example of FIG. 2 is 8 ns calculated by multiplying 2 ns by 4.
The second delay circuit 110B receives the pulse signal output from the first delay circuit 110A. Further, control signals D2 and D3 are input. Based on the control signal D1, a step interval corresponding to the selected first delay time is selected from n = 2 step intervals. One of n = 2 step intervals is a predetermined minimum delay time, which is 2 ns in the example of FIG. 2, and the other is 4 ns calculated by doubling the minimum delay time 2 ns. Based on the control signals D2 and D3, one second delay time is selected from 2 ^m2 = 4 delay times, and the input pulse signal is delayed. When the step interval is 2 ns, one of the four delay times is 0, and the other is 2, 4, 6 ns calculated by adding 0 to the 2 ns step. When the step interval is 4 ns, one of the four delay times is 0, and the other is 4, 8, 12 ns calculated by adding 0 to the 4 ns step.

  The first delay block 120 receives the control signal D1 and selects either the delay time 0 ns or 8 ns as the first delay time based on the control signal D1. The second delay block 130 receives the control signals D1 and D2, selects either the delay time 8 ns or 4 ns based on the control signal D1, and determines the delay time 0 ns or the control signal D1 based on the control signal D2. One of 8 ns or 4 ns selected by the above is selected as the second delay time. The third delay block 140 receives the control signals D1 and D3, selects either the delay time 4ns or 2ns based on the control signal D1, and determines the delay time 0ns or the control signal D1 based on the control signal D3. One of 4 ns or 2 ns selected by the above is selected as the second delay time. The input signal (HI or LI) is delayed at both the activation pulse edge and the deactivation pulse edge by the sum of the delay times selected by the first delay block 120, the second delay block 130, and the third delay block 140, respectively. The delayed output signal (HO or LO) is output from the delay circuit unit 101. The control signal DA controls selection of one delay time from a plurality of delay times in each of the first, second, and third delay blocks. That is, the delay circuit unit 101 sets the sum of the delay times selected by each delay block as a delay time that defines the dead time, and outputs the input pulse signal after delaying the set delay time.

  With each delay block, the delay time that defines the dead time can be set in a plurality of steps over a wide range. Further, the step interval can be changed according to the delay time. In FIG. 2, the dead time is set in 8 steps based on the control signals D1, D2, and D3. The step interval of the dead time set in 8 steps is controlled by the control signal D1. When the control signal D1 is one logic (for example, 0), the step interval is set to the above-mentioned minimum delay time of 2 ns, and when the other logic (one logic is 0, 1), the minimum delay time is 2 ns. Doubled to 4 ns. In this way, it is possible to set a delay time of a plurality of steps having different step intervals according to the delay time defining the dead time.

  The control signal DA is output from a control signal output unit (not shown) such as an external terminal. The control signal DA is controlled in value of H (1) and L (0) via an external terminal.

  FIG. 3 is a circuit diagram showing an example of the configuration of the first delay block 120. 3A, the first delay block 120-1 includes a delay element 121 and a selector 122. In FIG. 3B, the first delay block 120-2 includes a delay element 121 and a switch 123. An example is shown. The delay element 121 delays the signal by 8 ns. The control signal D1 sets the delay time by controlling the selector 122 or the switch 123 to control whether or not the signal that has passed through the delay element 121 is selected.

  FIG. 4 is a circuit diagram showing an example of the configuration of the second delay block 130. 4A, the second delay block 130-1 includes delay elements 131 and 132 and selectors 133 and 134. In FIG. 4B, the second delay block 130-2 includes delay elements 131 and 132. FIG. 4C illustrates an example in which the second delay block 130-3 includes delay elements 131 and 132 and switches 135 and 136. Yes. The delay elements 131 and 132 delay the signal by 4 ns. The control signal D1 sets the delay time by controlling the selector 133 or the switch 135 to control whether or not the signal that has passed through the delay element 131 is selected. The control signal D2 sets the delay time by controlling the selector 134 or the switch 136 to control whether or not the signal that has passed through the delay element 132 is selected.

  FIG. 5 is a circuit diagram showing an example of the configuration of the third delay block 140. 5A, the third delay block 140-1 includes delay elements 141 and 142 and selectors 143 and 144. In FIG. 5B, the third delay block 140-2 includes the delay elements 141 and 142. 142, the selector 144 and the switch 145 are shown. In FIG. 5C, the third delay block 140-3 is shown as an example including the delay elements 141 and 142 and the switches 145 and 146. Yes. The delay elements 141 and 142 delay the signal by 2 ns. The control signal D1 sets the delay time by controlling the selector 143 or the switch 145 to control whether or not the signal that has passed through the delay element 141 is selected. The control signal D3 sets the delay time by controlling the selector 144 or the switch 146 to control whether or not the signal that has passed through the delay element 142 is selected.

The delay elements of the first, second, and third delay blocks are composed of an even number, for example, two inverters connected in series, and the time is short in the first, second, and third order. Yes.
FIG. 6 shows an example of the configuration of the selector shown in FIGS. The selector 200 is connected to a circuit constituted by a NOT circuit 201 and NANDs 202 to 204 and a control signal DA for controlling the circuit. FIGS. 3 to 5 show examples of the configurations of the first, second, and third delay blocks. However, the configuration is not limited to these, and any configuration that realizes the same function may be used. It is not limited to these. Further, the step interval and the delay time are examples, and are not limited to these values.

  Next, the operation of the dead time control circuit 10 will be described with reference to FIGS. In the dead time control circuit 10 shown in FIGS. 1 to 5, the dead time can be set in the range of 0 to 20 ns. More details are as follows. The control signal (external terminal) takes values of L (0) and H (1).

  The first delay block 120 can be varied by 0 ns or 8 ns under the control of the control signal D1. The second delay block 130 can be varied by 0 ns or 4 ns when D1 = L and by 0 ns or 8 ns when D1 = H by the control of the control signal D2. The third delay block 140 can be varied by 0 ns or 2 ns when D1 = L and by 0 ns or 4 ns when D1 = H under the control of the control signal D3.

  Each logic input (control signals D1 to D3) realizes dead time digital control as shown in FIG. FIG. 7 is a diagram for explaining the operation of the dead time control circuit shown in FIG. As shown in FIG. 7, the dead time control circuit 10 can set dead times of 0, 2, 4, 6, 8, 12, 16, and 20 ns. Further, 0 to 8 ns can be set at a step interval, and 8 to 20 ns can be set at a step interval of 4 ns. As described above, by using the control signals D1 to D3, it is possible to set a dead time of a plurality of steps having different step intervals according to the dead time. For example, in FIG. 2, a wide range of dead time is controlled by a 3-bit signal line.

  As described above, in the preferred embodiment of the present invention, the delay circuit is devised so that a finer delay time can be set in a digital manner from a small number of external terminals. This makes it possible to change the step interval according to the dead time with an IC chip having a small circuit scale with a small number of external terminals and internal elements without externally attaching a delay element, and the dead time can be varied over a wide range of steps. It can be set with high accuracy.

  In the above-described embodiment, the two switching elements having the push-pull configuration to which the dead time control circuit of the present invention is applied have been described by way of example. It is applicable even in the case of comprising. In this case, the two pulse signals in which the activation pulse edge and the inactivation pulse edge that are input in parallel substantially coincide with each other are two pulse signals having the same logic level. Of the logic circuit units 102a and 102b, the logic circuit unit 102a includes an OR gate (OR circuit).

In the above embodiment, the control signal DA is m = 3 bits of the control signal DA, the first control signal is the control signal DA, the upper side m1 = 1 bit of the control signal D1, and the second control signal is the lower side m2. The control signals D2 and D3 of = m−m1 = 2 bits have been described as an example, but the present invention is not limited to this. That is, of the m-bit (m is an integer of 2 or more) control signal DA, the higher-order m1 bit (m1 is an integer of 1 or more) is input as the first control signal to the delay circuit unit, and the lower-order m2 bit (m2) Can be input as a second control signal. The dead time can be set in a maximum of 2 ^m steps based on the m-bit control signal DA. The step interval of the dead time set in 2 ^m steps can be controlled to n (≦ 2 ^m1 ) different step intervals (n is an integer of 2 or more) by the first control signal.

The first delay circuit can delay the input pulse signal by selecting one first delay time from n delay times based on the first control signal. One of the n delay times is 0, and the other n-1 methods have a predetermined minimum delay time (excluding 0) of 2 ⁰ × 2 ^m2 , ..., Σ2 ^{(m1 + 1-x)} × 2 It can be calculated by multiplying by ^m2 (x = 2 to n).
The second delay circuit can select a step interval corresponding to the selected first delay time among the n step intervals based on the first control signal. One of the n step intervals is a predetermined minimum delay time, and the other n-1 types are 2 ¹ ,..., 2 ^(X−1) (x = 2 to n) times the minimum delay time. Can be calculated. Based on the second control signal, it is possible to delay the input pulse signal by selecting one second delay time from a maximum of 2 ^m2 delay times. One of the 2 ^m2 delay times is 0, and the other can be calculated by adding to 0 at the step of the selected step interval.

It is a block diagram which shows an example of a structure of the dead time control circuit of this invention. It is a block diagram of the delay circuit used for the dead time control circuit of FIG. FIG. 3 is a circuit diagram illustrating an example of a first delay block of the delay circuit of FIG. 2. FIG. 3 is a circuit diagram illustrating an example of a second delay block of the delay circuit of FIG. 2. FIG. 3 is a circuit diagram illustrating an example of a third delay block of the delay circuit of FIG. 2. FIG. 6 is a circuit diagram illustrating an example of a selector illustrated in FIGS. 3 to 5. It is a figure explaining operation | movement of the dead time control circuit of FIG. 10 is a circuit diagram showing a drive circuit described in Patent Document 1. FIG. FIG. 9 is a timing chart of the drive circuit of FIG. 8. 10 is a circuit diagram showing a drive circuit described in Patent Document 2. FIG.

Explanation of symbols

10 dead time control circuit 100a first pulse signal generation circuit 100b second pulse signal generation circuit 101a, 101b delay circuit unit 102a, 102b logic circuit unit (AND gate)
110A First delay circuit 110B Second delay circuit 120, 120-1, 120-2 First delay block 121 Delay element 122 Selector 123 Switch 130, 130-1, 130-2, 130-3 Second delay block 131, 132 Delay element 133, 134 Selector 135, 136 Switch 140, 140-1, 140-2, 140-3 Third delay block 141, 142 Delay element 143, 144 Selector 145, 146 Switch 200 Selector 201 NOT circuit 202-204 NAND circuit

Claims (4)

Two pulse signals in which the activation pulse edge and the inactivation pulse edge substantially coincide with each other are input in parallel, and the activation pulse edge of the input pulse signal is delayed so that the inactivation pulse edge and the activation pulse edge of each other are delayed. A dead time control circuit that adds a dead time between and outputs in parallel,
A delay circuit unit that selects one of a plurality of delay times of a step interval according to the dead time based on a control signal and delays both pulse edges of the input pulse signal; and
A dead time control circuit comprising: a signal generation unit that logically processes the input pulse signal and the pulse signal delayed by the delay circuit unit to generate a signal in which the activation pulse edge is delayed. The control signal comprises a first control signal and a second control signal,
The delay circuit unit is
A first delay circuit that selects one first delay time from a plurality of delay times based on the first control signal and delays the input pulse signal;
A pulse signal output from the first delay circuit is input, and a delay time of a plurality of steps of a step interval corresponding to the selected first delay time is selected based on the first control signal, and the second A second delay circuit that selects one second delay time from a plurality of delay times of the selected step interval based on a control signal and delays the pulse signal input from the first delay circuit. The dead time control circuit according to claim 1. The control signal is composed of an m-bit (m is an integer of 2 or more) control signal,
The first control signal is the upper m1 bit (m1 is an integer of 1 or more) of the m bits,
The second control signal is lower m2 bits (m2 is an integer of 1 or more) of the m bits,
As the step interval, there are n (≦ 2 ^m1 , n is an integer of 2 or more) different step intervals, one of the n step intervals being a predetermined minimum delay time, and the other being a minimum delay. Calculated by multiplying the time by 2 ¹ ,..., 2 ^(X−1) (X = 2 to n),
The first delay circuit has n delay times as the plurality of delay times, one of the n delay times is 0, and the other has a predetermined minimum delay time of 2 ⁰ × 2 ^m2 , ..., a ^{Σ2 (m1 + 1-x)} × 2 m2 (x = 2~n) multiplied are calculated (n-1) delay time of the street,
The second delay circuit has a maximum of 2 ^m2 delay times as a plurality of delay times with a step interval according to the selected first delay time, and one of the 2 ^m2 delay times is 0 3. The dead time control circuit according to claim 2, wherein the other is a delay time calculated by being added to 0 at the step interval.   4. The dead time control circuit according to claim 1, wherein the two pulse signals are used as drive signals for driving two switching elements having a push-pull configuration.

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