JP2008172250A - Electrical wiring structure having carbon nanotubes and method for forming the same - Google Patents

Abstract

An electrical wiring structure having carbon nanotubes and a method for forming the same are provided.
An integrated circuit device includes conductive wiring including carbon nanotubes. The electrical wiring includes a first metal region. A first conductive barrier layer is provided on the upper surface of the first metal region, and a second metal region is provided on the first conductive barrier layer. The first conductive barrier layer includes a material that suppresses external diffusion of the first metal from the first metal region, and the second metal region includes a catalytic metal therein. An insulating layer having an opening therein is provided on the second metal region. A number of carbon nanotubes are provided as vertical electrical wiring in the openings.
[Selection] Figure 2E

Description

  The present invention relates to an integrated circuit device and a method for forming the integrated circuit device, and more particularly to a semiconductor wiring structure and a method for forming the same.

  In general, an integrated circuit device having a highly integrated semiconductor device uses a vertical wiring structure to connect vertically separated conductive wirings, semiconductor device structures and regions together. However, as the degree of integration of semiconductor devices in an integrated circuit increases, the line width and transverse width of conductive wiring and vertical wiring structures generally decrease. The reduction in the size of such conductive wiring and vertical wiring structures increases the need for wiring materials having low specific resistance. In order to cope with the increase in necessity as described above, a wiring structure including a highly conductive carbon nanotube structure has been developed. An example of a conventional wiring structure including carbon nanotubes is the “Method of Forming a Conducting Device of the Semiconductor and the Semiconductor Manufacturing and Manufacturing of the Semiconductor Nano and the United States of the United States.” This is disclosed in US Pat.

  Other conventional wiring structures containing carbon nanotubes are disclosed in US Pat. An integrated circuit device including a multi-walled carbon nanotube via is disclosed in Non-Patent Document 1 and Non-Patent Document 2.

US Pat. No. 7,247,897 US Patent Application Publication No. 2004/0182600 US Patent Application Publication No. 2006/0071334 Mizuhisa Nihei, “Carbon Nanotube Vias for Future LSI Interconnects”, Proceeding of the IEEE International Technology Technology. 4 251-253 Outside of Mizuhisa Nihei, “Low-resistence Multi-walled Carbon Nanotube Via with the Channel of the 6th of the World of World Channels and the World of Worlds.” 234-236

  The present invention has been made in view of the above-mentioned problems, and an object thereof is to provide a semiconductor device optimized for high integration and a method for forming the same.

  Another object of the present invention is to provide a semiconductor device optimized for high-speed operation and a method for forming the same.

  In order to achieve the above object, an integrated circuit device according to an embodiment of the present invention includes a conductive wiring including a carbon nanotube. According to one embodiment, the electrical wiring includes a first metal region having at least a first metal therein on the integrated circuit substrate. A first conductive barrier layer is provided on the upper surface of the first metal region, and a second metal region is provided on the first conductive barrier layer. The first conductive barrier layer includes a material that suppresses out diffusion of the first metal from the first metal region.

  According to an additional aspect of the present embodiment, an electrically insulating layer is provided on the second metal region. The electrical insulating layer has an opening inside which a predetermined portion of the second metal region is exposed. A number of carbon nanotubes are provided as vertical electrical wiring. The carbon nanotube extending into the opening is electrically coupled to the first metal region by the exposed portion of the second metal region and the first conductive barrier layer. According to an additional aspect of the present embodiment, the first metal can be copper, and the one conductive barrier layer is made of cobalt alloy, nickel alloy, palladium, indium, and combinations thereof. At least one of them can be included. The catalytic metal can be a metal selected from the group consisting of iron, nickel, cobalt, tungsten, yttrium, palladium and platinum.

  According to an additional embodiment of the present invention, a second conductive barrier layer may be provided on the multiple carbon nanotubes. The second conductive barrier layer may include a metal selected from the group consisting of tantalum, tantalum nitride, tungsten, and tungsten nitride.

  According to still another embodiment of the present invention, a conductive capping layer may be provided between the second metal region and the electrical insulating layer. The conductive cap layer includes a substance that suppresses oxygen external diffusion from the electrical insulating layer to the second metal region. The conductive cap layer may have an opening therein that is aligned with the opening in the electrically insulating layer. In particular, the conductive cap layer may be in contact with the upper surface of the second metal region, and may include a metal selected from the group consisting of cobalt alloy, nickel alloy, palladium, indium, and combinations thereof. . In particular, the metal includes a cobalt alloy doped with phosphorus (P), a cobalt alloy doped with boron, a nickel alloy doped with phosphorus, a nickel alloy doped with boron, palladium, indium, and the like. You can select from a group consisting of combinations.

  An integrated circuit device according to an additional embodiment of the present invention includes a semiconductor substrate and a first insulating layer on the semiconductor substrate. The first insulating layer has a recess therein. Further, a first conductive barrier layer is provided, wherein the first conductive barrier layer is provided with the recess so that the first conductive barrier layer extends between the first copper pattern and the first insulating layer. Cover the bottom and side walls. The first conductive barrier layer includes a material that suppresses external diffusion of copper from the first copper pattern. The first conductive barrier layer includes a cobalt alloy doped with phosphorus (P), a cobalt alloy doped with boron, a nickel alloy doped with phosphorus, a nickel alloy doped with boron, palladium, and indium. And a metal selected from the group consisting of these combinations.

  A second conductive barrier layer is provided on the upper surface of the first copper pattern. The second conductive barrier layer includes a material that suppresses external diffusion of copper from the first copper pattern. A catalytic metal layer is provided on the second conductive barrier layer, and a second interlayer insulating layer is provided on the catalytic metal layer. The catalytic metal layer may include at least one of iron, nickel, cobalt, and combinations thereof. The second interlayer insulating layer has an opening that exposes a predetermined portion of the catalyst metal layer. A number of carbon nanotubes are provided in the openings. The carbon nanotube is electrically coupled to the first copper pattern by the exposed portion of the catalytic metal layer and the second conductive barrier layer. The second conductive barrier layer includes a cobalt alloy doped with phosphorus (P), a cobalt alloy doped with boron, a nickel alloy doped with phosphorus, a nickel alloy doped with boron, palladium, and indium. And a metal selected from the group consisting of these combinations.

  Also, a capping layer is provided, and the cap layer extends between the catalytic metal layer and the second interlayer insulating layer. The cap layer includes a cobalt alloy doped with phosphorus (P), a cobalt alloy doped with boron, a nickel alloy doped with phosphorus, a nickel alloy doped with boron, palladium, indium, and a combination thereof. Metals selected from the group consisting of combinations can be included.

  An integrated circuit device according to another embodiment of the present invention includes a semiconductor substrate and a first interlayer insulating layer on the semiconductor substrate. The first interlayer insulating layer has a recess therein, and a copper pattern is formed in the recess in the first interlayer insulating layer. A conductive barrier layer is provided on the upper surface of the copper pattern. The conductive barrier layer includes a cobalt alloy doped with phosphorus (P), a cobalt alloy doped with boron, a nickel alloy doped with phosphorus, a nickel alloy doped with boron, palladium, indium, and the like. Including a metal selected from the group consisting of: A catalytic metal layer is provided on the conductive barrier layer, and a conductive cap layer is provided on the catalytic metal layer. The conductive cap layer has an upper surface that is coplanar with the upper surface of the first interlayer insulating layer. The conductive cap layer includes a cobalt alloy doped with phosphorus (P), a cobalt alloy doped with boron, a nickel alloy doped with phosphorus, a nickel alloy doped with boron, palladium, indium, and the like. A metal selected from the group consisting of a combination of: A second interlayer insulating layer is provided on the first interlayer insulating layer and on the conductive cap layer. The second interlayer insulating layer has an opening therein aligned with the opening in the conductive cap layer. A number of carbon nanotubes are provided, the carbon nanotubes extending through the openings in the second interlayer insulating layer and the conductive cap layer. The carbon nanotubes are in contact with the catalytic metal layer. A copper damascene pattern may be provided that extends into a recess in the second insulating layer and is electrically coupled to the multiple carbon nanotubes.

  According to an additional embodiment of the present invention, an integrated circuit device is formed by forming a first interlayer insulating layer having a recess therein on a substrate and then covering the recess with a first conductive barrier layer. Including methods. The covered recess is filled with a patterned copper layer. Thereafter, the first interlayer insulating layer is selectively etched to expose a sidewall of the first conductive barrier layer. A second conductive barrier layer is formed on the exposed sidewalls of the first conductive barrier layer and on the upper surface of the patterned copper layer, and a catalytic metal layer is formed on the second conductive barrier layer. It is formed. Thereafter, a second interlayer insulating layer is deposited on the catalytic metal layer. Thereafter, an opening is formed in the second interlayer insulating layer to expose a predetermined portion of the catalytic metal layer extending to the opposite side of the patterned copper layer. The opening in the second interlayer insulating layer is filled with a number of carbon nanotubes that are electrically coupled to the patterned copper layer by the catalytic metal layer and the second conductive barrier layer.

  In another embodiment of the present invention, a first metal layer is formed on a semiconductor substrate, a catalytic metal layer is formed on the first metal layer, and an interlayer insulating layer is formed on the catalytic metal layer. And a method of forming an integrated circuit device. The catalytic metal layer can be formed using an electroless plating technique. The interlayer insulating layer is patterned to define an opening exposing the upper surface of the catalytic metal layer. Thereafter, a step of removing oxygen from the catalytic metal layer may be performed using a chemical reduction process. For example, oxygen can be removed by exposing the catalyst metal layer to hydrogen so that the catalyst metal layer is exposed to plasma containing hydrogen. Alternatively, oxygen can be removed from the catalytic metal layer by exposing the catalytic metal layer to a gas containing hydrogen at a temperature range of about 200 ° C. to about 400 ° C. In addition, a step of forming a number of carbon nanotubes in the openings in the patterned interlayer insulating layer is performed. The carbon nanotubes can be covered with a copper damascene pattern.

  ADVANTAGE OF THE INVENTION According to this invention, the electromigration (Electro-migration, EM) generation | occurrence | production of copper wiring can be solved, and the wiring using the carbon nanomaterial which has a current characteristic better than copper can be applied easily to a semiconductor device. A semiconductor device optimized for high integration and high-speed operation can be obtained. In addition, since the catalytic metal layer is uniformly present only on the bottom of the plug, the carbon nanomaterial can be grown vertically and uniformly, and better current characteristics can be obtained.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein, and may be embodied in other forms. Rather, the embodiments presented herein are provided so that the content disclosed can be thoroughly and completely understood, and to convey the spirit of the present invention to those skilled in the art. In the drawings, like reference numerals indicate like elements in the several views.

  Referring to FIGS. 1A to 1E, a method of forming an integrated circuit device including an electrical wiring therein includes forming a first interlayer insulating layer 110 on a semiconductor substrate 100, and thereafter forming the first interlayer insulating layer 110 in the first interlayer insulating layer 110. Forming a recess 112 (eg, a trench pattern). The recess 112 can be formed by selectively etching the first interlayer insulating layer 110 using a mask (not shown). As shown in FIG. 1A, the first interlayer insulating layer 110 may be directly formed on the main surface of the semiconductor substrate 100, but other intervening layers (or) or device structures (or the like) (not shown) may be provided. It may be formed between the semiconductor substrate 100 and the first interlayer insulating layer 110. The first interlayer insulating layer 110 may be formed of a dielectric material such as silicon dioxide or a dielectric material having a low dielectric constant (low-k) such as SiCOH.

  The bottom and side walls of the recess 112 are covered with a first conductive barrier layer 122. According to one embodiment of the present invention, the first conductive barrier layer 122 includes a cobalt alloy doped with phosphorus (P), a cobalt alloy doped with boron, and a nickel alloy doped with phosphorus. , A barrier metal layer comprising a metal selected from the group consisting of boron-doped nickel alloys, palladium, indium and combinations thereof. Also, the first copper pattern may be formed in the recess 112 using a copper damascene forming technique including, for example, planarizing the deposited copper layer for a sufficient time to define the first copper pattern 124. 124 can be formed. The step of planarizing the copper layer includes polishing the copper layer chemically and mechanically. As shown in FIG. 1A, the first conductive barrier layer 122 extends between the first copper pattern 124 and the first interlayer insulating layer 110. The first conductive barrier layer 122 suppresses out diffusion of copper from the first copper pattern 124 to the surrounding first interlayer insulating layer 110. The first conductive barrier layer 122 and the first copper pattern 124 collectively define the conductive pattern 120.

  Referring to FIG. 1B, a second conductive barrier layer 132 is formed on the upper surface of the first copper pattern 124. The second conductive barrier layer 132 that suppresses the external diffusion of copper from the first copper pattern 124 is selectively formed on the first copper pattern 124 by using, for example, an electroless plating technique. It can also be formed. The second conductive barrier layer 132 may be formed of a cobalt alloy doped with phosphorus (P) (for example, a Co—WP alloy), a cobalt alloy doped with boron, a nickel alloy doped with phosphorus, It may be formed of a barrier metal layer comprising a metal selected from the group consisting of boron-doped nickel alloys, palladium, indium and combinations thereof. For example, the second conductive barrier layer 132 may be made of Co-WP, Co-Sn-P, Co-P, Co-B, Co-Sn-B, Co-WB, Ni-WP, It can be formed of a metal layer selected from the group consisting of Ni-Sn-P, Ni-P, Ni-B, Ni-Sn-B, Ni-WB, Pd, and In. Further, as shown in FIG. 1B, a catalytic metal layer 134 is formed on the second conductive barrier layer 132 using, for example, an electroless plating technique. According to an embodiment of the present invention, the catalytic metal layer 134 may include a material selected from the group consisting of iron, nickel, cobalt, and combinations thereof.

  Referring to FIGS. 1C to 1D, a second interlayer insulating layer 140 is formed and patterned on the first interlayer insulating layer 110 to define an opening 142 exposing the upper surface of the catalytic metal layer 134. The second interlayer insulating layer 140 may be formed of a dielectric material such as silicon dioxide or a dielectric material having a low dielectric constant (low-k) such as SiCOH. The formation of the opening 142 in the second interlayer insulating layer 140 may result in the formation of a native oxide film (not shown) on the catalytic metal layer 134. Thereafter, the formation of carbon nanotubes on the catalytic metal layer 140 can be suppressed. The natural oxide film exposes the second interlayer insulating layer 140 to hydrogen gas at a temperature range of about 200 ° C. to about 400 ° C., or exposes the second interlayer insulating layer 140 to a temperature range of about 25 ° C. to about 450 ° C. This can be removed by performing a chemical reduction process including a step of exposing to hydrogen plasma.

  In order to increase the formation rate of the nanotubes in the openings 142, a large number of carbon nanotubes 144 can be formed in the openings 142 using the catalytic metal layer 134. The carbon nanotubes 144 may be formed by conventional techniques such as chemical vapor deposition (CVD), plasma-enhanced CVD (CVD), atomic layer deposition, plasma-enhanced ALD (plasma-enhanced ALD). Can be formed. As shown, the carbon nanotube 144 is electrically connected to the first copper pattern 124 by the catalytic metal layer 134 and the second conductive barrier layer 132. As shown in FIG. 1E, the vertical wiring structure shown in FIG. 1D is extended on the second interlayer insulating layer 140 to form a conductive pattern 150 that is in electrical contact with the multiple carbon nanotubes 144. Can be completed. Additional materials that can function as catalytic metals for nanotube formation include tungsten, yttrium, palladium and gold.

  2A to 2E, a method of forming an electrical wiring according to an additional embodiment of the present invention forms a first interlayer insulating layer 110 on a semiconductor substrate 100 and uses a mask (not shown). Forming a recess 112 (eg, a trench pattern) in the first interlayer insulating layer 110 by selectively etching the first interlayer insulating layer 110. As shown in FIG. 2A, the first interlayer insulating layer 110 can be directly formed on the main surface of the semiconductor substrate 100, but other intervening layers (e.g.) or device structures (e.g.) (not shown) can be formed. It may be formed between the semiconductor substrate 100 and the first interlayer insulating layer 110. The first interlayer insulating layer 110 may be formed of a dielectric material such as silicon dioxide or a dielectric material having a low dielectric constant (low-k) such as SiCOH.

  The bottom and side walls of the recess 112 are covered with a first conductive barrier layer 122. According to one embodiment of the present invention, the first conductive barrier layer 122 includes a cobalt alloy doped with phosphorus (P), a cobalt alloy doped with boron, and a nickel alloy doped with phosphorus. And a barrier metal layer comprising a metal selected from the group consisting of boron-doped nickel alloys, palladium, indium and combinations thereof. Also, the first copper pattern 124 may be formed in the recess 112 by using a copper damascene forming technique including, for example, planarizing the deposited copper layer for a sufficient time to define the first copper pattern 124. Can be formed. The step of planarizing the copper layer includes polishing the copper layer chemically and mechanically. As shown in FIG. 2A, the first conductive barrier layer 122 extends between the first copper pattern 124 and the first interlayer insulating layer 110. The barrier layer 122 suppresses external diffusion of copper from the first copper pattern 124 to the surrounding first interlayer insulating layer 110. The barrier layer 122 and the first copper pattern 124 collectively define a conductive pattern 120.

  Referring to FIG. 2B, a second conductive barrier layer 132 is formed on the upper surface of the first copper pattern 124. The second conductive barrier layer 132 that suppresses the external diffusion of copper from the first copper pattern 124 is selectively formed on the first copper pattern 124 by using, for example, an electroless plating technique. It can also be formed. The second conductive barrier layer 132 includes a cobalt alloy doped with phosphorus (P) (eg, a Co—WP alloy), a cobalt alloy doped with boron, a nickel alloy doped with phosphorus, It can be formed as a barrier metal layer comprising a metal selected from the group consisting of boron-doped nickel alloys, palladium, indium and combinations thereof. For example, the second conductive barrier layer 132 may be made of Co-WP, Co-Sn-P, Co-P, Co-B, Co-Sn-B, Co-WB, Ni-WP, It can be formed of a metal layer selected from the group consisting of Ni-Sn-P, Ni-P, Ni-B, Ni-Sn-B, Ni-WB, Pd, and In. As shown in FIG. 2B, a catalytic metal layer 134 is formed on the second conductive barrier layer 132 using, for example, an electroless plating technique. According to an embodiment of the present invention, the catalytic metal layer 134 may include a material selected from the group consisting of iron, nickel, cobalt, and combinations thereof, but for forming carbon nanotubes. Other materials that function as catalytic metals can also be used.

  Referring to FIGS. 2C to 2D, a second interlayer insulating layer 140 is formed on the first interlayer insulating layer 110. The second interlayer insulating layer 140 may be formed of a dielectric material such as silicon dioxide or a dielectric material having a low dielectric constant (low-k) such as SiCOH. The second interlayer insulating layer 140 may be selectively patterned using a conventional technique to define a recess 143 therein, and extend through the second interlayer insulating layer to form the catalyst metal layer 134. An opening 142 that exposes the upper surface is defined.

  In order to increase the formation rate of nanotubes in the openings (eg, via opening) 142, a large number of carbon nanotubes 144 may be formed in the openings 142 using the catalytic metal layer 134. The carbon nanotubes 144 may be formed using conventional techniques such as chemical vapor deposition (CVD), plasma-enhanced CVD, plasma layer-enhanced CVD, plasma-enhanced ALD (plasma ALD). Can be formed. As shown, the carbon nanotube 144 is electrically connected to the first copper pattern 124 by the catalytic metal layer 134 and the second conductive barrier layer 132.

  Referring to FIG. 2E, a third barrier metal layer 152 may be deposited in the recess 143 so as to cover the bottom and side walls of the recess 143 and cover the carbon nanotube 144. A copper pattern 154 may be formed on the third barrier metal layer 152 to form a copper damascene structure 150 that is electrically connected to the carbon nanotubes 144. The third barrier metal layer 152 may include materials such as titanium nitride, tantalum, tantalum nitride, tungsten, and tungsten nitride, but other barrier materials may be used.

  Referring to FIGS. 3A to 3D, a method of forming an electrical wiring according to another embodiment of the present invention forms a first interlayer insulating layer 110 on a semiconductor substrate 100 and uses a mask (not shown). Forming a recess 112 (eg, a trench pattern) in the first interlayer insulating layer 110 by selectively etching the first interlayer insulating layer 110. As shown in FIG. 3A, the first interlayer insulating layer 110 can be formed directly on the main surface of the semiconductor substrate 100, but other intervening layers (e.g.) or device structures (e.g.) (not shown) It may be formed between the semiconductor substrate 100 and the first interlayer insulating layer 110. The first interlayer insulating layer 10 may be formed of a dielectric material such as silicon dioxide or a dielectric material having a low dielectric constant (low-k) such as SiCOH.

  The bottom and side walls of the recess 112 are covered with a first conductive barrier layer 122. According to one embodiment of the present invention, the first conductive barrier layer 122 includes a cobalt alloy doped with phosphorus (P), a cobalt alloy doped with boron, and a nickel alloy doped with phosphorus. And a barrier metal layer comprising a metal selected from the group consisting of boron-doped nickel alloys, palladium, indium and combinations thereof. Also, the first copper pattern 124 may be formed in the recess 112 by using a copper damascene forming technique including, for example, planarizing the deposited copper layer for a sufficient time to define the first copper pattern 124. Can be formed. The step of planarizing the copper layer includes polishing the copper layer chemically and mechanically. As shown in FIG. 3A, the first conductive barrier layer 122 extends between the first copper pattern 124 and the first interlayer insulating layer 110. The barrier layer 122 suppresses external diffusion of copper from the first copper pattern 124 to the surrounding first interlayer insulating layer 110. The barrier layer 122 and the first copper pattern 124 collectively define a conductive pattern 120.

  Referring to FIG. 3B, a second conductive barrier layer 132 is formed on the upper surface of the first copper pattern 124. The second conductive barrier layer 132 that suppresses the external diffusion of copper from the first copper pattern 124 is selectively formed on the first copper pattern 124 by using, for example, an electroless plating technique. It can also be formed. The second conductive barrier layer 132 includes a cobalt alloy doped with phosphorus (P) (eg, a Co—WP alloy), a cobalt alloy doped with boron, a nickel alloy doped with phosphorus, It can be formed as a barrier metal layer comprising a metal selected from the group consisting of boron-doped nickel alloys, palladium, indium and combinations thereof. For example, the second conductive barrier layer 132 may be made of Co-WP, Co-Sn-P, Co-P, Co-B, Co-Sn-B, Co-WB, Ni-WP, It can be formed of a metal layer selected from the group consisting of Ni-Sn-P, Ni-P, Ni-B, Ni-Sn-B, Ni-WB, Pd, and In. As shown in FIG. 3B, a catalytic metal layer 134 is formed on the second conductive barrier layer 132 using, for example, an electroless plating technique. According to one embodiment of the present invention, the catalytic metal layer 134 may include a material selected from the group consisting of iron, nickel, cobalt, and combinations thereof, but other materials may also be used. it can. In addition, referring to FIG. 3B, a conductive cap layer 136 is formed on the catalytic metal layer 134. The conductive cap layer 136 suppresses the outward diffusion of oxygen from a later formed dielectric dielectric layer to the catalytic metal layer 134, and during the subsequent process step (a), A material configured to suppress over-etch damage that may occur in the catalytic metal layer 134 is included. The conductive cap layer 136 includes a cobalt alloy doped with phosphorus (P) (for example, a Co-WP alloy), a cobalt alloy doped with boron, a nickel alloy doped with phosphorus, and boron. A material selected from the group consisting of doped nickel alloys, palladium, indium, and combinations thereof can be included, but other materials can also be used.

  Referring to FIGS. 3C to 3D, a second interlayer insulating layer 140 is formed on the first interlayer insulating layer 110. The second interlayer insulating layer 140 may be formed of a dielectric material such as silicon dioxide or a dielectric material having a low dielectric constant (low-k) such as SiCOH. The second interlayer insulating layer 140 is selectively patterned using a conventional technique to define an opening 142 therein, and the opening 142 includes the second interlayer insulating layer 140 and the conductive cap layer 136. The catalyst metal layer 134 is exposed. In order to increase the formation rate of nanotubes in the openings (for example, via openings) 142, a large number of carbon nanotubes 144 can be formed in the openings 142 using the catalytic metal layer 134. The carbon nanotubes 144 may be formed using conventional techniques such as chemical vapor deposition (CVD), plasma-enhanced CVD, plasma layer-enhanced CVD, plasma-enhanced ALD (plasma ALD). Can be formed. As shown in FIG. 3D, the carbon nanotube 144 is electrically connected to the first copper pattern 124 by the catalytic metal layer 134 and the second conductive barrier layer 132. The exemplary vertical wiring structure shown in FIG. 3D can be completed by extending the second interlayer insulating layer 140 to form a conductive pattern 150 that is in electrical contact with the multiple carbon nanotubes 144.

  4A to 4D, a method of forming an electrical wiring according to another embodiment of the present invention includes forming a first interlayer insulating layer 110 on a semiconductor substrate 100 and using a mask (not shown). Forming a recess 112 (eg, a trench pattern) in the first interlayer insulating layer 110 by selectively etching the first interlayer insulating layer 110. As shown in FIG. 4A, the first interlayer insulating layer 110 can be directly formed on the main surface of the semiconductor substrate 100, but other intervening layers (e.g.) or device structures (e.g.) (not shown) It may be formed between the semiconductor substrate 100 and the first interlayer insulating layer 110. The first interlayer insulating layer 110 may be formed of a dielectric material such as silicon dioxide or a dielectric material having a low dielectric constant (low-k) such as SiCOH.

  The bottom and side walls of the recess 112 are covered with a first conductive barrier layer 122. According to one embodiment of the present invention, the first conductive barrier layer 122 includes a cobalt alloy doped with phosphorus (P), a cobalt alloy doped with boron, and a nickel alloy doped with phosphorus. And a barrier metal layer comprising a metal selected from the group consisting of boron-doped nickel alloys, palladium, indium and combinations thereof. Also, the first copper pattern 124 may be formed in the recess 112 using a copper damascene forming technique including, for example, planarizing the copper layer for a sufficient time to define the first copper pattern 124. . The step of planarizing the copper layer includes polishing the copper layer chemically and mechanically.

  Referring to FIG. 4B, a step of selectively etching the first interlayer insulating layer 110 for a sufficient time to expose an upper sidewall of the first conductive barrier layer 122 is performed. Thereafter, as illustrated, a plating step (e.g., electroless plating) includes: (i) a second conductive barrier layer 132 ′, the exposed sidewalls of the first conductive barrier layer 122, and the first copper pattern. The step of plating on the upper surface of 124 and the step of (ii) plating the catalytic metal layer 134 ′ on the second conductive barrier layer 132 ′ are performed in this order.

  Referring to FIG. 4C, the intermediate structure shown in FIG. 4B can be repeatedly formed on the entire semiconductor substrate 100 in order to form a large number of copper patterns 124 located in the recesses arranged in the first interlayer insulating layer 110. . Thereafter, as illustrated, a second interlayer insulating layer 140 is deposited on the first interlayer insulating layer 110, and a plurality of openings 142 are formed in the second interlayer insulating layer 140. As shown in the drawing, when the adjacent first copper patterns 124 are sufficiently close, the second interlayer insulating layer 140 is formed at the interface with the first interlayer insulating layer 110 when the second interlayer insulating layer 140 is formed. A void 146 may be advantageously formed therein. The presence of the void 146 reduces the effective dielectric constant of the second interlayer insulating layer 140 in a region close to the copper pattern, for example, a parasitic coupling capacitance (between adjacent copper patterns 124). (parasitic coupling capacities) can be reduced. Thereafter, the steps illustrated and described with reference to FIGS. 1D to 1E are performed to form a carbon nanotube 144 in the opening 142 as shown in FIG. 4C, and on the carbon nanotube 144, A conductive pattern 150 is defined.

  The above-described preferred embodiments of the present invention are disclosed for the purpose of illustration, and those having ordinary knowledge in the technical field to which the present invention pertains depart from the technical idea of the present invention. Various substitutions, modifications, and alterations are possible within the scope of not being included, and such substitutions, alterations, and the like belong to the scope of the claims.

It is sectional drawing of the intermediate structure for demonstrating the method of forming the integrated circuit device by embodiment of this invention. It is sectional drawing of the intermediate structure for demonstrating the method of forming the integrated circuit device by embodiment of this invention. It is sectional drawing of the intermediate structure for demonstrating the method of forming the integrated circuit device by embodiment of this invention. It is sectional drawing of the intermediate structure for demonstrating the method of forming the integrated circuit device by embodiment of this invention. It is sectional drawing of the intermediate structure for demonstrating the method of forming the integrated circuit device by embodiment of this invention. It is sectional drawing of the intermediate structure for demonstrating the method of forming the integrated circuit device by other embodiment of this invention. FIG. 6 is a cross-sectional view of an intermediate structure for explaining a method of forming an integrated circuit device according to another embodiment of the present invention. It is sectional drawing of the intermediate structure for demonstrating the method of forming the integrated circuit device by other embodiment of this invention. It is sectional drawing of the intermediate structure for demonstrating the method of forming the integrated circuit device by other embodiment of this invention. It is sectional drawing of the intermediate structure for demonstrating the method of forming the integrated circuit device by other embodiment of this invention. It is sectional drawing of the intermediate structure for demonstrating the method of forming the integrated circuit device by other embodiment of this invention. It is sectional drawing of the intermediate structure for demonstrating the method of forming the integrated circuit device by other embodiment of this invention. It is sectional drawing of the intermediate structure for demonstrating the method of forming the integrated circuit device by other embodiment of this invention. It is sectional drawing of the intermediate structure for demonstrating the method of forming the integrated circuit device by other embodiment of this invention. It is sectional drawing of the intermediate structure for demonstrating the method of forming the integrated circuit device by other embodiment of this invention. It is sectional drawing of the intermediate structure for demonstrating the method of forming the integrated circuit device by other embodiment of this invention. It is sectional drawing of the intermediate structure for demonstrating the method of forming the integrated circuit device by other embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Semiconductor substrate 110 1st interlayer insulation layer 112 Recess 120 Conductive pattern 122 1st conductive barrier layer 124 1st copper pattern 132 2nd conductive barrier layer 134 Catalytic metal layer 140 2nd interlayer insulation layer 142 Opening 143 Recess 144 Carbon Nanotube 150 Copper Damascene Structure 152 Third Barrier Metal Layer 154 Copper Pattern

Claims (28)

A first metal region formed on the integrated circuit substrate and having a first metal therein;
A first conductive barrier layer formed on a surface of the first metal region, including a substance that suppresses external diffusion of the first metal from the first metal region;
A second metal region formed on the first conductive barrier layer and having a catalytic metal therein;
An insulating layer formed on the second metal region and having an opening inside which exposes a predetermined portion of the second metal region;
A plurality of carbon nanotubes extending in the opening and electrically coupled to the first metal region by the exposed portion of the second metal region and the first conductive barrier layer;
An integrated circuit device comprising:   The first metal of claim 1, wherein the first metal is copper, and the first conductive barrier layer includes at least one of a cobalt alloy, a nickel alloy, palladium, indium, and a combination thereof. Integrated circuit device.   3. The integrated circuit device according to claim 2, wherein the catalyst metal is a metal selected from the group consisting of iron, nickel, cobalt, tungsten, yttrium, palladium, and platinum.   The integrated circuit device according to claim 1, further comprising a second conductive barrier layer formed on the plurality of carbon nanotubes.   5. The integrated circuit device of claim 4, wherein the second conductive barrier layer comprises a metal selected from the group consisting of tantalum, tantalum nitride, tungsten, and tungsten nitride.   6. The integrated circuit device of claim 5, further comprising a copper damascene pattern formed on the second conductive barrier layer. A conductive cap layer between the second metal region and the insulating layer;
2. The integrated circuit device according to claim 1, wherein the conductive cap layer includes a material that suppresses external diffusion of oxygen from the insulating layer to the second metal region.   The integrated circuit device according to claim 7, wherein the conductive cap layer has an opening aligned with the opening in the insulating layer.   The conductive cap layer is in contact with an upper surface of the second metal region, and includes a metal selected from the group consisting of cobalt alloy, nickel alloy, palladium, indium, and combinations thereof. The integrated circuit device according to claim 7.   The conductive cap layer is in contact with the upper surface of the second metal region, and is a cobalt alloy doped with phosphorus, a cobalt alloy doped with boron, a nickel alloy doped with phosphorus, or a nickel alloy doped with boron. The integrated circuit device according to claim 7, comprising a metal selected from the group consisting of palladium, indium, and combinations thereof. A semiconductor substrate;
A first interlayer insulating layer formed on the semiconductor substrate and having a recess therein;
A first copper pattern formed in the recess in the first interlayer insulating layer;
First conductivity including a material that covers a bottom surface and a side wall of the recess so as to extend between the first copper pattern and the first interlayer insulating layer and suppresses external diffusion of copper from the first copper pattern. A barrier layer;
A second conductive barrier layer formed on an upper surface of the first copper pattern and including a material that suppresses external diffusion of copper from the first copper pattern;
A catalytic metal layer formed on the second conductive barrier layer;
A second interlayer insulating layer formed on the catalyst metal layer and having an opening inside which exposes a predetermined portion of the catalyst metal layer;
A plurality of carbon nanotubes extending in the opening and electrically coupled to the first copper pattern by the exposed portion of the catalytic metal layer and the second conductive barrier layer;
An integrated circuit device comprising:   The second conductive barrier layer may be formed of a cobalt alloy doped with phosphorus, a cobalt alloy doped with boron, a nickel alloy doped with phosphorus, a nickel alloy doped with boron, palladium, indium, or a combination thereof. The integrated circuit device of claim 11, comprising a metal selected from a group that is configured.   The integrated circuit device of claim 11, further comprising a cap layer extending between the catalytic metal layer and the second interlayer insulating layer.   The cap layer includes a phosphorus-doped cobalt alloy, a boron-doped cobalt alloy, a phosphorus-doped nickel alloy, a boron-doped nickel alloy, palladium, indium, and combinations thereof. The integrated circuit device of claim 13, comprising a metal selected from:   It further includes a cap layer formed between the catalyst metal layer and the second interlayer insulating film, and the cap layer includes a substance that suppresses external diffusion of oxygen from the insulation layer to the catalyst metal layer. The integrated circuit device according to claim 11.   The first conductive barrier layer may include a cobalt alloy doped with phosphorus, a cobalt alloy doped with boron, a nickel alloy doped with phosphorus, a nickel alloy doped with boron, palladium, indium, and combinations thereof. The integrated circuit device of claim 12, comprising a metal selected from the group comprised.   The integrated circuit device according to claim 12, wherein the catalytic metal layer includes at least one of iron, nickel, cobalt, and a combination thereof. A semiconductor substrate;
A first interlayer insulating layer formed on the semiconductor substrate and having a recess therein;
A copper pattern formed in the recess in the first interlayer insulating layer;
A cobalt alloy doped with phosphorus, a cobalt alloy doped with boron, a nickel alloy doped with phosphorus, a nickel alloy doped with boron, palladium, indium, and a combination thereof formed on the upper surface of the copper pattern A conductive barrier layer comprising a metal selected from the group consisting of:
A catalytic metal layer formed on the conductive barrier layer;
A cobalt alloy doped with phosphorus, a cobalt alloy doped with boron, a phosphorus alloy formed on the catalyst metal layer and having an upper surface formed on the same plane as the upper surface of the first interlayer insulating layer. A conductive cap layer comprising a metal selected from the group consisting of a doped nickel alloy, a boron-doped nickel alloy, palladium, indium, and combinations thereof;
A second interlayer insulating layer formed on the first interlayer insulating layer and having an opening therein aligned with the opening in the conductive cap layer;
A plurality of carbon nanotubes extending through the opening in the second interlayer insulating layer and the opening in the conductive cap layer and in contact with the catalytic metal layer;
An integrated circuit device comprising:   The integrated circuit device of claim 18, further comprising a copper damascene pattern extending to the second interlayer insulating layer and electrically coupled to the plurality of carbon nanotubes. Forming a first interlayer insulating layer having a recess therein on a substrate;
Covering the recess with a first conductive barrier layer;
Filling the covered recess with a patterned copper layer;
Selectively etching the first interlayer insulating layer to expose a sidewall of the first conductive ibarrier layer;
Plating a second conductive barrier layer on the exposed sidewalls of the first conductive barrier layer and on an upper surface of the patterned copper layer;
Plating a catalytic metal layer on the second conductive barrier layer;
Depositing a second interlayer insulating layer on the catalytic metal layer;
Forming an opening in the second interlayer insulating layer to expose a predetermined portion of the catalytic metal layer extending to the opposite side of the patterned copper layer;
Filling the openings in the second interlayer insulating layer with a plurality of carbon nanotubes electrically coupled to the patterned copper layer by the catalytic metal layer and the second conductive barrier layer;
A method for forming an integrated circuit device, comprising:   The method of claim 1, further comprising removing oxide from the exposed portion of the catalytic metal layer using a chemical reduction process including exposing the predetermined portion of the catalytic metal layer to hydrogen. Item 20. A method for forming an integrated circuit device according to Item 20. Forming a first metal layer on a semiconductor substrate;
Forming a catalytic metal layer on the first metal layer;
Forming an interlayer insulating layer on the catalytic metal layer;
Patterning the interlayer insulating layer to define an opening in the top that exposes an upper surface of the catalytic metal layer;
Removing oxide from the exposed upper surface of the catalytic metal layer using a chemical reduction process comprising providing hydrogen to the exposed upper surface;
Forming a number of carbon nanotubes in the openings in the patterned interlayer insulating layer;
A method for forming an integrated circuit device, comprising:   23. The method of forming an integrated circuit device according to claim 22, wherein the removing step includes providing hydrogen gas to the exposed upper surface in a temperature range of 200 to 400 degrees Celsius.   23. The method of forming an integrated circuit device according to claim 22, wherein the step of forming the catalytic metal layer includes a step of forming the catalytic metal layer using an electroless plating technique. Forming a first metal layer on a semiconductor substrate;
Forming a catalytic metal layer on the first metal layer;
Forming an interlayer insulating layer on the catalytic metal layer;
Patterning the interlayer insulating layer to define an opening in the top that exposes an upper surface of the catalytic metal layer;
Removing oxygen from the catalytic metal layer using a chemical reduction process;
Forming a number of carbon nanotubes in the openings in the patterned interlayer insulating layer;
A method for forming an integrated circuit device, comprising:   26. The method of forming an integrated circuit device according to claim 25, wherein the removing step includes a step of exposing the catalytic metal layer to hydrogen.   26. The method of forming an integrated circuit device according to claim 25, wherein the removing step includes a step of exposing the catalytic metal layer to a plasma containing hydrogen.   26. The method of forming an integrated circuit device according to claim 25, wherein the removing step includes a step of exposing the catalytic metal layer to a gas containing hydrogen in a temperature range of 200 ° C. to 400 ° C.

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