JP2008170757A - Display device and electronic equipment equipped therewith - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a liquid crystal display device which does not increase a peripheral edge area while containing a condenser necessary for a power source circuit in a glass substrate. <P>SOLUTION: The liquid crystal display device 910 is equipped with a display panel 911 which composed of an active matrix substrate 101 and a counter substrate 912 arranged to face the substrate, a power source circuit 304 which is arranged on the display panel for generating the prescribed power source potential from the power source potential inputted from an external power source circuit 784, and a plug-in capacitor 501 connected to the power source circuit or a bypass condenser 502. The active matrix substrate 101 has an overhang part 927 which protrudes from the portion where the active matrix substrate 101 faces the counter substrate 912. The condenser connected to the power source circuit is formed in the overhang part 927. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a display device, and more particularly, to a display device including two substrates disposed opposite to each other, and to a display device in which a power supply circuit is formed on the substrate and an electronic apparatus equipped with the display device.

  In recent years, so-called System On Glass (SOG) technology for forming a thin film transistor (TFT) circuit on a glass substrate using a low-temperature polysilicon thin film forming technology has been developed and is being mass-produced. A DC / DC converter circuit can be cited as a circuit having great merit by being built in the substrate. That is, only a relatively low voltage (eg, less than 5V) power supply and signal are applied to the circuit on the glass substrate from the external circuit, and a relatively high voltage (eg, 8V or more) power supply is generated by the DCDC converter circuit on the glass substrate. Then, it is supplied to the circuit on the glass substrate. With such a configuration, an IC constituting an external circuit can be manufactured by a medium and low withstand voltage process, so that the cost is reduced.

  At present, a charge pump circuit is most often used as a DCDC converter circuit. The charge pump circuit requires two types of capacitors: a flying capacitor driven by a pumping pulse signal and a bypass capacitor that stabilizes the output power supply. These capacitors are conventionally mounted outside the glass substrate as external components. It had been. Patent document 1 etc. are mention | raise | lifted as such a structural example.

JP 2004-226786 A

  Externally attaching the capacitor to the outside of the glass substrate leads to an increase in cost due to an increase in the number of components and an increase in the number of mounting steps, and the number of mounting terminals also increases, which is not preferable in terms of reliability.

  However, in order for the DCDC converter circuit to operate stably and efficiently, the capacitances of the flying capacitor and the bypass capacitor are required to be above a certain level, and differ depending on the power consumption etc. Is required. When a capacitor having such a large size is formed on the periphery of the glass substrate by the SOG technique, a very large area is required, and the conventional technology has a problem that the size of the periphery of the display device increases. It was.

  The bypass capacitor requires a large capacity for stabilizing the output voltage, but the frequency characteristic is not so much required. However, since the flying capacitor is driven by the pumping pulse signal, the frequency characteristic is important. It was difficult to form the capacitors on the same glass substrate while satisfying each other's requirements at the same time.

  According to the display device of an aspect of the present invention, the display device includes the first display substrate (active matrix substrate 101) and the second display substrate (counter substrate 912) disposed to face the first display substrate. A display panel (display panel 911), a power supply circuit (power supply circuit 304) that is disposed on the display panel and generates a predetermined power supply potential from a power supply potential input from outside the panel (external power supply circuit 784), and the power supply A display device (liquid crystal display device 910) including a capacitor (flying capacitor 501 and / or bypass capacitor 502) connected to a circuit, wherein the first substrate for display is arranged so that the second substrate for display is opposed to the display device. And a capacitor connected to the power supply circuit is formed on the protruding portion.

  Since the second substrate for display does not get in the way, the overhanging portion where the mounting terminal (first mounting terminal 320-1) and marks (panel number mark portion 510 and / or alignment mark 511, 511B for alignment) are arranged If the capacitor is arranged, the capacitor can be formed on the first substrate for display without increasing the peripheral edge of the display device.

  More specifically, a mounting terminal (signal input terminal (mounting terminal group) 320B) for mounting an IC or a flexible substrate (FPC (flexible substrate) 928) is provided on the projecting portion (projecting portion 927). The capacitors (the fifth flying capacitor 501B-1 to the eighth flying capacitor 501B-4 and / or the third bypass capacitor 502B-1 and the fourth bypass capacitor 502B-2) are connected to the mounting terminal (the fifth The mounting terminals 320B-3 to the eighth mounting terminal 320B-6 and / or the third mounting terminal 320B-1 and the fourth mounting terminal 320B-2) are formed in a region overlapping in plan view. Alternatively, the overhanging portion is provided with a panel number mark (panel number mark portion 510) for individual identification, and the capacitors (first bypass capacitor 502-1 and second bypass capacitor 502-2) are arranged on the panel. It is formed in a region that overlaps with the number mark (panel number mark portion 510, removal portion 510A) in a plane. Alternatively, an alignment mark (alignment alignment mark 511, 511B) for optical alignment is provided, and the capacitor (first flying capacitor 501-1) includes the alignment mark (alignment alignment mark 511, 511B) is formed in a region overlapping with the plane. More specifically, the alignment mark is an alignment mark when an IC or a flexible substrate is mounted on the projecting portion.

  With such a configuration, the capacitor can be formed on the first substrate for display while suppressing an increase in the area of the projecting portion. Further, when the mounting terminal portion and the capacitor are arranged in an overlapping manner, there is an advantage that the wiring of the capacitor is not required or the efficiency of the power supply circuit is increased because a minimum path is sufficient.

  According to another aspect of the display device of the present invention, a display panel including a first display substrate, a second display substrate disposed to face the first display substrate, and the display panel. A power supply circuit comprising a charge pump circuit that generates a predetermined power supply potential from a power supply potential input from the outside by pumping a flying capacitor (pumping pulse signal PCLK) whose potential at both ends periodically varies; A display capacitor connected to an output power supply potential from a power supply circuit and protruding from a portion where a bypass capacitor for stabilizing the output power supply potential and the first substrate for display and the second substrate for display are arranged to face each other. And a flying capacitor and a bypass capacitor on the first substrate for display. The flying capacitor and the bypass capacitor are stacked by a recon thin film forming technique, and the flying capacitor and the bypass capacitor are formed of different conductive layers (upper layer wiring 501B (the same film as the aluminum neodymium alloy thin film (AlNd) constituting the data line 202), Lower layer wiring 501A (the same film as the molybdenum thin film (Mo) constituting the capacitor line 203), upper layer wiring 502B (the same film as the molybdenum thin film (Mo) constituting the scanning line 201 and the capacitor line 203), lower layer wiring 502A ( And the insulating film (capacitor insulating film 501C (the same film as the interlayer insulating film)) and the capacitive insulating film 502C (the same as the gate insulating film). Membrane)).

  With such a configuration, the insulating film (capacitor insulating film 502C) constituting the bypass capacitor (bypass capacitor 502) can generally use the same film as the gate insulating film of an extremely thin transistor of 100 nm or less. However, all of the films constituting the electrodes of the flying capacitor (flying capacitor 501) are metal films (upper layer wiring 501B (molybdenum thin film (Mo)), lower layer wiring 501A (aluminum / neodymium alloy thin film (AlNd)). ))), The frequency characteristics are improved, and an optimum capacitor can be formed for each characteristic.

  Hereinafter, embodiments embodying the present invention will be described with reference to the drawings.

  FIG. 1 is a perspective configuration diagram (partially sectional view) of a transmissive liquid crystal display device 910 according to the present embodiment. In the liquid crystal display device 910, the active matrix substrate 101 (first substrate for display) and the counter substrate 912 (second substrate for display) are bonded to each other with a sealant 923 at a predetermined interval, and a liquid crystal material 922 in a nematic phase is sandwiched. A display panel 911. Although not shown, an alignment material made of polyimide or the like is applied onto the active matrix substrate 101 and rubbed to form an alignment film. Further, the counter substrate 912 is short-circuited with a color filter corresponding to a pixel (not shown), a black matrix for preventing light leakage and improving contrast, and a counter conductive portion 330 on the active matrix substrate 101, so that the common potential is reduced. A counter electrode 930 (electrode pad portion) made of an ITO film is supplied. An alignment material made of polyimide or the like is applied to a surface in contact with the liquid crystal material 922, and is rubbed in a direction orthogonal to the rubbing direction of the alignment film of the active matrix substrate 101.

  Further, an upper polarizing plate 924 is arranged outside the counter substrate 912, and a lower polarizing plate 925 is arranged outside the active matrix substrate 101 so that their polarization directions are orthogonal to each other (crossed Nicols). Further, a backlight unit 926 forming a surface light source is disposed below the lower polarizing plate 925. The backlight unit 926 may be a cold cathode tube or LED with a light guide plate or a scattering plate attached thereto, or may be a unit that emits light entirely from an EL element. The backlight unit 926 is connected to the electronic device main body through the connector 929, and is supplied with power and a control signal. Although not shown, if necessary, the periphery may be covered with an outer shell, or a protective glass or acrylic plate may be attached further above the upper polarizing plate 924, and optical for improving the viewing angle. A compensation film may be attached.

  In addition, the active matrix substrate 101 is provided with a protruding portion 927 that extends from the counter substrate 912, and an FPC (flexible substrate) 928 is mounted on the signal input terminal (mounting terminal group) 320 in the protruding portion 927. Electrically connected. An FPC (flexible substrate) 928 is connected to the main body of the electronic device and supplied with necessary power, control signals, and the like.

  In the conventional example, a plurality of capacitor components, for example, ceramic capacitors, are mounted on an FPC (flexible substrate) 928. However, in this embodiment, the capacitors are formed on the active matrix substrate 101 by using low-temperature polysilicon technology. It is formed by a system on glass (SOG) technique for circuit integration on a glass substrate constituting a display panel. Since the capacitor is formed on the glass substrate, the capacitor is not necessary on the FPC (flexible substrate) 928. As a result, the number of semiconductor components can be reduced, the assembly can be simplified, the external circuit board can be reduced, and the overall reduction in size, weight, and cost can be realized.

  FIG. 2 is a block diagram of the active matrix substrate 101. On the active matrix substrate 101, 480 scanning lines 201, 201-1 to 201-480 and 1920 data lines 202, 202-1 to 202-1920 are formed orthogonally, and 480 capacitors. The lines 203, 203-1 to 203-480 are arranged in parallel with the scanning lines 201-1 to 201-480. The capacitor lines 203-1 to 203-480 are short-circuited to each other, connected to the opposing conductive portion 330, and given an appropriate common potential from the common potential power supply circuit 306.

  The scanning lines 201-1 to 201-480 are connected to the scanning line driving circuit 301 and supplied with driving signals. Further, the data lines 202-1 to 202-1920 are connected to the data line driving circuit 302 and supplied with video signals. The common potential power supply circuit 306, the scanning line drive circuit 301, the data line drive circuit 302, and the signal circuit 305 are supplied with necessary potentials (for example, +9 V, −4 V power supply, etc.) from the power supply circuit 304. The scanning line driver circuit 301, the data line driver circuit 302, and the power supply circuit 304 are supplied with necessary signals (for example, SP, CLK signal, etc.) from the signal circuit 305. The data line driving circuit 302 also receives video signals D0 to D17 from a signal input terminal (mounting terminal group) 320. The signal circuit 305 is also supplied with necessary signals (master clock, SYNC signal, etc.) from a signal input terminal (mounting terminal group) 320, and the power supply circuit 304 is also supplied with a primary power supply (for example, + 5V power supply). Here, the signal input terminal (mounting terminal group) 320 is disposed on the overhanging portion 927. On the other hand, the scanning line driving circuit 301, the data line driving circuit 302, the power supply circuit 304, the signal circuit 305, the common potential power supply circuit 306, and the like are formed and disposed on the substrate region overlapping the counter substrate 912 on the active matrix substrate 101 by the SOG technique. Is done. The first mounting terminal 320-1 is one of the signal input terminals (mounting terminal group) 320 and is arranged at the right end, and the second mounting terminal 320-2 is also a signal input terminal (mounting terminal group). One of the terminals 320 is a terminal adjacent to the left side of the first mounting terminal 320-1, and the details will be described with reference to FIG.

  A panel number mark portion 510 is disposed on the overhang portion 927. In the panel number mark portion 510, the panel number is marked with a two-dimensional code for quality control and traceability ensuring, so that it can be read optically.

  Furthermore, four first flying capacitors 501-1 to 501-4, two first bypass capacitors 502-1 and second bypass capacitors 502-2 are connected to the power supply circuit 304. (In FIG. 2, only the first flying capacitor 501-1 and the first bypass capacitor 502-1 are shown, but the second flying capacitor 501-2 to the fourth flying capacitor 501-4 are the first flying capacitor. As with 501-1, the second bypass capacitor 502-2 is connected in the same manner as the first bypass capacitor 502-1). The first flying capacitor 501-1 to the fourth flying capacitor 501-4, the two first bypass capacitors 502-1 and the second bypass capacitor 502-2 are all disposed on the overhanging portion 927. The first bypass capacitor 502-1 and the panel number mark portion 510 are arranged so as to overlap each other, and the area of the overhang portion 927 is prevented from being enlarged.

  The scanning line driving circuit 301, the data line driving circuit 302, the power supply circuit 304, the signal circuit 305, and the common potential power supply circuit 306 are formed by circuit integration of polysilicon thin film transistors on an active matrix substrate by SOG technology, which will be described later. This is a so-called drive circuit built-in type liquid crystal display device manufactured in the same process as the pixel switching element 401-nm.

  FIG. 3 is a circuit diagram near the intersection of the mth data line 202-m and the nth scanning line 201-n in the pixel display area indicated by the dotted line 310 in FIG. A pixel switching element 401-n-m made of an N-channel field effect polysilicon thin film transistor is formed at each intersection of the scanning line 201-n and the data line 202-m, and its gate electrode is connected to the scanning line 201-n. The source electrode and the drain electrode are connected to the data line 202-m and the pixel electrode 402-nm, respectively. The pixel electrode 402-nm and the electrode that is short-circuited to the same potential form a capacitance line 203-n and an auxiliary capacitance capacitor 403-nm, and when assembled as the display panel 911, the liquid crystal element is sandwiched. Then, a capacitor is formed with the counter electrode 930 as a common (COM) electrode.

  FIG. 4 is a block diagram showing a specific configuration of the electronic apparatus in this embodiment. The liquid crystal display device 910 is the liquid crystal display device described in FIG. 1, and the external power supply circuit 784 and the video processing circuit 780 send necessary signals and power to the liquid crystal display device 910 through an FPC (flexible substrate) 928 and a connector 929. Supply. The central processing circuit 781 acquires input data from the input / output device 783 via the external I / F circuit 782. Here, the input / output device 783 is, for example, a keyboard, a mouse, a trackball, an LED, a speaker, an antenna, or the like. The central processing circuit 781 performs various arithmetic processing based on data from the outside, and transfers the result to the video processing circuit 780 or the external I / F circuit 782 as a command. The video processing circuit 780 updates the video information based on the command from the central processing circuit 761 and changes the signal to the liquid crystal display device 910, whereby the display video of the liquid crystal display device 910 changes. Specifically, the electronic device includes a monitor, a TV, a notebook computer, a PDA, a digital camera, a video camera, a mobile phone, a mobile photo viewer, a mobile video player, a mobile DVD player, a mobile audio player, and the like.

  FIG. 5 is a plan view showing an actual configuration of the circuit diagram of the pixel display region 310 shown in FIG. As shown in the legend of FIG. 5, different shaded parts indicate different material wirings, and the same shaded parts indicate the same material wiring. It consists of four layers of polysilicon thin film (Poly-Si), molybdenum thin film (Mo), aluminum / neodymium alloy thin film (AlNd), and indium tin oxide thin film (Indium Tin Oxiced = ITO). In this case, any one of silicon oxide, silicon nitride, and an organic insulating film or an insulating film formed by stacking them is formed. Specifically, a polysilicon thin film (Poly-Si) is 50 nm thick, a molybdenum thin film (Mo) is 200 nm thick, an aluminum / neodymium alloy thin film (AlNd) is 500 nm thick, and an indium oxide / tin thin film (ITO) is The film thickness is 100 nm. Further, a gate insulating film made of a 100 nm silicon oxide film is formed between the polysilicon thin film (Poly-Si) and the molybdenum thin film (Mo), and between the molybdenum thin film (Mo) and the aluminum-neodymium alloy thin film (AlNd). An interlayer insulating film in which a 200 nm silicon nitride film and a 500 nm silicon oxide film are stacked is formed, and a 200 nm silicon nitride film is formed between an aluminum / neodymium alloy thin film (AlNd) and an indium oxide / tin thin film (ITO). A protective insulating film is formed by laminating an organic planarizing film having an average of 1 μm, insulates the wirings from each other, and is connected to each other by opening contact holes at appropriate positions.

  As shown in FIG. 5, the data line 202-m is formed of an aluminum-neodymium alloy thin film (AlNd) and is connected to the source electrode of the pixel switching element 401-nm through a contact hole. The scanning line 201-n is composed of a molybdenum thin film (Mo) and also serves as the gate electrode of the pixel switching element 401-nm. The capacitor line 203-n is made of the same wiring material as the scanning line 201-n, the pixel electrode 402-nm is made of an indium oxide / tin thin film, and a contact hole is formed in the drain electrode of the pixel switching element 401-nm. Connected through. Further, the drain electrode of the pixel switching element 401-nm is also connected to a capacitor electrode 605 made of an n + type polysilicon thin film heavily doped with phosphorus, and overlaps the capacitor line 203-n in plan view to form an auxiliary capacitor. The capacitor 403-nm is configured.

  FIG. 6 is a diagram showing a cross-sectional structure of the pixel switching element 401-nm in the AA ′ line portion of FIG. Note that the scale is not constant in order to make the drawing easier to see. The active matrix substrate 101 is an insulating substrate made of alkali-free glass and having a thickness of 0.6 mm. The active matrix substrate 101 is made of a polysilicon thin film through a base insulating film 601 in which a 200 nm silicon nitride film and a 300 nm silicon oxide film are stacked. The silicon island 602 is disposed, and the scanning line 201-n is disposed above the silicon island 602 and the gate insulating film 606 described above. In the region overlapping with the scanning line 201-n, the silicon island 602 is an intrinsic semiconductor region 602I in which phosphorus ions are not doped at all or only in a very low concentration, and a specific resistance of about 20 kΩ in which phosphorus ions are lightly doped on the left and right sides thereof. This is an LDD (Lightly Doped Drain) structure in which there are n-regions 602L and n + regions 602N having a specific resistance of about 1 kΩ doped with phosphorus ions at high concentrations on both sides thereof. The left and right n + regions 602N are connected to the source electrode 603 and the drain electrode 604 through contact holes, the source electrode 603 is connected to the data line 202-m, and the drain electrode 604 is connected to the pixel electrode 402-nm. ing.

  FIG. 7 is a partial cross-sectional view of the auxiliary capacitor 403-nm in the BB ′ line portion of FIG. 5, in which the capacitor electrode 605 connected to the drain electrode 604 and the capacitor line 203-n sandwich the gate insulating film 606. The storage capacitor is formed by superimposing at.

  FIG. 8 is an enlarged plan view of the right end portion of the overhang portion 927 on the active matrix substrate 101. The legend is the same as in FIG. 5, but the scale is not constant for easy viewing of the figure. The first mounting terminal 320-1 and the second mounting terminal 320-2 are connected to an FPC (flexible substrate) 928 and receive the supply of power and signals from an external circuit to the right end of the signal input terminal (mounting terminal group) 320. The first mounting terminal 320-1 is connected to a power supply of 0V (GND), the second mounting terminal 320-2 is connected to a power supply of + 5V, and wiring is connected to the power supply circuit 304 on the glass substrate. Yes. Four first flying capacitors 501-1 to 501-4 are on the right side, and two first bypass capacitors 502-1 and second bypass capacitor 502- are on the right side. 2 are arranged respectively. Further, the first bypass capacitor 502-1 is disposed so as to overlap the panel number mark portion 510. Further, the same film as the pixel electrode 402-nm is formed on the first flying capacitor 501-1 to the fourth flying capacitor 501-4, the first bypass capacitor 502-1 and the second bypass capacitor 502-2. The shield wiring 520 is disposed, and the first flying capacitor 501-1 to the fourth flying capacitor 501-4 and the first bypass capacitor are detected from noise from an external circuit or FPC (flexible substrate) 928. 502-1 and the second bypass capacitor 502-2 are shielded. In this embodiment, the shield wiring 520 is not connected to a potential and is in a floating state, and the potential is lowered by capacitive division when the first flying capacitor 501-1 to the fourth flying capacitor 501-4 are driven. To prevent that. Further, the shield wiring 520 is the same indium oxide / tin thin film (ITO) as the pixel electrode 402-nm, and this film is processed by wet etching with oxalic acid or aqua regia. The electrode under the removal portion, particularly the aluminum / neodymium alloy thin film (AlNd), is easily corroded due to poor coverage or the like, which causes a decrease in yield. However, by leaving the shield wiring 520 on the capacitor as in this embodiment, Such a defect can be eliminated.

  FIG. 9 is a partial cross-sectional view of the second mounting terminal 320-2 in the CC ′ line portion of FIG. The second mounting terminal 320-2 is formed by laminating wiring layers of aluminum / neodymium alloy (AlNd) and indium oxide / tin thin film (ITO), and is connected to each other through a contact hole. When the FPC (flexible substrate) 928 is mounted, the indium oxide / tin thin film (ITO) and the wiring on the FPC (flexible substrate) 928 are connected via an ACF (AnisotroPic Conductive Film), and aluminum neodymium Conduction with the in-panel wiring 303 connected to the alloy (AlNd).

  FIG. 10 is a partial cross-sectional view of the fourth flying capacitor 501-4 and the first bypass capacitor 502-1 at the line DD ′ in FIG. The fourth flying capacitor 501-4 is composed of a lower layer wiring 501 </ b> A composed of the same film as the molybdenum thin film (Mo) constituting the scanning line 201 and the capacitance line 203, and an aluminum-neodymium alloy thin film (AlNd) constituting the data line 202. And a capacitor insulating film 501C formed of the same film as the interlayer insulating film between them, and a capacitor is interposed between the lower layer wiring 501A and the upper layer wiring 501B. Constitute.

  The first bypass capacitor 502-1 is an n + silicon thin film made of the same film as the silicon island 602 constituting the pixel switching element 401-nm, and having a specific resistance of 1 kΩ by phosphorous being doped at a high concentration. Upper layer wiring 502B composed of the same film as the molybdenum thin film (Mo) constituting the lower layer wiring 502A, the scanning line 201 and the capacitance line 203, and the capacitive insulating film 502C composed of the same film as the gate insulating film therebetween. It is composed of The upper layer wiring 502B has a plurality of removal units 510A constituting the panel number mark unit 510, and the removal unit 510A is two-dimensionally arranged to form a two-dimensional code. Yes. Information including a production number is stored in the two-dimensional code portion of the panel number mark portion 510, and the production information of the corresponding production number is stored. As a result, the panel number mark portion 510 can be read with an optical reader and any corresponding manufacturing information can be easily searched when a problem occurs after inspection before shipment or after shipment, resulting in a higher quality control level and higher yield. It becomes easy to raise.

  Since the two-dimensional code needs to be optically read and decoded by image recognition, the panel number mark portion 510 needs an area of several mm square. In this embodiment, since the panel number mark portion 510 and the bypass capacitor 502 are arranged on the same plane, a necessary capacitor is built in the power supply circuit 304 while preventing the area of the overhang portion 927 from increasing. The cost is low and the device can be miniaturized.

  In this embodiment, the flying capacitor 501 and the bypass capacitor 502 are formed on the substrate using the same conductive film and insulating film as the pixel display region 310 shown in FIGS. Capacitor parts can be reduced and the assembly can be simplified, and the external circuit board can be reduced. As a whole, a reduction in size, weight, and cost can be realized.

  Further, in this embodiment, the flying capacitor 501 is formed of a molybdenum thin film (Mo) and an aluminum neodymium alloy thin film (AlNd), while the bypass capacitor 502 is formed of a molybdenum thin film (Mo) and polysilicon (Poly-Si). is doing. Since the flying capacitor 501 is driven by a pumping pulse signal, the flying capacitor 501 needs to have a sufficiently flat frequency characteristic in a frequency range to be used. When polysilicon having a high specific resistance of several hundred Ω to several kΩ is used, the frequency characteristics rapidly deteriorate at about several hundreds k to several MHz. Therefore, the flying capacitor 501 is formed by laminating metal wirings. On the other hand, the bypass capacitor 502 is not strictly required for frequency characteristics, but requires a larger capacity than the flying capacitor 501 in order to stabilize the output waveform.

  The capacitive insulating film 502C constituting the bypass capacitor 502 is the same film as the gate insulating film 606, and its thickness is extremely thin, approximately 100 nm or less. On the other hand, the capacitive insulating film constituting the flying capacitor 501 (the same film as the interlayer insulating film) ) Is as thick as approximately 700 nm (stacked with a 200 nm silicon nitride film and a 500 nm silicon oxide film). In this way, by using the same film as the thin gate insulating film for the capacitor insulating film 502C constituting the bypass capacitor 502, the distance between both electrodes (upper layer wiring 502B and lower layer wiring 502A) constituting the bypass capacitor 502 is reduced. The capacity can be increased. In this embodiment, the capacity per area of the bypass capacitor 502 is about 6 times the capacity per area of the flying capacitor 501, and the capacity can be increased without increasing the area. In this way, the film type constituting the capacitor is changed in accordance with the required difference in characteristics between the flying capacitor 501 and the bypass capacitor 502.

  Here, the panel number mark portion 510 is formed by providing the removal portion 510A in the upper layer wiring 502B constituting the bypass capacitor 502. However, the removal portion 510A may be provided in the lower layer wiring 502A, or another metal film, For example, a thin film identical to the aluminum-neodymium alloy (AlNd) constituting the data line 202 may be formed in an upper layer of the upper wiring 502B, and the removal portion 510A may be provided in this film. In this case, the capacitance can be further increased by connecting the same thin film as the aluminum-neodymium alloy (AlNd) and the lower layer wiring 502A to each other through a contact hole.

  Further, in this embodiment, all the capacitances required for the power supply circuit 304 are formed in the overhanging portion 927. However, some of them may be configured on the active matrix substrate 101 other than the overhanging portion 927, or external components. May be implemented as

  FIG. 11 is a circuit diagram of the power supply circuit 304. The pumping pulse signal PCLK supplied from the signal circuit 305 is input to the first inverter circuit 521A, the second inverter circuit 522A, the fourth inverter circuit 521B, and the fifth inverter circuit 522B, respectively. The output of the second inverter circuit 522A is connected to the third inverter circuit 523A, and the output of the fifth inverter circuit 522B is connected to the sixth inverter circuit 523B. The output of the first inverter circuit 521A is connected to one end of the first flying capacitor 501-1. Similarly, the outputs of the third inverter circuit 523A, the fourth inverter circuit 521B, and the sixth inverter circuit 523B are respectively the second flying capacitor. 501-2, the third flying capacitor 501-3, and the fourth flying capacitor 501-4 are respectively connected to one end. The power supply of the first inverter circuit 521A, the second inverter circuit 522A, the third inverter circuit 523A, the fourth inverter circuit 521B, the fifth inverter circuit 522B, and the sixth inverter circuit 523B is connected to the first mounting terminal 320-1 on the Low side. The GND potential (± 0V) is supplied through the FPC (flexible substrate) 928, and the High side is connected to the second mounting terminal 320-2 and the + 5V potential is supplied through the FPC (flexible substrate) 928. The

  The node 1A at the other end of the first flying capacitor 501-1 has a drain electrode of the first p-type switching transistor 531A, a drain electrode of the first n-type switching transistor TFT 533A, a gate electrode of the second p-type switching transistor 532A, and a second n-type switching transistor. Each is connected to the gate electrode of the TFT 534A. The node 2A at the other end of the second flying capacitor 501-2 includes the drain electrode of the second p-type switching transistor 532A, the drain electrode of the second n-type switching transistor TFT 534A, the gate electrode of the first p-type switching transistor 531A, and the first n-type switching transistor. Each is connected to the gate electrode of the TFT 533A. The node 1B at the other end of the third flying capacitor 501-3 includes the drain electrode of the third n-type switching transistor 531B, the drain electrode of the third p-type switching transistor TFT 533B, the gate electrode of the fourth n-type switching transistor 532B, and the fourth p-type switching transistor. Each is connected to the gate electrode of the TFT 534B. The node 2B at the other end of the fourth flying capacitor 501-4 includes the drain electrode of the fourth n-type switching transistor 532B, the drain electrode of the fourth p-type switching transistor TFT 534B, the gate electrode of the third n-type switching transistor 531B, and the third p-type switching transistor. Each is connected to the gate electrode of the TFT 533B. The source electrodes of the first p-type switching transistor 531A and the second p-type switching transistor 532A are connected to the first mounting terminal 320-1, and are supplied with a GND potential (± 0 V) through an FPC (flexible substrate) 928. The source electrodes of the third n-type switching transistor 531B and the fourth n-type switching transistor 532B are connected to the second mounting terminal 320-2 and supplied with a + 5V potential through an FPC (flexible substrate) 928. The source electrodes of the first n-type switching transistor TFT 533A and the second n-type switching transistor TFT 534A are connected to one end of the first bypass capacitor 502-1 (referred to as node 3A), and further connected to the scanning line driving circuit 301 to be -4V power supply. Supply. The source electrodes of the third p-type switching transistor TFT 533B and the fourth p-type switching transistor TFT 534B are connected to one end of the second bypass capacitor 502-2 (referred to as a node 3B), and further, the scanning line driving circuit 301, the data line driving circuit 302, Connected to the signal circuit 305 and the common potential power supply circuit 306, + 9V power is supplied to each circuit.

  With this configuration, when the pumping pulse signal PCLK is High (5 V), the outputs from the first inverter circuit 521A and the fourth inverter circuit 521B are Low (0 V), and the third inverter circuit 523A and the sixth inverter The output from the circuit 523B is High (5V), the potential of the node 1A is −5 + ΔV1A, the potential of the node 2A is 0 + ΔV2A, the potential of the node 1B is 5-ΔV1B, the potential of the node 2B is 10−ΔV2B, and the first p Type switching transistor 531A, second n-type switching transistor TFT 534A, fourth n-type switching transistor 532B and third p-type switching transistor TFT 533B are turned OFF, and second p-type switching transistor 532A and first n-type switching transistor are turned off. TFT533A a first 3n-type switching transistor 531B and the 4p-type switching transistor TFT534B is turned ON. Here, the potential −5 + ΔV1A + ΔV1 is supplied from the node 1A to the node 3A, and the potential 10−ΔV2B−ΔV2 is supplied from the node 2B to the node 3B.

  When the pumping pulse signal PCLK becomes Low (5V), the outputs from the first inverter circuit 521A and the fourth inverter circuit 521B are High (5V), and the outputs from the third inverter circuit 523A and the sixth inverter circuit 523B are Low (0V). ), The potential of the node 1A is 0 + ΔV1A ′, the potential of the node 2A is −5 + ΔV2A ′, the potential of the node 1B is 10−ΔV1B ′, the potential of the node 2B is 5-ΔV2B ′, and the first p-type switching transistor 531A The second n-type switching transistor TFT 534A, the fourth n-type switching transistor 532B, and the third p-type switching transistor TFT 533B are turned ON, and the second p-type switching transistor 532A, the first n-type switching transistor TFT 533A, and the third n-type switching transistor are turned on. Tsu quenching transistor 531B and the 4p-type switching transistor TFT534B is turned OFF. Here, the potential −5 + ΔV2A + ΔV1 ′ is supplied from the node 2A to the node 3A, and the potential 10−ΔV1B−ΔV2 ′ is supplied from the node 1B to the node 3B.

  Here, ΔV1A, ΔV1B, ΔV2A, ΔV2B, ΔV1A ′, ΔV1B ′, ΔV2A ′, ΔV2B ′, ΔV1, ΔV2, ΔV1 ′, ΔV2 ′ are the first flying capacitor 501-1 to the fourth flying capacitor 501-4 and The capacity of the first bypass capacitor 502-1 and the second bypass capacitor 502-2 is sufficiently large, the pumping pulse signal PCLK is sufficiently fast, and the phase shift between the node 1A and the node 2A and between the node 1B and the node 2B can be ignored. In this case, the voltage drop is caused by the channel resistance, mounting resistance, wiring resistance, etc. of each switching transistor and the transistors constituting the inverter circuit, and in this embodiment, all are designed to be the same 0.5V. That is, regardless of whether the pumping pulse signal PCLK is High or Low, -4V is supplied to the node 3A and + 9V is supplied to the node 3B, thereby functioning as a DCDC converter.

  Each of the switching transistors and the transistors constituting the inverter circuit described in FIG. 11 is a thin film transistor using polysilicon, which is composed of the same film as the pixel switching element 401-nm and is manufactured in the same manufacturing process. . However, with respect to the p-type transistor, the ion species doped in the polysilicon is different.

  The configuration of the DCDC converter is not limited to the configuration of this embodiment, and may be combined with any known configuration of the DCDC converter. Even when an inductor type is used instead of a charge pump type as a DCDC converter, when a bypass capacitor is used, the bypass capacitor is disposed on the overhanging portion 927 as in the present embodiment, and a mark such as a panel number mark portion 510 is provided. The same effect can be obtained by superimposing and.

  In the present embodiment, the first bypass capacitor 502-1 is overlapped with the panel number mark portion 510. However, a plurality of first bypass capacitors 502-1, a second bypass capacitor 502-2, and a plurality of first flying components are used. One or a plurality of arbitrary capacitors among the capacitors 501-1 to 501-4 may be overlapped with the panel number mark portion 510. What is necessary is just to determine according to the size of the panel number mark part 510, and the required capacity | capacitance of each capacitor | condenser. Furthermore, not only the panel number mark portion 510 but also all kinds of marks arranged on the projecting portion 927 and each capacitor may be overlapped. For example, an FPC mounting alignment mark, a scribing / breaking alignment mark, an appearance inspection alignment mark, and the like. FIG. 12 shows such an embodiment. FIG. 12 is an enlarged plan view of the right end portion of the overhang portion 927 on the active matrix substrate 101 instead of FIG. 8 differs from FIG. 8 in that not only the first bypass capacitor 502-1 but also the second bypass capacitor 502-2 overlaps the panel number mark portion 510 ′, and the area of the panel number mark portion 510 ′ increases. Therefore, the amount of information of the two-dimensional code is further increased, and more precise quality control is possible. Further, the lower layer wiring 501A forming the first flying capacitor 501-1 has a cross shape, and is used for alignment when an FPC (flexible substrate) 928 is attached to the signal input terminals (mounting terminal group) 320. The alignment mark 511 is also used, and the area of the overhang portion 927 can be further reduced. In this embodiment, the shield wiring 520 ′ is short-circuited to the first mounting terminal 320-1, and is given a GND potential. With this configuration, the shielding capability is remarkably enhanced as compared with the configuration of the shield wiring 520 in FIG. 8, but capacitance division is performed when the first flying capacitor 501-1 to the fourth flying capacitor 501-4 are driven. A potential amplitude drop occurs due to. Which one should be selected can be determined after considering the advantages and disadvantages of each process and design. Since other parts in FIG. 12 are the same as those in FIG. 8, the description is omitted by giving the same symbols.

  FIG. 13 is a block diagram of the active matrix substrate 101B according to the present embodiment, which corresponds to FIG. 2 in the first embodiment (embodiment 1). Hereinafter, the difference from FIG. 2 will be mainly described. In FIG. 13, a third bypass capacitor 502B-1 and a fourth bypass capacitor 502B-2 are arranged instead of the first bypass capacitor 502-1 and the second bypass capacitor 502-2 in FIG. The fourth bypass capacitor 502B-2 is one of the signal input terminals (mounting terminal group) 320 and a third mounting terminal 320B-1 (corresponding to the first mounting terminal 320-1 in FIG. 2) located at the right end. It overlaps in a plane. The third bypass capacitor 502B-1 is one of the signal input terminals (mounting terminal group) 320, and is a fourth mounting terminal 320B-2 (shown in FIG. 2) located on the left side of the third mounting terminal 320B-1. And the second mounting terminal 320-2).

  Also, a fifth flying capacitor 501B-1 to an eighth flying capacitor 501B-4 are arranged instead of the first flying capacitor 501-1 to the fourth flying capacitor 501-4 in FIG. The eighth flying capacitor 501B-4 overlaps the fifth mounting terminal 320B-3 on the left side of the fourth mounting terminal 320B-2 in plan view. The seventh flying capacitor 501B-3 overlaps the sixth mounting terminal 320B-4 on the left side of the fifth mounting terminal 320B-3 in plan view. The sixth flying capacitor 501B-2 overlaps the seventh mounting terminal 320B-5 on the left side of the sixth mounting terminal 320B-4 in a plan view. Further, the fifth flying capacitor 501B-1 overlaps the eighth mounting terminal 320B-6 on the left side of the seventh mounting terminal 320B-5 in plan view. Note that the sixth flying capacitor 501B-2, the seventh flying capacitor 501B-3, the sixth mounting terminal 320B-4, and the seventh mounting terminal 320B-5 are shown in FIG. 13 in consideration of the visibility of the drawing. Are omitted, the sixth flying capacitor 501B-2 and the seventh flying capacitor 501B-3 are the same as the fifth flying capacitor 501B-1 and the eighth flying capacitor 501B-4, and the sixth mounting terminal 320B. -4 and the seventh mounting terminal 320B-5 are the same as the fifth mounting terminal 320B-3 and the eighth mounting terminal 320B-6, respectively.

  The third mounting terminal 320B-1 to the eighth mounting terminal 320B-6 are part of the right end of the signal input terminal (mounting terminal group) 320B, and are connected to an FPC (flexible substrate) 928 from the outside. Appropriate potential or signal is input. Specifically, the third mounting terminal 320B-1 has a GND potential (0V), the fourth mounting terminal 320B-2 has a + 5V potential, and the fifth mounting terminal 320B-3 has a pumping pulse signal PCLK1. The sixth mounting terminal 320B-4 receives the pumping pulse signal XPCLK1, the seventh mounting terminal 320B-5 receives the pumping pulse signal PCLK2, and the eighth mounting terminal 320B-6 receives the pumping pulse signal XPCLK2. The Here, the pumping pulse signal PCLK1 is a 50% duty rectangular wave of 30 KHz, the pumping pulse signal PCLK2 is a signal having the same waveform as the pumping pulse signal PCLK1, and the pumping pulse signal XPCLK1 is a reverse phase signal of the pumping pulse signal PCLK1. The pumping pulse signal XPCLK2 is a reverse phase signal of the pumping pulse signal PCLK2, and the potential amplitude of these signals is 0 to 5V.

  Except for what has been described, FIG. 13 is not different from FIG. Further, the pixel circuit diagram is the same as FIG. 3 of the first embodiment, the plan view of the pixel portion is FIG. 5 of the first embodiment, and the cross-sectional view of the pixel portion is no different from FIGS. 6 and 7 of the first embodiment. Therefore, the description thereof is also omitted.

  FIG. 14 is an enlarged plan view of the right end portion of the overhanging portion 927 on the active matrix substrate 101B, corresponding to FIG. 8 in the first embodiment, and the legend also follows FIG. Hereinafter, the difference from FIG. 8 will be mainly described.

  In this configuration, the eighth flying capacitor 501B-4 is the fifth mounting terminal 320B-3, the seventh flying capacitor 501B-3 is the sixth mounting terminal 320B-4, and the sixth flying capacitor 501B-2 is The seventh mounting terminal 320B-5 and the fifth flying capacitor 501B-1 overlap with the eighth mounting terminal 320B-6 in a plane. More specifically, the fifth mounting terminal 320B-3 to the eighth mounting terminal 320B-6 are composed of wiring layers of aluminum / neodymium alloy (AlNd) and indium / tin alloy (ITO), and the lower layer (more active matrix). The fifth flying capacitor 501B-1 to eighth flying capacitor 501B-4 are composed of a molybdenum thin film (Mo) near the substrate 101B. In FIG. 14, the sixth flying capacitor 501B-2, the seventh flying capacitor 501B-3, the sixth mounting terminal 320B-4, and the seventh mounting terminal are considered in the same manner as in FIG. 320B-5 is omitted.

  The fourth bypass capacitor 502B-2 is configured to overlap with the third mounting terminal 320B-1, and the third bypass capacitor 502B-1 is configured to overlap with the fourth mounting terminal 320B-2. More specifically, the third mounting terminal 320B-1 and the fourth mounting terminal 320B-2 are composed of a wiring layer of aluminum / neodymium alloy (AlNd) and indium oxide / tin thin film, and the lower layer (more active matrix substrate). The third bypass capacitor 502B-1 and the fourth bypass capacitor 502B-2 are composed of polysilicon and a molybdenum thin film (Mo) close to 101B. An alignment mark 511B for alignment and a panel number mark portion 510B are formed on the right side of the signal input terminal (mounting terminal group) 320. In this embodiment, there is no wiring corresponding to the shield wiring 520 in the first embodiment. Further, an alignment mark 511B for alignment and a panel number mark portion 510B are arranged on the right side of the third mounting terminal 320B-1.

  FIG. 15 is a partial cross-sectional view taken along the line EE ′ of FIG. Indium oxide and tin thin film (ITO), which is the same film as the pixel electrode 402-nm, and aluminum / neodymium alloy (AlNd), which is the same film as the data line 202, are laminated to form a fifth layer. The mounting terminal 320B-3 is formed. The aluminum-neodymium alloy (AlNd) constituting the fifth mounting terminal 320B-3 also serves as the upper layer wiring 501BB of the eighth flying capacitor 501B-4, and is formed of the same film as the interlayer insulating film. An eighth flying capacitor 501B-4 is formed between the lower layer wiring 501BA disposed across the insulating film 501BC. The lower layer wiring 501BA is made of a molybdenum thin film (Mo) which is the same film as the film constituting the scanning line 201 and the capacitor line 203.

  FIG. 16 is a partial cross-sectional view taken along the line FF ′ of FIG. A third layer is formed by laminating an indium oxide and tin thin film (ITO) that is the same film as the pixel electrode 402-nm, and an aluminum and neodymium alloy (AlNd) that is the same film as the data line 202. Mounting terminal 320B-1 is formed, and a fourth bypass capacitor 502B-2 is formed so as to overlap with the mounting terminal 320B-1. The fourth bypass capacitor 502B-2 includes an upper layer wiring 502BB made of a molybdenum thin film (Mo) which is the same film as the film forming the scanning line 201 and the capacitor line 203, and a silicon island forming the pixel switching element 401-nm. A capacitive insulating film 502BC composed of the same film as the gate insulating film and the lower layer wiring 502BA composed of an n + polysilicon thin film composed of the same film as 602 and controlled to a specific resistance of about 1 kΩ by dosing phosphorus. Consists of.

  The perspective configuration diagram of the transmissive liquid crystal display device according to the present embodiment is FIG. 1 in the first embodiment, and the block diagram showing the specific configuration of the electronic device in the second embodiment is the first embodiment. 4 is the same as FIG. 4 except that the active matrix substrate 101B is replaced with the active matrix substrate 101B, and a description thereof will be omitted.

  FIG. 17 is a circuit diagram of the power supply circuit 304B. In this embodiment, the pumping pulse signals PCLK1, XPCLK1, PCLK2, and XPCLK2 are input from the outside through the fifth mounting terminal 320B-3 to the eighth mounting terminal 320B-6. The 1 inverter circuit 521A, the second inverter circuit 522A, the third inverter circuit 523A, the fourth inverter circuit 521B, the fifth inverter circuit 522B, and the sixth inverter circuit 523B are not necessary. Except this point, the first bypass capacitor 502-1 and the second bypass capacitor 502-2 are replaced with the third bypass capacitor 502B-1 and the fourth bypass capacitor 502B-2, and the first flying capacitor 501-1. To the fourth flying capacitor 501-4 to the fifth flying capacitor 501B-1 to the eighth flying capacitor 501B-4, and the first mounting terminal 320-1 and the second mounting terminal 320-2 to the third. Except for replacing the mounting terminal 320B-1 and the fourth mounting terminal 320B-2, respectively, there is no difference from FIG. 11 in the first embodiment.

  Thus, in this embodiment, a part of the signal input terminal (mounting terminal group) 320B, the third bypass capacitor 502B-1, the fourth bypass capacitor 502B-2, and the fifth flying capacitor 501B-1 to eighth Since the capacitor necessary for the power supply circuit 304 is built in while preventing the increase in the area of the overhanging portion 927 by configuring the flying capacitors 501B-4 in an overlapping manner, the cost can be reduced and the apparatus can be downsized. Also, since the flying capacitor is overlapped with the mounting terminal part of the pumping pulse signal and the bypass capacitor is overlapped with the mounting terminal part of the power supply potential, the wiring path length is 0 or minimum, and the resistance / capacitance of the wiring is small. In addition, there is a merit that the efficiency of the power supply circuit is increased.

  Further, the film type constituting the capacitor is changed according to the required difference in characteristics between the flying capacitor 501 and the bypass capacitor 502, which is the same as the first embodiment.

  In the present embodiment, the bypass capacitor is disposed under the terminal portion of the power supply. However, it may be disposed under the terminal portion other than the power supply such as a drive signal. However, when a capacitor is arranged under a terminal portion of a signal line that is not at a constant potential, noise must be generated in the capacitor when the signal changes, so that it is necessary to design with care in this regard. Conversely, the flying capacitor may be arranged under the power supply or other signal terminal instead of the pumping pulse signal. However, such a configuration also causes problems such as noise on the flying capacitor and low drive amplitude. Therefore, it is necessary to design with attention to this.

  Further, in combination with the first embodiment, some bypass capacitors and flying capacitors may be arranged on mark portions such as alignment mark 511B for alignment and panel number mark portion 510B.

  Furthermore, in this embodiment, only the FPC (flexible substrate) is mounted on the overhanging portion, but if it is a so-called COG (Chip On Glass) display device in which a driving IC or the like is mounted on the overhanging portion, driving is possible. What is necessary is just to comprise the signal input terminal (mounting terminal group) used for mounting with IC, a bypass capacitor, and a flying capacitor.

  The present invention is not limited to the embodiments, and is used for liquid crystal display devices such as a vertical alignment mode (VA mode) instead of the TN mode, an IPS mode using a lateral electric field, and an FFS mode using a fringe electric field. It doesn't matter. Moreover, not only a total transmission type but also a total reflection type and a reflection / transmission combined type may be used.

  Moreover, you may use for an organic electroluminescent display and a field emission type display instead of a liquid crystal display device.

The perspective view of the liquid crystal display device 910 which concerns on the Example of this invention. 1 is a configuration diagram of an active matrix substrate 101 according to a first embodiment of the present invention. 1 is a pixel circuit diagram of an active matrix substrate 101 according to an embodiment of the present invention. 1 is a block diagram illustrating an embodiment of an electronic device of the present invention. The top view of the pixel part of the pixel display area 310 which concerns on the Example of this invention. FIG. 5A is a partial cross-sectional view along AA ′. FIG. 5B is a partial cross-sectional view taken along the line BB ′. The top view of the overhang | projection part 927 which concerns on the 1st Example of this invention. FIG. 9 is a partial cross-sectional view taken along the line CC ′. FIG. 8D is a partial cross-sectional view taken along the line DD ′. 1 is a circuit diagram of a power supply circuit 304 according to a first embodiment of the present invention. The top view of the overhang | projection part 927 which concerns on another embodiment of the 1st Example of this invention. The block block diagram of the active matrix substrate 101B which concerns on the 2nd Example of this invention. The top view of the overhang | projection part 927 which concerns on the 2nd Example of this invention. FIG. 14E is a partial cross-sectional view taken along the line EE ′. FIG. 14 is a partial cross-sectional view taken along line F-F ′. The circuit diagram of the power supply circuit 304B which concerns on the 2nd Example of this invention.

Explanation of symbols

  1A, 1B, 2A, 2B, 3A, 3B ... nodes, 101, 101B ... active matrix substrates, 201, 201-1 to 201-480, 201-n ... scanning lines, 202, 202-1 to 202-1920, 202 -M ... data line, 203, 203-1 to 203-480, 203-n ... capacitance line, 301 ... scanning line drive circuit, 302 ... data line drive circuit, 303 ... in-panel wiring, 304, 304B ... power supply circuit, 305 ... Signal circuit, 306 ... Common potential power supply circuit, 310 ... Pixel display area, 320, 320B ... Signal input terminal (mounting terminal group), 320-1 ... First mounting terminal, 320-2 ... Second mounting terminal , 320B-1 ... third mounting terminal, 320B-2 ... fourth mounting terminal, 320B-3 ... fifth mounting terminal, 320B-4 ... sixth mounting terminal, 320B-5 ... seventh Mounting terminal, 320B-6 ... eighth mounting terminal, 330 ... opposing conductive part, 401-nm, pixel switching element, 402-nm, pixel electrode, 403-nm, auxiliary capacitor, 501 ... Flying capacitor, 501-1 ... first flying capacitor, 501-2 ... second flying capacitor, 501-3 ... third flying capacitor, 501-4 ... fourth flying capacitor, 501A, 501BA, 502A, 502BA ... lower layer wiring, 501B, 501BB, 502B, 502BB ... upper layer wiring, 501B-1 ... fifth flying capacitor, 501B-2 ... sixth flying capacitor, 501B-3 ... seventh flying capacitor, 501B-4 ... first 8 flying capacitors, 501BC, 501C, 502BC, 50 C: Capacitance insulating film, 502 ... Bypass capacitor, 502-1 ... First bypass capacitor, 502-2 ... Second bypass capacitor, 502B-1 ... Third bypass capacitor, 502B-2 ... Fourth bypass capacitor , 510 ', 510, 510B ... panel number mark portion, 510A ... removal portion, 511, 511B ... alignment mark for alignment, 520', 520 ... shield wiring, 521A ... first inverter circuit, 521B ... fourth inverter circuit, 522A ... 2nd inverter circuit, 522B ... 5th inverter circuit, 523A ... 3rd inverter circuit, 523B ... 6th inverter circuit, 531A ... 1st p-type switching transistor, 531B ... 3n-type switching transistor, 532A ... 2nd p-type switching Transis 532B: Fourth n-type switching transistor, 533A: First n-type switching transistor TFT, 533B: Third p-type switching transistor TFT, 534A: Second n-type switching transistor TFT, 534B: Fourth p-type switching transistor TFT, 601: Base insulating film 602 ... Silicon island, 602I ... Intrinsic semiconductor region, 602L ... n- region, 602N ... n + region, 603 ... Source electrode, 604 ... Drain electrode, 605 ... Capacitor electrode, 606 ... Gate insulating film, 761, 781 ... Center Arithmetic circuit, 780 ... Video processing circuit, 782 ... External I / F circuit, 783 ... Input / output device, 784 ... External power supply circuit, 910 ... Liquid crystal display device, 911 ... Display panel, 912 ... Counter substrate, 922 ... Liquid crystal material, 923 ... Sealing material, 924 Upper polarizing plate, 925 ... Lower polarizing plate, 926 ... Backlight unit, 927 ... Overhang, 928 ... FPC (flexible substrate), 929 ... Connector, 930 ... Counter electrode as common (COM) electrode, D0 to D17 ... Video signal, PCLK, PCLK1, PCLK2, XPCLK1, XPCLK2 ... Pumping pulse signal.

Claims (10)

A display panel comprising a first substrate for display and a second substrate for display disposed opposite to the first substrate for display;
A power supply circuit disposed on the display panel and generating a predetermined power supply potential from a power supply potential input from outside the panel;
A display device comprising a capacitor connected to the power supply circuit,
The first display substrate has an overhanging portion protruding from a portion where the second display substrate is opposed to the display substrate,
The display device, wherein the capacitor connected to the power supply circuit is formed in the projecting portion. A display comprising: a first display substrate; a second display substrate disposed opposite to the first display substrate; and a liquid crystal sandwiched between the first display substrate and the second display substrate. A panel,
A power supply circuit disposed on the display panel and generating a predetermined power supply potential from a power supply potential input from the outside;
A display device comprising a capacitor connected to the power supply circuit,
The first substrate for display has a protruding portion protruding from a portion where the liquid crystal is sandwiched,
The display device, wherein the capacitor connected to the power supply circuit is formed in the projecting portion. The overhanging portion includes a mounting terminal for mounting an IC or a flexible substrate,
The display device according to claim 1, wherein the capacitor is formed in a region overlapping with the mounting terminal. The overhang part is provided with a panel number mark for individual identification,
The display device according to claim 1, wherein the capacitor is formed in a region overlapping with the panel number mark. The overhang portion includes an alignment mark for optical alignment,
The display device according to claim 1, wherein the capacitor is formed in a region overlapping with the alignment mark.   The display device according to claim 5, wherein the alignment mark is an alignment mark when an IC or a flexible substrate is mounted on the projecting portion.   The display device according to claim 1, wherein the capacitor is covered with a transparent electrode. A first display substrate in which circuits such as thin film transistors are laminated on a substrate by a low-temperature polysilicon thin film formation technique, and a display panel comprising a second display substrate disposed to face the first display substrate;
A power supply circuit comprising a charge pump circuit which is disposed on the first substrate for display and generates a predetermined power supply potential from a power supply potential input from the outside by pumping a flying capacitor whose potential at both ends periodically fluctuates; ,
A bypass capacitor connected to the output power supply potential from the power supply circuit and for stabilizing the output power supply potential;
A display device comprising: a protruding portion of the first display substrate that protrudes from a portion where the first display substrate and the second display substrate are arranged to face each other;
The flying capacitor and the bypass capacitor are stacked on the first substrate for display by the low-temperature polysilicon thin film forming technique, and the flying capacitor and the bypass capacitor have different layers as a conductive film and / or an insulating film. A display device characterized by that.   9. The display device according to claim 8, wherein only at least one of the conductive films constituting the bypass capacitor is a polysilicon film.   An electronic apparatus comprising the display device according to any one of claims 1 to 9.

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