JP2008166549A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device which can make two different conductive type impurity regions of high concentration appear in a contact hole, even if the number of masks is reduced by the utilization of an interlayer insulation film as a channel contact mask. <P>SOLUTION: The method for manufacturing a semiconductor device (1) which is manufactured by adding a second conductive type impurities (204) in a layer (20) having a first conductive type impurity region (202) has a process to form an interlayer insulation film (40) on the layer (20), a process to form a penetrated portion (CH1)in the interlayer insulation film (40), a process to inject the second conductive type impurities (204) into the layer (20) through the penetrated portion (CH1) of the interlayer insulation film, and a process to form a contact hole (CH2) by expanding the penetrated portion (CH1) of the interlayer insulation film. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a contact hole of an insulated gate semiconductor device such as a MOSFET or an IGBT (Insulated Gate Bipolar Transistor).

  An insulated gate semiconductor device such as a MOSFET having a trench gate structure or an IGBT (Insulated Gate Bipolar Transistor) has an n + type impurity region and a p + type impurity region at the position of a contact hole where a source electrode is formed on the surface of a channel layer. ing.

  The n + -type impurity region and the p + -type impurity region are mainly impurities (n-type impurity or p-type impurity) ionized inside the channel layer by covering the surface of the channel layer of the semiconductor device with a resist mask and ion implantation. Injected and thermally diffused.

  The procedure for forming the n + type impurity region and the p + type impurity region and the procedure for forming the contact hole are as follows. That is, a resist mask is formed on the channel layer by photolithography, and an n-type impurity is implanted into the surface of the channel layer to form an n + type impurity region. Thereafter, a resist mask (referred to as a “channel contact mask”) is formed on the channel layer by photolithography, and p-type impurity regions are formed by implanting p-type impurities on the surface of the channel layer. After that, an interlayer insulating film is provided on the channel layer, and a resist mask (on the interlayer insulating film is formed by photolithography so that a part of the n + type impurity region and the p + type impurity region formed in the channel layer appear. A contact hole is formed in the interlayer insulating film by etching.

As described above, generally, a mask for forming contact holes in an interlayer insulating film and a mask for injecting impurities are used differently.
On the other hand, recently, there are attempts to reduce the number of masks used for manufacturing semiconductor devices. For example, there is one that omits the manufacture of a channel contact mask by photolithography. That is, an interlayer insulating film is provided on the channel layer provided with the n + -type impurity region, and the interlayer insulating film is etched through a photolithography process so that the contact hole has a target shape (final shape). Then, a p-type impurity is implanted into the channel layer using the interlayer insulating film as a channel contact mask instead of the resist mask. (For example, patent document 1 etc.).
JP 2006-228906 A (paragraphs “0031”-“0059”, etc.) JP 2006-49401 A

  As described above, an insulated gate semiconductor device such as a MOSFET or an IGBT (Insulated Gate Bipolar Transistor) has a structure in which an n + -type impurity region and a p + -type impurity region appear at the position of a contact hole.

However, the p + -type impurity region is thermally diffused in the process after the p-type impurity is implanted, and enters the n + -type impurity region.
Although there is an attempt to reduce the number of masks used for manufacturing a semiconductor device, when the number of masks is reduced by using the above-described interlayer insulating film as a channel contact mask, the contact is caused by the p-type impurity entering the n + -type impurity region. A high concentration n + type impurity region in the hole is eliminated. This is a problem because it directly leads to a decrease in contact between the source electrode formed in the contact hole and the n + type impurity region.

  In Patent Document 1, p-type impurity implantation from the contact hole into the channel layer is performed so that the concentration peak is deeper than the n + -type impurity region, that is, the ions are accelerated at a higher voltage to increase the channel. I try to drive it into the layer. In this case, a p + type impurity region appears due to the diffusion of the p type impurity in the region having no n + type impurity region on the surface of the channel layer, and when the n + type impurity region is present, the diffused p type impurity is the n + type impurity region. A p + type impurity region is formed at a deep position and does not reach the surface of the channel layer.

  The present invention has been made in view of the above problems, and allows two impurity regions of different conductivity types to appear in contact holes even when the number of masks is reduced by using an interlayer insulating film as a channel contact mask. An object of the present invention is to provide a method for manufacturing a semiconductor device capable of performing

In order to solve the above problems, the present invention is configured as follows.
One aspect of a method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device in which a second conductivity type impurity is added to a layer having a first conductivity type impurity region. Forming an interlayer insulating film; forming a through-hole in the interlayer insulating film; injecting the second conductivity type impurity into the layer through the through-hole in the interlayer insulating film; and Forming a contact hole by expanding the penetrating portion.

  In the step of forming a through portion in the interlayer insulating film, the shape of the interlayer insulating film after the formation of the through portion is narrowed by the entry of the diffusion region of the second conductivity type impurity formed in the layer. In the step of forming the through hole and forming the contact hole so as to have a shape similar to the final shape of the interlayer insulating film such that the first conductivity type impurity region later appears at the position of the contact hole Preferably, the interlayer insulating film is formed into the final shape by isotropic etching to widen the through portion and form a contact hole.

The semiconductor device is preferably an insulated gate semiconductor device having a trench gate structure.
Another aspect of the method for manufacturing a semiconductor device of the present invention is a gate manufactured by adding a second conductivity type impurity in a channel layer having a first conductivity type impurity region adjacent to a gate electrode of a trench structure. A method for manufacturing an insulating semiconductor device, the method comprising: forming an interlayer insulating film on the channel layer; and after the diffusion region of the second conductivity type impurity formed in the channel layer is narrowed Forming a through-hole in the interlayer insulating film so as to have a shape similar to the final shape of the interlayer insulating film such that the first conductivity type impurity region appears at the position of a contact hole; Injecting the second conductivity type impurity into the channel layer, and forming the interlayer insulating film into the final shape by isotropic etching.

  According to the present invention, even if the production of two types of masks, a contact mask and a channel contact mask, is reduced to one in the manufacturing process of a semiconductor device, it is possible to cause impurity regions of two conductivity types with different high concentrations to appear in contact holes. become.

Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to the drawings.
In the embodiment of the present invention, a method for manufacturing a semiconductor device, particularly a method for forming a contact hole will be described with reference to a structural diagram of a MOSFET having a trench gate structure.

  FIG. 1 is an explanatory diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIGS. 4A to 4F are cross-sectional views of the semiconductor device in each process until contact holes are formed. However, each drawing schematically shows a cross section of a main part of the semiconductor device according to the method for manufacturing a semiconductor device of the present invention, and other portions are omitted from the drawing.

  In the semiconductor device 1 of FIG. 1, a drain region 10 is formed on the lower side of the drawing. A channel layer 20 is formed on the drain region 10. Then, a gate electrode 30 having a trench structure that penetrates the channel layer 20 in the thickness direction (vertical direction in FIG. 1) and reaches the drain region 10 is formed. An n + type source region 202 is formed adjacent to the periphery of the gate electrode 30.

  Each of the above parts is formed by a manufacturing procedure as described in, for example, Japanese Patent Application Laid-Open No. 2006-228906 (for example, paragraphs “0040” to “0050”). That is, the drain region 10 is formed by laminating an n− type epitaxial layer 101 on an n + type silicon semiconductor substrate (not shown). The channel layer 20 (p-type channel layer) forms an oxide film (not shown) on the surface, and then etches the oxide film in the region where the channel layer 20 is formed, and uses the oxide film as a mask to cover the entire surface of the channel layer 20. A p-type impurity (for example, boron (B) or the like) is implanted into and diffused. The gate electrode 30 forms a trench 300 that penetrates the channel layer 20 and reaches the drain region 10, and the inner wall of the trench 300 is coated with a gate insulating film (oxide film) 301 and coated with the gate insulating film 301. The trench 300 is formed by filling polysilicon 302.

  The source region 202 is provided with a resist mask (not shown) in which a portion where the source region 202 is to be formed is opened, and a region on the channel layer 20 where the source region 202 is to be formed is opened through this mask. Then, n-type impurity arsenic (As) is ion-implanted and diffused from the opening to form a source region (first conductivity type impurity region) 202 which is an n + -type impurity region in the channel layer.

In the method of manufacturing a semiconductor device according to the embodiment of the present invention, an interlayer insulating film is first formed on the channel layer for the semiconductor device being manufactured as described above (step 1).
FIG. 1A is a cross-sectional view of a main part of a semiconductor device in which an interlayer insulating film 40 is formed on the channel layer 20.

The interlayer insulating film 40 is formed by depositing an insulating film such as BPSG (Boron Phosphorus Silicate Glass) and a multilayer film on the entire surface of the channel layer 20 by a CVD (Chemical Vapor Deposition) method.

Subsequently, a penetrating portion is formed in the interlayer insulating film (step 2).

FIG. 1B and FIG. 1C are cross-sectional views of the main part of the semiconductor device in the process of forming the through portion in the interlayer insulating film 40.
The through portion is formed by forming a resist mask 50 for forming a channel contact on the interlayer insulating film 40 through a photolithography process (resist application, exposure, development) or the like, and etching the interlayer insulating film 40 using the resist mask 50 as a mask. Is done.

  For example, a resist is applied to the entire surface of the interlayer insulating film 40 (a resist is applied up to the broken line in FIG. 1B), an area corresponding to a position where a channel contact is formed is exposed, and the exposure area is immersed in a developer. The resist is removed (leaving the shaded portion 500 in FIG. 1B).

  Then, the interlayer insulating film 40 is removed from the upper surface to the surface of the channel layer 20 (including the insulating film and the multilayer film) by anisotropic etching such as dry etching (for example, reactive ion etching), so that the through-hole CH1 is formed. It forms (FIG.1 (c)). The remaining interlayer insulating film 40 becomes the interlayer insulating film 400.

In this manner, a region for forming a channel contact in the surface of the channel layer 200 is opened.
Subsequently, a second conductivity type impurity is implanted into the channel layer 20 through the through portion CH1 of the interlayer insulating film 400 (step 3).

In Step 3, for example, a p-type impurity such as boron (B) is implanted into the channel layer 20 by ion implantation or the like to form a p + -type impurity region 204 (FIG. 1D).
The p + -type impurity region 204 is thermally diffused at a later arbitrary point by a process such as heat treatment.

  However, in this example, heat treatment or the like is performed at this point, and the p + -type impurity region 204 is thermally diffused and the p + -type impurity region enters the end of the source region 202 as indicated by the arrow in FIG. As a thing, the following process is demonstrated.

Subsequently, the through hole CH1 of the interlayer insulating film 400 is expanded to form a contact hole (final shape contact hole) CH2 (step 4).
Specifically, the side surface direction of the penetrating portion CH1 is widened (the side surface of the interlayer insulating film 500 is removed) so that the high concentration portion of the source region 202 appears in the opening region on the channel layer 20.

  As a method of expanding the penetration part CH1, for example, there is isotropic etching (FIG. 1 (f)). In this case, the shape of the penetrating portion CH1 is set in advance to be similar to the shape of the final contact hole. By doing so, for example, if the exposed portion of the interlayer insulating film 500 is exposed to an etching solution for a predetermined time, the interlayer insulating film 500 (including the insulating film and the multilayer film) is uniformly removed from the film surface, After a predetermined time after exposure to the etching solution, the interlayer insulating film 400 ′ is reduced in size, and the through hole CH1 becomes the shape of the final contact hole CH2.

  Note that after the contact hole CH2 is formed as described above, a source electrode is formed in the contact hole CH2 as in the prior art. For example, although not shown, a barrier metal layer made of a titanium-based material is formed as described in the specification of JP-A-2006-228906. Then, for example, an aluminum alloy is sputtered to a thickness of about 50000 mm on the entire surface. Thereafter, an alloying heat treatment is performed to stabilize the metal and silicon surfaces. The source electrode is patterned into a desired shape, and SiN or the like serving as a passivation film is provided.

As described above, a high concentration portion of the source region can appear from the contact hole CH2, and the contact property between the source electrode and the source region can be prevented from being deteriorated.
In the embodiment of the present invention, the semiconductor device manufacturing method of the present invention has been described by taking a MOSFET having a trench gate structure as an example.

  However, the semiconductor device manufacturing method of the present invention is not a method that can be applied only to the manufacture of a MOSFET having a trench gate structure, and may be applied to an insulated gate semiconductor device such as an IGBT (Insulated Gate Bipolar Transistor).

The method for manufacturing a semiconductor device of the present invention may be applied not only to a trench gate structure but also to a semiconductor device having a planar gate structure.
Even when applied to these semiconductor devices, certain effects can be obtained.

According to the embodiment of the present invention, it is possible to reduce the production of two types of masks, a contact mask and a channel contact mask, to one in a semiconductor device manufacturing process.
It is also possible to cause two conductivity type impurity regions having different concentrations to appear in a contact hole formed in the semiconductor device.

In addition, when the electrode is formed in the contact hole, the contact property between the electrode and each conductivity type impurity region is kept good.
Further, the width of the channel contact region can be freely selected regardless of the shape of the contact hole. In other words, since the width of the channel contact region is not uniquely determined by the final shape of the contact hole, it is possible to provide a certain degree of freedom in determining the width of the contact channel region.

It is explanatory drawing of the manufacturing method of the semiconductor device by embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor device 10 Drain region 101 Epitaxial layer 20 Channel layer 202 Source region 204 P + type impurity region 30 Gate electrode 300 Trench 301 Gate insulating film 302 Polysilicon 40, 400 Interlayer insulating film 50 Resist film 500 Channel contact mask CH1 Through portion CH2 Contact hole

Claims (4)

A method for manufacturing a semiconductor device, which is manufactured by adding a second conductivity type impurity in a layer having a first conductivity type impurity region,
Forming an interlayer insulating film on the layer;
Forming a penetrating portion in the interlayer insulating film;
Injecting the second conductivity type impurity into the layer through the through portion of the interlayer insulating film;
Expanding the through portion of the interlayer insulating film to form a contact hole;
A method of manufacturing a semiconductor device. In the step of forming a through portion in the interlayer insulating film,
The first conductivity type impurity region after the shape of the interlayer insulating film after formation of the through-hole is narrowed by entering the diffusion region of the second conductivity type impurity formed in the layer is the position of the contact hole Forming the through-hole so as to have a shape similar to the final shape of the interlayer insulating film as it appears in
In the step of forming the contact hole,
By forming the interlayer insulating film in the final shape by isotropic etching, the through portion is expanded to form a contact hole.
The method of manufacturing a semiconductor device according to claim 1. The semiconductor device includes:
An insulated gate semiconductor device having a trench gate structure.
3. A method of manufacturing a semiconductor device according to claim 1, wherein the method is a semiconductor device. A method of manufacturing a gate insulating semiconductor device, which is manufactured by adding a second conductivity type impurity in a channel layer having a first conductivity type impurity region adjacent to a trench structure gate electrode,
Forming an interlayer insulating film on the channel layer;
The final shape of the interlayer insulating film is such that the first conductivity type impurity region after the diffusion region of the second conductivity type impurity formed in the channel layer is narrowed by entering the channel layer appears at the position of the contact hole. Forming a penetrating portion in the interlayer insulating film so as to have a similar shape;
Injecting the second conductivity type impurity into the channel layer through the penetrating portion;
Forming the interlayer insulating film into the final shape by isotropic etching;
A method of manufacturing a semiconductor device.