JP2008166415A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

A semiconductor device capable of reducing characteristic variation and improving operation reliability and a method of manufacturing the same are provided.
A memory cell, a resistance element formed on a second semiconductor region electrically isolated from each other by a second element isolation region, and a third semiconductor region formed immediately below the second element isolation region. 47, and the resistance element is electrically connected to the conductor layer 12 formed on the second semiconductor region 10 with the third insulating film 60 interposed therebetween, and to both ends of the conductor layer 12. The first electrode 14, 15 and the second electrode 14, 15, and an electrode separation region 44 that electrically separates the first and second electrodes 14, 15, and the second electrode adjacent to the electrode separation region 44. The element isolation region has a recess 38 on the surface, the third semiconductor region 47 has a second conductivity type opposite to the first conductivity type, and is located immediately below the recess 38 in the second element isolation region. Is provided.
[Selection] Figure 7

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof. For example, the present invention relates to a configuration of a semiconductor device including a NAND flash memory.

  Conventionally, EEPROM (Electrically Erasable and Programmable Read Only Memory) is known as a nonvolatile semiconductor memory. An EEPROM memory cell usually has a MISFET structure including a stacked gate in which a charge storage layer and a control gate are stacked on a semiconductor substrate. This memory cell stores data in a nonvolatile manner due to a difference in threshold between the state in which charges are injected into the charge storage layer and the state in which charges are released.

  In the NAND-type EEPROM, a tunnel insulating film provided between the charge storage layer and the semiconductor substrate is used to inject electrons into the charge storage layer (data writing) and to release electrons from the charge storage layer (data erasure). This is done by a tunneling current through Even in the NOR type EEPROM, in order to make it less susceptible to the short channel effect at the time of data erasing, electrons are emitted from the charge storage layer by a tunnel current.

  The data is erased simultaneously for a plurality of memory cells in order to increase the number of memory cells erased per unit time. At this time, a positive voltage of 10 V or more, for example, 20 V, is applied to the well region where the memory cell is formed. On the other hand, when writing data, the well region is kept at 0V, and a positive voltage of 10V or more is applied to the source and drain. Thereby, the power required for charging / discharging the well region can be reduced, and the operation speed can be improved.

  Further, for example, in the NAND type EEPROM, it is necessary to reduce the variation in the read current by sufficiently reducing the variation in the threshold value of the non-selected memory cells connected in series to the selected memory cell. Therefore, it is necessary to control the positive voltage to be applied at the time of data writing in a variation range of 0.5 V or less, for example.

  Further, in the conventional EEPROM, the erase, write, and read operations of the EEPROM are switched by a signal given from the outside. Therefore, a logic peripheral circuit for changing the well voltage by external input or outputting read data to the outside is required. These are currently formed using CMOS circuits to reduce power consumption. As the voltage for external input / output, a voltage of 5 V or less, for example, 3.3 V or 1.8 V, which is much lower than the voltage used during the erase operation or the write operation is used.

  In the logic peripheral circuit, in order to feedback control the positive voltage used at the time of erasing or writing, a technique of converting the positive voltage into a low voltage by resistance division is adopted. In this case, it is preferable that the resistance element used for resistance division has a higher resistance value in that power consumption in the resistance element can be reduced. Further, in the logic peripheral circuit, a charge pump circuit is used to generate a positive voltage used at the time of erasing and writing. In the charge pump circuit, a capacitive element that accumulates charges is required. Therefore, it is important to use a capacitor element having a small occupation area and a large capacitance for downsizing the charge pump circuit (see, for example, Patent Document 1).

However, the conventional resistance element and capacitance element have a problem that the variation in characteristics is large and the operation margin of the EEPROM is small.
JP 2006-294649 A

  The present invention provides a semiconductor device capable of reducing characteristic variation and improving operation reliability, and a method for manufacturing the same.

  A semiconductor device according to an aspect of the present invention includes a first element isolation region formed in a semiconductor substrate, a first semiconductor region electrically isolated from each other by the first element isolation region, and the first semiconductor region. A memory cell capable of holding data; a second element isolation region formed in the semiconductor substrate; and a stripe-shaped second semiconductor region electrically isolated from each other by the second element isolation region; , The stripe-shaped resistance element formed on the second semiconductor region, first and second metal wiring layers respectively connected to one end and the other end of the resistance element, and immediately below the second element isolation region A third semiconductor region formed in the semiconductor substrate, the memory cell having a first conductivity type floating gate electrode formed on the first semiconductor region with a first insulating film interposed therebetween; Floating A control gate electrode formed on the gate electrode with a second insulating film interposed therebetween, and the resistance element includes a conductor layer formed on the second semiconductor region with a third insulating film interposed therebetween, A first electrode and a second electrode electrically connected to both ends of the stripe shape of the conductor layer in the longitudinal direction and respectively connected to the first and second metal wiring layers; An electrode isolation region for electrically separating two electrodes, and the conductor layer is formed in a self-aligned manner with respect to the second element isolation region, and the floating gate electrode and the conductor layer are the same The control gate electrode and the first and second electrodes are formed using the same material, and the second element isolation region adjacent to the electrode isolation region has a recess on the surface. And the third semiconductor region has the first conductive region. A second conductivity type type conductivity type opposite, are provided immediately below the recess of the second isolation region.

  According to another aspect of the invention, there is provided a method for manufacturing a semiconductor device, comprising: forming a gate insulating film over a semiconductor substrate; and forming a first conductivity type semiconductor layer functioning as a resistance element over the gate insulating film. And a second direction perpendicular to the first direction in the semiconductor substrate, the stripe-shaped first groove extending in the first direction so as to penetrate the gate insulating film and the semiconductor layer. A step of forming an isolation region by embedding an insulating film in the first trench, a step of forming an inter-gate insulating film on the semiconductor layer, and a step between the gates Removing a part of the insulating film to form a first opening and a second opening and exposing the semiconductor layer in the first and second openings; and the first opening and the second opening On the semiconductor layer so as to cover the part Forming a resistance element electrode layer on the inter-gate insulating film and the element isolation region; and the semiconductor layer sandwiched between the element isolation regions adjacent to each other in the second direction. And patterning the stripe shape along the first direction so as to cover the inter-gate insulating film, exposing the upper surface of the element isolation region, and removing the electrode layer to remove the gate. The semiconductor layer is electrically separated from each other by dividing the electrode layer into two regions along the first direction by exposing an inter-layer insulating film, and through the first and second openings, respectively. In the step of forming the first electrode and the second electrode in contact with each other and the step of removing a part of the electrode layer, the element isolation region of the region adjacent to the region where the electrode layer is removed in the second direction Of the insulating film Removing the surface to form a second groove in the insulating film; and the first direction on the first and second electrodes and on the semiconductor layer in the region where the electrode layer has been removed. Forming a stripe-shaped first mask material along the first and second ion implantations of the second conductivity type first impurity using the first mask material as a mask, thereby forming a region immediately below the second groove Implanting the first impurity into the semiconductor substrate to form an impurity implanted layer, and removing the first mask material, covering the upper surface of the element isolation region, and in the first direction Forming a second mask material having a stripe shape along the second mask material, and performing ion implantation of a second impurity of the first conductivity type using the second mask material as a mask, to the region immediately below the second groove While preventing the implantation of the second impurity, The method includes a step of injecting the second impurity into the semiconductor layer and the first and second electrodes, and a step of forming contact plugs on the first and second electrodes.

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor device which can reduce characteristic variation and can improve operation | movement reliability, and its manufacturing method can be provided.

  Embodiments of the present invention will be described below with reference to the drawings. In the description, common parts are denoted by common reference symbols throughout the drawings. It should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones.

[First Embodiment]
A semiconductor device and a manufacturing method thereof according to a first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram showing a part of the configuration of the NAND flash memory according to the present embodiment.

  As illustrated, the NAND flash memory 1 includes a memory cell array 2 and a peripheral circuit 3. First, the configuration of the memory cell array 2 will be described.

  As shown, the memory cell array 2 has a plurality of NAND cells. FIG. 1 shows only one row of NAND cells. Each of the NAND cells includes 32 memory cell transistors MT0 to MT31 and select transistors ST1 and ST2. Hereinafter, for simplification of description, the memory cell transistors MT0 to MT31 may be simply referred to as memory cell transistors MT. The memory cell transistor MT includes a charge storage layer (for example, a floating gate) formed on a semiconductor substrate with a gate insulating film interposed therebetween, and a control gate electrode formed on the floating gate with an inter-gate insulating film interposed therebetween. A stacked gate structure is provided. The number of memory cell transistors MT is not limited to 32, and may be 8, 16, 64, 128, 256, etc., and the number is not limited. Adjacent ones of the memory cell transistors MT share a source and a drain. And it arrange | positions so that the current path may be connected in series between selection transistor ST1, ST2. The drain region on one end side of the memory cell transistors MT connected in series is connected to the source region of the select transistor ST1, and the source region on the other end side is connected to the drain region of the select transistor ST2.

  The control gate electrodes of the memory cell transistors MT in the same row are commonly connected to one of the word lines WL0 to WL31, and the gates of the select transistors ST1 and ST2 of the memory cells in the same row are connected to the select gate lines SGD and SGS, respectively. Commonly connected. Further, the drains of the select transistors ST1 in the same column in the memory cell array are commonly connected to any one of bit lines BL0 to BLn (n is a natural number). For simplification of description, the word lines WL0 to WL31 and the bit lines BL0 to BLn are sometimes simply referred to as the word line WL and the bit line BL, respectively. The sources of the selection transistors ST2 are commonly connected to the source line SL. Note that both the selection transistors ST1 and ST2 are not necessarily required, and only one of them may be provided as long as a NAND cell can be selected.

  In FIG. 1, only one row of NAND cells is shown, but a plurality of rows of NAND cells are arranged in the memory cell array 2, and NAND cells in the same column are connected to the same bit line BL. Data is collectively written in the memory cell transistors MT connected to the same word line WL, and this unit is called one page. Further, data is erased collectively from a plurality of NAND cells, and this unit is called a block.

  Next, the planar configuration of the memory cell array 2 having the above configuration will be described with reference to FIG. FIG. 2 is a plan view of the memory cell array 2. As shown in the drawing, a plurality of stripe-shaped element regions AA along the first direction are provided in the semiconductor substrate 10 along a second direction orthogonal to the first direction. An element isolation region STI is formed between adjacent element regions AA, and the element region AA is electrically isolated by the element isolation region STI. On the semiconductor substrate 10, stripe-shaped word lines WL and select gate lines SGD, SGS are formed along the second direction so as to straddle the plurality of element regions AA. A floating gate FG is provided in a region where the word line WL and the element region AA intersect. A memory cell transistor MT is provided in a region where the word line WL and the element region AA intersect, and selection transistors ST1 and ST2 are provided in regions where the select gate lines SGD and SGS and the element region AA intersect, respectively. It has been. In the element region AA between the word lines WL adjacent in the first direction, between the select gate lines, and between the word line and the select gate line, the source region or the drain region of the memory cell transistor MT and the select transistors ST1 and ST2 An impurity diffusion layer is formed.

  The impurity diffusion layer formed in the element region AA between the select gate lines SGD adjacent in the first direction functions as the drain region of the select transistor ST1. A contact plug CP1 is formed on the drain region. The contact plug CP1 is connected to a stripe-shaped bit line BL (not shown) provided along the first direction. Further, the impurity diffusion layer formed in the element region AA between the select gate lines SGS adjacent in the first direction functions as a source region of the select transistor ST2. A contact plug CP2 is formed on the source region. Contact plug CP2 is connected to a source line (not shown).

  Next, a cross-sectional configuration of the NAND cell having the above configuration will be described with reference to FIG. 3 is a cross-sectional view taken along the bit line direction (first direction) of the NAND cell, and is a cross-sectional view taken along the line Y1-Y1 'in FIG. FIG. 4 is a cross-sectional view taken along the word line direction (second direction) of the NAND cell, and is a cross-sectional view taken along line X1-X1 ′ in FIG.

First, a cross-sectional configuration in the bit line direction will be described with reference to FIG. As shown in the figure, a gate insulating film 11 is formed on a p-type semiconductor substrate 10, and gate electrodes of a memory cell transistor MT and select transistors ST 1 and ST 2 are formed on the gate insulating film 11. The gate electrodes of the memory cell transistor MT and the select transistors ST1, ST2 are a polycrystalline silicon layer 12 formed on the gate insulating film 11, an intergate insulating film 13 formed on the polycrystalline silicon layer 12, and an intergate insulating film. 13 has a polycrystalline silicon layer 14 and a metal layer 15 formed on 13, and an insulating film 16 formed on the metal layer 15. The inter-gate insulating film 13 is, for example, a silicon oxide film, an ON film, a NO film, or an ONO film, which is a stacked structure of a silicon oxide film and a silicon nitride film, or a stacked structure including them, TiO ₂ , HfO ₂ It is formed of a laminated structure of an Al ₂ O ₃ , HfAlO _x , HfAlSi film and a silicon oxide film or a silicon nitride film. The gate insulating film 11 functions as a tunnel insulating film.

In the memory cell transistor MT, the polycrystalline silicon layer 12 functions as a floating gate (FG). On the other hand, the polycrystalline silicon layer 14 and the metal layer 15 are commonly connected to each other adjacent to each other in the direction orthogonal to the bit line, and function as a control gate electrode (word line WL). In the select transistors ST1 and ST2, the polysilicon layers 12 and 14 and the metal layer 16 that are adjacent in the word line direction are commonly connected. The polycrystalline silicon layers 12 and 14 and the metal layer 15 function as select gate lines SGS and SGD. Only the polycrystalline silicon layer 12 may function as a select gate line. In this case, the potentials of the polycrystalline silicon layer 14 and the metal layer 15 of the selection transistors ST1 and ST2 are set to a constant potential or a floating state. An n ⁺ -type impurity diffusion layer 17 is formed in the surface of the semiconductor substrate 10 located between the gate electrodes. The impurity diffusion layer 17 is shared by adjacent transistors and functions as a source (S) or a drain (D). In addition, a region between the adjacent source and drain functions as a channel region serving as an electron moving region. The gate electrode, the impurity diffusion layer 17, and the channel region form a MOS transistor that becomes the memory cell transistor MT and the select transistors ST1 and ST2.

  A sidewall insulating film 18 is formed on the sidewall of the gate electrode. The sidewall insulating film 18 fills between the gate electrodes of the adjacent memory cell transistors MT and between the gate electrodes of the adjacent memory cell transistors MT and select transistors ST1 and ST2. On the semiconductor substrate 10, an interlayer insulating film 19 is formed so as to cover the memory cell transistor MT and the select transistors ST1, ST2. In the interlayer insulating film 19, a contact plug CP2 reaching the impurity diffusion layer (source) 17 of the source side select transistor ST2 is formed. On the interlayer insulating film 19, a metal wiring layer 20 connected to the contact plug CP2 is formed. The metal wiring layer 20 functions as the source line SL. In the interlayer insulating film 19, a contact plug CP3 reaching the impurity diffusion layer (drain) 17 of the drain side select transistor ST1 is formed. On the interlayer insulating film 19, a metal wiring layer 21 connected to the contact plug CP3 is formed.

  An interlayer insulating film 22 is formed on the interlayer insulating film 19 so as to cover the metal wiring layers 20 and 21. A contact plug CP 4 reaching the metal wiring layer 21 is formed in the interlayer insulating film 22. On the interlayer insulating film 22, a metal wiring layer 23 commonly connected to the plurality of contact plugs CP4 is formed. The metal wiring layer 13 functions as the bit line BL, and the contact plugs CP3 and CP4 correspond to the contact plug CP1 in FIG.

  Next, a cross-sectional configuration in the word line direction will be described with reference to FIG. As illustrated, a plurality of stripe-shaped grooves 30 along the first direction are formed in the p-type semiconductor substrate 10 along the second direction. An insulating film 31 is formed on the sidewall of the groove 30 by using, for example, a silicon oxide film, and an insulating film 32 is further formed on the insulating film 31 by using, for example, a silicon oxide film. The inside of the groove 30 is filled with the insulating film 32. It is. These insulating films 31 and 32 form an element isolation region STI. A region between adjacent device isolation regions STI is a device region AA. Then, the gate insulating film 11 and the polycrystalline silicon layer 12 described above are formed on the element region AA. The insulating film 32 is also formed on the side wall portion of the polycrystalline silicon layer 12, and an insulating film 33 is further formed between the polycrystalline silicon layer 12 and the insulating film 32. Further, the insulating film 32 is formed up to a position higher than the polycrystalline silicon layer 12 at the boundary portion (not shown) between the memory cell array 2 and the peripheral circuit 3. On the polycrystalline silicon layer 12 and the insulating film 32, the inter-gate insulating film 13, the polycrystalline silicon layer 12, the metal layer 15, and the insulating film 16 are formed. The metal wiring layer 23 functioning as a bit line is formed on the interlayer insulating film 22 so as to be located immediately above the element region AA.

  Next, the peripheral circuit 3 will be described. The peripheral circuit transmits / receives data to / from the memory cell array 2 and applies a voltage in accordance with an externally applied command. The peripheral circuit includes a voltage generation circuit that generates a voltage when data is written to the memory cell array, for example. As described in the background art, the voltage generation circuit includes a resistance element for stepping down the voltage and a charge pump circuit for stepping up the voltage. Below, the structure of the said resistive element is demonstrated. Of course, the use of the resistance element described below is not limited to step-down. This resistance element is formed on the same semiconductor substrate 10 as the memory cell array of the NAND flash memory described above. FIG. 5 is a plan view of the resistance element according to the present embodiment. 6 to 8 are cross-sectional views of the resistance element according to this embodiment, and are cross-sectional views taken along lines X2-X2 ', X3-X3', and Y2-Y2 'in FIG. 5, respectively. The plan view of FIG. 5 shows a planar structure at the level of the surfaces of insulating films 18 and 16 to be described later.

  FIG. 5 shows a state in which two resistance elements are connected in series. One end of each of the two resistance elements is connected to the metal wiring layer 39, and the other end is connected to the common metal wiring layer 38. That is, the two resistance elements are connected in series between the two metal wiring layers 39. The potential difference between the two metal wiring layers 39 is divided in half by the two resistance elements, and the divided voltage can be taken out from the metal wiring layer 38. 5 shows a configuration in which the voltage between the metal wiring layers 39 is halved by two resistance elements. Of course, by changing the number of resistance elements and the resistance value of each resistance element, The partial pressure ratio can be changed.

  As shown in the figure, in the semiconductor substrate 10, for example, four stripe-shaped element regions AA along the first direction are formed along the second direction. The resistance element is formed on the element region AA. In FIG. 5, of the four element areas AA, only the resistance elements formed on the two central element areas AA function as actual resistance elements, and the outer two are dummy resistance elements. Become. Hereinafter, for simplification of description, a dummy element is referred to as a “dummy element”, and an element that functions as an actual resistance element is referred to as a “resistance element”. That is, two stripe-shaped resistance elements along the first direction are sandwiched between the two dummy elements in the second direction. Of course, two or more resistance elements may be sandwiched between the dummy elements. Since the dummy element and the resistance element have substantially the same configuration, the configuration of the resistance element will be described below, but the configuration of both is the same unless otherwise specified.

  An element isolation region STI is formed in a region between the element regions AA. The configuration of the element isolation region STI is the same as that of the element isolation region STI in the memory cell array 2. That is, the element isolation region STI is formed by the insulating film 31 formed on the surface of the groove 30 formed in the semiconductor substrate 10 and the insulating film 32 formed on the insulating film 31.

  A polycrystalline silicon layer 12 is formed on element region AA with gate insulating film 60 interposed. A polycrystalline silicon layer 14, a metal layer 15, and an insulating film 16 are sequentially formed on the polycrystalline silicon layer 12 with an intergate insulating film 13 interposed therebetween. In each element region AA, the inter-gate insulating film 13, the polycrystalline silicon layer 14, the metal layer 15, and the insulating film 16 are divided into three regions along the first direction (see FIG. 5). Hereinafter, the three regions will be referred to as regions A1, A2, and A3, respectively. In FIG. 5, since the planar patterns of the element region AA and the polycrystalline silicon layer 12 are the same, both are denoted by reference numeral 12 (AA). The regions A1 and A3 are regions of both end portions along the first direction in the resistance element, and the region A2 is a central portion region sandwiched between the regions A1 and A3 along the first direction.

The insulating film 32 in the element isolation region STI is formed up to a position higher than the surface of the polycrystalline silicon layer 12. Further, an insulating film 33 is formed of, for example, a silicon oxide film between the polycrystalline silicon layer 12 and the insulating film 32 formed using, for example, a silicon oxide film. The insulating film 33 is deposited in order to reduce the introduction of defects into the silicon substrate 10 when the insulating film 32 is deposited. Therefore, when there are few defects introduced into the silicon substrate 10, the insulating film 33 may or may not be formed. Further, in the region A2, an impurity implantation region 35 is formed in a region in contact with the insulating film 33 in the polycrystalline silicon layer 12. The impurity implanted region 35 has a higher resistivity and lower conductivity than the other polycrystalline silicon layers 12. Further, in the element isolation region STI in the region between the regions A1 and A2 and the region between the regions A2 and A3, a part of the insulating film 32 is removed, and a groove 38 as shown in FIG. Is formed. In the semiconductor substrate 10, ap ⁺ -type impurity implantation layer 47 is formed in a region located immediately below the trench 38 so as to be in contact with the insulating film 31. In the regions A1 and A3, a part of the inter-gate insulating film 13 is removed, thereby forming an opening 34. The polycrystalline silicon layers 12 and 14 are electrically connected through the opening 34.

  As described above, the sidewall insulating film 18 is further formed on the sidewalls of the polycrystalline silicon layer 14, the metal layer 15, and the insulating film 16 separated in each of the regions A 1, A 2, and A 3 and on the sidewalls of the trench 38. Has been. An interlayer insulating film 19 is formed on the semiconductor substrate 10 so as to cover the resistance element. Contact plugs 37 and 36 reaching the metal layer 15 in the regions A1 and A3 are formed in the interlayer insulating film 19, respectively. Further, in the interlayer insulating film 19, metal wiring layers 39 and 38 connected to the contact plugs 37 and 36, respectively, are formed. The metal wiring layer 38 connects the two resistance elements with the contact plug 36 interposed therebetween.

  In the above configuration, the polycrystalline silicon layer 12 formed linearly from the regions A1 to A3 is a region that substantially functions as a resistance in the resistance element. The polycrystalline silicon layer 14 and the metal layer 15 in the regions A1 and A3 function as electrodes in the resistance element.

  That is, the configuration of the resistance element can be described as follows. One resistance element includes a linear region (polycrystalline silicon layer 12) along the first direction. This linear region functions as a substantial resistance portion. A polycrystalline silicon layer 14 and a metal layer 15 that function as electrodes of a resistance element are formed on both end portions (regions A1 and A3) of the linear region. These electrodes are electrically separated from each other by a region 44 to be called an electrode separation region. The linear region, the polycrystalline silicon layer 14 and the metal layer 15 are electrically connected by the opening 34. In regions A1 and A3, contact plugs 37 and 36 are formed on the metal layer 15 to form one resistance element. Also in the region A2 between the regions A1 and A3, the polycrystalline silicon layer 14, the metal layer 15, and the insulating film 16 are formed. However, the polycrystalline silicon layer 14 and the metal layer 15 in the region A2 are electrically separated from the polycrystalline silicon layer 12 by the inter-gate insulating film 13.

  And the two resistive elements of the said structure are arrange | positioned along the 2nd direction. Further, two dummy elements having the same configuration are arranged so as to sandwich the two resistance elements in the second direction. The two resistance elements are connected in series by the metal wiring layer 38, and the two resistance elements connected in series are connected between the two metal wiring layers 39. In the case of a dummy element, the contact plugs 36 and 37 and the metal wiring layers 38 and 39 are not formed.

  As described above, it is sufficient that a plurality of resistance elements are periodically arranged in parallel along the second direction, and the number is not limited to two. In addition, the width in the second direction and the adjacent interval of the polycrystalline silicon layer 12 of each resistance element are the same. The polycrystalline silicon layers 12 and 14 and the metal layer 15 may be conductive layers, but are formed of the same material as the memory cell array described with reference to FIGS.

Next, a method for manufacturing the NAND flash memory having the above configuration will be described with reference to FIGS. 9 to 39, particularly focusing on the memory cell array and the resistance elements.
First, the first step will be described with reference to FIGS. FIG. 9 is a plan view of the resistance element, and shows the same region as FIG. FIG. 10 is a cross-sectional view of the memory cell array and shows the same region as FIG. 11 and 12 are sectional views taken along lines X2-X2 'and Y2-Y2' in FIG. As described above, the resistance elements in the memory cell array 2 and the peripheral circuit 3 are formed on the same p-type semiconductor substrate (silicon substrate) 10.

  First, as shown in FIG. 10, in the memory cell array 2, the trench 30 for forming the element isolation region STI, the polycrystalline silicon layer 12, and the element region AA are processed in a self-aligned manner. In the memory cell array 2, the polycrystalline silicon layer 12 functions as a floating gate electrode. In the peripheral circuit 3, the trench 30 for forming the element isolation region STI, the polycrystalline silicon layer 12, and the element region AA are processed in a self-aligned manner. In the memory cell array 2 and the peripheral circuit 3, the polycrystalline silicon layer 12 is formed so that the semiconductor substrate 10 does not drop downward at the corners. The above will be described in detail below.

  First, a gate insulating film 11 that becomes a tunnel oxide film of a nonvolatile memory cell (memory cell transistor MT) is formed on a p-type semiconductor substrate (silicon substrate or a p-type semiconductor region formed on the surface of the semiconductor substrate). A silicon oxide film or a silicon oxynitride film having a thickness of 4 nm to 12 nm is used to form the memory cell array 2. Furthermore, on the p-type semiconductor substrate 10, a gate insulating film 60 serving as an insulating film for providing electrical isolation between the resistance element and the semiconductor substrate 10 is a silicon oxide film having a film thickness in the range of 13 nm to 40 nm, or A silicon oxynitride film is used to form the peripheral circuit 3.

The gate insulating film 60 has a thickness of, for example, 13 nm or more, and suppresses the occurrence of tunnel leakage even when a high voltage of 5 V or more is applied between the polycrystalline silicon layer 12 and the semiconductor substrate 10. Reliability degradation can be suppressed. The gate insulating film 60 may be formed in common as a gate insulating film of a high voltage transistor that applies a voltage of 5 V or more, for example. Thereby, for example, in order to obtain a low voltage by dividing a high voltage of 10 V or more necessary for writing in the flash memory by a resistance, a high voltage is applied to the polycrystalline silicon layer 12 using this resistance element. Even in this case, a highly reliable element can be realized. As the concentration of the semiconductor substrate 10, for example, by adding a boron surface concentration of 10 ¹⁶ cm ⁻³ or more, the inversion threshold can be increased, and thereby the floating gate electrode capacitance with respect to the semiconductor substrate 10 can be reduced. As a result, the parasitic capacitance of the resistance element can be further reduced, and an element with a small increase in CR delay due to the parasitic capacitance can be realized.

Subsequently, the polycrystalline silicon layer 12 and the cap layer 40 are sequentially formed on the gate insulating films 11 and 60. The polycrystalline silicon layer 12 functions as a floating gate electrode in the memory cell transistor MT, and functions as a substantial resistance portion in the resistance element. The polycrystalline silicon layer is an n-type semiconductor in which phosphorus or arsenic as an n-type impurity is added in the range of 10 ¹⁸ cm ⁻³ to 10 ²² cm ⁻³ as a conductive impurity. The polycrystalline silicon layer 12 may be replaced with, for example, a SiGe layer. The polycrystalline silicon layer 12 has a thickness of 20 nm to 200 nm, and the insulating film 40 has a thickness of about 20 nm to 300 nm. As a material for the insulating film 40, a silicon nitride film or a silicon oxide film can be used.

  Next, a trench 30 is dug in a region to be an element isolation region STI by a photolithography process and etching. Specifically, the cap layer 40 (silicon nitride film or silicon oxide film), the polycrystalline silicon layer 12, the gate insulating films 11 and 60, and the semiconductor substrate 10 are sequentially etched. As a result, the trench 30 for forming the element isolation region STI is formed in a self-aligned manner with the polycrystalline silicon layer 12 and the cap layer 40. In the memory cell array 2, the depth of the trench 30 dug in the semiconductor substrate 10 is, for example, in the range of 100 nm to 400 nm, and the width and interval of the trench 30 are 10 nm or more and 140 nm or less.

  The width and interval of the grooves 30 in the peripheral circuit 3 are sufficiently larger than those in the memory cell array 2. Thereby, the resistance change due to the dimensional variation is reduced. For this reason, in the peripheral circuit 3, the width and interval of the trench 30 in the resistance element and dummy element formation region correspond to the interval and width of the cap layer 40 as shown in FIG. Is desirable. Here, the element area AA of the dummy element portion is formed of a groove having the same width and the same width as the resistance element in parallel with the resistance element, and is formed adjacent to at least one resistance element. It is desirable to prevent dimensional variation due to non-uniformity and form a resistance element with a more uniform width. This is because the periodic pattern can reduce the dimensional variation as lithography, and can prevent the microloading effect in which the etching depth and the etching side taper change depending on the groove width in the case of etching. Further, the length of the cap layer 40 in the longitudinal direction (length along the first direction) is sufficiently longer than the width of the cap layer 40 (length along the second direction), for example, 1 μm or more and 1 mm or less. . As a result, the configuration shown in FIGS. 9 to 12 is obtained.

  Next, the second step will be described with reference to FIGS. FIG. 13 is a cross-sectional view of the memory cell array and shows the same region as FIG. 14 and 15 are cross-sectional views corresponding to directions along the lines X2-X2 'and Y2-Y2' in FIG.

  As shown in the drawing, after forming the groove 30, thin insulating films 31 and 33 are formed as necessary. The insulating films 31 and 33 are silicon oxide films formed by, for example, a thermal oxidation method, oxygen plasma, or high temperature oxide (a silicon oxide film deposition method in the range of 700 ° C. to 900 ° C .; hereinafter referred to as HTO). The insulating film 31 is formed on the surface of the groove 30 of the semiconductor substrate 10, and the insulating film 33 is formed on the side surface of the polycrystalline silicon layer 12. The film thickness is, for example, about 1 nm to 30 nm.

  As a result, the trench 30, the polycrystalline silicon layer 12, and the element region AA are processed in a self-aligned manner, and the polycrystalline silicon layer 12 is formed so as not to drop into the element isolation region STI. This realizes miniaturization of the memory cell transistor MT and also prevents the polycrystalline silicon layer 12 from being formed so as to cover the corner portion of the element region AA. Variations can be suppressed. In the present embodiment, the case where the polycrystalline silicon layer 12 is formed in the memory cell array 2 and the peripheral circuit 3 is shown, but they may be replaced with different materials. However, when both are polycrystalline silicon layers, the polycrystalline silicon layer 12 is not formed so as to cover the corner portion of the element region AA in the gate insulating film 60, so that the effect of electric field concentration can be achieved. It is possible to suppress the breakdown voltage degradation and the variation in capacity characteristics due to the above.

  Next, an insulating film 32 (silicon oxide film) is buried in the trench 30 by, for example, a HDP (High Density Plasma) method or an HTO method, and a film that is converted into a silicon oxide film such as HARP or polysilazane. Thereafter, the insulating film 32 is planarized by a method such as CMP (Chemical Mechanical Polish) using the upper surface of the cap layer 40 as an etching stopper. As a result, the element isolation region STI is completed. Note that the insulating film 32 embedded in the trench 30 is embedded in a shape in which the cap layer 40 is slightly lowered in a self-aligning manner at the end of the floating gate. As a result, the configuration shown in FIGS. 13 to 15 is obtained.

  Next, the third step will be described with reference to FIGS. FIG. 16 is a cross-sectional view of the memory cell array and shows the same region as FIG. 17 and 18 are cross-sectional views corresponding to directions along the lines X2-X2 'and Y2-Y2' in FIG.

  As shown, the cap layer 40 is removed. As a result, a shape in which the surface of the insulating film 32 is located higher than the surface of the polycrystalline silicon layer 12 is exposed on the surface of the peripheral circuit 3. If the insulating film 40 is a silicon nitride film, it can be easily removed by processing with a chemical such as hot phosphoric acid.

  Next, a photoresist 41 is applied to the entire surface. Then, the photoresist 41 in the memory cell array 2 is removed by photolithography and etching. Next, the insulating films 32 and 33 in the memory cell array 2 are dropped to a desired height by etching back the oxide film. The drop height should not be lower than the height of the boundary between the polycrystalline silicon layer 12 (floating gate electrode) and the gate insulating film 11. Thus, by exposing the upper surface and side surfaces of the floating gate electrode 12, the following effects can be obtained. In other words, the capacitance between the floating gate electrode 12 and the control gate electrode (polycrystalline silicon layer 14 and metal layer 15) of the memory cell transistor MT can be made larger than when only the upper surface of the floating gate electrode 12 is exposed. Therefore, even when a material having a lower withstand voltage is used for the inter-gate insulating film 13, a highly reliable memory cell can be formed.

  In the above process, the reliability of the resistance element can be improved by not etching back the insulating films 32 and 33 in the resistance element and the dummy element. That is, even when a high voltage of, for example, 10 V or higher is applied to the polycrystalline silicon layer 14 and 0 V is applied to the semiconductor substrate 10, the insulation breakdown voltage with the insulating film 32 sandwiched can be secured, and more reliable. A high resistance element can be realized. Further, even when the polycrystalline silicon layers 12 and 14 are used as a capacitive element through the inter-gate insulating film 13 (described in the second embodiment), a more reliable capacitive element can be realized. As a result, the configurations of FIGS. 16 to 18 are obtained.

  Next, the fourth step will be described with reference to FIGS. FIG. 19 is a plan view of the resistance element, and shows the same region as FIG. FIG. 20 is a cross-sectional view of the memory cell array and shows the same region as FIG. 21 and 22 are sectional views taken along lines X2-X2 'and Y2-Y2' in FIG.

  As shown in the figure, the photoresist 41 is peeled off with, for example, an asher or a sulfuric acid / hydrogen peroxide mixture. Thereafter, in the memory cell array 2 and the peripheral circuit 3, on the polycrystalline silicon layer 12, for example, a silicon oxide film having a thickness of about 8 nm to 20 nm or three layers of silicon oxide film / silicon nitride film / silicon oxide film An intergate insulating film 13 having a structure is deposited on the entire surface. The film thickness in the case of the three-layer structure is, for example, in the range of 3 nm to 10 nm, in the range of 3 nm to 10 nm, and in the range of 3 nm to 10 nm, respectively.

  Further, a photoresist 42 is applied on the entire surface. Then, the photoresist 42 at both end portions along the first direction in the element region AA of the resistance element forming portion is removed by photolithography and etching. As a result, an opening 43 as shown is formed. In the opening 43, the surface of the inter-gate insulating film 13 is exposed. At this time, the opening 43 has a shape extending along the first direction. The opening 43 is for forming the region 34. Therefore, by making the shape extending along the first direction, the contact area of the polycrystalline silicon layers 12 and 14 can be increased, and the parasitic resistance at the contact portion can be reduced. Further, as shown in FIG. 19, the opening 43 is preferably formed so as to be located inside the element region AA in the top surface shape. This is because the inter-gate insulating film 13 can remain in any etching cross section in an etching process described later with reference to FIGS. Thereby, the uniformity of etching described with reference to FIGS. 27 and 28 can be improved.

  The width of the opening 43 (the length along the second direction) is naturally smaller than the width of the element region AA, and is formed inside, for example, 20 nm to 100 nm. Further, the length of the opening 43 (length along the first direction) is, for example, not less than 50 nm and not more than 10 μm. The resistance element does not need to be designed with the minimum design size required for the memory cell transistor MT. Therefore, the opening 43 can be formed by a lithography apparatus with a lower resolution that is cheaper than that for forming the element region AA. At this time, it is not always necessary to provide the opening 43 in the photoresist 42 of the dummy element portion.

  Next, the fifth step will be described with reference to FIGS. FIG. 23 is a cross-sectional view of the memory cell array, showing the same region as FIG. 24 and 25 are cross-sectional views corresponding to the directions along the lines X2-X2 'and Y2-Y2' in FIG.

As shown in the drawing, first, the inter-gate insulating film 13 exposed in the opening 43 is removed by anisotropic etching for etching the silicon oxide film and the silicon nitride film. Subsequently, in the memory cell array 2 and the peripheral circuit 3, a polycrystalline silicon layer 14 is deposited with a film thickness in the range of 10 nm to 300 nm, for example. Further, a metal layer 15 using WSi, CoSi, NiSi, W, or Al as a material is deposited on the polycrystalline silicon layer 14. Further, the insulating film 16 is deposited to a thickness of 10 nm to 500 nm using, for example, a silicon oxide film or a silicon nitride film as a material. The polycrystalline silicon layer 14 is an n-type semiconductor to which phosphorus or arsenic, which is an n-type impurity, is added as a conductive impurity in a range of 10 ¹⁸ cm ⁻³ to 10 ²² cm ⁻³ . As a result, the configurations of FIGS. 23 to 25 are obtained.

  Next, the sixth step will be described with reference to FIGS. FIG. 26 is a plan view of the resistance element, and shows the same region as FIG. 27 and 28 are sectional views taken along lines X2-X2 'and Y2-Y2' in FIG.

  As shown in the drawing, in the peripheral circuit 3, the polycrystalline silicon layer 14, the metal layer 15, and the insulating film 16 are etched by anisotropic etching. The polycrystalline silicon layer 14, the metal layer 15, and the insulating film 16 are processed into a stripe shape along the first direction as well as the element region AA and so as to cover the element region AA. At this time, as shown in FIG. 26, the polycrystalline silicon layer 14, the metal layer 15, and the insulating film 16 have a shape protruding from the end of the element region AA by about 0.02 μm to 0.5 μm. Therefore, these layers 14 to 16 completely cover the upper surface of the polycrystalline silicon layer 12. In this step, since the width of the resistance element and the dummy element is sufficiently larger than that of the memory cell transistor MT, it is not always necessary to perform high-precision and high-resolution lithography and etching similar to the memory cell array 2. In other words, if the photolithography and etching of the memory cell array are separate steps, the lithography can be performed with lower resolution and lower cost. In this case, if the width expanded from the end of the element area AA of the resistance element and the dummy element in the range from 0.02 μm to 0.5 μm is larger than the alignment accuracy with the element area AA, Since the capacitance through the inter-gate insulating film 13 hardly fluctuates, a resistive element with high parasitic capacitance accuracy can be realized even by using inexpensive lithography. In the case of the second embodiment in which this configuration is used as a capacitive element, a capacitive element with a small variation in parasitic capacitance can be realized.

  Further, in this step, the polycrystalline silicon layer 14, the metal layer 15, and the insulating film 16 are also etched in the memory cell array 2. In the memory cell array 2, these layers 14 to 16 are processed into a stripe shape along the second direction (see FIG. 2). As a result, a stacked gate of the memory cell transistor MT and the select transistor ST as shown in FIGS. 3 and 4 is completed.

  Next, the seventh step will be described with reference to FIGS. FIG. 29 is a plan view of the resistance element, and shows the same region as FIG. 30 and 31 are sectional views taken along lines X3-X3 'and Y2-Y2' in FIG.

  As shown in FIGS. 29 and 31, the polycrystalline silicon layer 14, the metal layer 15, and the insulating film 16 in the peripheral circuit 3 are etched by photolithography and anisotropic etching. This etching is performed so as to remove each of the layers 14 to 16 along the second direction. As a result, the layers 14 to 16 are separated into regions A1, A2, and A3. Each region is electrically separated by region 44. At this time, etching is performed so that the position of the region 44 is closer to the center of the element region AA than to the opening 34. In other words, each of the regions A1 and A3 is performed so as to completely cover the opening 34. The length of the region 44 along the first direction is, for example, not less than 50 nm and not more than 1 μm. As described above, the resistance element can be formed by an inexpensive lithographic apparatus with low resolution.

  In addition, by preventing the layers 14 to 16 belonging to the region A2 from coming into contact with the opening 34, the layers 14 to 16 can be in an electrically floating state. In addition, this makes it possible to keep the potential difference between the polycrystalline silicon layers 12 and 14 smaller than in the case where the opening portion 34 is closer to the element region AA than on the one side, and has higher breakdown voltage and reliability. A high resistance element can be realized.

  The etching in this step uses etching conditions in which the etching rate of the silicon oxide film is slower than that of the polycrystalline silicon layer 14. As a result, the inter-gate insulating film 13 remains as shown in FIGS. Thereby, it is possible to prevent a part of the polycrystalline silicon layer 12 from being etched in the region 44 (see FIG. 31). That is, it is possible to prevent a reduction in the area of the region that functions as a substantial resistance portion of the resistance element, and it is possible to realize a more accurate resistance element.

  In this step, in order to form the region 44, a mask material having a stripe-shaped opening including the region 44 formation scheduled region located in the same row is formed. Then, the insulating film 32 in the element isolation region STI is exposed in the region between the regions 44 adjacent in the second direction. Therefore, as shown in FIG. 30, the surface of the insulating film 32 in the region is also etched, and a recess 38 is formed on the surface of the element isolation region STI. The bottom of the recess 38 is lower than the surface of the element area AA, and the depth is about 0.03 μm to 0.20 μm from the interface with the semiconductor substrate 10.

  Next, the eighth step will be described with reference to FIGS. FIG. 32 is a plan view of the resistance element, and shows the same region as FIG. 33 and 35 are sectional views taken along lines X2-X2 ', X3-X3', and Y2-Y2 'in FIG.

  As shown in FIGS. 33 to 35, the insulating film 32 exposed on the sidewalls of the polycrystalline silicon layer 14, the metal layer 15, and the insulating film 16 exposed in the region 44 and in the recess 38 of the element isolation region STI is formed. On the side wall, the side wall insulating film 18 is formed to a thickness of about 5 nm to 500 nm using, for example, a silicon oxide film or a silicon nitride film as a material. The sidewall insulating film 18 is used as a mask for forming an LDD region of a MOS transistor (not shown) formed in the peripheral circuit 3. By forming the LDD region, it is possible to secure a breakdown voltage and a junction breakdown voltage between a source or drain electrode (not shown) and a gate electrode (for example, the polycrystalline silicon layer 14 and the metal layer 15) in the MOS transistor. The sidewall insulating film 18 also plays a role of ensuring electrical isolation between the contact plugs 36 and 37 formed in a later step and the polycrystalline silicon layer 14 and the metal layer 15 in the region A2. The sidewall insulating film 18 can be formed by, for example, the following method. That is, after depositing a silicon oxide film or a silicon nitride film on the polycrystalline silicon layer 14, the metal layer 15, and the insulating films 16 and 32, the polycrystalline silicon layer 14, the metal layer 15, and the insulating film are formed by anisotropic ion etching. The film 16 is left only on the side wall of the insulating film 32 in the recess 38. This sidewall insulating film 18 may be formed in the same process as the sidewall insulating film 18 of the stacked gate in the memory cell array 2 or may be formed in a separate process.

  Subsequently, a photoresist 45 is applied on the entire surface, and the photoresist 45 is patterned by a photolithography process as shown in FIG. That is, the photoresist 45 has a stripe shape along the first direction, and its width is smaller than the width of the polycrystalline silicon layer 12 (length along the second direction). The photoresist 45 is formed so as to be completely placed on the insulating film 16 in the regions A1, A2, and A3. That is, as shown in FIG. 32, in the regions A1, A2, and A3, the upper surfaces of the insulating films 16 and 18 on which the photoresist 45 is placed are exposed on both sides of the photoresist 45 along the second direction. Further, in the region 44, the photoresist 45 is formed on the polycrystalline silicon layer 12, and the upper surface of the polycrystalline silicon layer 12 on which the photoresist 45 is placed is exposed on both sides of the photoresist 45. Further, the upper surface of the element isolation region STI between the sidewall insulating films 18 in the regions A1, A2, and A3 and the upper surface of the element isolation region STI between the polycrystalline silicon layers 12 in the region 44 are also exposed. The photoresist coating process and the photolithography process are a photoresist coating process performed for selective ion implantation of p-type impurities for forming a p-type source diffusion layer and a drain diffusion layer, which will be described below. By using the same process as the photolithography process, an increase in the number of processes can be prevented.

That is, after the photolithography process, ion implantation of p-type impurities is performed in order to form the source and drain diffusion layers of the p-type MISFET formed on the same semiconductor substrate 10. Boron or BF ₂ is used as the p-type implantation impurity, and an implantation amount of 10 ¹⁴ cm ⁻² to 10 ¹⁶ cm ⁻² is used as the implantation energy with an energy between 2 keV and 40 keV.

By this ion implantation, a p-type impurity is implanted into the semiconductor substrate 10 through the trench in the region 44 and the bottom of the recess in the insulating film 32. A region where the p-type impurity is implanted and the concentration of the p-type impurity is higher than that of the surroundings is hereinafter referred to as a p ⁺ -type impurity implanted layer 47. The concentration of the injection layer 47 is, for example, 10 ¹⁶ cm ^{−3 to} 5 × 10 ¹⁸ cm ⁻³ , and the depth is about 0.03 μm to 0.5 μm from the interface between the semiconductor substrate 10 and the insulating film 31.

  Further, in the opening portion of the photoresist 45, the edge portion of the polycrystalline silicon layer 12 in the region 44 is exposed. Accordingly, the p-type impurity is also implanted into the exposed polycrystalline silicon layer 12. As a result, p-type impurity implantation layer 35 is also formed in the side wall portion of polycrystalline silicon layer 12 in region 44. As a result, in the polycrystalline silicon layer 12, the electron concentration is lowered in the p-type impurity implantation layer 35. As a result, the leakage current through the insulating films 33 and 32 can be reduced.

  Further, even when an etching residue of the polycrystalline silicon layer 14 occurs along the polycrystalline silicon layer 12 in the region 44, p-type impurities are implanted into the remaining polycrystalline silicon layer 14. Accordingly, it is possible to lower the conductivity by reducing the electron concentration in the remaining etching portion of the polycrystalline silicon layer 14. As a result, the leakage current flowing between the polycrystalline silicon layers 14 sandwiching the region 44 can be reduced. The boundary of the photoresist 45 is formed so as to open the recess 38 in the region 44. Preferably, a region of 50 nm or less is opened as the distance from the edge and end of the upper surface of the polycrystalline silicon layer 12. It is desirable to form so that.

  With the above configuration, the p-type impurity is not implanted into the central portion of the polycrystalline silicon layer 12 also in the region 44. Further, when the inter-gate insulating film 13 is peeled off by etching on the polycrystalline silicon layer 12 in the region 44, the polycrystalline silicon layer 12 is also etched, and the etching depth varies. Therefore, when the polycrystalline silicon layer 12 is used as a resistance element, the depth and dose amount of impurities ion-implanted into that portion also vary. However, according to the present embodiment, since the p-type impurity is not implanted into the central portion of the polycrystalline silicon layer 12 also in the region 44, the above problem is alleviated. Therefore, the problem that the accuracy as the resistance element decreases due to the increase in resistance of the polycrystalline silicon layer 12 in the region 44 is alleviated.

  Next, the ninth step will be described with reference to FIGS. FIG. 36 is a plan view of the resistance element, and shows the same region as FIG. 37 to 39 are sectional views taken along lines X2-X2 ', X3-X3', and Y2-Y2 'in FIG.

  After removing the photoresist 45, a photoresist 46 is applied again on the entire surface. Then, the photoresist 46 is patterned by a photolithography process as shown in FIGS. That is, the photoresist 46 has a stripe-shaped opening along the first direction, and the surface of the polycrystalline silicon layer 12 in the region 44 and the surface of the insulating film 16 in the regions A1 to A3 are formed in the opening. Patterned to expose. At this time, patterning is performed so that the photoresist 46 covers the insulating film 32 between the adjacent resistance elements and the upper surface of the p-type impurity implantation layer 35. Therefore, in the region 44, the central portion of the polycrystalline silicon layer 12, that is, the upper surface of the region where the p-type impurity is not implanted in FIGS. 32 to 35 is exposed. That is, in the region 44, a region separated by 50 nm or more from the end portion of the polycrystalline silicon layer 12 along the second direction is exposed. This step increases the number of steps by using the same steps as the photoresist coating step and the photolithography step that are performed to selectively ion-implant n-type impurities for forming an n-type source / drain diffusion layer described later. Can be prevented.

After the photolithography process, n-type impurity ion implantation is performed to form an n-type source region and drain region of a MISFET (not shown) formed on the same semiconductor substrate 10. The n-type implanted impurity used is phosphorus or arsenic, the implantation energy is between 5 keV and 60 keV, and the implantation amount is about 10 ¹⁴ cm ⁻² to 10 ¹⁶ cm ⁻² . At this time, the n-type impurity is injected not only into the MISFET but also into a region not covered with the photoresist 46 in the resistance element.

  In this step, n-type impurities are not implanted into the edge of the polycrystalline silicon layer 12 in the region 44, that is, the p-type impurity implanted layer 35. Accordingly, the conductivity of the polycrystalline silicon layer 12 along the insulating film 32 (that is, the injection layer 35) can be reduced by reducing the electron concentration, and the leakage current through the insulating films 33 and 32 can be reduced. .

  Further, even when the polycrystalline silicon layer 14 remains on the polycrystalline silicon layer 12 in the region 44 due to insufficient etching, the polycrystalline silicon layer 12 and the edge of the remaining polycrystalline silicon layer 14 Similarly, p-type impurities are implanted and n-type impurities are not implanted. Therefore, the electron concentration at the edge of the remaining polycrystalline silicon layer 14 can be lowered to reduce the conductivity, and the leakage current between the adjacent polycrystalline silicon layers 14 across the region 44 can be reduced. Note that as the boundary of the photoresist 46, the upper surface of the polycrystalline silicon layer 12 is exposed in the region 44, and preferably a portion of 50 nm or more along the second direction from the edge (end) of the upper surface of the polycrystalline silicon layer 12. To be exposed. FIG. 36 shows the case where the photoresist 46 is not opened on the region 44 for the dummy element, because this region is not used as a circuit element. May be.

  When the intergate insulating film 13 in the region 44 is peeled off by etching, the underlying polycrystalline silicon layer 12 is also etched, and the etching depth varies. For this reason, when the polycrystalline silicon layer 12 is used as a resistance element, the depth and dose amount of impurities ion-implanted into that portion also vary. However, in this embodiment, n-type impurities are implanted into the polycrystalline silicon layer 12 in the region 44. Therefore, the electron concentration can be increased more than before injection. Thereby, the absolute value of the series resistance component of the polycrystalline silicon layer 12 in the region 44 can be reduced. For this reason, when the polycrystalline silicon layer 12 is used as a resistance element, variation in the resistance value in the region shown in FIG. 38 can be reduced, and the accuracy as the resistance element can be improved. As a result, since the fluctuation range of the resistance value is small, the relative fluctuation of the resistance value is small, and it is not necessary to ensure a large timing margin when used in the circuit timing generation circuit.

Further, as shown in FIG. 38, in the region 44, a part of the insulating film 32 in the element isolation region STI is deeply etched to form a recess 38. Then, when the n-type impurity ions are implanted, if the recess 38 becomes deep, there is a possibility that the semiconductor substrate 10 under the element isolation insulating film STI is implanted. However, in the present embodiment, the recess 38 is filled with the photoresist 46. Therefore, the problem that the n-type impurity is implanted into the semiconductor substrate 10 does not occur. Therefore, the problem of capacitive coupling between the region where the n-type impurity is implanted in the semiconductor substrate 10 and the resistance element is alleviated, and an increase in parasitic capacitance can be suppressed. Thereby, there is no problem that the CR time constant of the resistance element increases, and it can be used as a resistance element of a circuit operating at high speed.
Note that the n-type impurity implantation step described with reference to FIGS. 36 to 39 may be performed in a different order from the p-type impurity implantation step illustrated in FIGS. 32 to 35 or may not be a continuous step. Further, even if the photoresist patterning process described in FIGS. 36 to 39 is performed independently of the photoresist patterning process of FIGS. 32 to 35, the n-type impurity is not implanted into the region 47. Also, since the effect of implanting the p-type impurity at the position of the region 47 is obtained independently, there is no problem.

  Thereafter, an interlayer insulating film 19 is formed on the entire surface so as to cover the resistance element and the memory cell array. The interlayer insulating film 19 is formed of, for example, silicate glass such as BPSG, BSG, or PSG, HSQ, MSQ, SiLK, or the like, and the film thickness is, for example, 100 nm or more and 1 μm or less. Next, the interlayer insulating film 19 is planarized by CMP. Subsequently, a contact hole reaching the metal layer 15 in the regions A1 and A3 is formed in the interlayer insulating film 19 with a diameter of about 20 nm to 200 nm, for example. Further, a groove is formed on the surface of the interlayer insulating film 19 such that the upper surface of the contact hole is located at the bottom. The depth of the groove is, for example, about 50 nm to 500 nm. Thereafter, a barrier metal layer such as Ti, TiN, or TaN is formed in the trench and the contact hole, and further, W, Cu, or the like is embedded therein, and these are planarized by CMP. As a result, contact plugs 36 and 37 and metal wiring layers 38 and 39 as shown in FIG. 8 are formed. In FIG. 8, the contact plugs 36 and 37 and the metal wiring layers 38 and 39 are shown as being separate, but can be integrally formed by the same process as described above. Needless to say, the metal wiring layers 38 and 39 may be formed by forming W and Al on the interlayer insulating film 19 after forming the contact plugs 36 and 37 and etching them into a wiring shape by RIE. In this step, contact plugs CP2 and CP3 and metal wiring layers 20 and 21 in the memory cell array 2 are also formed. Thereafter, an interlayer insulating film 22 is further formed on the interlayer insulating film 19. Then, the contact plug CP4 and the metal wiring layer 23 are formed in the memory cell array 2. As a result, the memory cell array 2 shown in FIGS. 2 to 4 and the resistance element shown in FIGS. 5 to 8 are completed.

  FIG. 1 shows an example in which two polycrystalline silicon layers 12 adjacent in the second direction adjacent to each other are connected by the contact plug 36 and the metal wiring layer 38. With this configuration, the voltage applied to one polycrystalline silicon layer 12 is 5 V or less, and the potential difference generated between the polycrystalline silicon layers 12 and 14 is kept low, while being generated between the metal wiring layers 37. A high voltage of 20 V or higher can be divided, and the reliability of the resistance element can be improved.

[Second Embodiment]
Next explained is a semiconductor device and its manufacturing method according to the second embodiment of the invention. The present embodiment relates to the configuration of the capacitive element included in the peripheral circuit 3 in the first embodiment. Note that the configuration and manufacturing method of the capacitive element according to the present embodiment has many parts similar to those of the resistive element described in the first embodiment, and therefore, the following description will be focused on differences from the resistive element.

  The capacitive element according to the present embodiment is used in a peripheral circuit 3 for a charge pump circuit that generates a positive or negative high voltage. Of course, the application is not limited to the charge pump circuit. This capacitive element is formed on the same semiconductor substrate 10 as the memory cell array 2 of the NAND flash memory described in the first embodiment.

  FIG. 40 is a plan view of the capacitive element according to the present embodiment. 41 to 43 are sectional views of the capacitive element according to the present embodiment, and are sectional views taken along lines X4-X4 ′, X5-X5 ′, and Y3-Y3 ′ in FIG. 40, respectively. . Note that the plan view of FIG. 40 shows a planar structure at the level of the surfaces of the insulating films 18 and 16.

  FIG. 40 shows a configuration in which two capacitive elements each having a stripe shape along the first direction are provided. Each capacitive element is formed between the metal wiring layer 58 and the n-type impurity diffusion layer 50 formed in the semiconductor substrate 10, and the gate insulating film 60 and the inter-gate insulating film 13 function as a capacitor insulating film. In the present embodiment, in order to ensure a large capacitance with the semiconductor substrate 10, the gate insulating film 60 is, for example, the same insulating film as the gate insulating film 11 serving as a tunnel oxide film, that is, a film thickness of 4 nm to 12 nm. It is preferable to use a silicon oxide film or silicon oxynitride film in the range. Hereinafter, the configuration of the capacitive element will be described in detail.

  As shown in the drawing, in the semiconductor substrate 10, for example, four stripe-shaped element regions AA along the first direction are formed along the second direction, similarly to the resistance element described in the first embodiment. ing. The capacitor element is formed on the element region AA. In FIG. 40, of the four element regions AA, only the capacitive element formed on the two central element areas AA functions as an actual capacitive element, and the outer two are dummy capacitive elements. Become. Hereinafter, for simplification of description, a dummy element is referred to as a “dummy element”, and an element that functions as an actual capacitance element is referred to as a “capacitance element”. That is, the two capacitive elements are sandwiched between the two dummy elements in the second direction. Of course, two or more resistance elements may be sandwiched between the dummy elements, or the dummy elements may not be provided. Since the dummy element and the resistance element have substantially the same configuration, the configuration of the resistance element will be described below, but the configuration of both is the same unless otherwise specified.

An element isolation region STI is formed in a region between the element regions AA. The configuration of the element isolation region STI is the same as that of the first embodiment. An n-type impurity diffusion layer 50 is formed in the surface of the element region AA. Polycrystalline silicon layer 12 is formed on diffusion layer 50 in element region AA with gate insulating film 60 interposed. A polycrystalline silicon layer 14, a metal layer 15, and an insulating film 16 are sequentially formed on the polycrystalline silicon layer 12 with an intergate insulating film 13 interposed therebetween. In each element region AA, the intergate insulating film 13, the polycrystalline silicon layer 14, the metal layer 15, and the insulating film 16 are divided into two regions along the first direction (FIGS. 40 and 43). reference). Hereinafter, the two areas will be referred to as areas A4 and A5, respectively, and the area for separating them will be referred to as area 51. In the region facing the region A4 along the first direction across the region A5, the gate insulating film 60, the polycrystalline silicon layers 12 and 14, the inter-gate insulating film 13, the metal layer 15, and the insulating film 16 are Has been removed. This area is hereinafter referred to as area A6 (see FIGS. 40 and 43). In the region A6, an n ⁺ -type impurity diffusion layer 52 is formed in the surface of the diffusion layer 50. In FIG. 40, since the planar patterns of the element region AA and the diffusion layer 50 are the same, both are denoted by reference numeral AA (50).

The insulating film 32 in the element isolation region STI is formed up to a position higher than the surface of the polycrystalline silicon layer 12. An insulating film 33 is formed between the polycrystalline silicon layer 12 and the insulating film 32. Further, in the region A2, an impurity implantation region 35 is formed in a region in contact with the insulating film 33 in the polycrystalline silicon layer 12. The impurity implanted region 35 has a higher resistivity and lower conductivity than the other polycrystalline silicon layers 12. Furthermore, in the element isolation region STI in the region 51 between the regions A4 and A5, a part of the insulating film 32 is removed, and a groove 38 as shown in FIG. 42 is formed. In the semiconductor substrate 10, ap ⁺ -type impurity implantation layer 47 is formed in a region located immediately below the trench 38 so as to be in contact with the insulating film 31. Further, in the region A4, a part of the inter-gate insulating film 13 is removed, thereby forming an opening 53. The polycrystalline silicon layers 12 and 14 are electrically connected through the opening 53.

  In the regions A4 and A5, a sidewall insulating film 18 is further formed on the sidewalls of the polycrystalline silicon layer 14, the metal layer 15, and the insulating film 16 and on the sidewalls of the trench 38. A sidewall insulating film 18 is also formed on the sidewalls of the intergate insulating film 13 and the polycrystalline silicon layer 12 at the boundary between the regions A5 and A6. An interlayer insulating film 19 is formed on the semiconductor substrate 10 so as to cover the capacitive element. In the interlayer insulating film 19, contact plugs 55 and 56 reaching the metal layer 15 in the regions A4 and A5 and a contact plug 57 reaching the diffusion layer 52 are formed. Further, a metal wiring layer 58 connected to the contact plug 55 and a metal wiring layer 59 connected to the contact plugs 56 and 57 are formed in the interlayer insulating film 19.

  In the above configuration, the metal layer 15 and the polycrystalline silicon layers 12 and 14 in the region A4 and the polycrystalline silicon layer 12 in the regions A4 and A5 function as one electrode of the capacitor. Further, the polycrystalline silicon layer 14 and the metal layer 15 in the region A4, and the diffusion layers 50 and 52 in the regions A4 to A6 function as the other electrode of the capacitor. The gate insulating film 60 and the inter-gate insulating film 13 function as a capacitor insulating film.

  That is, the configuration of the capacitive element according to the present embodiment can be described as follows. That is, one capacitive element includes a first capacitive element and a second capacitive element. First, the polycrystalline silicon layer 12 functions as one electrode, the polycrystalline silicon layer 14 in the region A5 functions as the other electrode, and the inter-gate insulating film 13 in the region A5 functions as a capacitor insulating film. Is formed. Furthermore, the polycrystalline silicon layer 12 functions as one electrode, the diffusion layer 50 functions as the other electrode, and the gate insulating film 60 functions as a capacitor insulating film, thereby forming the second capacitor element. The other electrodes of the first and second capacitive elements are connected by a metal wiring layer 59. In this configuration, a potential difference is applied between the metal wiring layer 58 and the diffusion layer 50. As described above, with the configuration according to the present embodiment, the first capacitive element and the second capacitive element are stacked, thereby realizing a capacitive element having an improved capacitance per unit area. As shown in FIG. 40, a plurality of capacitive elements having a stripe shape along the first direction of the above configuration are arranged along the second direction.

  Note that the number of capacitive elements is not limited to two. Further, the width in the second direction of the polycrystalline silicon layer 12 and the adjacent interval of each capacitive element are the same. The polycrystalline silicon layers 12 and 14 and the metal layer 15 may be conductive layers, but are formed of the same material as the memory cell array described with reference to FIGS.

  Next, a method for manufacturing the capacitor having the above structure will be described with reference to FIGS. First, n-type impurities are implanted into the surface of the semiconductor substrate 10 to form the n-type impurity diffusion layer 52. 9 to 25 described in the first embodiment, the element isolation region STI, the gate insulating film 60, the polycrystalline silicon layers 12 and 14, the inter-gate insulating film 13, the metal layer 15, Then, the insulating film 16 is formed. Further, a similar opening 53 is formed in the region A4 instead of the opening 34 in FIG. Subsequent steps will be described as the first step and below.

  First, the first step will be described with reference to FIGS. FIG. 44 is a plan view of the capacitive element and shows the same region as FIG. 45 and 46 are sectional views taken along lines X4-X4 'and Y3-Y3' in FIG.

  As shown in the figure, the polycrystalline silicon layer 14, the metal layer 15, and the insulating film 16 are etched by anisotropic etching in the same manner as in the steps of FIGS. 26 to 28 described in the first embodiment. That is, in the peripheral circuit 3, the layers 14 to 16 are processed into a stripe shape along the first direction and are separated from each other along the second direction. At this time, the layers 14 to 16 remain in the regions A4 and A5, but are removed together with the intergate insulating film 13 and the polycrystalline silicon layer 12 in the region A6. As a result, the surface of the gate insulating film 13 is exposed in the region A6. At the same time, in the memory cell array 2, the layers 14 to 16 are etched to form a stacked gate of the memory cell transistor MT.

  As described in the first embodiment, the shape protrudes outward from the end of the element region AA (ie, the diffusion layer 50 and the polycrystalline silicon layer 12) by about 0.02 μm to 0.5 μm. In this step, the width of the capacitor element and the dummy element is sufficiently larger than that of the memory cell transistor MT, and therefore it is not always necessary to perform lithography and etching with the same high accuracy and high resolution as those of the memory cell array 2. That is, if photolithography and etching of the memory cell array 2 are separate steps, it can be performed by inexpensive lithography with lower resolution. In this case, if the width of the capacitive element and the dummy element, which is widened in the range from 0.02 μm to 0.5 μm from the end of the element area AA, is larger than the alignment accuracy with the element area AA, Since the capacitance through the inter-gate insulating film 13 hardly fluctuates, a capacitive element with high parasitic capacitance accuracy can be realized even by using inexpensive lithography.

  Next, the second step will be described with reference to FIGS. FIG. 47 is a plan view of the capacitive element and shows the same region as FIG. 48 and 49 are sectional views taken along lines X4-X4 'and Y3-Y3' in FIG.

  As shown in FIGS. 47 and 49, the polycrystalline silicon layer 14, the metal layer 15, and the insulating film 16 in the peripheral circuit 3 are etched by photolithography and anisotropic etching. This etching is performed so as to remove each of the layers 14 to 16 along the second direction. As a result, each layer 14-16 is isolate | separated into area | region A4, A5. Each region is electrically separated by region 51. The length of the region 51 along the first direction is, for example, not less than 50 nm and not more than 1 μm. As described above, in the capacitor element, the region 51 can be formed by an inexpensive low-resolution lithography apparatus. Etching is performed so that the position of the region 51 is close to the opening 53. Thereby, the length along the first direction of the region A5 can be increased, and the electrode facing area of the capacitive element using the inter-gate insulating film 13 as the capacitor insulating film can be secured.

  The etching in this step uses etching conditions in which the etching rate of the silicon oxide film is slower than that of the polycrystalline silicon layer 14. As a result, as shown in FIG. 49, the inter-gate insulating film 13 in the region 51 remains. Thereby, it is possible to prevent part of the polycrystalline silicon layer 12 from being etched in the region 51. Further, similarly to the first embodiment, as shown in FIG. 48, the surface of the insulating film 32 in the region 51 is also etched, and a recess 38 is formed in the element isolation region STI.

  Next, the third step will be described with reference to FIGS. FIG. 50 is a plan view of the capacitive element, and shows the same region as FIG. 51 to 53 are sectional views taken along lines X4-X4 ', X5-X5', and Y3-Y3 'in FIG. In this step, the sidewall insulating film 18 is first formed, as in the steps of FIGS. 32 to 35 described in the first embodiment. The difference from the first embodiment is that the side surfaces of the polycrystalline silicon layer 12 and the intergate insulating film 13 are exposed at the boundary between the regions A5 and A6. Is formed.

  Thereafter, a p-type impurity implantation step similar to that of the first embodiment is performed. At this time, the photoresist 45 has a stripe shape along the first direction in the regions A4 and A5, and the width thereof is smaller than the width of the polycrystalline silicon layer 12 (length along the second direction). The photoresist 45 is formed so as to be completely placed on the insulating film 16 in the regions A4 and A5. That is, as shown in FIG. 50, in the regions A4 and A5, the upper surfaces of the insulating films 16 and 18 on which the photoresist 45 is placed are exposed on both sides of the photoresist 45 along the second direction. Further, in the region 51, the photoresist 45 is formed on the polycrystalline silicon layer 12, and the upper surface of the polycrystalline silicon layer 12 on which the photoresist 45 is placed is exposed on both sides of the photoresist 45. Further, the upper surface of the element isolation region STI between the sidewall insulating films 18 in the regions A4 and A5, and the upper surface of the element isolation region STI between the polycrystalline silicon layers 12 and the bottom surface of the recess 38 are exposed in the region 51. In the region A6, the entire surface is covered with the photoresist 45. That is, the diffusion layer 50 in the region A6 is covered with the photoresist 45.

After the photolithography process, ion implantation of p-type impurities is performed in order to form the source and drain diffusion layers of the p-type MISFET formed on the same semiconductor substrate 10. Boron or BF ₂ is used as the p-type implantation impurity, and an implantation amount of 10 ¹⁴ cm ⁻² to 10 ¹⁶ cm ⁻² is used as the implantation energy with an energy between 2 keV and 40 keV. By this ion implantation, a p-type impurity implantation layer 47 is formed in the semiconductor substrate 10 through the groove of the region 51 and the bottom of the recess of the insulating film 32. A p-type impurity implantation layer 35 is also formed in the region 51. As a result, in the polycrystalline silicon layer 12, the electron concentration in the p-type impurity implantation layer 35 is lowered. As a result, the leakage current through the insulating films 33 and 32 can be reduced. The details of this step and the effects of the injection layers 35 and 47 are as described in the first embodiment.

  Next, the fourth step will be described with reference to FIGS. FIG. 54 is a plan view of the capacitive element and shows the same region as FIG. 55 and 57 are sectional views taken along lines X4-X4 ', X5-X5', and Y3-Y3 'in FIG. In this step, an n-type impurity is implanted into the central portion of the polycrystalline silicon layer 12 in the region 51 as in the steps of FIGS. 36 to 39 described in the first embodiment.

  After removing the photoresist 45, a photoresist 46 is applied again on the entire surface. Then, the photoresist 46 is patterned by a photolithography process as shown in FIGS. That is, the photoresist 46 has a stripe-shaped opening along the first direction, and the surface of the polycrystalline silicon layer 12 in the region 51 and the surface of the insulating film 16 in the regions A4 and A5 are in the opening. Patterned to expose. At this time, patterning is performed so that the photoresist 46 covers the insulating film 32 between the adjacent capacitive elements and the upper surface of the p-type impurity implantation layer 35. Further, in the region A6, the photoresist 46 is removed, and the surface of the element isolation region STI and the surface of the diffusion layer 52 are exposed. Therefore, in the region 51, the central portion of the polycrystalline silicon layer 12, that is, the upper surface of the region where the p-type impurity is not implanted in FIGS. 50 to 53 is exposed. That is, in the region 51, a region separated by 50 nm or more from the end portion of the polycrystalline silicon layer 12 along the second direction is exposed. This step increases the number of steps by using the same steps as the photoresist coating step and the photolithography step that are performed to selectively ion-implant n-type impurities for forming an n-type source / drain diffusion layer described later. Can be prevented.

After the photolithography process, ion implantation of n-type impurities is performed as in FIGS. 36 to 39 described in the first embodiment. As described above, the n-type implanted impurity used is phosphorus or arsenic, the implantation energy is an energy between 5 keV and 60 keV, and the implantation amount is about 10 ¹⁴ cm ⁻² to 10 ¹⁶ cm ⁻² .

  In this step, the n-type impurity is not implanted into the edge of the polycrystalline silicon layer 12 in the region 51, that is, the p-type impurity implanted layer 35. Accordingly, the conductivity of the polycrystalline silicon layer 12 along the insulating film 32 (that is, the injection layer 35) can be reduced by reducing the electron concentration, and the leakage current through the insulating films 33 and 32 can be reduced. . Further, the same effect can be obtained even when the polycrystalline silicon layer 14 remains in the region 51. Note that, as the boundary of the photoresist 46, the upper surface of the polycrystalline silicon layer 12 is exposed in the region 51, and preferably a portion of 50 nm or more along the second direction from the edge (end) of the upper surface of the polycrystalline silicon layer 12 To be exposed. FIG. 54 shows the case where the photoresist 46 is not opened on the region 51 for the dummy element. This is because this region is not used as a circuit element. May be.

  When the inter-gate insulating film 13 in the region 51 is peeled off by etching, the underlying polycrystalline silicon layer 12 is also etched, and the etching depth varies. For this reason, the depth and dose of impurities implanted into the polycrystalline silicon layer 12 also vary. However, in this embodiment, n-type impurities are implanted into the polycrystalline silicon layer 12 in the region 51. Therefore, the electron concentration can be increased more than before injection. Thereby, the absolute value of the series resistance component of the polycrystalline silicon layer 12 in the region 44 can be reduced. For this reason, when the polycrystalline silicon layer 12 is used as an electrode of a capacitive element, the parasitic resistance value of the electrode portion can be reduced and the accuracy of the capacitive element can be improved. As a result, since the absolute value and fluctuation range of the series parasitic resistance are small, a circuit having a small time constant can be formed when used in a circuit timing generation circuit, and a circuit operating at higher speed can be created.

Further, as shown in FIG. 56, in the region 51, a part of the insulating film 32 in the element isolation region STI is deeply etched to form a recess 38. Then, when the n-type impurity ions are implanted, if the recess 38 becomes deep, there is a possibility that the semiconductor substrate 10 under the element isolation insulating film STI is implanted. However, in the present embodiment, the recess 38 is filled with the photoresist 46. Therefore, the problem that the n-type impurity is implanted into the semiconductor substrate 10 does not occur. Therefore, the fluctuation range of the capacitance of the capacitive element can be reduced, and when used in a circuit timing generation circuit, an operation margin can be secured even if the timing margin is reduced.
Note that the n-type impurity implantation step described with reference to FIGS. 54 to 57 may be performed in the same order as the p-type impurity implantation step in FIGS. 50 to 53, or may not be a continuous process. Further, even if the photoresist patterning process described with reference to FIGS. 54 to 57 is performed independently of the photoresist patterning process of FIGS. Also, since the effect of implanting the p-type impurity at the position of the region 47 is obtained independently, there is no problem.

  Thereafter, interlayer insulating films, contact plugs, metal wiring layers, and the like are formed in the same manner as in the first embodiment, and the capacitive element shown in FIGS. 40 to 43 is completed.

The embodiment of the present invention is not limited to the above. For example, as an insulating film for element isolation or an insulating film forming method, a method other than converting silicon into a silicon oxide film or a silicon nitride film may be used. For example, a method of injecting oxygen ions into the deposited silicon or a method of oxidizing the deposited silicon may be used. Further, the gate insulating film 13, Ti0 ₂ or _{HfO, Al 2 0 3, HfAlO} , HfSiO, tantalum oxide film, a barium strontium titanate and titanate, lead zirconium titanate, silicon oxynitride film, a silicon oxide film, a silicon A nitride film or a laminated film of these may be used.

  In the above embodiment, an example in which a p-type silicon substrate is used as the semiconductor substrate 10 has been described. However, an n-type silicon substrate or an SOI substrate may be used instead of the p-type silicon substrate, or another single crystal semiconductor substrate containing silicon such as a SiGe mixed crystal or SiGeC mixed crystal may be used. Furthermore, the metal layer 16 can use a metal such as silicide or polycide such as SiGe mixed crystal, SiGeC mixed crystal, TiSi, NiSi, CoSi, TaSi, WSi, and MoSi, Ti, A1, Cu, TiN, and W, It may be polycrystalline or may be a layered product. Further, amorphous silicon, amorphous SiGe, or amorphous SiGeC can be used in place of the polycrystalline silicon layers 12 and 14, and a laminated structure thereof may be used.

  In the capacitive element described in the second embodiment, the polysilicon layer 14 and the metal layer 15 in the region A2 in the first embodiment may be provided between the regions A4 and A5. That is, the polycrystalline silicon layer 12 and the metal layer 15 may be provided on the polycrystalline silicon layer 12 with the inter-gate insulating film 13 interposed between the regions A4 and A5. In this case, the newly provided polycrystalline silicon layer 14 and the metal layer 15 are electrically separated from the polycrystalline silicon layer 14 and the metal layer 15 in the regions A4 and A5 by the region 51. Furthermore, also in the second embodiment, similarly to the first embodiment, a plurality of capacitive elements arranged along the second direction may be electrically connected to each other by the metal wiring layer 58 or 59.

That is, the semiconductor device according to the first embodiment of the present invention includes a first element isolation region (element isolation region STI in the memory cell array 2, see FIGS. 2 and 4) formed in the semiconductor substrate 10.
A first semiconductor region (element region AA in the memory cell array 2, see FIG. 2 and FIG. 4) electrically isolated from each other by the first element isolation region;
A memory cell (memory cell transistor MT, see FIG. 3) formed on the first semiconductor region and capable of holding data;
A second element isolation region formed in the semiconductor substrate 10 (element isolation region STI in the peripheral circuit 3, see FIGS. 5 to 8);
Stripe-shaped second semiconductor regions (element regions AA in the peripheral circuit 3, see FIG. 5) electrically isolated from each other by the second element isolation regions;
The stripe-shaped resistance element (polycrystalline silicon layers 12 and 14, metal layer 15 and region 44 in the peripheral circuit 3, see FIGS. 5 to 8) formed on the second semiconductor region;
First and second metal wiring layers connected to one end and the other end of the resistance element (see metal wiring layers 39 and 38 in the peripheral circuit 3, FIGS. 5 and 8),
A third semiconductor region (p-type impurity implantation layer 47 in the peripheral circuit 3, see FIGS. 5 and 7) formed in the semiconductor substrate immediately below the second element isolation region.
As shown in FIG. 3, the memory cell includes a first conductive type floating gate electrode 12 formed on the first semiconductor region with a first insulating film 11 interposed therebetween, and a floating gate electrode 12 on the floating gate electrode 12. And control gate electrodes 14 and 15 formed with a second insulating film 13 interposed therebetween.
Further, as shown in FIGS. 5 to 8, the resistance element includes a conductor layer 12 formed on the second semiconductor region with a third insulating film 60 interposed, and a stripe shape of the conductor layer 12. First electrodes (polycrystalline silicon layer 14 and metal layer 15 in region A1, see FIG. 8) that are electrically connected to both ends in the longitudinal direction and connected to the first and second metal wiring layers 39 and 38, respectively. ) And the second electrode (polycrystalline silicon layer 14 and metal layer 15 in region A3, see FIG. 8) and the electrode separation region (region 44, FIG. 5 and FIG. 8) for electrically separating the first and second electrodes. Reference).
Further, the conductor layer (polycrystalline silicon layer 12 in the peripheral circuit 3) is formed in a self-aligned manner with respect to the second element isolation region,
The floating gate electrode 12 and the conductor layer 12 are formed using the same material,
The control gate electrodes 14 and 15 and the first and second electrodes (polycrystalline silicon layer 14 and metal layer 15 in the peripheral circuit 3) are formed using the same material,
The second element isolation region adjacent to the electrode isolation region 44 has a recess 38 (see FIGS. 5 and 7) on the surface,
The third semiconductor region 47 has a second conductivity type opposite to the first conductivity type, and is provided immediately below the recess 38 in the second element isolation region (see FIG. 7).

Furthermore, the semiconductor device according to the second embodiment of the present invention includes a first element isolation region (element isolation region STI in the memory cell array 2, see FIGS. 2 and 4) formed in the semiconductor substrate 10.
A first semiconductor region (element region AA in the memory cell array 2, see FIG. 2 and FIG. 4) electrically isolated from each other by the first element isolation region;
A memory cell (memory cell transistor MT, see FIG. 3) formed on the first semiconductor region and capable of holding data;
A second element isolation region (element isolation region STI in the peripheral circuit 3, see FIGS. 40 to 43) formed in the semiconductor substrate;
A second semiconductor region (element region AA in the peripheral circuit 3, see FIGS. 40 to 43) electrically isolated from each other by the second element isolation region;
A capacitive element formed on the second semiconductor region (polycrystalline silicon layers 12 and 14, intergate insulating film 13, metal layer 15 and region 51 in the peripheral circuit 3, see FIGS. 40 to 43);
First and second metal wiring layers (refer to metal wiring layers 59 and 58 in the peripheral circuit 3, see FIGS. 40 and 43) respectively connected to one electrode and the other electrode of the capacitive element;
A third semiconductor region (p-type impurity implantation layer 47 in the peripheral circuit 3, see FIGS. 40 and 42) formed in the semiconductor substrate immediately below the second element isolation region.
As shown in FIG. 3, the memory cell includes a first conductive type floating gate electrode 12 formed on the first semiconductor region with a first insulating film 11 interposed therebetween, and a floating gate electrode 12 on the floating gate electrode 12. And control gate electrodes 14 and 15 formed with a second insulating film 13 interposed therebetween.
As shown in FIGS. 40 to 43, the capacitive element is formed on the conductor layer 12 formed on the second semiconductor region with a third insulating film 60 interposed therebetween, and on the conductor layer 12. A fourth insulating film 13; a first electrode (polycrystalline silicon layer 14 and metal layer 15 in region A5) formed on the fourth insulating film 13 and connected to the first metal wiring layer 59; A second electrode (polycrystalline silicon layer 14 and metal layer 15 in region A4) formed to be electrically connected to body layer 12 and connected to second metal wiring layer 58; And an electrode separation region (see region 51, FIG. 40 and FIG. 43) for electrically separating the two electrodes.
Further, the conductor layer (polycrystalline silicon layer 12 in the peripheral circuit 3) is formed in a self-aligned manner with respect to the second element isolation region,
The floating gate electrode 12 and the conductor layer 12 are formed using the same material,
The control gate electrodes 14 and 15 and the first and second electrodes (polycrystalline silicon layer 14 and metal layer 15 in the peripheral circuit 3) are formed using the same material,
The second element isolation region adjacent to the electrode isolation region 51 has a recess 38 (see FIGS. 40 and 42) on the surface,
The third semiconductor region 47 has a second conductivity type opposite to the first conductivity type, and is provided immediately below the recess 38 in the second element isolation region (see FIG. 42).

  Note that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention in the implementation stage. Further, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, the problem described in the column of the problem to be solved by the invention can be solved, and the effect described in the column of the effect of the invention Can be extracted as an invention.

1 is a block diagram of a flash memory according to a first embodiment of the present invention. 1 is a plan view of a memory cell array provided in a flash memory according to a first embodiment of the present invention. FIG. 3 is a cross-sectional view taken along line Y1-Y1 ′ in FIG. 2. FIG. 3 is a cross-sectional view taken along line X1-X1 ′ in FIG. 2. 1 is a plan view of a resistance element included in a flash memory according to a first embodiment of the present invention. FIG. 6 is a cross-sectional view taken along line X2-X2 ′ in FIG. 5. Sectional drawing along the X3-X3 'line | wire in FIG. FIG. 6 is a cross-sectional view taken along line Y2-Y2 'in FIG. FIG. 6 is a plan view of a first manufacturing process of the resistance element included in the flash memory according to the first embodiment of the present invention. 1 is a cross-sectional view of a memory cell array in a first manufacturing process of a resistance element included in a flash memory according to a first embodiment of the present invention. FIG. 10 is a cross-sectional view taken along a line X2-X2 ′ in FIG. 9, in a first manufacturing process of the resistance element included in the flash memory according to the first embodiment of the present invention. FIG. 10 is a cross-sectional view taken along a line Y2-Y2 ′ in FIG. 9, illustrating a first manufacturing process of the resistance element included in the flash memory according to the first embodiment of the present invention. Sectional drawing of the memory cell array in the 2nd manufacturing process of the resistive element with which the flash memory which concerns on 1st Embodiment of this invention is provided. FIG. 10 is a cross-sectional view of the resistance element included in the flash memory according to the first embodiment of the present invention in a second manufacturing process, corresponding to a line X2-X2 ′ in FIG. 9; FIG. 10 is a cross-sectional view of the resistance element included in the flash memory according to the first embodiment of the present invention in a second manufacturing process, corresponding to the Y2-Y2 ′ line in FIG. 9. Sectional drawing of the memory cell array in the 3rd manufacturing process of the resistive element with which the flash memory which concerns on 1st Embodiment of this invention is provided. FIG. 10 is a cross-sectional view of the resistance element included in the flash memory according to the first embodiment of the present invention in a third manufacturing process, corresponding to the line X2-X2 ′ in FIG. 9; FIG. 10 is a cross-sectional view of the resistance element included in the flash memory according to the first embodiment of the present invention in a third manufacturing process, corresponding to the line Y2-Y2 ′ in FIG. 9. The top view of the 4th manufacturing process of the resistance element with which the flash memory which concerns on 1st Embodiment of this invention is provided. Sectional drawing of the memory cell array in the 4th manufacturing process of the resistive element with which the flash memory which concerns on 1st Embodiment of this invention is provided. FIG. 20 is a cross-sectional view taken along a line X2-X2 ′ in FIG. 19, which is a cross-sectional view in the fourth manufacturing process of the resistive element included in the flash memory according to the first embodiment of the present invention. FIG. 20 is a cross-sectional view taken along a Y2-Y2 ′ line in FIG. 19, in a fourth manufacturing process of the resistance element included in the flash memory according to the first embodiment of the present invention. Sectional drawing of the memory cell array in the 5th manufacturing process of the resistive element with which the flash memory which concerns on 1st Embodiment of this invention is provided. FIG. 20 is a cross-sectional view of the resistance element included in the flash memory according to the first embodiment of the present invention in the fifth manufacturing process, corresponding to the line X2-X2 ′ in FIG. 19; FIG. 20 is a cross-sectional view of the resistor element included in the flash memory according to the first embodiment of the present invention in a fifth manufacturing process, corresponding to the line Y2-Y2 ′ in FIG. 19. A top view of the 6th manufacturing process of a resistance element with which a flash memory concerning a 1st embodiment of this invention is provided. FIG. 27 is a cross-sectional view of the resistance element included in the flash memory according to the first embodiment of the present invention in a sixth manufacturing process, taken along line X2-X2 ′ in FIG. 26. FIG. 27 is a cross-sectional view taken along the line Y2-Y2 ′ in FIG. 26, showing a cross-sectional view in the sixth manufacturing process of the resistive element included in the flash memory according to the first embodiment of the present invention. A top view of the 7th manufacturing process of a resistance element with which a flash memory concerning a 1st embodiment of this invention is provided. FIG. 30 is a cross-sectional view taken along a line X3-X3 ′ in FIG. 29, illustrating a seventh embodiment of the resistance element included in the flash memory according to the first embodiment of the present invention. FIG. 29 is a cross-sectional view taken along the line Y2-Y2 ′ in FIG. 29, showing a cross-sectional view in the seventh manufacturing process of the resistive element included in the flash memory according to the first embodiment of the present invention. The top view of the 8th manufacturing process of the resistive element with which the flash memory which concerns on 1st Embodiment of this invention is provided. FIG. 33 is a cross-sectional view taken along the line X2-X2 ′ of FIG. 32, illustrating a resistance element included in the flash memory according to the first embodiment of the present invention in an eighth manufacturing process. FIG. 33 is a cross-sectional view taken along the line X3-X3 ′ in FIG. 32, illustrating a resistance element included in the flash memory according to the first embodiment of the present invention in an eighth manufacturing process. FIG. 33 is a cross-sectional view taken along the line Y2-Y2 ′ of FIG. 32, illustrating a resistance element included in the flash memory according to the first embodiment of the present invention in an eighth manufacturing process. A top view of the 9th manufacturing process of a resistance element with which a flash memory concerning a 1st embodiment of this invention is provided. FIG. 37 is a cross-sectional view taken along the line X2-X2 ′ of FIG. 36, illustrating a ninth embodiment of the resistive element included in the flash memory according to the first embodiment of the present invention. FIG. 37 is a cross-sectional view taken along the line X3-X3 ′ in FIG. 36, illustrating a ninth embodiment of the resistive element included in the flash memory according to the first embodiment of the present invention. FIG. 37 is a cross-sectional view taken along a line Y2-Y2 ′ in FIG. 36, illustrating a ninth embodiment of the resistive element included in the flash memory according to the first embodiment of the present invention. The top view of the capacitive element with which the flash memory which concerns on 2nd Embodiment of this invention is provided. FIG. 41 is a cross-sectional view taken along line X4-X4 ′ in FIG. 40. FIG. 41 is a sectional view taken along line X5-X5 ′ in FIG. 40. FIG. 41 is a cross-sectional view taken along line Y3-Y3 'in FIG. The top view of the 1st manufacturing process of the capacitive element with which the flash memory which concerns on 2nd Embodiment of this invention is provided. FIG. 45 is a cross-sectional view taken along the line X4-X4 ′ of FIG. 44, illustrating a first manufacturing process of the capacitive element included in the flash memory according to the second embodiment of the present invention. FIG. 45 is a cross-sectional view taken along the line Y3-Y3 ′ in FIG. 44, illustrating a cross-sectional view in the first manufacturing process of the capacitive element included in the flash memory according to the second embodiment of the present invention. The top view of the 2nd manufacturing process of the capacitive element with which the flash memory which concerns on 2nd Embodiment of this invention is provided. FIG. 48 is a cross-sectional view of the capacitive element included in the flash memory according to the second embodiment of the present invention in a second manufacturing process, taken along line X5-X5 ′ in FIG. 47. FIG. 48 is a cross-sectional view taken along the line Y3-Y3 ′ in FIG. 47, illustrating a cross-sectional view in the second manufacturing process of the capacitive element included in the flash memory according to the second embodiment of the present invention. The top view of the 3rd manufacturing process of the capacitive element with which the flash memory which concerns on 2nd Embodiment of this invention is provided. FIG. 52 is a cross-sectional view taken along the line X4-X4 ′ in FIG. 50, illustrating a third manufacturing process of the capacitive element included in the flash memory according to the second embodiment of the present invention. FIG. 52 is a cross-sectional view taken along the line X5-X5 ′ in FIG. 50, illustrating a third manufacturing process of the capacitive element included in the flash memory according to the second embodiment of the present invention. FIG. 52 is a cross-sectional view taken along the line Y3-Y3 ′ in FIG. 50, illustrating a third manufacturing process of the capacitive element included in the flash memory according to the second embodiment of the present invention. The top view of the 4th manufacturing process of the capacitive element with which the flash memory which concerns on 2nd Embodiment of this invention is provided. FIG. 55 is a cross-sectional view of the capacitive element included in the flash memory according to the second embodiment of the present invention in the fourth manufacturing process, and is a cross-sectional view along the line X4-X4 ′ in FIG. 54. FIG. 56 is a cross-sectional view of the capacitive element included in the flash memory according to the second embodiment of the present invention in the fourth manufacturing process, taken along line X5-X5 ′ in FIG. 55. FIG. 56 is a cross-sectional view of the capacitive element included in the flash memory according to the second embodiment of the present invention in the fourth manufacturing process, and is a cross-sectional view taken along the line Y3-Y3 ′ in FIG. 55.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... NAND type flash memory, 2 ... Memory cell array, 3 ... Peripheral circuit, 10 ... Semiconductor substrate, 11, 60 ... Gate insulating film, 12, 14 ... Polycrystalline silicon layer, 13 ... Inter-gate insulating film, 15 ... Metal layer 16, 16, 19, 22, 31-33, 40 ... insulating film, 17, 52 ... n ⁺ -type impurity diffusion layer, 20, 21, 23, 38, 39, 58, 59 ... metal wiring layer, 30 ... groove , 34, 44, 51 ... region, 35, 47 ... p-type impurity implantation layer, 36, 37, 55-57 ... contact plug, 41, 42, 45, 46 ... photoresist, 43, 53 ... opening, 50 ... n-type diffusion layer

Claims (5)

A first element isolation region formed in the semiconductor substrate;
A first semiconductor region electrically isolated from each other by the first element isolation region;
A memory cell formed on the first semiconductor region and capable of holding data;
A second element isolation region formed in the semiconductor substrate;
Stripe-shaped second semiconductor regions electrically isolated from each other by the second element isolation region;
The stripe-shaped resistance element formed on the second semiconductor region;
First and second metal wiring layers respectively connected to one end and the other end of the resistance element;
A third semiconductor region formed in the semiconductor substrate immediately below the second element isolation region, and the memory cell is formed by interposing a first insulating film on the first semiconductor region. A conductive floating gate electrode; and a control gate electrode formed on the floating gate electrode with a second insulating film interposed therebetween,
The resistance element is electrically connected to a conductor layer formed on the second semiconductor region with a third insulating film interposed therebetween, and to both ends in the longitudinal direction of the stripe shape of the conductor layer; and A first electrode and a second electrode connected to the first and second metal wiring layers, respectively, and an electrode separation region for electrically separating the first and second electrodes;
The conductor layer is formed in a self-aligned manner with respect to the second element isolation region,
The floating gate electrode and the conductor layer are formed using the same material,
The control gate electrode and the first and second electrodes are formed using the same material,
The second element isolation region adjacent to the electrode isolation region has a recess on the surface,
The third semiconductor region has a second conductivity type opposite to the first conductivity type, and is provided immediately below the concave portion of the second element isolation region. The second semiconductor region is disposed in parallel at a constant width and interval via the second element isolation region,
The resistance element is formed on each of the second semiconductor regions, and any one of the first and second electrodes of the adjacent resistance elements is electrically connected to each other. Item 14. The semiconductor device according to Item 1. A first element isolation region formed in the semiconductor substrate;
A first semiconductor region electrically isolated from each other by the first element isolation region;
A memory cell formed on the first semiconductor region and capable of holding data;
A second element isolation region formed in the semiconductor substrate;
A second semiconductor region electrically isolated from each other by the second element isolation region;
A capacitive element formed on the second semiconductor region;
First and second metal wiring layers respectively connected to one electrode and the other electrode of the capacitive element;
A third semiconductor region formed in the semiconductor substrate immediately below the second element isolation region, and the memory cell is formed by interposing a first insulating film on the first semiconductor region. A conductive floating gate electrode; and a control gate electrode formed on the floating gate electrode with a second insulating film interposed therebetween,
The capacitive element includes a conductor layer formed on the second semiconductor region with a third insulating film interposed therebetween, a fourth insulating film formed on the conductor layer, and a fourth insulating film on the fourth insulating film. A first electrode formed and connected to the first metal wiring layer; a second electrode formed to be electrically connected to the conductor layer and connected to the second metal wiring layer; An electrode separation region for electrically separating the first and second electrodes,
The conductor layer is formed in a self-aligned manner with respect to the second element isolation region,
The floating gate electrode and the conductor layer are formed using the same material,
The control gate electrode and the first and second electrodes are formed using the same material,
The second element isolation region adjacent to the electrode isolation region has a recess on the surface,
The third semiconductor region has a second conductivity type opposite to the first conductivity type, and is provided immediately below the concave portion of the second element isolation region. Forming a gate insulating film on the semiconductor substrate;
Forming a first conductivity type semiconductor layer functioning as a resistance element on the gate insulating film;
A plurality of stripe-shaped first grooves extending in the first direction so as to penetrate the gate insulating film and the semiconductor layer are formed in the semiconductor substrate along the second direction orthogonal to the first direction. Forming, and
Forming an element isolation region by embedding an insulating film in the first trench;
Forming an intergate insulating film on the semiconductor layer;
Removing a part of the inter-gate insulating film to form a first opening and a second opening, and exposing the semiconductor layer in the first and second openings;
Forming an electrode layer of the resistive element on the semiconductor layer, on the inter-gate insulating film, and on the element isolation region so as to cover the first opening and the second opening;
Patterning the electrode layer in a stripe shape along the first direction so as to cover the semiconductor layer and the inter-gate insulating film sandwiched between the element isolation regions adjacent in the second direction; Exposing the upper surface of the element isolation region;
The electrode layer is separated into two regions along the first direction by removing a part of the electrode layer and exposing the intergate insulating film, thereby being electrically separated from each other, and 1. forming a first electrode and a second electrode in contact with the semiconductor layer through a second opening;
In the step of removing a part of the electrode layer, the surface of the insulating film in the element isolation region in a region adjacent to the region in which the electrode layer is removed in the second direction is removed, Forming a second groove;
Forming a stripe-shaped first mask material along the first direction on the first and second electrodes and on the semiconductor layer in the region where the electrode layer is removed;
By implanting ions of a second conductivity type first impurity using the first mask material as a mask, the first impurity is implanted into the semiconductor substrate in a region immediately below the second groove, thereby Forming an injection layer;
After removing the first mask material, covering the upper surface of the element isolation region and forming a stripe-shaped second mask material along the first direction;
By performing ion implantation of the first conductivity type second impurity using the second mask material as a mask, the second impurity is prevented from being implanted into the region immediately below the second groove. Injecting into the semiconductor layer and the first and second electrodes;
And a step of forming contact plugs on the first and second electrodes. Forming a gate insulating film on the semiconductor substrate;
Forming a first conductivity type semiconductor layer on the gate insulating film;
A plurality of stripe-shaped first grooves extending in the first direction so as to penetrate the gate insulating film and the semiconductor layer are formed in the semiconductor substrate along the second direction orthogonal to the first direction. Forming, and
Forming an element isolation region by embedding an insulating film in the first trench;
Forming an inter-gate insulating film functioning as a capacitor insulating film of a capacitive element on the semiconductor layer;
Removing a part of the inter-gate insulating film to form an opening, and exposing the semiconductor layer in the opening;
Forming an electrode layer of the capacitive element on the semiconductor layer, the inter-gate insulating film, and the element isolation region so as to cover the opening;
Patterning the electrode layer in a stripe shape along the first direction so as to cover the semiconductor layer and the inter-gate insulating film sandwiched between the element isolation regions adjacent in the second direction; Exposing the upper surface of the element isolation region;
The electrode layer is divided into two regions along the first direction by removing a part of the electrode layer to expose the inter-gate insulating film, so that the inter-gate insulating film and the semiconductor layer are separated from each other. Forming a first electrode electrically separated, and a second electrode spaced apart from the first electrode and in contact with the semiconductor layer through the opening;
In the step of removing a part of the electrode layer, the surface of the insulating film in the element isolation region in a region adjacent to the region in which the electrode layer is removed in the second direction is removed, Forming a second groove;
Forming a stripe-shaped first mask material along the first direction on the first and second electrodes and on the semiconductor layer in the region where the electrode layer is removed;
By implanting ions of a second conductivity type first impurity using the first mask material as a mask, the first impurity is implanted into the semiconductor substrate in a region immediately below the second groove, thereby Forming an injection layer;
After removing the first mask material, covering the upper surface of the element isolation region and forming a stripe-shaped second mask material along the first direction;
By performing ion implantation of the first conductivity type second impurity using the second mask material as a mask, the second impurity is prevented from being implanted into the region immediately below the second groove. Injecting into the semiconductor layer and the first and second electrodes;
And a step of forming contact plugs on the first and second electrodes.

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