JP2008166334A - Display device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a TFT element which can ensure enough covering property of a passivation film that is formed on the upper layer of signal wiring made mainly of Al and which has high performance and reliability, and to provide its manufacturing method. <P>SOLUTION: The display device includes signal wiring, which is provided with a lower wiring 11 that is mainly made of aluminum and is formed on an insulation layer 10, being in contact with the insulation layer 10, and an upper wiring 12 that is mainly made of 4-group or 6-group element and is formed in the upper layer of the lower wiring 11, being in contact with the lower wiring 11 and of which end is located inside that of the lower wiring 11. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a display device and a method for manufacturing the display device, and more particularly to a display device having a two-layer structure wiring having a lower layer wiring and an upper layer wiring formed as an upper layer of the lower layer wiring as a signal wiring.

  A thin liquid crystal panel, which is one of display devices, is widely used for monitors of personal computers and portable information terminal devices, taking advantage of low power consumption and small size and light weight. In recent years, it is also widely used as a TV application.

  Such a thin liquid crystal panel uses a thin film transistor (TFT) element as a pixel switching element, and such a panel is called an active matrix type. In addition, a MOS structure using a semiconductor film is generally used for the TFT element. The semiconductor film includes an amorphous silicon thin film and a polycrystalline silicon thin film, and the MOS structure includes an inverted stagger type and a top gate type. These MOS structures are appropriately selected according to the use and characteristics of the thin liquid crystal panel. For example, in a small thin liquid crystal panel, a TFT element is formed using a polycrystalline silicon thin film having high carrier mobility in order to reduce the element size.

  In a thin liquid crystal panel using such a TFT element, a low resistance material such as aluminum (Al) is generally used as a signal wiring. The TFT element is electrically connected to the upper wiring layer by embedding the signal wiring in the contact hole provided in the interlayer insulating film layer and the gate insulating film layer formed in the upper layer of the TFT element.

  In such a case, since the polycrystalline silicon thin film and the Al wiring are in direct contact with each other, the resistance becomes high. Therefore, the signal wiring is mainly composed of chromium (Cr), molybdenum (Mo), titanium (Ti), tantalum (Ta), or the like. It is generally performed to connect with a polycrystalline silicon thin film through a barrier metal. On the other hand, a metal layer mainly composed of (Cr), molybdenum (Mo), titanium (Ti), tantalum (Ta) or the like is generally formed on the upper layer of the Al wiring as a countermeasure against Al hillocks. That is, when an Al wiring is connected to the polycrystalline silicon thin film, the Al wiring has a three-layer structure of a barrier metal layer, an Al layer, and a metal layer. When the signal wiring has such a three-layer structure, the etching of the barrier metal layer and the metal layer proceeds more than the Al layer due to the difference in the etching rate when forming the wiring. In such a case, the Al layer protrudes from the barrier metal layer and the metal layer in the cross-sectional shape. When such protrusions occur, the covering property of the passivation film formed on the upper layer of the signal wiring deteriorates, and the performance of the TFT element is deteriorated and the transparent electrode formed on the passivation film is disconnected.

  On the other hand, even in a signal wiring that does not contact the polycrystalline silicon thin film through a contact hole or the like, it is common to provide a metal layer above the Al layer as a countermeasure against hillocks. A technique relating to such wiring is disclosed in Patent Document 1. FIG. 4 shows a cross-sectional shape of the wiring 110 in the display device described in Patent Document 1. As shown in FIG. 4, in the wiring 110, a metal layer 112 having a bottom surface wider than the top surface of the Al wiring 111 is formed on the Al wiring 111. As a result, even if a hillock 120 occurs in the Al wiring 111, the adjacent wiring is not short-circuited.

  However, even in the technique described in Patent Document 1, the width of the Al wiring 111 that is the lower layer of the wiring 110 is narrower than the width of the metal layer 112. That is, in the cross-sectional shape of the wiring described in Patent Document 1, a void is formed in a region below the metal layer 112 where the Al wiring 111 is not formed, and deterioration of the film quality of the passivation film is not improved.

On the other hand, Patent Document 2 discloses a technique for preventing the formation of such voids. In the technique described in Patent Document 2, silver (Ag) wiring is used instead of Al wiring, and wiring wider than the metal layer is formed. Thereby, in the technique described in Patent Document 2, the film property of the film formed on the upper layer of the wiring layer is improved. However, in Patent Document 2, when Al wiring is used for wiring, a void is formed (see Patent Document 2, paragraphs 0026 to 0030).
JP 2001-102445 A Japanese Patent Laid-Open No. 2001-242483

  Even with the techniques described in Patent Documents 1 and 2, when Al is used as the wiring, the coverage of the film formed on the upper layer of the wiring layer is deteriorated, the performance of the TFT element is deteriorated, and the transparent formed on the passivation film There is a problem that electrode disconnection occurs.

  The display device according to the present invention is a display device having a signal wiring, wherein the signal wiring includes aluminum as a main component and a lower layer wiring formed on the insulating layer so as to be in contact with the insulating layer; A main component is a group 6 element, the upper layer wiring is formed on the upper layer of the lower layer wiring so as to be in contact with the lower layer wiring, and the upper layer wiring is located on the inner side of the end of the lower layer wiring. It is.

  A display device according to the present invention includes: a lower layer wiring mainly composed of aluminum; and an upper layer wiring mainly composed of a group 4 to group 6 element and formed on the upper layer of the lower layer wiring so as to be in contact with the lower layer wiring. A signal wiring, a gate insulating layer in which a contact hole is formed, a thin film transistor, and a transparent electrode formed on at least an upper layer of the thin film transistor and formed in the contact hole. The signal line and the thin film transistor are electrically connected through a hole.

  The display device according to the present invention provides a TFT element having a high performance and high reliability while ensuring a sufficient film property of a passivation film formed on an upper layer of a signal wiring mainly composed of Al.

  Hereinafter, embodiments to which the present invention can be applied will be described. The following description is about an embodiment of the present invention, and the present invention is not limited to the following embodiment.

Embodiment 1
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In this embodiment, a display device in which a top gate thin film transistor (TFT) element is formed over an insulating substrate having transparency such as a glass substrate or a quartz substrate will be described. A schematic diagram of a cross-sectional structure of this display device is shown in FIG.

  First, the structure of the display device according to this embodiment will be described. As shown in FIG. 1, in the display device according to the embodiment, a silicon nitride film 2 and a silicon oxide film 3 are formed on the surface of a glass substrate 1. The silicon nitride film 2 and the silicon oxide film 3 are barrier layers that prevent mobile ions such as sodium (Na) from the polysilicon layer 4 formed on the surface from flowing out to the glass substrate 1. It is good also as a shape which forms only one layer.

  A polysilicon layer 4 is formed in a predetermined region on the surface of the silicon oxide film 3. A barrier metal layer 5 is formed in a region corresponding to the source region or drain region on the surface of the polysilicon layer 4. The barrier metal layer 5 formed in a region corresponding to the drain region of the barrier metal layer 5 is formed so as to extend to a region corresponding to the capacitor portion. An insulating film is formed so as to cover the surface of the silicon oxide film 3 on which the polysilicon layer 4 is not formed, the polysilicon layer 4, and the barrier metal layer 5. Here, in order to distinguish from other insulating films, this insulating film is hereinafter referred to as a gate insulating film 6.

  A gate electrode 7, a capacitor electrode 8, and a gate wiring 9 are formed in predetermined regions on the surface of the gate insulating film 6, respectively. Since the display device according to the present embodiment uses a TFT element having a twin gate structure, two gate electrodes 7 are formed above the region corresponding to the channel region of the polysilicon layer 4 that functions as the transistor portion. Is done. A capacitor electrode 8 is formed on the polysilicon layer 4 above the region corresponding to the capacitor portion. In the cross-sectional view shown in FIG. 1, the gate wiring 9 is formed in the upper layer of the gate insulating film 6 of the source / drain layer / gate layer conversion portion formed in the region where the polysilicon layer 4 is not formed. The source / drain layer / gate layer converter is a region that physically and electrically connects the layer in which the gate wiring 9 is formed and the layer in which the signal wiring is formed. Then, an insulating film is formed so as to cover the gate electrode 7, the capacitor electrode 8, and the gate wiring 9. Here, in order to distinguish from other insulating films, this insulating film is hereinafter referred to as an interlayer insulating film 10.

  A signal wiring is formed in a predetermined region on the surface of the interlayer insulating film 10. This signal wiring has a two-layer structure having a lower layer wiring 11 formed so as to be in contact with the interlayer insulating film 10 and an upper layer wiring 12 formed in an upper layer of the lower layer wiring 11. The lower layer wiring 11 is a wiring formed of, for example, aluminum (Al) or an alloy film containing Al as a main component. On the other hand, the upper layer wiring 12 is a metal formed of a group 4 to group 6 element (for example, chromium (Cr), molybdenum (Mo), titanium (Ti), tantalum (Ta)) or an alloy film containing these metals as a main component. Is a layer. In the present embodiment, hillocks generated in the lower layer wiring 11 are prevented by forming such an upper layer wiring 12 in the upper layer of the lower layer wiring 11 mainly composed of Al. Further, the end portion of the upper layer wiring 12 is formed inside the end portion of the lower layer wiring 11. That is, the upper layer wiring 12 is narrower than the lower layer wiring 11. Then, an insulating film is formed on the interlayer insulating film 10 where the signal wiring and the signal wiring are not formed. Here, in order to distinguish from other insulating films, this insulating film is hereinafter referred to as a passivation film 13.

  For example, a transparent electrode 15 is formed in a predetermined region on the surface of the passivation film 13. As the transparent electrode 15, for example, an ITO film or an IZO film is used. The transparent electrode 15 passes through the passivation film 13, the interlayer insulating film 13, and the gate insulating film 6 through the contact hole 14 formed so as to expose a desired wiring in order to ensure electrical continuity. Connected to other wiring. At this time, a conductive film is formed of the same material as that for forming the transparent electrode in at least a region along the side wall of the contact hole 14. Then, the transparent electrode 15 is electrically connected to other wiring by the conductive film. Here, a contact hole is a hole-like wiring region opened to connect wirings and electrodes formed in different layers, and in the following description, such a wiring region is used regardless of an insulating layer that penetrates. Is referred to as a contact hole.

  Here, in order to explain the structure of the wiring layer and the passivation film 13 thereabove according to the present embodiment, an enlarged view of a region indicated by A in FIG. 1 is shown in FIG. As shown in FIG. 2, in the display device according to the present embodiment, the lower layer wiring 11 is formed directly on the surface of the interlayer insulating film 10. The end portion of the upper layer wiring 12 is located inside the lower layer wiring 11 with respect to the end portion of the lower layer wiring 11. Therefore, the passivation film 13 has a gentle shape along the side walls of the lower layer wiring 11 and the upper layer wiring 12. As a result, no void occurs in the vicinity of the signal wiring and the surface of the passivation film 13. That is, the transparent electrode formed on the surface of the passivation film 13 is not broken by the unevenness on the surface of the passivation film 13.

  In the present embodiment, the thickness of the passivation film 13 formed so as to be in contact with the side wall of the lower layer wiring 11 is L1, the thickness of the passivation film 13 formed on the surface of the upper layer wiring 12 is L2, and L2 When L is 300 nm or less, L1 / L2 is 90% or more. That is, in the display device according to the present embodiment, the passivation film 13 can maintain good coverage even if it is an upper layer of the signal wiring. From the above, the display device according to the present embodiment can realize a high-performance TFT element with high reliability of the passivation film 13 and the wiring formed on the surface thereof.

  Next, a method for manufacturing the display device according to the present embodiment will be described. First, in the first step, a silicon nitride film 2 and a silicon oxide film 3 are formed on the surface of the glass substrate 1. Thereafter, an amorphous silicon film is formed on the surface of the silicon oxide film 3 by a plasma CVD (Chemical Vapor Deposition) method so that the film thickness becomes 50 to 70 nm. Then, an annealing process such as excimer laser annealing or YAG (yttrium / aluminum / garnet) laser annealing is performed to melt, cool and solidify the amorphous silicon film, thereby forming the polysilicon layer 4. The polysilicon layer 4 is removed by dry etching except for a predetermined region where the transistor portion and the capacitor portion of the TFT element are formed.

  In the second step, a barrier metal layer 5 such as Mo, Cr, Ti, tungsten (W) or the like is formed on the polysilicon layer 4 remaining after the dry etching in the first step. Thereafter, patterning is performed so that the barrier metal layer 5 remains in portions corresponding to the source region, drain region, and capacitor portion of the transistor. In this embodiment, etching is performed using different patterns in the first step and the second step, but these patterns are performed in one photolithography process using a halftone or gray tone technique. May be formed.

  In the third step, the gate insulating film 6 is formed on the entire surface of the substrate formed up to the second step using a plasma CVD method. Then, a conductive film to be the gate electrode 7, the capacitor electrode 8, and the gate wiring 9 is formed on the gate insulating film 6 by a sputtering method using a DC magnetron. These conductive films may be, for example, Mo, Cr, W, Al, Ta, or an alloy film containing these as main components. Thereafter, patterning is performed to form the gate electrode 7, the capacitor electrode 8, and the gate wiring 9, respectively.

  In the fourth step, an impurity is introduced into the polysilicon layer 4 by ion implantation or ion doping in order to form a source region and a drain region of the transistor. Impurities introduced at this time are phosphorus (P) and boron (B). When phosphorus is introduced into the polysilicon layer 4, the transistor is an n-type transistor, and when boron is introduced, the transistor is a p-type transistor. An n-type transistor and a p-type transistor can be formed on the same substrate by introducing phosphorus or boron in accordance with the polarity of the transistor. Note that the drain region may have an LDD (Lightly Doped Drain) structure in order to improve the reliability of the transistor.

  In the fifth step, an interlayer insulating film 10 is formed on the entire surface of the substrate including the upper layer of the gate electrode 7, the capacitor electrode 8, and the gate wiring 9 formed in the third step by plasma CVD. The interlayer insulating film 10 is, for example, a silicon oxide film or a silicon nitride film. Thereafter, in order to activate the impurities introduced in the fourth step, heat treatment is performed to bring the entire substrate to 400 ° C. or higher.

  In the sixth step, a conductive film to be a signal wiring is formed by a sputtering method using a DC magnetron. This conductive film has a two-layer structure in which Al or an alloy film mainly composed of Al is formed as a lower layer wiring, and Mo, Cr, W, Ta or an alloy film mainly composed of these is formed in an upper layer of the lower layer wiring. It has become. Since the signal wiring has a two-layer structure, sputtering is performed twice in this sixth step. For example, the lower layer wiring is formed in the first sputtering process, and the upper layer wiring is formed in the second sputtering process. Then, patterning is performed according to a desired shape, and a signal wiring is formed by dry-etching the conductive film in an etching process. In this dry etching, since the lower layer wiring 11 and the upper layer wiring 12 have different etching rates, the upper layer wiring 12 is etched more than the lower layer wiring 11. That is, the side wall of the upper layer wiring 12 is formed inside the side wall of the lower layer wiring 11.

  In the seventh step, a silicon nitride film serving as a passivation film 13 (protective film) is formed on the entire substrate including the upper layer of the signal wiring. Then, an opening is provided in the passivation film 13 by dry etching, and a contact hole 14 is formed in a desired region. The contact hole 14 is formed at a depth that penetrates the passivation film 13 and exposes the wiring and electrodes located below the contact hole 14. That is, the contact hole 14 penetrates a plurality of insulating films depending on the region to be formed.

  In the eighth step, the transparent electrode 15 is formed on the surface of the passivation film 13. The transparent electrode 15 is formed by a sputtering method using a DC magnetron. The transparent electrode 15 is formed of an ITO film or an IZO film containing indium oxide as a main component. The transparent electrode 15 is formed in a region covering at least the opening of the contact hole 14, and a conductive film is also formed at least in a portion along the side wall of the contact hole 14. That is, the wiring or electrode under the contact hole 14 and the transparent electrode 15 formed on the surface are physically and electrically connected via the conductive film.

  From the above description, in the display device according to the present embodiment, the signal wiring and other wirings and electrodes connected to the signal wiring are connected via the transparent electrode 15 formed on the surface. Thus, even if the signal wiring has a two-layer structure of a lower layer wiring mainly composed of Al and an upper layer wiring mainly composed of Mo or the like, it is possible to connect the wirings. In addition, since the signal wiring has a two-layer structure, and the upper layer wiring is narrower than the lower layer wiring, no voids are generated in the signal wiring portion, and good coverage of the passivation film is achieved. It is possible to obtain.

  Further, in the display device according to the present embodiment, the contact hole for opening the other wiring and the electrode connected to the signal wiring through the contact hole and the contact hole for opening the signal wiring are only in the seventh step. It is formed. That is, in the display device according to the present embodiment, the contact opening process is only one process, which is closely related to the structure in which all the conductive films connecting different layers through the contact holes are transparent electrodes. . Thus, a display device with a small number of manufacturing steps and low cost can be obtained in this embodiment mode.

  Furthermore, in this embodiment, the signal wiring is connected to other wirings and electrodes through the upper wiring of the signal wiring. In other words, aluminum used in the lower layer wiring reacts at the interface when it is directly connected to the transparent oxide conductive material such as ITO used for the transparent electrode or the polysilicon layer, resulting in problems such as increased connection resistance. Such a connection does not occur in the lower-layer wiring in the form. Thereby, in this embodiment mode, a connection between the signal wiring and the other wirings and electrodes can be satisfactorily performed, and a display device having excellent electrical characteristics can be obtained.

Embodiment 2
In the display device according to the first embodiment, the signal wiring and other wiring are physically and electrically connected through the transparent electrode formed on the surface of the passivation film 13. On the other hand, the display device according to the second embodiment connects a lower layer wiring of a signal wiring and another wiring through a contact hole formed under the signal wiring.

  FIG. 3 shows a cross-sectional view of the display device according to the second embodiment. As shown in FIG. 3, the display device according to the second embodiment is physically and electrically connected to wirings or electrodes formed under the lower layer wirings 11 through contact holes 16. The Here, a conductive film made of the same material as that of the lower layer wiring is formed in the contact hole 16 at least in a portion including the side wall of the contact hole 16. The lower layer wiring 11 is connected to the lower wiring or electrode through this conductive film. In addition, the transparent electrode 15 formed on the surface of the passivation film 13 is connected to the upper layer wiring 12 of the signal wiring through a contact hole 14 formed under the transparent electrode 15.

  Next, regarding the method for manufacturing the display device according to the second embodiment, the part after the sixth step different from the method for manufacturing the display device according to the first embodiment will be described. In addition, description is abbreviate | omitted about the part used as the manufacturing method same as Embodiment 1. FIG.

  In the sixth step, first, the contact hole 16 is opened. Thereafter, a conductive film to be a signal wiring is formed by a sputtering method using a DC magnetron. This conductive film has a two-layer structure in which Al or an alloy film mainly composed of Al is formed as a lower layer wiring, and Mo, Cr, W, Ta or an alloy film mainly composed of these is formed in an upper layer of the lower layer wiring. It has become. At this time, when the lower layer wiring 11 is formed by sputtering, a conductive film is formed along the side wall of the contact hole 16. Further, since the signal wiring has a two-layer structure, sputtering is performed twice in the sixth step. For example, the lower layer wiring is formed in the first sputtering process, and the upper layer wiring is formed in the second sputtering process. Then, patterning is performed according to a desired shape, and a signal wiring is formed by dry-etching the conductive film in an etching process. In this dry etching, since the lower layer wiring 11 and the upper layer wiring 12 have different etching rates, the upper layer wiring 12 is etched more than the lower layer wiring 11. That is, the side wall of the upper layer wiring 12 is formed inside the side wall of the lower layer wiring 11.

  In the seventh step, a silicon nitride film to be the passivation film 13 is formed on the entire substrate including the upper layer of the signal wiring. Then, an opening is provided in the passivation film 13 by dry etching, and a contact hole 14 is formed in a desired region. The contact hole 14 is formed at a depth that penetrates the passivation film 13 and exposes the upper wiring located under the contact hole 14.

  In the eighth step, the transparent electrode 15 is formed on the surface of the passivation film 13. The transparent electrode 15 is formed by a sputtering method using a DC magnetron. The transparent electrode 15 is formed of an ITO film or an IZO film containing indium oxide as a main component. The transparent electrode 15 is formed in a region covering at least the opening of the contact hole 14, and a conductive film is also formed at least in a portion along the side wall of the contact hole 14. That is, the upper wiring under the contact hole 14 and the transparent electrode 15 formed on the surface are physically and electrically connected via the conductive film.

  From the above description, also in the display device according to the second embodiment, it is possible to realize a desired wiring using a signal wiring having a two-layer structure. Further, in the display device according to the second embodiment, the signal wiring is connected to another wiring or electrode using the lower layer wiring 11 using a material cheaper than the transparent electrode 15, thereby reducing the manufacturing cost of the device. It is possible.

1 is a schematic diagram illustrating a cross-sectional structure of a display device according to a first embodiment. It is an enlarged view of the area | region shown by A in the display apparatus shown in FIG. FIG. 6 is a schematic diagram illustrating a cross-sectional structure of a display device according to a second embodiment. It is sectional drawing of the signal wiring shown by a prior art example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Glass substrate 2 Silicon nitride film 3 Silicon oxide film 4 Polysilicon layer 5 Barrier metal layer 6 Gate insulating film 7 Gate electrode 8 Capacitance electrode 9 Gate wiring 10 Interlayer insulating film 11 Lower layer wiring 12 Upper layer wiring 13 Passivation film 14 Contact hole 15 Transparent Electrode 16 Contact hole

Claims (6)

A display device having signal wiring,
The signal wiring is
Lower layer wiring mainly composed of aluminum and formed on the insulating layer so as to be in contact with the insulating layer;
And an upper-layer wiring having a group 4 to 6 element as a main component, formed in contact with the lower-layer wiring on an upper layer of the lower-layer wiring, and having an end located inside an end of the lower-layer wiring. Display device.   The upper layer wiring is electrically connected to a transparent electrode formed on the surface of the passivation film through a contact hole formed through the passivation film formed so as to cover the signal wiring. The display device according to claim 1.   When the thickness of the passivation film formed so as to cover the signal wiring is 300 nm or less, the thickness of the passivation film formed on the side surface of the lower wiring is the thickness of the passivation film formed on the signal wiring. The display device according to claim 1, wherein the display device is 90% or more of the film thickness.   The display device further includes a thin film transistor, and the thin film transistor has a barrier metal layer above the source region and the drain region, and is formed in a contact hole formed through the insulating layer above the thin film transistor. The display device according to claim 1, wherein the signal wiring and the barrier metal layer are connected by a conductive film.   The signal wiring is connected to a region formed in the lower layer of the signal wiring with the same material as the lower wiring through a contact hole formed through an insulating layer below the signal wiring. The display device according to any one of claims 1 to 3. A signal wiring comprising: a lower layer wiring mainly composed of aluminum; and an upper layer wiring mainly composed of a group 4 to group 6 element and formed in contact with the lower layer wiring on an upper layer of the lower layer wiring;
A gate insulating layer in which a contact hole is formed;
A thin film transistor;
In the upper layer of the thin film transistor, having at least a transparent electrode formed in the contact hole,
The display device, wherein the transparent electrode electrically connects the signal line and the thin film transistor through the contact hole.

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