JP2008165463A - Bus control device - Google Patents

Abstract

Even when DMA transfer competes, bus data is transferred efficiently.
A bus control device 100 performs control for causing a plurality of DMAC built-in devices including a DMAC 113 that controls DMA transfer of data to use a data bus 130 that connects these DMAC built-in devices. Includes a DMAC control unit 114 that controls the operation of the DMAC, and the second DMAC 113 is used by the first DMAC 113 during the first DMA transfer while the first DMAC built-in device 110 is used as the data bus bus master. Setting for completing transfer of untransferred data of the first DMA transfer from the first DMAC control unit 114 to the second DMAC control unit 124 according to a predetermined condition when DMA transfer is requested After the information is transmitted, the second DMA transfer is executed by the first DMAC.
[Selection] Figure 1

Description

  The present invention relates to a bus control device in a bus system used for an information processing device or the like, and in particular, a DMAC (Direct Memory Access) transfer that is mounted on a large scale integrated circuit (LSI) or the like. The present invention relates to a bus control device for using a bus in a bus system to which a DMAC built-in device having a built-in Memory Access Controller is connected.

  Conventionally, in a bus system used for an information processing apparatus such as a personal computer, a workstation, or an office computer, DMA transfer is performed in which data is directly exchanged between an I / O device and a memory through a bus without using a CPU. There is something. Some bus systems are equipped with a DMAC, which is a controller that realizes DMA transfer that enables high-speed and large-capacity data transfer without CPU overhead, and stores data received from external devices as main memory. Data transfer is performed such as writing to a memory serving as a copy unit, reading out transmission data from the memory, and outputting the data to an external device. When performing the data transfer, in a low-speed system, a central processing unit (CPU: Central Processing Unit) has a bus right and performs data transfer between the CPU and the memory. In a high-speed system, Since the transfer by the CPU takes time, the DMAC has the bus right and controls the input / output (I / O) module which is an interface of the external device, and directly transfers the data to the memory without using the CPU. Executed to realize DMA transfer.

  When performing DMA transfer in a system in which multiple modules are connected to a common data bus, the DMAC arbitrates DMA transfer requests from each module and grants permission to the modules capable of DMA transfer. DMA transfer is being performed. In this case, the module that issued the DMA transfer request earlier or the module with a higher priority occupies the data bus continuously, and DMA transfer of other modules may not be possible.

In order to improve the bus use efficiency in such a DMA transfer system, Patent Document 1 discloses that when DMAC arbitrates a DMA transfer request issued from each module and the DMA transfer request conflicts, The DMA transfer request is granted to the DMA transfer request of the module with the higher priority, and the module to which the permission is given performs the DMA transfer using the data bus, while the permission for the DMA transfer request is granted. A bus control device is disclosed in which each module is provided with a register for setting a DMA transfer request interval indicating a waiting time until the next module can execute a DMA transfer request. This bus control device distributes the timing for generating DMA transfer requests, allows modules with low priority to use the data bus at a certain rate, and enables efficient use of the bus.
JP 2002-351815 A

  In the bus control device that improves the bus use efficiency as described above, for example, in the bus system 600 in which the first ASIC 610 and the second ASIC 620 that are two devices as shown in FIG. 6, when data is transferred from the first memory 612 to the second memory 622 using the first DMAC 611 that realizes the DMA transfer in the first ASIC 610, the first ASIC 610 is used. Becomes the bus master of the data bus 630, and the second ASIC 620 becomes the bus slave of the data bus 630.

  However, if another task in the bus system 600 needs to DMA transfer data from the first memory 612 to the first I / O 614 and there is only one channel of DMAC in the first ASIC 610, the first 6 waits for the transfer from the first memory 612 to the second memory 622 to be completed and the first DMAC 611 becomes free, or by using the second DMAC 621 in the second ASIC 620, as shown by a one-dot chain line shown in FIG. Then, transfer is performed in the following manner: memory bus 631 → first ASIC 610 → data bus 630 → second ASIC 620 → data bus 630 → first ASIC 610 → first I / O bus 632 → first I / O 614. Alternatively, the transfer must be performed by the CPU 640. That is, when DMA transfer competes, in any case, the transfer speed becomes slow or the bus is occupied unnecessarily, so that the data transfer efficiency is very poor.

  Accordingly, the present invention has been made in view of the above-described problems of the conventional bus control device and bus control method, and an object of the present invention is to efficiently transfer bus data even when DMA transfers compete. It is an object of the present invention to provide a new and improved bus control device.

  In order to solve the above-described problem, according to an embodiment of the present invention, a plurality of DMAC built-in devices including a DMAC that controls DMA transfer of data use a data bus that connects these DMAC built-in devices. A bus control device that performs control, wherein a second DMAC subsequent to the use of one DMAC included in the one DMAC built-in device during execution of the first DMA transfer using the one DMAC built-in device as the bus master of the data bus When a DMA transfer is requested, a DMAC that executes DMA transfer of the remaining untransferred data of the first DMA transfer and a DMAC that executes the second DMA transfer are determined according to predetermined conditions. A bus control device is provided.

  With this configuration, for example, when one DMAC is operating and it is desired to use the one DMAC for the second DMA transfer, it is necessary to wait until the operation of the one DMAC in operation is completed. As a result, the data transfer on the data bus when the DMA transfer conflicts can be executed quickly. In addition, if the second DMA transfer is performed by another DMAC from the beginning, there is a possibility that a wasteful occupation of the data bus may occur, so that the bus bandwidth when the DMA transfer competes can be minimized. In addition, when the DMA transfer during operation is completed while switching the DMAC, it is more efficient to wait for the DMA transfer currently being performed to complete than to switch the bus master. DMA transfer is executed according to the usage status.

  At this time, in the above-described embodiment, the DMAC built-in device includes the DMAC control unit that controls the operation of the DMAC. The predetermined condition is that the first DMA transfer in operation is stopped and the first DMA transfer is stopped. The first condition for causing the DMA transfer of the remaining untransferred data of the transfer to be processed by another DMAC and the second DMA transfer to be processed by one DMAC, and the DMA transfer of the remaining untransferred data of the first DMA transfer The second condition in which the second DMA transfer is processed by another DMAC while the data is processed as it is by one DMAC, and a comparison in which the use efficiency of the data bus in the case is determined by one DMAC control unit provided in the one DMAC It may also mean the result.

  With such a configuration, the DMAC control units of each device exchange setting information via the data bus without intervention of the CPU. Therefore, the CPU that controls the operation of the bus control device first If the DMA setting is performed only once, it is not necessary to stop or reset the DMA transfer in the middle, so that waste of operation control in the CPU can be reduced. Also, the DMAC used by the DMAC control unit is determined so as to simulate in advance what the data path of each DMA transfer after the bus master change will be, and the bus system as a whole has the highest bus use efficiency. Even when the DMA transfer competes, the bus data can be transferred more reliably and efficiently.

  At this time, in the above embodiment, when one DMAC control unit detects that the first condition is more efficient in use of the data bus, the other DMAC built-in device from the one DMAC control unit The setting information for completing the DMA transfer of the remaining untransferred data of the first DMA transfer may be transmitted to the DMAC control unit.

  With such a configuration, when DMA transfer competes, the bus data can be transferred efficiently without reducing the bus bandwidth of the data bus.

  At this time, in the above embodiment, a setting information dedicated line for communicating setting information is provided between the plurality of DMAC built-in devices so as to connect the plurality of DMAC built-in devices independently of the data bus. It is good as well.

  With such a configuration, setting information for completing the transfer of untransferred data in the first DMA transfer is exchanged via a dedicated line independent from the data bus. The band is not dropped.

  At this time, in the above-described embodiment, the second DMA transfer may be processed by the DMAC under the condition that the use efficiency of the data bus is improved in the comparison result determined by one DMAC control unit.

  By adopting such a configuration, the DMAC used by the DMAC control unit is determined in accordance with the bus usage efficiency so that the bus usage efficiency becomes the highest in the entire bus system. Even in this case, the bus data can be reliably and efficiently transferred with a more suitable processing path.

  At this time, in the above embodiment, the DMAC may include a management number setting area to which a unique management number corresponding to the DMA transfer in operation is assigned. In particular, when the CPU that controls the operation of the bus control device sets the first DMA transfer, the management number is attached to the transfer data of the first DMA transfer, and the number information of the management number is the management number setting. When the first DMA transfer is stopped due to contention of one DMAC and the first DMA transfer is shifted to another DMAC, the management number number information is also transmitted and set at the same time. It is preferable.

  With this configuration, by assigning a management number to each DMA transfer, it is possible to determine which DMA transfer has been completed when the DMAC that finally completes the DMA transfer is different from the DMAC initially set by the CPU. The CPU can recognize it.

  At this time, in the above embodiment, when one DMAC built-in device stops the first DMA transfer and transmits / sets the remaining untransferred data of the first DMA to another DMAC. DMA management serving as an interrupt number indicated by the management number assigned to the one DMAC that is a transmission source of the remaining untransferred etas corresponding to other DMACs in the middle and a serial number indicating the correspondence order of each DMA transfer It is good also as providing the interruption management part which manages a number.

  With this configuration, if the interrupt number managed by the interrupt management unit is associated with the DMA management number, the DMAC interrupt number initially set by the CPU finally completes the DMA transfer. Even when the interrupt number is different, the CPU can correctly execute processing for each DMA transfer completion interrupt.

  As described above, according to the present invention, the bus masters of a plurality of DMAC built-in devices connected to the bus system can be switched according to a predetermined condition without intervention of the CPU. Even in this case, data transfer by DMA transfer of the bus can be efficiently realized by minimizing the bus bandwidth.

  Exemplary embodiments of the present invention will be described below in detail with reference to the accompanying drawings. In the present specification and drawings, components having substantially the same functional configuration are denoted by the same reference numerals, and redundant description is omitted.

  First, the configuration of the first embodiment of the bus control device of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of the bus control device according to the present embodiment.

  As shown in FIG. 1, the bus control device 100 according to the present embodiment has a structure in which a first ASIC 110 and a second ASIC 120 are connected to a common data bus 130, and the first ASIC 110 and the CPU bus 136 are connected to each other. The operation control of the bus control device 100 is executed by the CPU 140 connected through the bus 140.

  The first ASIC 110 is connected to a first memory 111 serving as a main storage unit that stores received data from an external device (not shown) via a first memory bus 131, and the first I / O 110 is connected to the first ASIC 110. A first I / O 112 serving as an interface portion with a peripheral device (not shown) of the bus control device 100 is connected via the bus 134.

  In addition, the first ASIC 110 is provided with a first DMAC 113 that controls DMA transfer in which data is directly exchanged between the I / O device and the memory via the data bus 130 without using the CPU 140. That is, the first ASIC 110 becomes a DMAC built-in device including the first DMAC 113 that controls DMA transfer, writes received data from an external device to the first memory 111, and transmits transmission data from the first memory 111. Data transfer such as reading and outputting to an external device is executed.

  The second ASIC 120 is connected to a second memory 121 serving as a main storage unit for storing received data from an external device (not shown) via a second memory bus 132, and a second I / O. A second I / O 122 serving as an interface part with a peripheral device (not shown) of the bus control device 100 is connected via the bus 135.

  Further, an external I / F 150 serving as an interface portion with an external device (not shown) is connected via the external I / F bus 133. Via this external I / F 150, data transfer is performed such as writing received data from an external device into the second memory 121, reading out transmission data from the second memory 121, and outputting the data to the external device. .

  Further, the second ASIC 120 is provided with a second DMAC 123 that controls the DMA transfer, similarly to the first ASIC 110. That is, the second ASIC 120 becomes a DMAC built-in device including the second DMAC 123 that controls the DMA transfer, writes the reception data from the external device to the second memory 121, and transmits the transmission data from the second memory 121. Data transfer such as reading and outputting to an external device is executed.

  In the present embodiment, the first and second DMACs 113 and 123 indicate which DMA transfer has been completed when the DMAC that finally completes the DMA transfer is different from the DMAC initially set by the CPU 140. Is provided with a management number setting area (not shown) to which a unique management number corresponding to the DMA transfer in operation is assigned. At this time, particularly when the DMA transfer is set by the CPU 140, a management number corresponding to the DMA transfer is added to the data transferred by the DMA transfer, and the number information of the management number is stored in the management number setting area. When the DMA transfer is stopped when the DMACs 113 and 123 compete with each other and the DMA transfer is transferred to the other DMACs 113 and 123, the number information of the management number is preferably transmitted and set at the same time.

  As shown in FIG. 1, the bus control device 100 according to the present embodiment includes a plurality of devices 110 and 120 (two in FIG. 1) to which memories 111 and 121 are locally connected, connected via a data bus 130. Has been. In such a configuration, the bus control device 100 according to the present embodiment transfers data when performing DMA transfer between the memory 111 and the memory 121 or between the memory 111 and 121 and the I / O 112 and 122. The DMACs 113 and 123, which are devices serving as bus masters, are dynamically switched to enable efficient DMA transfer.

  Next, the characteristic part of this embodiment for the bus controller 100 of this embodiment to perform efficient DMA transfer by dynamically switching the bus master will be described with reference to FIG. FIG. 2 is a detailed explanatory diagram of the block diagram of the bus control device of the present embodiment shown in FIG.

  The first ASIC 110 serving as a DMAC built-in device includes a first DMAC control unit 114 that controls the operation of the first DMAC 113. Further, as shown in FIG. 2, the first ASIC 110 includes a CPU interface unit 117 serving as an interface with the CPU 140, a first memory control unit 115 that executes control on the first memory 111, and a first I / I A first I / O control unit 116 that executes control for O112 is provided.

  On the other hand, the second ASIC 120 serving as a DMAC built-in device includes a second DMAC control unit 124 that controls the operation of the second DMAC 123. In addition, as shown in FIG. 2, the second ASIC 120 includes a second memory control unit 125 that executes control on the second memory 121 and a second I / O that executes control on the second I / O 122. An O control unit 126 and an external I / F control unit 127 that executes control on the external I / F 150 are provided.

  In the present embodiment, the first ASIC 110 and the second ASIC 120 occupy the data bus 130 and prevent the bus bandwidth from being reduced. These are connected via a DMA control line 160 which is a dedicated setting information line for communicating setting information for completing DMA transfer of untransferred data of the DMA transfer.

  By configuring the bus control device 100 according to the present embodiment as described above, the first ASIC 110 stops the DMA transfer of the first ASIC 110 operating as the bus master of the data bus 130, and the remaining DMAs The transfer is performed by the second DMAC 123 in the second ASIC 120, so that the first DMAC 113 in the first ASIC 110 can be used for another task such as a subsequent DMA transfer.

  Such an operation of switching between the DMACs 113 and 123 allows the transfer of DMA transfer data such as subsequent transfer address information and the remaining transfer data size between the first ASIC 110 and the second ASIC 120 without using the CPU 140. It is executed and automatically set in the second DMAC 123 of the second ASIC 120 based on the DMA transfer data so that it can be activated. That is, if the CPU 140 first sets and activates the first DMA transfer only once for the first DMAC 113 in the first ASIC 110, the subsequent DMA transfer processing is performed by the first ASIC 110. When contention of one DMAC 113 occurs, automatic switching is automatically performed between the first DMAC control unit 114 of the first ASIC 110 and the second DMAC control unit 124 of the second ASIC 120.

  As a result, the DMA transfer from the first memory 111 to the first I / O 112 is performed using the first DMAC 113 in the first ASIC 110 that has become empty, as shown in FIG. From 131 to the first ASIC 110, the first I / O bus 134, and the first I / O 112, transfer is possible with the shortest path.

  Furthermore, in the present embodiment, for example, the CPU 140 can stop the first DMA transfer of the first ASIC 110 and perform DMA transfer of the remaining untransferred data of the first DMA transfer to the second DMAC 123. The interrupt number indicated by the management number of the first DMAC 113 that is the transmission source of the remaining untransferred actor indicating the interrupt source corresponding to the second DMAC 123 in operation And an interrupt management unit 170 that manages a DMA management number that is a serial number indicating the correspondence order of each DMA transfer. These interrupt numbers and DMA management numbers are described in an interrupt number management table as shown in FIG. 3 as an example of a reference table included in the interrupt management unit 170. These interrupt numbers and DMA management numbers described in the interrupt number management table are updated by the CPU 140 and the DMAC control units 114 and 124 so as to always keep the latest state.

  At that time, when the first ASIC 110 initially set for processing the first DMA transfer by the CPU 140 and the first DMA transfer are finally completed, for example, when the interrupt numbers of the second ASIC 120 are different. In preparation, when the CPU 140 accepts the interrupt processing, the CPU 140 first refers to the interrupt number management table as shown in FIG. Recognize.

  For example, when the CPU 140 sets the first DMA transfer for the first DMAC 113, as shown in FIG. 3, the DMA management number 1 that is the serial number in the order of correspondence of the DMA transfer, and the main body that issues the interrupt request The interrupt number 1 indicated by the management number of the first DMAC 113 is added to the interrupt number management table. Next, the CPU 140 issues a DMA request to the first DMAC control unit 114 so that the second DMA transfer is performed by the first DMAC 113, and the CPU 140 also performs the second DMA transfer by the first DMAC 113. Since it is intended to be performed, the interrupt number is set to 1 as in the first DMA transfer, and the interrupt number 1 and the DMA management number 2 are added to the interrupt number management table. The first DMAC control unit 114 that has received the request for the second DMA transfer causes the second DMAC 123 to perform DMA transfer of the remaining untransferred data of the first DMA transfer. The DMA setting information serving as setting information for completing the DMA transfer of the untransferred data of the first DMA transfer is transferred to 124 together with the DMA management number (in this case, 1). The DMAC control unit 124 updates the interrupt number of the first DMA transfer corresponding to the DMA management number 1 in the interrupt number management table of the interrupt management unit 170 because it is the main body that issues an interrupt request.

  As described above, in the present embodiment, the interrupt number and the DMA management number are described in the interrupt number management table provided in the interrupt management unit 170, and the CPU 140 and each DMAC control unit 114, 124 always keep the latest interrupt number management table. Updated to keep state. For this reason, if the interrupt number managed by the interrupt management unit 170 is associated with the DMA management number, the interrupt number of the DMAC initially set by the CPU 140 is different from the interrupt number of the DMAC that finally completes the DMA transfer. Even in this case, the CPU 140 can correctly execute processing for each DMA transfer completion interrupt.

  Next, the DMA transfer operation by the bus control device 100 of this embodiment will be described with reference to the drawings. FIG. 4 shows that the second DMA transfer using the first DMAC is requested while the first ASIC is used as the bus master of the data bus and the first DMA transfer is being executed in the bus controller of this embodiment. FIG. 5 is a flowchart showing an operation process for switching the DMA transfer process of the untransferred data of the first DMA transfer shown in FIG. 4 from the first DMAC to the second DMAC. .

  While the first ASIC 110 is used as the bus master of the data bus 130 in the bus control device 100 of the present embodiment and the first DMA transfer is being executed, a subsequent second DMA transfer using the first DMAC 113 is requested, When the second DMA transfer is started, first, it is determined whether or not the first DMAC 113 on the bus master side is operating (step S401).

  If it is detected in step S401 that the first DMAC 113 is operating, it is determined whether or not the second DMAC 123 on the bus slave side is operating (step S411).

  On the other hand, if the first DMAC 113 is not detected as being in operation in step S401, the CPU 140 sets the second DMA transfer for the first DMAC 113 (step S402).

  Then, after starting the second DMA transfer to the first DMAC 113 (step S403), it is determined whether or not there is a second DMA transfer completion interrupt (step S404). If it is detected in step S404 that the second DMA transfer completion interrupt is present, the second DMA transfer is terminated. On the other hand, if it is detected in step S404 that there is no second DMA transfer completion interrupt, it is determined again whether there is a second DMA transfer completion interrupt (step S404).

  If it is detected in step S411 that the second DMAC 123 on the bus slave side is not in operation, the bus use efficiency is verified (step S412). In step S412, the first DMA transfer in operation is stopped, the remaining first DMA transfer for the unprocessed portion is processed by the second DMAC 123, and the second DMA transfer is processed by the first DMAC 113. Efficiency of the data bus 130 and the efficiency of the data bus 130 when the second DMA transfer is processed by the second DMAC 123 while the first DMA transfer 113 is operated as it is. To verify. The usage efficiency of the data bus 130 is calculated based on the determination of how much the data bus 130 is occupied, specifically, based on the clock (time).

  After verifying the bus efficiency in step S412, it is determined whether the usage efficiency of the data bus 130 is higher than that of the first DMAC 113 (step S413). If it is detected in step S413 that the usage efficiency of the first DMAC 113 is lower with respect to the usage efficiency of the data bus 130, then the second DMA transfer is set by the CPU 140 for the second DMAC 123 (step S413). S414), the second DMA transfer is started with respect to the second DMAC 123 (step S415).

  After the second DMA transfer is started, it is determined whether or not there is an interrupt for the completion of the second DMA transfer (step S416). If it is detected in step S416 that the second DMA transfer completion interrupt is present, the second DMA transfer ends. On the other hand, if it is detected in step S416 that there is no second DMA transfer completion interrupt, after the second DMA transfer is started again, it is determined whether or not there is a second DMA transfer completion interrupt (process step). S416).

  If it is detected in step S413 that the usage efficiency of the first DMAC 113 is higher than the usage efficiency of the data bus 130, it is determined whether or not the remaining transfer amount of the first DMAC 113 in operation is small ( Step S417). If it is detected in step S417 that the remaining transfer amount of the first DMAC 113 that is operating is small, then the second DMA transfer is set for the second DMAC 123 by the CPU 140 (step S414). After S414, as described above, the process continues to Step S415 and Step S416.

  On the other hand, if it is not detected in step S417 that the remaining transfer amount of the first DMAC 113 that is operating is small, the DMA transfer processing of the untransferred data of the first DMA transfer shown in FIG. Then, the process proceeds to the operation process for switching to the second DMAC 123.

  As shown in FIG. 5, when an operation process for switching the transfer process of the untransferred data of the first DMA transfer from the first DMAC 113 to the second DMAC 123 is started, the first DMAC control unit 114 first performs the first process. The operation of the DMAC 113 is stopped (step S501). Thereafter, the remaining transfer information which is untransferred data of the first DMA transfer is transmitted to the second DMAC control unit 124 (step S502).

  When the second DMAC control unit 124 receives the remaining transfer information of the first DMA transfer, the second DMAC control unit 124 sends the remaining transfer information of the first DMA transfer to the second DMAC 123. The DMA transfer of the untransferred data is set (step S503).

  Thereafter, the interrupt management information in the interrupt number management table provided in the interrupt management unit 170 that manages the interrupt source corresponding to the second DMAC 123 in operation is updated (step S504).

  After updating the interrupt management information, transfer of untransferred data, which is the remaining transfer information of the first DMA transfer, is started to the second DMAC 123 (step S505).

  Thereafter, the second DMA transfer is set for the first DMAC 113 by the CPU 140 (step S506), and the second DMA transfer is started for the first DMAC 113 (step S507).

  After the start of the second DMA transfer, it is determined whether or not there is a second DMA transfer completion interrupt (step S508). If it is detected in step S508 that there is a second DMA transfer completion interrupt, the second DMA transfer ends. On the other hand, when it is detected that there is no second DMA transfer completion interrupt, it is determined whether or not there is a second DMA transfer completion interrupt (step S508).

  Note that the first DMAC control unit 114 performs the DMAC switching process because the remaining transfer data of the active DMA transfer is small even though the data transfer efficiency is improved by switching the DMAC to be used. In addition, when the DMA transfer in operation is completed, it is more efficient to wait for the DMA transfer currently in operation to be completed than to switch the bus master. Therefore, the DMA transfer in operation without switching the DMAC. Wait for completion.

  As described above, the bus control device 100 according to the present embodiment uses the first DMAC 113 while the first ASIC 110 is used as the bus master of the data bus 130 to execute the first DMA transfer. When the DMA transfer is requested, the first DMAC control unit 114 causes the second DMAC control unit 124 to complete the DMA transfer of the remaining untransferred data of the first DMA transfer according to a predetermined condition. After transmitting the setting information for the second DMA transfer, the first DMAC 113 executes the second DMA transfer.

  For this reason, when it is desired to use the first DMAC 113 for the second DMA transfer while the first DMAC 113 is in operation, there is no need to wait until the operation of the first DMAC 113 in operation is completed. In the case of contention, the data transfer on the data bus 130 is executed quickly without taking extra time. Further, when the second DMA transfer is executed by the second DMAC 123 from the beginning, it may cause unnecessary occupancy of the data bus 130, so that the bus bandwidth when the DMA transfer conflicts is minimized. Can do. Further, since the DMAC control units of the respective devices exchange setting information via the data bus 130 or the DMA control line 160 without the intervention of the CPU 140, the CPU 140 that controls the operation of the bus control device 100 first If the DMA setting is performed only once, it is not necessary to stop or reset the DMA transfer in the middle, so that waste of operation control in the CPU 140 can be reduced.

  As mentioned above, although preferred embodiment of this invention was described referring an accompanying drawing, it cannot be overemphasized that this invention is not limited to the example which concerns. It will be apparent to those skilled in the art that various changes and modifications can be made within the scope of the claims, and these are naturally within the technical scope of the present invention. Understood.

  For example, in the first embodiment described above, the case where the number of ASICs serving as DMAC built-in devices sharing a data bus is described as two, but the ASIC serving as a DMAC built-in device sharing the data bus is The bus control device of the present invention can also be applied to three or more bus systems.

It is a block diagram which shows schematic structure of the bus control apparatus in the 1st Embodiment of this invention. It is a detailed explanatory view of a block diagram of the bus control device in the same embodiment. It is a figure which shows an example of the interrupt number management table contained in the interrupt management part of the bus control apparatus in the embodiment. Operation when a second DMA transfer is requested by using the first DMAC during execution of the first DMA transfer with the first ASIC as the data bus bus master in the bus controller in the embodiment It is a flowchart which shows a process. 6 is a flowchart showing an operation process for switching the transfer process of untransferred data of the first DMA transfer shown in FIG. 4 from the first DMAC to the second DMAC. It is a block diagram which shows schematic structure of the conventional bus control apparatus.

Explanation of symbols

100 Bus control device 110 One DMAC built-in device (first ASIC)
113 One DMAC (first DMAC)
114 One DMAC control unit (first DMAC control unit)
120 Other DMAC built-in device (second ASIC)
123 Other DMAC (second DMAC)
124 Other DMAC control unit (second DMAC control unit)
130 Data bus 140 CPU
160 Setting information dedicated line (DMA control line)
170 Interrupt Manager

Claims (8)

A bus control device that performs control for causing a plurality of DMAC built-in devices including a DMAC (Direct Memory Access Controller) that controls DMA (Direct Memory Access) transfer of data to use a data bus connecting the DMAC built-in devices. And
While a first DMA transfer is being executed with one DMAC-embedded device as the bus master of the data bus, a subsequent second DMA transfer is requested by using one DMAC included in the one DMAC-embedded device. A bus control device that determines a DMAC that executes a DMA transfer of the remaining untransferred data of the first DMA transfer and a DMAC that executes the second DMA transfer according to a predetermined condition. The DMAC built-in device includes a DMAC control unit that controls the operation of the DMAC,
The predetermined condition is that one DMAC control unit included in the one DMAC stops the first DMA transfer in operation, and other DMA transfers of the remaining untransferred data of the first DMA transfer are performed. A first condition in which the second DMA transfer is processed by the one DMAC;
A second condition for processing the second DMA transfer with the other DMAC while operating the DMA transfer of the remaining untransferred data of the first DMA transfer as it is with the one DMAC;
The bus control device according to claim 1, which means a comparison result obtained by determining use efficiency of the data bus in this case.   When the one DMAC control unit detects that the first condition is more efficient in using the data bus, the one DMAC control unit transfers to another DMAC control unit provided in the other DMAC built-in device. 3. The bus control device according to claim 2, wherein setting information for completing the DMA transfer of the remaining untransferred data of the first DMA transfer is transmitted.   A setting information dedicated line for communicating the setting information is provided between the plurality of DMAC built-in devices so as to connect the plurality of DMAC built-in devices independently of the data bus. The bus control device according to claim 3.   5. The second DMA transfer is processed by the DMAC under the condition that the use efficiency of the data bus is improved in the comparison result determined by the one DMAC control unit. 6. The bus control device according to claim 1.   The bus control device according to claim 1, wherein the DMAC includes a management number setting area to which a unique management number corresponding to an active DMA transfer is assigned.   When the CPU for controlling the operation of the bus control device sets the first DMA transfer, the management number is attached to the transfer data of the first DMA transfer, and the number information of the management number is the management number. When the first DMA transfer is stopped because the one DMAC competes with the setting area, and the first DMA transfer shifts to another DMAC, the number information of the management number is also 7. The bus control device according to claim 6, wherein the bus control device transmits and sets to the other DMAC at the same time.   When the one DMAC built-in device stops the first DMA transfer and transmits / sets the remaining untransferred data of the first DMA transfer to the other DMAC, the other DMAC that is operating An interrupt number indicated by the management number assigned to the one DMAC which is a transmission source of the remaining untransferred eta corresponding to the DMAC, and a DMA management number which is a serial number indicating the correspondence order of the DMA transfer, The bus control device according to claim 1, further comprising an interrupt management unit that manages

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