JP2008160578A - Synchronous control device - Google Patents

Abstract

A synchronization control device capable of synchronizing the operation of an asynchronous circuit with the operation of a reference circuit without making the buffer size redundant.
A first processing block that executes a first process and outputs a first instruction signal upon completion of the first process, and operates so that a processing speed can be changed according to supplied power. A second processing block of an asynchronous circuit that executes a second process related to the process of the first processing block and outputs a second instruction signal when the second process is completed; and the first instruction signal And a control means for determining a power value to be supplied to the second processing block according to a time difference between input timings of the second instruction signal and a power corresponding to the power value to the second processing block Supply means.
[Selection] Figure 1

Description

  The present invention relates to a synchronous control device for an asynchronous circuit.

  Conventionally, in the field of electronic circuit design, a synchronous circuit design technique for designing by a combination of sequential circuits synchronized with a clock frequency has been used. On the other hand, there is an asynchronous circuit design technique for designing on the basis of another signal (for example, a communication protocol) without using a clock frequency as a reference for operation. In addition, a device that realizes a predetermined function by combining a synchronous circuit and an asynchronous circuit created by both of these techniques is widely used.

  For the asynchronous circuit described above, various techniques have been proposed. For example, in Patent Document 1, a voltage corresponding to the buffer fullness of the processing block is applied to a processing block designed as an asynchronous circuit. Thus, a technique for controlling the processing speed of the processing block and preventing data from overflowing from the buffer is disclosed.

JP-A-5-265607

  However, the technique described in Patent Document 1 has a problem that the buffer size becomes redundant and power consumption increases because environmental changes such as temperature and voltage are compensated only by the buffer. In the technique described in Patent Document 1, the control loop relating to the control of the processing block is closed, and no consideration is given to the relationship with other circuits. Therefore, there is a problem that it cannot be applied when there is a time limit such as synchronization of processing speed in relation to the operation of other circuits.

  The present invention has been made in view of the above, and provides a synchronization control device capable of synchronizing the operation of an asynchronous circuit with the operation of a reference circuit without making the buffer size redundant. With the goal.

  In order to solve the above-described problems and achieve the object, the invention according to claim 1 executes a first process and outputs a first instruction signal when the first process is completed. And a second instruction signal when the second process is completed, and the second process related to the process of the first process block is executed. And a control means for determining a power value to be supplied to the second processing block in accordance with a time difference in input timing between the first instruction signal and the second instruction signal. And supply means for supplying power corresponding to the power value to the second processing block.

  According to the present invention, the power of the second processing block is determined according to the time difference between the input timings of the first instruction signal from the first processing block serving as a reference and the second instruction signal from the second processing block. Determine and supply the value. Therefore, the operation of the second processing block of the asynchronous circuit can be synchronized with the operation of the reference first processing block without making the buffer size redundant.

  Exemplary embodiments of an asynchronous circuit control device will be described below in detail with reference to the accompanying drawings.

[First Embodiment]
FIG. 1 is a block diagram showing the configuration of the synchronization control device 1 according to the present embodiment. As shown in FIG. 1, the synchronization control device 1 includes a processing block 11, a buffer 12, a processing block 13, a buffer 14, a post-processing block 15, a power supply control unit 16, and a voltage variable circuit 17.

  The processing block 11 is configured by a synchronous circuit or an asynchronous circuit, performs predetermined data processing, and generates DATA1 as the processing result. In addition, the processing block 11 outputs the generated DATA1 to the buffer 12, and outputs a trigger signal TRG1 that indicates that the DATA1 is updated new data to the buffer 12 and the power supply control unit 16.

  The buffer 12 is a storage device having a volatile storage medium. When receiving the TRG1 from the processing block 11, the buffer 12 holds DATA1 input together with the TRG1 as DATA1 'until the next TRG1 is input. The buffer 12 outputs the trigger signal TRG1 'to the post-processing block 15 every time the DATA1' is updated, and notifies the post-processing block 15 that the new DATA1 is held.

  The processing block 13 is composed of an asynchronous circuit, performs predetermined data processing, and generates DATA2 as a processing result. In addition, the processing block 13 outputs the generated DATA2 to the buffer 14 and outputs a trigger signal TRG2 instructing that the DATA2 is new data to the buffer 14 and the power supply control unit 16.

  The processing target data processed in the processing block 11 and the processing block 13 are different from each other, but both data have a paired relationship, and both processed data (DATA1 ′, DATA2 ′). Based on the above, processing is performed in the post-processing block 15 in the subsequent stage.

  In the present embodiment, in the post-processing block 15, it is assumed that time constraints are set for the input timing of both processed data (DATA 1 ′, DATA 2 ′). Therefore, the processing target data to be processed by the processing block 11 and the processing block 13 has a temporal relationship with respect to the operations of the processing block 11 and the processing block 13. It is related to the synchronization. The processing target data is input to each of the processing block 11 and the processing block 13 in units of data from an external device (circuit) (not shown).

  The buffer 14 is a storage device provided with a volatile storage medium. When receiving the TRG2 from the processing block 13, the buffer 14 holds DATA2 input together with the TRG2 as DATA2 'until the next TRG2 is input. The buffer 14 outputs the trigger signal TRG2 'to the post-processing block 15 every time the DATA2' is updated, and notifies the post-processing block 15 that the new DATA2 is held.

  The post-processing block 15 acquires DATA1 ′ from the buffer 12 and DATA2 ′ from the buffer 14 when the trigger signals TRG1 ′ and TRG2 ′ are both in the data update state, and performs predetermined processing and computation based on these data. A circuit (device) to perform.

  The power supply control unit 16 monitors TRG1 and TRG2, compares the data of TRG1 and TRG2 that have been updated first when both indicate data update, and determines the control signal REGIN according to the time difference as a voltage. Output to the variable circuit 17. Here, the determination of the prior relationship between TRG1 and TRG2 is based on the trigger signals (TRG1 and TRG2) that are input when the processing target data related to the synchronization between the first processing block and the second processing block is completed. Shall be performed.

  The voltage variable circuit 17 supplies the processing block 13 with power having a voltage value REGOUT instructed by REGIN using REGIN as a reference signal. Although the voltage value (REGOUT) indicated by REGIN will be described later, it is assumed that the voltage value at which the time difference between TRG1 and TRG2 is a predetermined time is indicated.

  Next, the power supply control unit 16 described above will be described in detail. In this embodiment, each of TRG1 and TRG2 output from the processing block 11 and the processing block 12 is a single pulse having a time width within one reference clock time as a signal indicating the end of processing of one data unit. It shall be output in the form of a signal.

  FIG. 2 is a diagram showing an internal configuration of the power control unit 16. As shown in FIG. 2, the power supply control unit 16 includes a control voltage generation unit 161, a JK-FF (Jack Knife Flip-Flop) circuit 162, an OR circuit 163, a NAND circuit 164, an AND circuit 165, a T-FF (Toggle). Flip-Flop) circuit 166 is provided.

  The control voltage generator 161 includes a counter circuit 1611, a multiplier 1612, and a DA converter 1613 inside. The counter circuit 1611 includes a register for holding a counter value therein, and performs counting up or counting down according to the input of the input terminal SIGN while 1 is input to the input terminal VALID. For example, when 1 is input to SIGN, the counter value held therein is counted up, and when 0 is input, it is counted down. Note that the magnitude of the counter value is related to the value of the voltage value supplied to the processing block 13, and the voltage (power) corresponding to the counter value is supplied to the processing block 13.

  The multiplier 1612 multiplies the output value (counter value) from the counter circuit 1611 by a coefficient α. The DA converter 1613 converts the output value multiplied by the coefficient α into an analog signal, and then outputs it as a REGIN signal. Here, it is assumed that the coefficient α is stored in advance in a storage device such as a register (not shown), and the multiplier 1612 reads the value every time. Note that the aspect relating to the acquisition of the coefficient α is not limited to this, and may be, for example, an aspect in which the value of the coefficient α is received from an external control processor.

  As shown in FIG. 2, the signals of TRG1 and TRG2 are countered via the JK-FF circuit 162 to the SIGN input of the counter circuit 1611, and through the OR circuit 163, NAND circuit 164, AND circuit 165, and T-FF circuit 166. Connected to the VALID input of circuit 1611.

  The signal input to SIGN of the counter circuit 1611 is determined by inputting TRG1 to J and TRG2 to K of the JK-FF circuit 162. Here, the JK-FF circuit 162 inputs “1” to the SIGN of the counter circuit 1611 when TRG1 inputs the pulse signal first and “0” when the TRG2 inputs the pulse signal first. Output.

  Further, the signal input to VALID of the counter circuit 1611 is determined by TRG1 and TRG2 passing through the logic circuit (OR circuit 163 to T-FF circuit 166) shown in FIG. Here, the logic circuit operates so that the counter signal is switched ON / OFF every time the TRG1 and TRG2 pulse signals are generated.

For example, as shown in FIG. 3A, when a pulse signal first appears in TRG1, SIGN is “1”, and VALID is “1” during the time interval Δt from the TRG1 pulse signal to the TRG2 pulse signal. It becomes. During this time, the counter value is incremented. In FIG. 3-2, on the contrary, SIGN is “0” during the time interval Δt from the TRG2 pulse signal to the TRG1 pulse signal and becomes “1” after the TRG1 pulse signal is input. Since only Δt is “1”, the counter value is subtracted only during that period. In FIG. 3C, TRG1 and TRG2 output pulse signals simultaneously, and SIGN changes. However, since VALID remains 0, the counter value does not change.

Specifically, while the VALID is “1”, the control voltage generation unit 161 sets the amount (time) corresponding to the integral value of the VALID signal as the time interval Δt, and determines the value of SIGN in the time interval Δt. Thus, it is determined which processing time of the processing block 11 or the processing block 13 is earlier. For example, if SIGN is “0”, it can be considered that the processing time of the processing block 13 is early, so the counter value is subtracted in the direction of decreasing the voltage, that is, in the negative direction. In this case, the output value from the counter circuit 1611 is output as REGIN having a waveform as shown in FIG. 4A after undergoing the processing of the multiplier 1612 and the DA converter 1613. Further, as shown in FIG. 4B, the above operation is repeated for a plurality of cycles, whereby the voltage can be lowered from the voltage V at the start of the operation to the target voltage V1. On the other hand, when it is determined that the processing time of the processing block 11 is early, the counter value is added in the direction of increasing the voltage, that is, in the positive direction.

  Note that the coefficient α is a control amount determined in advance according to the operation specifications of the voltage variable power supply 17, and it is assumed that the time until the voltage value converges is increased by increasing the value of α. Conversely, by reducing the value of α, the time until the voltage value converges is increased.

  As described above, according to the synchronization control device 1 of the present embodiment, the power value of the processing block 13 according to the time difference between the input timings of the TRG 1 from the reference processing block 11 and the TRG 2 from the processing block 13. Determine and supply. Thereby, even if it is a case where it fluctuates due to a change in processing parameter or a temperature change, the operation of the processing block 13 can be synchronized with the operation of the reference processing block 11 without making the buffer size redundant. Thereby, the efficiency of the process performed by the cooperation of the process block 11 and the process block 13 can be achieved.

  In the present embodiment, the power supply control unit 16 includes a logic circuit (OR circuit 163 to T-FF circuit 166). However, the configuration is not limited to this, and may be configured as shown in FIG. . Hereinafter, another mode (power control unit 18) of the power control unit 16 will be described with reference to FIG.

  FIG. 5 is a diagram showing an internal configuration of the power supply control unit 18. As illustrated in FIG. 5, the power supply control unit 18 includes an EXOR circuit 181 instead of the logic circuit (OR circuit 163 to T-FF circuit 166) described in FIG. 2. In this embodiment, the processing block 11 and the processing block 13 switch the pulse state of TRG1 and TRG2 from negate (0) to assert (1) when generating (updating) new DATA1 and DATA2. It is assumed that the data is output continuously until the process is started.

  In the above configuration, as shown in FIG. 6, TRG1 and TRG2 complete the predetermined processing by updating each of the processing block 11 and the processing block 13 and update the data DATA1 and DATA2 as the processing results. Change to 1.

  The EXOR circuit 181 calculates an exclusive OR of the input TRG1 and TRG2, and outputs the result (VALID signal) to the VALID of the counter circuit 1611. For example, when TRG2 finishes processing before TRG1, a VALID signal having a waveform as shown in FIG. 6 is output. Further, the input TRG1 is configured to be input to the SIGN of the counter circuit 1611, and is used as a control voltage code.

  With the above configuration, compared with the configuration of the power supply control unit illustrated in FIG. 2, the circuit scale can be further simplified and the cost can be reduced and the power consumption can be suppressed.

  Further, the control voltage generation unit 161 may adopt a configuration as shown in FIG. Hereinafter, another aspect of the control voltage generation unit 161 (the control voltage generation unit 19) will be described with reference to FIG.

  FIG. 7 is a diagram showing an internal configuration of the control voltage generator 19. As shown in FIG. 6, the control voltage generation unit 19 includes a switch 191, an inverter 192, an integrator 193, and a multiplier 194.

  The switch 191 switches the output end of the signal input to VALID according to the value of the signal input to SIGN, and connects to the input end of the inverter 192 or the input end of the path L1 that bypasses the inverter 192. For example, when the value of the signal input to SIGN is “0”, the output terminal of the signal input to VALID is switched to be connected to the input terminal of the inverter 192. The inverter 192 inverts the value of the input signal and outputs it to the integrator 193.

  The integrator 193 outputs a signal that increases the voltage value when the value is positive and decreases the voltage value when the value is negative according to the value of the input signal. The multiplier 194 multiplies the output signal from the integrator 193 by a coefficient α, and then outputs this signal as REGIN.

  In such a configuration, the function of the control voltage generation unit 161 described above can be realized only by an analog circuit, so that the circuit scale can be reduced by an amount unnecessary for the DA converter 1613, resulting in consumption. Power can be reduced.

[Second Embodiment]
Next, a second embodiment of the asynchronous circuit control device will be described. In addition, about the element similar to 1st Embodiment mentioned above, it shows using the same code | symbol and the description is abbreviate | omitted suitably.

  FIG. 8 is a block diagram showing the configuration of the synchronization control device 2 of the present embodiment. As shown in FIG. 8, each functional unit of the synchronization control device 2 is configured by the same functional units as those in the first embodiment (see FIG. 1) except for the power supply control unit 21. 11 differs in that signal processing is performed using the processing data of the processing block 13 as an input. Specifically, the processing block 11 receives DATA2 ′ from the buffer 14 according to the trigger signal of TRG2 ′, performs a predetermined process, and then outputs the processing result DATA1 to the buffer 12 together with the trigger signal TRG1. .

  In FIG. 8, the processing block 11 performs processing of the data (DATA2 ′) processed in the processing block 13, but a time restriction is set for the processing time of the processing block 11 and the processing block 13. Shall. Therefore, the processing target data to be processed by the processing block 11 and the processing block 13 has a temporal relationship with respect to the operations of the processing block 11 and the processing block 13. It is related to the synchronization. It is assumed that processing target data to be processed by the processing block 13 is input from an external device (circuit) (not shown).

  FIG. 9 is a diagram showing an internal configuration of the power supply control unit 21. As shown in FIG. 9, the power supply control unit 21 of this embodiment is obtained by adding a delay circuit 211 to the configuration of the power supply control unit 16 shown in FIG.

  The delay circuit 211 receives TRG2 from the processing block 13 and a delay amount T2 to be described later, and operates to delay the input timing of TRG2 by a time corresponding to T2, as shown in FIG. Then, the delay circuit 211 outputs the delayed TRG2 as TRG2T to the JF-FF circuit 162, the OR circuit 163, and the NAND circuit 164.

  Here, the delay amount T2 is a signal for instructing the delay amount by the delay circuit 211, and may be stored in advance in the delay circuit 211, or may be input from an external control device or the like. Note that a value based on the connection position between the processing block 11 and the processing block 13, the timing of the operation between the processing block 11 and the processing block 13, or the like may be set as the delay amount indicated by T <b> 2. It is preferable that a value capable of efficiently performing processing is set.

  The TRG2T output from the delay circuit 211 is processed in the same manner as the TRG2 in FIG. 2 described above. When the TRG2T outputs a pulse signal after the TRG1, the signal as shown in FIG. The data is output to SIGN and VALID of the generation unit 161. On the contrary, when TRG1 is after TRG1, the signal as shown in FIG. 11-2 and the signal as shown in FIG. 11-3 are the same as the SIGN of the control voltage generator 161. Output to VALID.

  In the above configuration, the output value from the counter circuit 1611 is output as REGIN having a waveform as shown in FIG. 4A after being processed by the multiplier 1612 and the DA converter 1613. Further, as shown in FIG. 4B, the above operation is repeated for a plurality of cycles, whereby the voltage can be lowered from the voltage V at the start of the operation to the target voltage V1.

  As described above, the power value of the processing block 13 is determined and supplied according to the time difference between the input timings of the TRG 1 output from the reference processing block 11 and the TRG output from the processing block 13. Thereby, even if it is a case where it fluctuates due to a change in processing parameter or a temperature change, the operation of the processing block 13 can be synchronized with the operation of the reference processing block 11 without making the buffer size redundant. Thereby, the efficiency of the process performed by the cooperation of the process block 11 and the process block 13 can be achieved.

  In the present embodiment, the power supply control unit 21 includes a logic circuit (OR circuit 163 to T-FF circuit 166). However, the configuration is not limited thereto, and for example, the configuration illustrated in FIG. Good. Hereinafter, with reference to FIG. 12, another mode (power control unit 22) of the power control unit 21 will be described.

  FIG. 12 is a diagram showing an internal configuration of the power supply control unit 22. As shown in FIG. 12, the power supply control unit 22 includes an EXOR circuit 221 instead of the logic circuit (OR circuit 163 to T-FF circuit 166) described in FIG. In the present embodiment, the processing block 11 and the processing block 13 output the pulse state of TRG1 and TRG2 by switching from negate (0) to assert (1) when generating (updating) new DATA1 and DATA2. It shall be.

  In the above configuration, TRG1 and TRG2 change from 0 to 1 when each of the processing block 11 and the processing block 13 completes predetermined processing and updates DATA1 and DATA2 as processing results.

  As shown in FIG. 13, the delay circuit 211 delays the input timing of the TRG2 by T2, and outputs it to the EXOR circuit 221 as TGR2T.

  The EXOR circuit 221 calculates the exclusive OR of the input TRG1 and TRG2T and outputs the result (VALID signal) to the VALID of the counter circuit 1611. For example, when TRG2T finishes processing before TRG1, a VALID signal having a waveform as shown in FIG. 14 is output. Further, the input TRG1 is configured to be input to the SIGN of the counter circuit 1611, and is used as a control voltage code.

  With the above configuration, compared with the configuration of the power supply control unit illustrated in FIG. 9, the circuit scale can be further simplified and the cost can be reduced and the power consumption can be suppressed.

  Further, the synchronization control device 2 described above can be applied to various uses. Hereinafter, a specific application example of the synchronization control device 2 will be described.

  FIG. 15 is a diagram illustrating a configuration of the frame processing device 3 to which the synchronization control device 2 is applied. The frame processing device 3 is used in a wireless communication system or the like, and performs predetermined processing for each data (frame) in a predetermined time (frame time) section.

  As illustrated in FIG. 15, the frame processing device 3 corresponds to the frame control processing unit 31 corresponding to the processing block 11, the buffer 32 corresponding to the buffer 12, the turbo decoding processing unit 33 corresponding to the processing block 13, and the buffer 14. A buffer 34, a post-processing unit 35 corresponding to the post-processing block 15, a power control unit 36 corresponding to the power control unit 21, a voltage variable power source 37 corresponding to the voltage variable power source 17, and a frame buffer 38 are provided.

  The frame buffer 38 stores a plurality of processing target data (processing target data) divided into frame units. It is assumed that the data to be processed has been previously turbo encoded by an encoder (not shown), and the frame buffer 38 stores turbo encoded data.

  The turbo decoding processing unit 33 is a functional unit corresponding to the processing block 23 and performs turbo decoding processing for decoding a turbo code on a data set of processing target data stored in the frame buffer 38. In addition, the turbo decoding processing unit 33 outputs the processing result DATA2 to the buffer 34, and sends a trigger signal SIG2 (TRG2) instructing that the DATA2 is new data to the buffer 34 and the power supply control unit 26. Output.

  When the buffer 34 receives SIG2 from the buffer turbo decoding processor 33, the buffer 34 holds DATA2 input together with the SIG2 as DATA2 'until the next SIG2 is input. The buffer 34 outputs the trigger signal SIG2 'to the frame control processing unit 31 every time the DATA2' is updated, and notifies the frame control processing unit 31 that the new DATA2 'is held.

  The frame control processing unit 31 performs a frame control process for converting the data to be processed (DATA2 ') into a MAC frame. Further, the frame control processing unit 31 outputs the processing result DATA1 to the buffer 32, and sends a trigger signal SIG1 (TRG1) to the buffer 32 and the power supply control unit 26 to instruct that the DATA1 is new data. Output.

  Upon receiving SIG1 from the frame control processing unit 31, the buffer 32 holds DATA1 input together with the SIG1 as DATA1 'until the next SIG1 is input. Further, the buffer 32 outputs the trigger signal SIG1 'to the post-processing unit 35 every time the DATA1' is updated, and notifies the post-processing unit 35 that the new DATA1 'is held.

  The post-processing unit 35 acquires DATA1 ′ from the buffer 32 when the trigger signal TRG1 ′ is in the data update state, and performs predetermined processing, calculation, and the like based on the DATA1 ′. Output to layer or application layer.

  In the above configuration, in order to perform processing efficiently, the operation of the turbo decoding processing unit 33 and the operation of the frame control processing unit 31 need to be synchronized at a predetermined timing. Hereinafter, the operation of the power supply control unit 26 related to the control of the operations of the turbo decoding processing unit 33 and the frame control processing unit 31 will be described.

  First, it is assumed that the voltage value supplied to the frame control processing unit 31 to operate in one frame time is set in advance. In this case, it is assumed that the voltage V1 and power P1 of the frame control processing unit 31 are as shown in the graph shown in the upper part of FIG. Here, the processing time Tp2 of the frame control process corresponds to one frame time.

  On the other hand, it is assumed that the voltage in the initial state supplied to the turbo decoding processing unit 33 is V2 'in the graph shown in the middle stage of FIG. 16, and the processing time at this time is Tp2'. Further, it is assumed that the power consumption of the turbo decoding processing unit 33 is P2 'in the graph shown in the lower part of FIG. 16, and the processing time at this time is Tp2'.

  In the above state, it is assumed that the frame control processing unit 31 performs frame control processing for one frame, and the state of SIG1 changes from 0 to 1 after the processing is completed. In addition, it is assumed that the turbo decoding processing unit 33 performs turbo decoding processing for one frame for Tp2 ', and the state of SIG2 changes from 0 to 1 after the processing ends.

  In such a case, the power supply control unit 36 applies a voltage to the turbo decoding processing unit 33 according to the time difference between the acquisition timings of SIG1 and SIG2 input from the frame control processing unit 31 and the turbo decoding processing unit 33, respectively. The value is determined as V2 corresponding to one frame time (see the middle part of FIG. 16).

  Therefore, as shown in the lower graph of FIG. 16, the voltage value of the turbo decoding processing unit 33 becomes V2 as a result of control by the power supply control unit 26. Therefore, the power consumption of the turbo decoding processing unit 33 is P2, the processing time is Tp2.

Here, as a specific numerical example, consider a case where the initial voltage value V2 ′ and the post-control voltage value V2 of the turbo decoding processing unit 33 are set to V2 ′ = 1.2V and V2 = 0.8V, respectively. In this case, the ratio of the power consumption after the initial state and the control is P2 ′ = (V2 ′) ² , P2 = (V2) ² , Tp2 ′ = Tp2 / 2. It can be seen that the power consumption after the control is smaller than the power consumption in the initial state.
P2 × Tp2 / (P2 ′ × Tp2 ′) = 0.64 × Tp2 / (1.44 × Tp2 ′) = 1.28 / 1.44 <1.0 (1)

  That is, according to the configuration of the present embodiment, the turbo decoding processing unit 33 can be operated in accordance with the operation time of the reference frame control processing unit, and the power consumption of the turbo decoding processing unit 33 can be suppressed. Can do.

[Third Embodiment]
Next, a third embodiment of the asynchronous circuit control device will be described. In addition, about the element similar to 1st and 2nd embodiment mentioned above, it shows using the same code | symbol and the description is abbreviate | omitted suitably.

  FIG. 17 is a block diagram showing the configuration of the synchronization control device 4 of the present embodiment. As shown in FIG. 17, in the configuration of the synchronization control device 4 of the present embodiment, the relationship between the processing block 11 and the processing block 13 is reversely connected in the configuration of FIG. 8 described above. .

  In FIG. 17, the processing block 13 performs processing of the data (DATA1 ′) processed in the processing block 11, and time restrictions are set for the processing times of the processing block 13 and the processing block 11. Shall. Therefore, the processing target data to be processed by the processing block 13 and the processing block 11 has a temporal relationship with respect to the operations of the processing block 13 and the processing block 11. It is related to the synchronization. It is assumed that processing target data to be processed by the processing block 11 is input from an external device (circuit) (not shown).

  FIG. 18 is a diagram illustrating an internal configuration of the power supply control unit 41 of the present embodiment. As shown in FIG. 18, the configuration of the power supply control unit 41 is obtained by adding a delay circuit 411 to the configuration of FIG. 2 described above.

  As shown in FIG. 19, the delay circuit 411 operates so as to delay the input timing of TRG1 by a time designated by a delay amount T1 described later. The delay circuit 411 outputs the delayed TRG1 as TRG1T to the JF-FF circuit 162, the OR circuit 163, and the NAND circuit 164.

  Here, the delay amount T1 is a signal for instructing the delay amount by the delay circuit 411, and may be stored in advance in the delay circuit 411 or may be input from an external control device or the like. Note that a value based on the connection position between the processing block 11 and the processing block 13, the timing of the operation between the processing block 11 and the processing block 13, or the like may be set as the delay amount indicated by T <b> 1. It is preferable that a value capable of efficiently performing processing is set.

  The TRG1T output from the delay circuit 411 is processed in the same manner as the TRG2 of the first embodiment described above. When the TRG1T outputs a pulse signal after the TRG2, the signal as shown in FIG. Are output to SIGN and VALID of the control voltage generator 161. Conversely, when TRG2 outputs a pulse signal after TRG1T, signals as shown in FIG. 20-2 are output to SIGN and VALID of the control voltage generation unit 161. Further, when the TRG2 pulse signal and the TRG1T pulse signal are output simultaneously, signals as shown in FIG. 20-3 are output to SIGN and VALID of the control voltage generator 161.

  In the above configuration, the output value from the counter circuit 1611 is output as REGIN having a waveform as shown in FIG. 4A after being processed by the multiplier 1612 and the DA converter 1613. Further, as shown in FIG. 4B, the above operation is repeated for a plurality of cycles, whereby the voltage can be lowered from the voltage V at the start of the operation to the target voltage V1.

  As described above, according to the synchronization control device 4 of the present embodiment, the power value of the processing block 13 according to the time difference between the input timings of the TRG 1 from the reference processing block 11 and the TRG 2 from the processing block 13. Determine and supply. Thereby, even if it is a case where it fluctuates due to a change in processing parameter or a temperature change, the operation of the processing block 13 can be synchronized with the operation of the reference processing block 11 without making the buffer size redundant. Thereby, the efficiency of the process performed by the cooperation of the process block 11 and the process block 13 can be achieved.

  In the present embodiment, the power supply control unit 41 includes a logic circuit (OR circuit 163 to T-FF circuit 166). However, the configuration is not limited thereto, and for example, the configuration illustrated in FIG. Good. Hereinafter, another mode (power control unit 42) of the power control unit 41 will be described with reference to FIG.

  FIG. 21 is a diagram showing an internal configuration of the power supply control unit 42. As shown in FIG. 21, the power supply control unit 42 includes an EXOR circuit 421 instead of the logic circuit (OR circuit 163 to T-FF circuit 166) described in FIG. In the present embodiment, the processing block 11 and the processing block 13 output the pulse state of TRG1 and TRG2 by switching from negate (0) to assert (1) when generating (updating) new DATA1 and DATA2. It shall be.

  In the above configuration, TRG1 and TRG2 change from 0 to 1 when each of the processing block 11 and the processing block 13 completes predetermined processing and updates DATA1 and DATA2 as processing results.

  As shown in FIG. 22, the delay circuit 411 delays the input TRG1 by T1, and outputs it to the EXOR circuit 421 as TGR1T.

  The EXOR circuit 421 calculates the exclusive OR of the input TRG2 and TRG1T, and outputs the result (VALID signal) to the VALID of the counter circuit 1611. For example, when TRG1T finishes processing before TRG2, a VALID signal having a waveform as shown in FIG. 23 is output. The TRG1T subjected to the delay process is configured to be input to the SIGN of the counter circuit 1611, and is used as a control voltage sign.

  Compared with the configuration of the power supply control unit shown in FIG. 18, the configuration described above can be simplified and the circuit scale can be reduced, so that the cost can be reduced and the power consumption can be suppressed.

  The above-described synchronization control device 4 can be applied to various uses. Hereinafter, a specific application example of the synchronization control device 4 will be described with reference to FIG.

  FIG. 24 is a diagram illustrating a configuration of the despreading processing device 5 to which the synchronization control device 4 is applied. This despreading processing device 5 is used for a CDMA wireless device or the like, and generates a spreading code in accordance with each path timing of multipath, multiplies it by received sampling data, and synthesizes it by RAKE processing. is there.

  Here, the multipath increases / decreases depending on the location and moving speed of the receiver. Therefore, when there is only one path, despreading multiplication is performed once per sample data, but when there are multiple paths, it is proportional to the number of paths. Then increase. In other words, the clock of the input sampling data is always constant, but the number of processes increases in proportion to the number of passes.

  The despreading processing device 5 includes an AD conversion processing unit 51 corresponding to the processing block 11, a buffer 52 corresponding to the buffer 12, a despreading processing unit 53 corresponding to the processing block 13, a buffer 54 corresponding to the buffer 14, and a post-processing block 15, a power supply control unit 56 corresponding to the power supply control unit 41, and a voltage variable power supply 57 corresponding to the voltage variable power supply 17.

  The AD conversion processing unit 51 digitally converts an analog baseband signal to be processed into digital data, and generates the AD converted data as DATA1. In addition, the AD conversion processing unit 51 outputs the generated DATA1 to the buffer 52, and outputs a trigger signal TRG1 indicating that the DATA1 is updated new data to the buffer 52 and the power supply control unit 56. .

  When receiving TRG1 from the AD conversion processing unit 51, the buffer 52 holds DATA1 input together with the TRG1 as DATA1 'until the next TRG1 is input. The buffer 52 outputs the trigger signal TRG1 'to the despreading processing unit 53 every time the DATA1' is updated, and notifies the despreading processing unit 53 that the new DATA1 is held.

  The despreading processing unit 53 includes six code generators 531 to 536, a multiplexer 537, and a multiplier 538. Each of the code generators 531 to 536 generates the same spreading code at different timings, and outputs the generated spreading code to the multiplexer 537. The despreading processing unit 53 operates only the number corresponding to the number of paths to be received among the code generators 531 to 532.

  The multiplexer 537 sequentially selects the spreading codes generated by the code generators 531 to 536 and outputs them to the multiplier 538. The multiplier 538 multiplies the spreading code input from the multiplexer 537 and the data held in the buffer 52 and outputs the processing result to the buffer 54 as DATA2.

  Further, when the despreading process for the paths to be combined is completed, the despreading processing unit 53 outputs a trigger signal TRG2 indicating this to the buffer 54 and to the power supply control unit 56.

  For example, when performing despreading processing of six paths, the despreading processing unit 53 generates spreading codes according to the timing of each path by the code generators 531 to 536 for DATA1 ′ of the buffer 52, respectively. A series of operations of outputting the multiplication result of the spread code and the data from the buffer 52 to the RAKE processing unit 55 is performed six times.

  The buffer 54 holds DATA2 input from the despreading processing unit 53 as DATA2 '. Further, when receiving the TRG2 from the despreading processing unit 53, the buffer 54 outputs a trigger signal TRG2 ′ to the RAKE processing unit 55 and notifies the RAKE processing unit 55 that the new DATA2 ′ is held. .

  When receiving the trigger signal TRG2 ', the RAKE processing unit 55 acquires DATA2' from the buffer 54, and synthesizes the DATA2 'according to the delay for each path.

  The power supply control unit 56 monitors TRG1 and TRG2, compares the data of TRG1 and TRG2 that have been updated first when both indicate data update, and determines the control signal REGIN according to the time difference as a voltage. Output to the variable power source 57.

  The voltage variable circuit 57 supplies the despreading processing unit 53 with power that becomes the voltage value REGOUT instructed by REGIN using REGIN as a reference signal. It is assumed that the voltage value (REGOUT) indicated by REGIN is a value set in advance so that the time difference between TRG1 and TRG2 becomes a predetermined value.

  Specifically, when the number of receivable paths changes to one path, the processing time of the despreading processing unit 53 is shortened to about 1/6, and the power supply control unit 56 reads this change from the time difference between TRG1 and TRG2. The voltage control signal REGIN corresponding to the time difference is given to the voltage variable power source 57, and the voltage variable power source 57 changes the voltage for the despreading processing unit 53 to one corresponding to the processing time of the number of passes 1 to reduce the processing speed. Let

  By the way, when a function similar to the above configuration is realized by a known method, the buffer 54 needs to be sized to store data for 6 samples according to the change width of the processing speed, and the circuit scale is It will increase by minutes. However, in the configuration of the present embodiment, the size of the data for one sample may be sufficient, so the buffer size is not made redundant, and the change in the amount of despreading processing is adjusted even in a multipath environment where the fluctuation is severe. It is possible to operate with voltage, and power consumption can be suppressed.

  As mentioned above, although this invention has been demonstrated using the 1st-3rd embodiment, a various change or improvement can be added to embodiment mentioned above.

It is the block diagram which showed an example of the structure of the synchronous control apparatus. It is the block diagram which showed an example of the structure of the power supply control part. It is a figure for demonstrating operation | movement of a power supply control part. It is a figure for demonstrating operation | movement of a power supply control part. It is a figure for demonstrating operation | movement of a power supply control part. It is a figure for demonstrating operation | movement of a power supply control part. It is a figure for demonstrating operation | movement of a power supply control part. It is the block diagram which showed an example of the structure of the power supply control part. It is a figure for demonstrating operation | movement of a power supply control part. It is the block diagram which showed an example of the structure of the control voltage generation part. It is the block diagram which showed an example of the structure of the synchronous control apparatus. It is the block diagram which showed an example of the structure of the power supply control part. It is a figure for demonstrating operation | movement of a delay circuit. It is a figure for demonstrating operation | movement of a power supply control part. It is a figure for demonstrating operation | movement of a power supply control part. It is a figure for demonstrating operation | movement of a power supply control part. It is the block diagram which showed an example of the structure of the power supply control part. It is a figure for demonstrating operation | movement of a delay circuit. It is a figure for demonstrating the operation | movement of an EXOR circuit. It is the block diagram which showed the structure of the frame processing apparatus. It is a figure for demonstrating operation | movement of a frame processing apparatus. It is the block diagram which showed an example of the structure of the synchronous control apparatus. It is the block diagram which showed an example of the structure of the power supply control part. It is a figure for demonstrating operation | movement of a delay circuit. It is a figure for demonstrating operation | movement of a power supply control part. It is a figure for demonstrating operation | movement of a power supply control part. It is a figure for demonstrating operation | movement of a power supply control part. It is the block diagram which showed an example of the structure of the power supply control part. It is a figure for demonstrating operation | movement of a delay circuit. It is a figure for demonstrating the operation | movement of an EXOR circuit. It is the block diagram which showed the structure of the despreading processing apparatus.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Synchronous control apparatus 11 Processing block 12 Buffer 13 Processing block 14 Buffer 15 Post-processing block 16 Power supply control part 161 Control voltage generation part 1611 Counter circuit 1612 Multiplier 1613 DA converter 162 JK-FF circuit 163 OR circuit 164 NAND circuit 165 AND Circuit 166 T-FF circuit 17 Voltage variable power supply 18 Power supply control unit 181 EXOR circuit 19 Control voltage generation unit 191 Switch 192 Inverter 193 Integrator 194 Multiplier 2 Synchronization control device 21 Power supply control unit 211 Delay circuit 22 Power supply control unit 221 EXOR circuit 3 frame processing device 31 frame control processing unit 32 buffer 33 turbo decoding processing unit 34 buffer 35 post-processing unit 36 power control unit 37 voltage variable power supply 38 frame buffer 4 synchronization control device DESCRIPTION OF SYMBOLS 1 Power supply control part 411 Delay circuit 42 Power supply control part 421 EXOR circuit 5 Despreading processing apparatus 51 AD conversion processing part 52 Buffer 53 Despreading processing part 531 Code generator 532 Code generator 533 Code generator 534 Code generator 535 Code generation 536 Code generator 537 Multiplexer 538 Multiplier 54 Buffer 55 RAKE processing unit 56 Power supply control unit 57 Voltage variable power supply

Claims (8)

A first processing block that executes a first process and outputs a first instruction signal upon completion of the first process;
The processing speed can be changed in accordance with the supplied power, the second processing related to the processing of the first processing block is executed, and the second instruction signal is output when the second processing is completed. A second processing block of the asynchronous circuit to
Control means for determining a power value to be supplied to the second processing block according to a time difference in input timing between the first instruction signal and the second instruction signal;
Supply means for supplying power corresponding to the power value to the second processing block;
A synchronization control device comprising:   The control means uses the input timing of the first instruction signal as a reference time, and determines a power value to be supplied to the second processing block so that the time difference becomes a predetermined time with respect to the reference time. The synchronous control device according to claim 1. The first processing block and the second processing block individually process the processing target data having a temporal relationship with respect to each other's operation,
When the first instruction signal is input prior to the second instruction signal when the processing of the processing target data is completed, the control means includes the first instruction signal and the second instruction signal. The synchronous control device according to claim 1, wherein the voltage value is increased in accordance with a time difference in input timing with respect to the input timing. The first processing block and the second processing block individually process the processing target data having a temporal relationship with respect to each other's operation,
When the second instruction signal is input prior to the first instruction signal when the processing of the processing target data is completed, the control means includes the first instruction signal and the second instruction signal. The synchronous control device according to claim 1, wherein the voltage value is decreased in accordance with a time difference in input timing. An EXOR operator that calculates an exclusive OR between the assertion period of the first instruction signal and the assertion period of the second instruction signal is further provided. The control unit is asserted by the exclusive OR. 2. The synchronous control device according to claim 1, wherein the period is a time difference between the acquisition timings of the two instruction signals.   The synchronous control device according to claim 1, wherein the first processing block and the second processing block are connected in parallel.   The synchronous control apparatus according to claim 1, wherein the first processing block and the second processing block are connected in series.   The apparatus further comprises delay means for delaying input timing of the first instruction signal or the second instruction signal by a time corresponding to a connection position between the first processing block and the second processing block. The synchronization control device according to claim 7.

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