JP2008160010A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

An object of the present invention is to prevent the generation of voids in an interelectrode insulating film, improve the uniformity of an interelectrode insulating film embedded between a plurality of adjacent control gate electrodes, and reduce the resistance of the control gate electrode. .
Since the upper part of the metal silicide film 9 is projected on the adjacent interelectrode insulating film 11, the cross-sectional area of the Y-direction cross section can be increased as compared with the conventional one. When the interelectrode insulating film 11 is embedded, the interelectrode insulating film 11 can be embedded with a lower aspect ratio than in the prior art.
[Selection] Figure 3

Description

  The present invention relates to a semiconductor device having a stacked gate electrode and a method for manufacturing the same.

  For example, a nonvolatile semiconductor memory device typified by a flash memory device includes a memory cell for storing data. Since data can be held in a memory cell without power supply, it is widely used as a storage medium for multimedia cards. Such a semiconductor device has recently been desired to have a larger capacity, and it is necessary to highly integrate stacked gate electrodes constituting a memory cell.

  A method of manufacturing such a flash memory device is disclosed in Patent Document 1. The main part of the manufacturing method described in Patent Document 1 will be explained. A tunnel insulating film and a first conductive layer are formed on a semiconductor substrate, a trench groove is formed, and an element isolation insulating film is formed in the trench groove. And forming a second conductive layer on the first conductive layer, depositing an inter-gate insulating film and a control gate on the second conductive layer, and performing gate processing to complete the cell structure. ing. In the manufacturing method of Patent Document 1, it is necessary to embed a plurality of stacked gate electrodes with an interelectrode insulating film when performing gate processing. However, when the gap between adjacent stacked gate electrodes is narrowed for high integration, stacked gates are used. The aspect ratio between the electrodes increases, and voids (seams or voids) are generated in the inter-electrode insulating film when the gap between adjacent stacked gate electrodes is filled with the inter-electrode insulating film.

In addition, since the width dimension of each stacked gate electrode becomes narrower with higher integration, the cross-sectional area of the control gate electrode is reduced, and wiring delay is likely to occur. In order to reduce the resistance value of the control gate electrode, it is conceivable to increase the thickness of the control gate electrode, but at the same time, there arises a physical contradiction that the aspect ratio between the control gate electrodes increases.
JP 2001-284556 A (FIG. 5, paragraphs 0092 to 0096)

  The first object of the present invention is to prevent the generation of voids in the interelectrode insulating film and to improve the uniformity of the interelectrode insulating film embedded between a plurality of adjacent control gate electrodes. A second object of the present invention is to provide a semiconductor device and a method for manufacturing the same.

  One embodiment of the present invention is adjacent to a semiconductor substrate, a first gate insulating film formed over the semiconductor substrate, and a plurality of stacked gate electrodes juxtaposed over the first gate insulating film. An interelectrode insulating film formed between the plurality of stacked gate electrodes, wherein the plurality of stacked gate electrodes are separated from each other, and each of the floating gate electrodes is formed on the first gate insulating film. And a second gate insulating film formed on the floating gate electrode, and a projecting portion formed on the second gate insulating film and projecting on the adjacent interelectrode insulating film. A semiconductor device including a gate electrode is provided.

  One embodiment of the present invention includes a step of forming a first gate insulating film material over a semiconductor substrate, a step of forming a floating gate electrode material over the first gate insulating film material, and a step of forming over the floating gate electrode material. Forming a second gate insulating film material on the second gate insulating film material, forming a control gate electrode base material made of silicon on the second gate insulating film material, a second control gate electrode base material, A step of dividing the gate insulating film material and the floating gate electrode material into a plurality of steps, a step of embedding an inter-electrode insulating film in the divided region divided into the plurality of portions, a step of selectively growing the silicon material, and the selective growth And a method of manufacturing a semiconductor device, comprising: siliciding at least a part of the silicon material.

According to one embodiment of the present invention, the uniformity of an interelectrode insulating film embedded between a plurality of adjacent control gate electrodes can be improved.
According to one embodiment of the present invention, the resistance of the control gate electrode can be reduced.

  Hereinafter, an embodiment of the present invention applied to a NAND flash memory device having a stacked gate electrode structure will be described with reference to the drawings. In the following description in the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones.

FIG. 1 is an equivalent circuit diagram showing a part of a memory cell array formed in a memory cell region of a NAND flash memory device.
As shown in FIG. 1, the memory cell array Ar configured in the memory cell region M of the NAND flash memory device 1 includes two select gate transistors Trs1 and Trs2, and between the select gate transistors Trs1 and Trs2. In contrast, NAND cell units SU including a plurality of (for example, 8: 2 to the nth power (where n is a positive number)) memory cell transistors Trm connected in series are formed in a matrix. . In the NAND cell unit SU, a plurality of memory cell transistors Trm are formed by sharing adjacent source / drain regions.

  In FIG. 1, the memory cell transistors Trm arranged in the X direction (corresponding to the word line direction and the gate width direction) are commonly connected by a word line (control gate line) WL. Further, the select gate transistors Trs1 arranged in the X direction in FIG. 1 are commonly connected by a select gate line SGL1. Similarly, the select gate transistors Trs2 arranged in the X direction in FIG. 1 are commonly connected by a select gate line SGL2.

  A bit line contact CB is connected to the drain region of the select gate transistor Trs1. The bit line contact CB is connected to a bit line BL extending in the Y direction (corresponding to the gate length direction and the bit line direction) orthogonal to the X direction in FIG. The select gate transistor Trs2 is connected to a source line SL extending in the X direction in FIG. 1 through a source region.

  FIG. 2 is a plan view showing a layout pattern of a part of the memory cell region. In a p-type silicon substrate 2 as a semiconductor substrate, an element isolation region Sb having an STI (Shallow Trench Isolation) structure is formed along the Y direction in FIG. A plurality of element isolation regions Sb are formed at predetermined intervals in the X direction, whereby element formation regions (active regions) Sa are separately formed in the X direction in FIG.

  The word line WL is formed over the element isolation regions Sb and the element formation regions Sa along the X direction in FIG. 2 orthogonal to the extending direction of the element formation region Sa. The word line WL is an electrical component that functions as a control gate electrode, and is formed in the gate electrode formation region GC. A plurality of word lines WL are formed apart from each other in the Y direction in FIG. 2, and the plurality of word lines WL are formed between the gate electrode isolation regions GV (between two gate electrode formation regions GC adjacent in the Y direction). The inter-electrode insulating film 11 (interlayer insulating film: see later) embedded in the region) is electrically separated in the Y direction.

  Further, the selection gate line SGL1 of the selection gate transistor Trs1 is formed on both sides in the Y direction of the bit line contact CB and is formed across the plurality of element isolation regions Sb and the element formation regions Sa along the X direction in FIG. Has been. The selection gate line SGL1 is formed in a pair in plan view with the bit line contact CB sandwiched in the Y direction. The bit line contact CB is formed on each element formation region (active region) Sa between the pair of selection gate lines SGL1. Each is formed.

  On the element formation region Sa intersecting with each word line WL, the gate electrode MG (laminated gate electrode: floating gate electrode FG and control gate electrode CG (described later in FIG. 3A and FIG. 3) of the memory cell transistor Trm, respectively. (B))) is formed. On the element formation region Sa intersecting with each selection gate line SGL1, the selection gate electrode SG of the selection gate transistor Trs1 is configured and commonly connected by the selection gate line SGL1.

  In the present embodiment, the structure of the word line WL (corresponding to a control gate line and a control gate electrode) in the memory cell region M, the structure of the gate electrode isolation region GV therebetween, and the manufacturing method thereof are provided. This part will be described in detail, and description of the structure of the peripheral circuit area will be omitted. Hereinafter, the structure of each memory cell transistor Trm will be described with reference to FIGS. 3 (a) and 3 (b).

  3A schematically shows a longitudinal section (a part of the X-direction section in the memory cell region M) along the line AA in FIG. 2, and FIG. 3B is a diagram of FIG. A vertical section (part of the Y-direction section in the memory cell region M) along the line BB is schematically shown.

  A plurality of element isolation grooves 3 are formed along the Y direction on the surface layer of the silicon substrate 2 as a semiconductor substrate, and a plurality of element isolation grooves 3 are arranged in parallel in the X direction. Each of these element isolation trenches 3 is embedded with an element isolation insulating film 4 to form an element isolation region Sb having an STI (Shallow Trench Isolation) structure. The element isolation region Sb is a region that partitions a plurality of element formation regions (active regions: active areas) Sa on the surface layer of the silicon substrate 2, and the plurality of element formation regions Sa are formed along the Y direction and are arranged in the X direction. It is installed.

  The element formation region Sa partitioned by the element isolation insulating film 4 is composed of a region including the source / drain region 2a of the memory cell transistor Trm and the channel region 2b sandwiched between these source / drain regions 2a.

  A silicon oxide film 5 is formed on the element formation region Sa of the silicon substrate 2. The silicon oxide film 5 is a thermal oxide film formed by thermally oxidizing the surface of the silicon substrate 2, and functions as a gate oxide film, a tunnel insulating film, and a first gate insulating film.

  Polycrystalline silicon layers 6 are formed on the silicon oxide film 5 in the plurality of gate electrode formation regions GC, respectively. The polycrystalline silicon layer 6 is doped with an impurity such as phosphorus, and is formed by depositing amorphous silicon and then polycrystallizing by heat treatment.

  As shown in FIG. 3A, the element isolation insulating film 4 is made of, for example, a silicon oxide film, and its upper surface protrudes upward from the upper surface of the silicon oxide film 5, and the upper surface is polycrystalline. It is formed so as to be located below the upper surface of the silicon layer 6.

  As shown in FIG. 3A, the polycrystalline silicon layer 6 is configured such that the upper portion (for example, about 2/3 of the total height) protrudes above the upper surface of the element isolation insulating film 4. The polycrystalline silicon layer 6 is formed in alignment with the side wall surfaces of the silicon oxide film 5 and the element isolation insulating film 4.

  The polycrystalline silicon layers 6 are juxtaposed in the X direction and the Y direction via the silicon oxide films 5 on the plurality of element formation regions Sa, respectively, and function as the first gate electrode and the floating gate electrode FG. The element isolation insulating film 4 is configured to electrically and structurally isolate the polycrystalline silicon layer 6 that is the floating gate electrode FG adjacent in the X direction.

  An interpoly insulating film 7 is formed on part of the side surface and upper surface of the polycrystalline silicon layer 6 and on the upper surface of the element isolation insulating film 4. The interpoly insulating film 7 is formed so as to cover the polycrystalline silicon layer 6 and functions as an intergate insulating film, a second gate insulating film, and a conductive interlayer insulating film. The interpoly insulating film 7 is composed of, for example, an ONO film (Oxide (silicon oxide film layer) -Nitride (silicon nitride film layer) -Oxide (silicon oxide film layer)). The interpoly insulating film 7 is configured to be sandwiched between a polycrystalline silicon layer 6 and a polycrystalline silicon layer 8 described later, and functions as a conductive interlayer insulating film. The interpoly insulating film 7 also functions as an inter-gate insulating film between the floating gate electrode FG and the control gate electrode CG (word line WL).

  The control gate electrode CG is formed on the interpoly insulating film 7 and is formed as a word line WL so as to cross over the polycrystalline silicon layer 6 and the element isolation insulating film 4 arranged in parallel in the X direction. ing. The control gate electrode CG is constituted by the lower polycrystalline silicon layer 8 and the upper metal silicide film 9 and is configured as a second gate electrode. The polycrystalline silicon layer 8 is formed by laminating a thin polycrystalline silicon layer 8a on the lower layer side and a silicon layer 8b on the upper layer side. The polycrystalline silicon layer 8a and the polycrystalline silicon layer 6 are interpoly insulating films. 7 to face each other. The metal silicide film 9 is made of, for example, cobalt silicide, and the resistance of the control gate electrode CG is reduced.

  As described above, the stacked gate electrode 10 is formed by sequentially stacking the polycrystalline silicon layer 6, the interpoly insulating film 7, the polycrystalline silicon layer 8, and the metal silicide film 9 on the silicon substrate 2 via the silicon oxide film 5. Configured. As shown in FIG. 3B, these stacked gate electrodes 10 are formed separately from each other in the Y direction, and they have substantially the same stacked form. An interelectrode insulating film 11 is formed on the silicon substrate 2 in the gate electrode isolation region GV to electrically and structurally isolate the control gate electrodes CG adjacent in the Y direction.

  The interelectrode insulating film 11 is made of, for example, TEOS (Tetra Ethoxy Ortho Silicate), and the upper part thereof is formed at a position lower than the upper surface of the metal silicide film 9. The upper surface of the metal silicide film 9 is formed in a so-called dome shape, and the upper edge portion 9 a is formed as an overhanging portion that protrudes over a part of the interelectrode insulating film 11 adjacent to the metal silicide film 9. In FIG. 3B, the interelectrode insulating film 11 is formed directly on the silicon substrate 2, but the silicon oxide film 5 on the source / drain region 2a is left and the interelectrode insulating film 11 is made of silicon. It may be formed on the silicon substrate 2 via the oxide film 5. An interlayer insulating film (not shown) such as a silicon oxide film is formed on the metal silicide film 9 and the interelectrode insulating film 11, but the description thereof is omitted because it is not related to the characteristic part of this embodiment. Thus, the memory cell structure of the memory cell region M of the flash memory device 1 is configured.

  According to the structure according to the present embodiment, since the upper part of the metal silicide film 9 is configured to protrude on the adjacent interelectrode insulating film 11, the cross-sectional area of the Y-direction cross section can be increased as compared with the conventional case. it can. Thereby, the resistance of the control gate electrode CG can be reduced, and the operation of the memory cell can be speeded up.

<About manufacturing method>
Hereinafter, a method for manufacturing the memory cell region M of the flash memory device 1 will be described with reference to FIGS. In addition, although it demonstrates centering on the characteristic part which concerns on this embodiment, if this invention can achieve the objective described in the subject column which invention intends to solve and has the effect described in the column of the effect of invention, Any of the steps described below may be omitted as necessary, and may be added if a general step is necessary during the following description step. Further, instead of the material of each functional film, other materials may be applied as long as they are applicable, and the film thickness may be changed as appropriate.

  As shown in FIG. 4, a silicon oxide film 5 is formed on a p-type silicon substrate 2 to a thickness of about 10 [nm] by a thermal oxidation method. Next, as shown in FIG. 5, amorphous silicon doped with an impurity such as phosphorus is deposited on the silicon oxide film 5 by a low pressure CVD (Chemical Vapor Deposition) method as a floating gate electrode material. Since this amorphous silicon is transformed into a polycrystalline silicon layer 6 by a subsequent heat treatment, reference numeral 6 is assigned as the polycrystalline silicon layer 6 in the drawings subsequent to FIG.

  Next, as shown in FIG. 6, a silicon nitride film 12 is deposited on the polycrystalline silicon layer 6 by low pressure CVD, and a silicon oxide film 13 is formed on the silicon nitride film 12 as a hard mask.

Next, as shown in FIG. 7, a mask pattern is formed on the silicon oxide film 13 by patterning a resist 14 in regions X separated from each other in the X direction.
Next, as shown in FIG. 8, the silicon oxide film 13 is etched using the patterned resist 14 as a mask. This region is a region between two (plural) floating gate electrodes FG and FG forming regions (see FIG. 3A) adjacent to each other in the X direction, and separates the floating gate electrode FG into a plurality in the X direction. This is an area for dividing.

Next, as shown in FIG. 9, the resist 14 is removed by exposing the processing substrate to O ₂ plasma, and the silicon nitride film 12, the polycrystalline silicon layer 6, the silicon oxide film 5, Then, the upper part of the silicon substrate 2 is etched by the RIE method to form the element isolation groove 3 (corresponding to the groove) in the upper part of the polycrystalline silicon layer 6, the silicon oxide film 5, and the silicon substrate 2.

  Next, as shown in FIG. 10, the silicon oxide film 13 is removed and heated to 1000 ° C. in an oxygen atmosphere to form a silicon oxide film along the inner surface of the element isolation trench 3, and on the inner side thereof The element isolation insulating film 4 is embedded by depositing a silicon oxide film by HDP-CVD (High Density Plasma Chemical Vapor Deposition) method. Next, as shown in FIG. 11, the element isolation insulating film 4 is planarized by CMP using the silicon nitride film 12 as a stopper.

Next, as shown in FIG. 12, the element isolation insulating film 4 is removed by RIE so that the upper surface is located above the upper surface of the silicon oxide film 5 and below the upper surface of the polycrystalline silicon layer 6.
Next, as shown in FIG. 13, the silicon nitride film 12 is removed by phosphoric acid treatment (wet etching treatment) at 150 ° C. and immersed in an NH ₄ F solution to expose the upper surface of the polycrystalline silicon layer 6, thereby isolating and isolating elements. An interpoly insulating film 7 is formed on the film 4 and the polycrystalline silicon layer 6 as a second gate insulating film material by, for example, a low pressure CVD method.

  Next, as shown in FIG. 14, amorphous silicon doped with impurities such as phosphorus is thinly formed on the interpoly insulating film 7 by low pressure CVD. Note that the amorphous silicon film is transformed and polycrystallized by heat treatment later, and therefore, a reference numeral is given as a polycrystalline silicon layer 8a in FIG. The polycrystalline silicon layer 8a is formed as a base material for the control gate electrode CG. FIG. 15 shows a longitudinal sectional view in the middle of manufacture corresponding to FIG. 3B at this time point. At this time, the upper surface of the polycrystalline silicon layer 8a is formed in a planar shape in the Y direction.

  FIGS. 16-21 has shown the longitudinal cross-sectional view in the middle of manufacture corresponding to FIG.3 (b) after the process shown in FIG. As shown in FIG. 16, a silicon nitride film 15 is formed as a hard mask on the polycrystalline silicon layer 8a, a resist 16 is applied on the silicon nitride film 15, and the resist 16 is patterned into a plurality spaced apart in the Y direction. Ning.

  Next, as shown in FIG. 17, the silicon nitride film 15, the polycrystalline silicon layer 8a, the interpoly insulating film 7, the polycrystalline silicon layer 6, and the silicon oxide film 5 are formed by RIE using the patterned resist 16 as a mask. The control gate electrode CG and the floating gate electrode FG are separated into a plurality in the Y direction. Next, the resist 16 is removed using an ashing process or the like. Note that the silicon oxide film 5 is not necessarily removed and may be left. The timing of removing the resist 16 may be before the layers 5 to 8a are processed as long as the silicon nitride film 15 is removed and processed. Next, n-type impurities are ion-implanted into the surface layer of the silicon substrate 2 to form source / drain regions 2a.

  Next, as shown in FIG. 18, the interelectrode insulating film 11 made of a TEOS-based silicon oxide film is formed in a range of 600 to 800 ° C., for example, with respect to a region (divided region) between the layers 5 to 8 a and 15 separated into a plurality of It embeds by the low pressure CVD (LP-CVD) method under the internal temperature conditions. As a result, the height from the surface of the silicon substrate 2 to the upper surface of the silicon nitride film 15 is reduced as compared with the conventional structure, and the aspect ratio is reduced. Therefore, the inside of the interelectrode insulating film 11 between the adjacent layers 5 to 15 No voids (voids, seams, etc.) are formed in. The interelectrode insulating film 11 is formed of a material that can obtain high selectivity during etching with the silicon nitride film 15.

  Next, as shown in FIG. 19, the interelectrode insulating film 11 is removed by RIE so that the entire upper surface of the silicon nitride film 15 is exposed. Then, the interelectrode insulating film 11 is configured so that the upper center in the Y direction of the interelectrode insulating film 11 is recessed.

  Next, as shown in FIG. 20, the silicon nitride film 15 is removed by etching. In this case, it is preferable to clean the upper surface of the polycrystalline silicon layer 8a by performing a wet etching process.

  Next, as shown in FIG. 21, a silicon material is selectively grown on the polycrystalline silicon layer 8a. By performing this process, the thickness of the silicon is increased, and the upper surface of the silicon is configured to have a convex curved shape. In FIG. 21, reference numeral 8b is assigned to the portion subjected to the selective growth processing. The silicon selective growth process is performed, for example, by using dichlorosilane and hydrochloric acid as source gases and reacting the gases at about 600 to 900 ° C. When this selective growth process is performed, the silicon layer 8b is selectively grown on the polycrystalline silicon layer 8a, but is not grown in other regions.

  When the selective growth process proceeds and reaches the upper surface of the interelectrode insulating film 11, the silicon layer 8 b further grows upward from the upper surface of the interelectrode insulating film 11, and the adjacent interelectrode insulating film 11. Promote growth so that it projects upward. That is, by performing the selective growth process, the film grows first in the vertical direction and increases the thickness of the silicon layer 8b, but when it reaches the upper surface of the interelectrode insulating film 11, it grows slightly in the Y direction. At this time, by adjusting the processing time, the silicon layer 8b is formed on the upper surface of the interelectrode insulating film 11 and is not in contact with the silicon layer 8b adjacent in the Y direction.

  Next, as shown in FIG. 3 (b), a metal such as cobalt is sputtered on the silicon layer 8b, and heat treatment is performed to combine at least a part of the upper portion of the silicon layer 8b with the metal. A metal silicide film 9 is formed by siliciding at least a part of the layer 8b. Next, the stacked gate electrode 10 is completed by removing unreacted metal.

  In the subsequent processing, an interlayer insulating film and a metal wiring layer (both not shown) are formed on the laminated gate electrode 10 by a conventional method. Thereby, the flash memory device 1 can be completed.

  As described above, according to the manufacturing method according to the present embodiment, the thin polycrystalline silicon layer 8a is formed on the interpoly insulating film 7, and the layers 5 to 8a are divided into a plurality of parts. After the interelectrode insulating film 11 is embedded in, the silicon layer 8b is selectively grown on the polycrystalline silicon layer 8a, and at least a part of the silicon layer 8b is silicided. It is possible to embed in a state where the ratio is lower than in the conventional case, the embeddability in the interelectrode insulating film 11 is improved, and the uniformity of the interelectrode insulating film 11 can be improved.

  Further, in the step of selectively growing the silicon layer 8b, since the upper portion of the silicon layer 8b is selectively grown so as to be located above the upper surface of the interelectrode insulating film 11, the cross-sectional area in the Y direction as compared with the prior art is increased. The resistance of the control gate electrode CG can be reduced.

  Further, in the step of selectively growing the silicon layer 8b, since the silicon layer 8b is formed so as to protrude on the interelectrode insulating film 11, the cross-sectional area in the Y direction can be increased compared to the conventional case, and the control gate can be increased. The resistance of the electrode CG can be reduced.

Further, since the control gate electrode CG (silicon layer 8b, metal silicide film 9) is formed to protrude on the adjacent interelectrode insulating film 11, the cross-sectional area in the Y direction can be increased as compared with the conventional case. In addition, the resistance of the control gate electrode CG can be reduced.
Since the upper surface of the silicon layer 8b is wet-etched before the silicon layer 8b is selectively grown, the silicon layers 8b constituting the plurality of stacked gate electrodes 10 can be grown uniformly.

(Other embodiments)
The present invention is not limited to the above embodiment, and can be modified or expanded as follows.
Although an embodiment in which the p-type silicon substrate 2 is applied as a semiconductor substrate has been described, a semiconductor substrate of another material may be applied in the present invention.
Although the embodiment in which the silicon oxide film 5 is applied as the first gate insulating film has been described, a gate insulating film of another material may be applied in the present invention.

Although the embodiment in which the element isolation region Sb having the STI structure is configured has been described, it may be configured as necessary.
Although an embodiment in which a silicon oxide film is applied as the interelectrode insulating film 11 is shown, the interelectrode insulating film 11 of another material may be applied in the present invention.

  Although an embodiment in which an ONO film is applied as the interpoly insulating film 7 (second gate insulating film) has been shown, the present invention is a nonon film (silicon nitride film-silicon oxide film-silicon nitride film-silicon oxide film-silicon nitride). A laminated structure of an oxide film layer or a nitride film layer or other high dielectric constant material may be applied.

Although the embodiment in which the polycrystalline silicon layer 8a is applied as the base layer material of the control gate electrode CG has been shown, other materials may be applied in the present invention.
Although the embodiment in which cobalt is applied as the metal for siliciding the upper portion of the control gate electrode CG has been described, other metals such as tungsten may be applied.

The stacked gate electrode is not limited to two layers, and a multilayer gate electrode structure of three or more layers may be applied in the present invention.
Although the embodiment applied to the flash memory device 1 is shown, it may be applied to other semiconductor devices such as a nonvolatile semiconductor memory device.

The figure which shows a part of electrical structure of the memory cell area | region in the flash memory device in one Embodiment of this invention. A plan view schematically showing a layout pattern of a part of a memory cell region (A) is a typical longitudinal cross-sectional view shown along the AA line of FIG. 2, (b) is a schematic longitudinal cross-sectional view shown along the BB line of FIG. 3A corresponding diagram in the middle of manufacturing (part 1) 3A corresponding diagram in the middle of manufacture (part 2) FIG. 3A corresponding diagram in the middle of manufacturing (part 3) FIG. 3A corresponding diagram in the middle of manufacturing (part 4) FIG. 3A corresponding diagram in the middle of manufacturing (part 5) FIG. 3A corresponding diagram in the middle of manufacture (No. 6) FIG. 3A corresponding diagram in the middle of manufacturing (part 7) FIG. 3A corresponding diagram in the middle of manufacture (No. 8) FIG. 3A corresponding diagram in the middle of manufacture (No. 9) FIG. 3A corresponding diagram in the middle of manufacturing (part 10) FIG. 3A corresponding diagram in the middle of manufacturing (part 11) 3B corresponding diagram in the middle of manufacture (part 1) 3B corresponding diagram in the middle of manufacturing (part 2) 3B corresponding diagram in the middle of manufacturing (part 3) FIG. 3B corresponding diagram in the middle of manufacturing (part 4) FIG. 3B corresponding diagram in the middle of manufacturing (part 5) FIG. 3B corresponding diagram in the middle of manufacture (No. 6) FIG. 3B corresponding diagram in the middle of manufacturing (part 7)

Explanation of symbols

  In the drawings, 1 is a flash memory device (semiconductor device), 2 is a silicon substrate (semiconductor substrate), 3 is an element isolation trench (groove), 5 is a silicon oxide film (first gate insulating film), and 6 is polycrystalline silicon. 8a is a polycrystalline silicon layer (base material of the control gate electrode), 8b is a silicon layer (silicon material), 9 is a metal silicide film, 9a is an upper edge (overhang), 10 is a laminated gate electrode, 11 Denotes an interelectrode insulating film, FG denotes a floating gate electrode, and CG denotes a control gate electrode.

Claims (5)

A semiconductor substrate;
A first gate insulating film formed on the semiconductor substrate;
A plurality of stacked gate electrodes arranged in parallel on the first gate insulating film;
An inter-electrode insulating film formed between the plurality of adjacent stacked gate electrodes,
The plurality of stacked gate electrodes are formed separately from each other, and each includes a floating gate electrode formed on the first gate insulating film, a second gate insulating film formed on the floating gate electrode, A semiconductor device comprising: a control gate electrode that is formed on the second gate insulating film and has an overhanging portion that protrudes on the adjacent interelectrode insulating film. Forming a first gate insulating film material on the semiconductor substrate;
Forming a floating gate electrode material on the first gate insulating film material;
Forming a second gate insulating film material on the floating gate electrode material;
Forming a base material of a control gate electrode made of a silicon material on the second gate insulating film material;
Dividing the base material of the control gate electrode, the second gate insulating film material, and the floating gate electrode material into a plurality of parts;
Embedding an inter-electrode insulating film in the divided region divided into the plurality,
Selectively growing the silicon material;
And a step of siliciding at least a part of the selectively grown silicon material. Forming a first gate insulating film material on the semiconductor substrate;
Forming a floating gate electrode material on the first gate insulating film material;
Forming a trench in the floating gate electrode material, the first gate insulating film material, and the semiconductor substrate along a first direction in the surface of the semiconductor substrate;
Forming an element isolation insulating film in the trench so as to protrude upward from the surface of the semiconductor substrate and expose at least part of the floating gate electrode material;
Forming a second gate insulating film material on the floating gate electrode material and the element isolation insulating film;
Forming a base material of a control gate electrode made of a silicon material on the second gate insulating film material;
Dividing the base material of the control gate electrode, the second gate insulating film material, and the floating gate electrode material into a plurality along a second direction intersecting the first direction;
Forming an inter-electrode insulating film in the plurality of divided regions;
Selectively growing the silicon material;
And a step of siliciding at least a part of the selectively grown silicon material.   4. The semiconductor according to claim 2, wherein in the step of selectively growing the silicon material, the silicon material is selectively grown so that an upper portion of the silicon material is positioned above an upper surface of an interelectrode insulating film in the divided region. Device manufacturing method.   5. The method of manufacturing a semiconductor device according to claim 2, wherein in the step of selectively growing the silicon material, the silicon material is formed so as to protrude on an interelectrode insulating film in the dividing region. .

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