JP2008159919A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To minimize increase of the excessive chip area under the condition where an evaluation pad also increases with a bonding pad in a high-speed DRAM or the like. <P>SOLUTION: With respect to the DRAM for one chip on a wafer, in a center section on a chip there are lined a plurality of pads (No. 1 to No. 103) with various functions such as an address pin, a data pin, a power supply pin, a ground pin or the like. Out of these pads (No. 1 to No. 103), beside a pad 3 which carries out a bonding at the time of a package assembly but is not used in the times of a packaging stage for evaluation and a probe test, there is adjacently arranged an evaluation pad 4 for a power supply monitor in which no bonding is carried out at the time of the package assembly. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device such as a DRAM (Dynamic Random Access Memory) in which a plurality of pads are arranged at the center of a chip. In particular, it relates to the layout of pads on a semiconductor chip.

  Semiconductor devices such as DRAM include many types of product packages such as FBGA (Fine pitch Ball Grid Array) and TSOP (Thin Small Outline Package). In the DRAM, pads on the chip are arranged in a line at the center of the chip in order to reduce the size of the package and increase the memory speed (FIG. 4). These pads are provided with pads for chip evaluation in addition to external electrode connection pads that are connected to the external electrodes of the package by wire bonding or the like when the product package is assembled. The evaluation pad is required for applying a voltage from the outside of the chip in an operation check and a probe test (wafer test) at the evaluation package stage before the product. This evaluation pad is a pad having the same size as the external electrode connection pad, and many pads are required for evaluating the internal power supply voltage. The number of pads for evaluation is increasing due to the adoption of step-down power supplies. In addition, the size of the pad does not become very small even when the process is miniaturized, and the proportion of the pad on the chip tends to increase as the chip shrinks.

Conventionally, under such an increase in the number of pads, the pads on the semiconductor chip cannot be arranged in a single row due to the element layout, and there are cases where the two rows have to be arranged (see paragraph [0007] of Patent Document 1). [0008] and FIG. 7B).
JP 2006-278805 JP

  However, when the pads are arranged in two rows, it is necessary to increase the pad spacing to some extent due to restrictions at the time of wafer test and product package assembly, resulting in an extra increase in chip area. Specifically, bonding is not possible due to securing the tensile strength of the bonding ball or due to restrictions of the bonding apparatus (for example, the width of the capillary or the displacement of the bonding position from the center of the pad in the direction in which the bonding wire is stretched). In general, it is necessary to ensure a sufficient distance between adjacent pads (the distance A and the distance B in FIG. 5). Also, in the wafer test in which multiple chips on the wafer are tested at the same time, the distance between adjacent pads (the distance A and the distance B in FIG. 5) where the probe tips of the probe card are set up at the same time can be secured. It is essential. This is due to restrictions such as the probe width (cantilever tip width) and the amount of offset of the tip of the needle tip relative to the cantilever end, and the pad contact position of the needle tip may shift depending on the probe card alignment accuracy and needle pressure adjustment. It is.

  Such an area for securing the pad interval is useless because it cannot be used for arrangement of other elements, resulting in an excessive increase in chip area.

  SUMMARY OF THE INVENTION In view of the above-described problems of the prior art, an object of the present invention is to minimize an increase in an extra chip area under the situation where chip evaluation pads are increased together with bonding pads in a high-speed DRAM or the like.

  The present invention is a semiconductor device in which a plurality of pads are arranged in one direction on a chip, and at least a part of the plurality of pads is arranged in two rows. One of the two pads adjacent to each other in the inter-column direction is a pad that only performs electrical connection when assembling the product package, and the other pad is a temporary pad for testing the chip internal circuit. This is an evaluation pad in which only the electrical connection is performed.

  The electrical connection at the time of assembling the product package is a bonding connection with an external electrode provided on the product package, and the temporary electrical connection at the time of the chip internal circuit test is a probe contact during the probe test or evaluation. It is a bonding connection at the time of the operation test in the package stage.

  In such an invention, in the inter-row direction of the two-row pad arrangement, the external electrode connection pads to be bonded simultaneously are not arranged, and further, the chip evaluation pads to which the probe is applied are not arranged. Therefore, in setting the interval between adjacent pads in the inter-column direction, the pad interval can be made as close as possible without being restricted by the configuration and operation of the prober and bonding apparatus. Therefore, the problem that an extra chip area is increased in forming two rows is solved.

  The pad arrangement of the present invention is suitable for a semiconductor device such as a DRAM in which a plurality of pads are arranged in one direction at the center of a semiconductor chip.

  According to the present invention, while the number of chip evaluation pads is increased together with the bonding pads in a high-speed DRAM or the like in which a plurality of pads are arranged at the center of the chip, an extra increase in the chip area can be minimized.

  In the present invention, when the pads at the center of the chip must be arranged in two rows due to the increase in the number of pins in the high-speed DRAM and the convenience of the element layout, they are adjacent to the direction orthogonal to the row of pads (inter-column direction) The problem of the prior art was solved by not combining the two pads to be arranged with the pads for connecting external electrodes to be bonded at the same time, and further without combining the pads for chip evaluation with each other. In other words, one of the two pads is a pad that is used only during product package assembly (bonding), and the other is a pad that is used only during probe testing and operation check at the evaluation package stage. did.

  First, an example is given of pads that are bonded at the time of assembling the product package but are not used in the probe test or evaluation package stage.

  1) In a multi-bit parallel test (parallel test) performed to reduce time and the number of probes at the time of a probe test on a DRAM chip, pins for supplying write data and pins for outputting a read determination result are limited. Therefore, for example, even if a product has 8 I / O pins (DQ pins: data pins), probe standing and temporary bonding are performed on all pads (data pads) connected to the I / O pins during the parallel test. There is no need. However, when assembling the product package, bonding is performed on all data pads.

  2) Since the pads such as the data power supply (VDDQ) and data ground (VSSQ) of the output circuit are connected to each other inside the chip, the power supply for data is used in the probe test and the operation check at the evaluation package stage. There is no problem if all the pads on the data ground are not probed or bonded. However, when assembling the product package, bonding may be performed on all the pads in order to avoid potential fluctuation noise.

  As described above, bonding is performed when the product package is assembled, but there are pads that are not used (or may not be used) in the probe test or evaluation package stage.

  Next, an example of pads used in the probe test or evaluation package stage will be given although bonding is not performed during product package assembly.

  When checking the operation of the internal circuit of the DRAM at the probe test or evaluation package stage, to measure the output voltage at the output terminal of the internal power supply circuit or to check the operation margin by forcibly applying the voltage from the outside There is a necessary pad. There are also pads required to monitor special internal signals (eg, power-on reset signals) in probe tests. These pads are not required in the product package state, and bonding is not performed on the pads. Such an evaluation pad is a pad that is not bonded at the time of assembling the product package, but is probed and bonded at the probe test and evaluation package stage.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 shows a pad arrangement on a chip in the first embodiment of the semiconductor device of the present invention. In the central portion on the semiconductor chip, pads 1 for data power supply (VDDQ), data ground (VSSQ), and data signals (DQ0, DQ1, DQ2, DQ5, DQ6, DQ7, etc.) are arranged in a line. These pads 1 are external electrode connection pads on which bonding is performed during product package assembly. The extending direction of the bonding wires (not shown) from the pads arranged in one direction is sequentially reversed for each pad 1, thereby minimizing the adjacent pad interval.

  Among these pads 1, the data pads DQ5, DQ6, and DQ7 are pads that do not raise a probe (needle) during the probe test by the parallel test, as in the above 1). In the present embodiment, the evaluation pads 2 are arranged adjacent to some of the data pads not used at the time of the probe test, thereby achieving two rows.

  This evaluation pad 2 is probed and bonded in the probe test and the operation check at the evaluation package stage, but is not bonded in assembling the product package. Therefore, the arrangement of the evaluation pad 2 is not subject to restrictions (for example, restrictions from the bonding apparatus) when assembling the product package, and the evaluation pad 2 is used as a data pad of DQ5, DQ6, and DQ7 as much as possible. Can be placed close together.

  In addition, since the data pads of DQ5, DQ6, and DQ7 are pads on which no probe is raised during the probe test, the inter-pad distance between the data pad and the evaluation pad 2 adjacent to the data pad is determined on the probe card during the wafer check. There are no technical restrictions. FIG. 1 schematically shows the extending direction of the probe 5 and the cantilever provided with the probe 5 standing on the pad at the time of the probe test by the elongated triangle drawn in the drawing. On the pad side facing the evaluation pad 2, It can be seen that there is no need to provide a probe card cantilever. That is, the evaluation pad 2 can be disposed close to the data pads DQ5, DQ6, and DQ7.

  As described above, when the pads are arranged in two rows, the pad interval can be minimized, and an extra increase in the chip area can be minimized.

(Second Embodiment)
FIG. 2 is a schematic view showing a pad arrangement in the second embodiment of the semiconductor device of the present invention. In FIG. 2, a plurality of pads 1 such as a data power supply (VDDQ), a data ground (VSSQ), and data signals (DQ0, DQ1, DQ2, DQ5, DQ6, DQ7) arranged in a line on a semiconductor chip are These are external electrode connection pads on which bonding is performed during product package assembly. However, among these pads 1, each VDDQ pad is connected inside the chip as described in 2) above, and in the probe test, it is not necessary to place a probe on all VDDQ pads.

  In the present embodiment, evaluation pads 2 are arranged adjacent to some power supply pads that need not be used during such a probe test, so that two rows are formed. As in the first embodiment, the evaluation pad 2 is not bonded when the product package is assembled. Therefore, the evaluation pad 2 is placed as close as possible to the VDDQ power supply pad as shown in the figure without being restricted by package assembly (for example, restrictions from the bonding apparatus) regarding the placement of the evaluation pad 2. Can do.

  In addition, since the VDDQ power pad is a pad that does not require a probe to be raised during the probe test, the technical restrictions of the probe card during the wafer check regarding the inter-pad distance between the power pad and the evaluation pad 2 adjacent thereto. I will not receive it. As can be seen from the extending direction of the probe 5 shown by the elongated triangle in FIG. 2 and the cantilever including the probe 5, it is not necessary to provide the probe of the probe card on the pad side facing the evaluation pad 2. That is, the evaluation pad 2 can be disposed close to the VDDQ power supply pad.

  As described above, as in the first embodiment, it is possible to minimize the interval between adjacent pads arranged in two rows, and to suppress an unnecessary increase in chip area.

  Finally, FIG. 3 illustrates a pad layout of a product manufactured by employing the present invention. In the DRAM for one chip on the wafer shown in this figure, a plurality of pads (No. 1 to 103) having various functions such as an address pin, a data pin, a power supply pin, and a ground pin are provided at the center of the chip. ) Are arranged in a line. A plurality of evaluation pads are required to check the operation of the internal circuit of the chip, but when the evaluation pads are arranged in a row together with the No. 1 to 103 pads, the chip area is increased in the arrangement direction. It will increase. Therefore, a plurality of evaluation pads may have to be arranged substantially parallel to the side of the pad rows No. 1 to 103. In some cases, such a two-row arrangement is used due to element layout and manufacturing convenience. In such a case, if an evaluation pad that requires the same probe stand or temporary bonding is arranged side by side on the side of the pad where the probe stand at the time of the probe test or the temporary bonding connection at the evaluation package stage is performed, As for the arrangement interval, a sufficient distance must be taken so that the probe standing operation or the bonding operation can be carried out reliably and accurately. Such an interval is useless because other elements cannot be arranged, and also causes an extra increase in the chip area. Therefore, out of a plurality of pads (No. 1 to 103) arranged in a row, pay attention to pad 3 (VDDQ, VSSQ, etc.) that is not necessarily required to stand a probe during a probe test because it is connected inside the chip. Next, an evaluation pad 4 for power supply monitoring is disposed adjacent to the pads 3 (FIG. 3). As a result, even when the arrangement of two rows is unavoidable, the pad spacing between the first row and the second row can be minimized, and an unnecessary increase in chip area can be suppressed.

  Note that the connection destination of bonding at the time of assembling the product package is not limited to the external electrode on the package, but includes, for example, connection with pads on other chips in the same package and other pads on the own chip.

  Although the present invention has been described in detail based on the embodiments, the present invention is not limited to the above two embodiments, and various modifications can be made without departing from the technical concept thereof. Needless to say.

It is a schematic diagram which shows the pad arrangement | positioning in 1st Embodiment of the semiconductor device of this invention. It is a schematic diagram which shows the pad arrangement | positioning in 2nd Embodiment of the semiconductor device of this invention. It is a schematic diagram which shows the pad of the DRAM chip which implemented this invention. It is an example of a row of pads in a conventional DRAM. It is an example of two rows of pad arrangements in a conventional DRAM.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Bonding pad 2 Evaluation pad 3 Pad which is not used in the probe test or evaluation package stage 4 Power supply monitor evaluation pad 5 Bonding wires when assembling the probe needle or product package and their extending directions

Claims (4)

In a semiconductor device in which a plurality of pads are arranged in one direction on a chip,
At least a part of the plurality of pads is arranged in two rows, and only one of the two pads adjacent in the inter-row direction is electrically connected when the product package is assembled. 2. A semiconductor device, wherein the pad is an evaluation pad, and the other pad is an evaluation pad in which only temporary electrical connection is performed during a chip internal circuit test.   The electrical connection at the time of assembling the product package is a bonding connection with an external electrode provided on the product package, and the temporary electrical connection at the time of the chip internal circuit test is a probe contact during a probe test, or The semiconductor device according to claim 1, which is a bonding connection at the time of a test in an evaluation package stage.   The semiconductor device according to claim 1, wherein the plurality of pads are arranged in one direction at a center portion of the chip.   The semiconductor device according to claim 1, wherein the chip is a chip constituting a DRAM.

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