JP2008159858A - Electronic component manufacturing method and electronic component - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electronic component manufacturing method capable of removing burrs in the state of appropriately rounding a corner part, sufficiently exposing the end of an internal electrode and forming a high-contrast marker, and an electronic component. <P>SOLUTION: On a lower layer exterior material 2 on a base 10, insulating layers 31-33 and the internal electrodes 41 and 42 are laminated to form an element body 3 and a marker 5 is formed. Then, after a laminate comprising the lower layer exterior material 2, the element body 3 and the marker 5 is cut into a plurality of chips 6, the base 10 is peeled off and the chips 6 are calcinated. Thereafter, the respective chips 6 are polished in a barrel and an inductor 1 is manufactured. The hardness of the marker 5 is set larger than the hardness of the lower layer exterior material 2 and the hardness of the element body 3. Preferably, the hardness of the lower layer exterior body 2 and the hardness of the element body 3 are made different corresponding to a difference between the edge rounding time of the lower layer exterior material 2 and the exposure time of the outer ends 41b and 42b of the internal electrodes 41 and 42. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an electronic component manufacturing method and an electronic component for manufacturing a multilayer electronic component, and more particularly to an electronic component manufacturing method and an electronic component for manufacturing an electronic component such as a boardless inductor.

In recent years, from the viewpoint of thinning and high density of electronic components such as inductors, so-called substrate-less multilayer electronic components formed by microfabrication such as photolithography without using a thick substrate have been proposed (for example, Patent Document 1).
This type of electronic component is manufactured as follows.
First, a lower layer exterior material such as an insulating layer is formed on an easily peelable substrate such as a carrier film, and then exposed and developed by a photolithography method while laminating a photosensitive insulating paste or a photosensitive conductor pattern. Thus, an insulating layer and a wiring pattern are alternately stacked to form a stacked body. And after dividing this laminated body into chips, the substrate is peeled from each chip, and each chip from which the substrate has been peeled is fired. Thereafter, a barrel process is performed to remove burrs generated during chip division from the chip, round the chip edge, and expose the end of the internal electrode in the chip to the chip end. And an external part is formed in the both ends of a chip | tip, and the electronic component of a desired characteristic is manufactured.

JP 2005-109097 A

However, in the above-described conventional electronic component manufacturing method, it is very difficult to adjust the barrel time for executing the barrel process. As a result, the remaining burr, the poor exposure of the end of the internal electrode, the thinness of the directional marker, the chip There is a problem that products with a high risk of rollover are likely to be manufactured.
That is, during the manufacturing process, a directional marker indicating the mounting direction of the electronic component is formed with a predetermined thickness on the upper surface of the electronic component, and the barrel time is adjusted so that the thickness of the marker does not become thin. If the barrel time is such that it does not become thin, the barrel time with respect to other parts becomes short, so that there are situations in which burrs remain on the chip and the end portions of the internal electrodes are not sufficiently exposed.
However, if the barrel time is set to be long so as to reliably remove the chip burrs and expose the end of the internal electrode, the marker will be over-polished and the marker will be thin, resulting in false recognition. Frequently occur, and mounting failure of electronic parts may occur frequently.
On the other hand, it is also conceivable to increase the thickness of the marker in advance. However, it is not easy to process a large thickness, and when the barrel process is performed until a marker with a large thickness reaches the desired thickness, other parts of the chip, particularly the edges, are over-polished, and the lower surface of the chip The whole is rounded and the electronic component is easy to roll over when mounted.

  The present invention has been made to solve the above-described problem, and can remove burrs in a state in which corners are appropriately rounded and can sufficiently expose the end portions of internal electrodes. An object of the present invention is to provide an electronic component manufacturing method and an electronic component capable of forming a marker with high contrast.

In order to solve the above-mentioned problems, the first aspect of the present invention is to form an element body by placing a lower-layer exterior material on a base material, and laminating an insulating layer and internal electrodes on the lower-layer exterior material. A first step of forming a marker on the substrate, and a second step of cutting each of the chips after peeling the substrate after cutting the laminate made of the substrate, the lower layer exterior material, the element body and the marker into a plurality of chips And a third step of forming external electrodes on both ends of the chip after polishing each fired chip with a barrel, and the marker of the chip after firing in the second process is composed of an inorganic material as a main component and hardness adjustment The base material and lower layer exterior material of the chip after firing in the second step are made of the main component inorganic material and the hardness adjusting material, and the marker, the base body, and the lower layer exterior material. Is set by the ratio of hardness adjusting material to inorganic material That an electronic component manufacturing method, as the hardness of the marker is greater than the hardness of the hardness and body of the lower exterior member, a structure in which to set the percentage of hardness adjusting material.
With this configuration, by executing the first step, a laminate composed of the lower layer exterior material and the element body is formed on the base material, and a marker is formed on the upper surface of the element body. And after performing this 2nd process, after this laminated body is cut | disconnected by the chip | tip, each chip | tip is baked. After such firing, the material of the chip marker is the main component inorganic material, the hardness adjusting material, and the pigment, and the base material and the lower layer exterior material are both the main component inorganic material and the hardness adjusting material. . Then, by executing the third step, each chip is polished by the barrel. At this time, since the ratio of the hardness adjusting material is set so that the hardness of the marker is greater than the hardness of the lower layer exterior material and the hardness of the element body, the lower layer exterior material and the element body are within the predetermined barrel time. Polishing to a desired value prior to the marker. As a result, the marker retains the desired thickness, and the marker maintains a clear contrast, so that no erroneous recognition of the marker occurs. External electrodes are formed on both ends of the chip.

According to a second aspect of the present invention, in the electronic component manufacturing method according to the first aspect, the ratio of the hardness adjusting material is set so that the hardness of the lower-layer exterior material is smaller than the hardness of the base body.
If there is a burr on the chip or the end of the internal electrode of the element body is already exposed, the barrel time required to deburr the chip and round the edge to the desired angle is greater than the end of the internal electrode. Longer than the barrel time required to expose In such a case, even if the end of the internal electrode is polished until it is sufficiently exposed from the element body, burrs remain on the element body and the edge is not polished to a desired angle. However, since the present invention has the above-described configuration and the hardness of the lower layer exterior material is smaller than the hardness of the base body, the time for the edge of the chip to be rounded to the desired angle is shortened, and this time and the internal electrode are exposed. The time is almost equal. As a result, in the third step, the end portion of the internal electrode can be sufficiently exposed from the element body in a short time, the burr can be removed, and the edge can be rounded to a desired angle.

According to a third aspect of the present invention, in the electronic component manufacturing method according to the first aspect, the ratio of the hardness adjusting material is set so that the hardness of the element body is smaller than the hardness of the lower-layer exterior material.
When the end of the internal electrode of the element body is covered with a thick insulating layer, the barrel time required to expose the end of the internal electrode of the chip is rounded to the desired angle. It will be longer than the barrel time required. In such a case, if the end of the internal electrode is polished until it is sufficiently exposed from the element body, the edge becomes overpolished, and the entire lower surface of the chip becomes rounded, so that it tends to roll over during mounting. However, since the present invention has the above configuration and the hardness of the element body is smaller than the hardness of the lower layer exterior material, the time until the end of the internal electrode is exposed is shortened, and this time and the edge are set at a desired angle. The time until rounding is almost equal. As a result, in the third step, the burrs can be removed and the edges can be rounded to a desired angle in a short time, and the end portions of the internal electrodes can be sufficiently exposed from the element body.

  According to a fourth aspect of the present invention, in the electronic component manufacturing method according to any one of the first to third aspects, the lower-layer exterior material is arranged at a corner portion of the lower portion of the element body.

  According to a fifth aspect of the present invention, there is provided a chip having an element body in which a lower layer exterior material, an insulating layer and an internal electrode are laminated on the lower layer exterior material, and a marker provided on the upper surface of the element body, and provided at both ends of the chip. It has external electrodes, the chip marker is made of the main component inorganic material, the hardness adjusting material, and the pigment, and the element body and the lower layer exterior material are both made of the main component inorganic material and the hardness adjusting material. In addition, the hardness of the marker, the base body, and the lower layer exterior material is an electronic component set by the ratio of the hardness adjusting material to the inorganic material, and the marker hardness is set larger than the hardness of the lower layer exterior material and the base body It was set as the structure.

  According to a sixth aspect of the present invention, in the electronic component according to the fifth aspect, the hardness of the lower layer exterior material is smaller than the hardness of the element body.

  According to a seventh aspect of the present invention, in the electronic component according to the fifth aspect, the hardness of the element body is smaller than the hardness of the lower layer exterior material.

  According to an eighth aspect of the present invention, in the electronic component according to any one of the fifth to seventh aspects, the lower-layer exterior material is disposed at a corner of the lower portion of the element body.

  A ninth aspect is the electronic component according to any one of the fifth to eighth aspects, wherein the inorganic material is glass, the hardness adjusting material is alumina, and the pigment is cobalt.

As described above in detail, according to the present invention, at the time of barrel polishing, the marker retains a desired thickness and does not deteriorate the contrast between the marker and the element body, thereby preventing a mounting failure due to misrecognition. There is an excellent effect of being able to.
Also, the barrel time required to round the chip edge to the desired angle is usually reduced by reducing the hardness of the lower exterior material to be less than the hardness of the element body and shortening the time for the chip edge to round to the desired angle. However, even in the case where the barrel time required to expose the end portion of the internal electrode is longer, the edge rounding time can be made substantially equal to the time until the internal electrode is exposed. As a result, the end portions of the internal electrodes can be sufficiently exposed from the element body, and burrs can be removed and the edges can be rounded to a desired angle in a short time.
Also, by reducing the time until the end of the internal electrode is exposed by making the hardness of the element body smaller than the hardness of the lower packaging material, it is usually necessary to expose the end of the internal electrode of the chip. Even when the barrel time required is longer than the barrel time required to round the edge of the chip to the desired angle, the internal electrode exposure time and the time to round the edge to the desired angle should be approximately equal. Can do. As a result, the burr can be removed and the edge can be rounded to a desired angle, the end of the internal electrode can be sufficiently exposed from the element body in a short time, and the electronic component can be rolled over by over-polishing the edge. Can also be prevented.

  The best mode of the present invention will be described below with reference to the drawings.

1 is an exploded perspective view of an inductor which is an electronic component according to a first embodiment of the present invention, FIG. 2 is a perspective view showing the inductor through, and FIG. 3 is a perspective view of FIG. It is -A sectional drawing.
As shown in FIG. 1, an electronic component 1 of this embodiment is a so-called boardless multilayer inductor, a chip 6 having a lower exterior material 2, an element body 3, and a marker 5, and a pair of external electrodes 7- 1 and 7-2.

  The lower-layer exterior material 2 is an insulating layer disposed on the bottom of the element body 3, and is mainly composed of glass, which is an inorganic material, and alumina as a hardness adjusting material.

The element body 3 has a structure in which insulating layers 31 to 33 are stacked and the coil body 4 is included therein.
The insulating layers 31 to 33 constituting the element body 3 are made of glass, which is an inorganic material, as a main component, and alumina as a hardness adjusting material, like the lower-layer exterior material 2.
The coil body 4 is composed of a silver internal electrode 41 and an internal electrode 42. Specifically, the internal electrode 41 is patterned on the insulating layer 31 and the internal electrode 42 is patterned on the insulating layer 32. The inner end portion 41 a of the internal electrode 41 and the inner end portion 42 a of the internal electrode 42 are connected by the via hole 43, and the 2.5-turn coil body 4 is formed inside the element body 3.

The marker 5 is an identification member that indicates the mounting direction of the inductor 1, and is patterned on the surface of the uppermost insulating layer 33 of the element body 3. Similarly to the lower layer exterior material 2 and the element body 3, the marker 5 is mainly composed of glass which is an inorganic material and alumina as a hardness adjusting material, but further contains cobalt as a pigment.
As will be described later, the hardness of the marker 5 is set to be larger than the hardness of the lower-layer exterior material 2 and the hardness of the element body 3 in order to prevent the marker 5 from being thinned during manufacturing. That is, the ratio of alumina to the glass constituting the marker 5 is set larger than the ratio of alumina to the glass constituting the lower-layer exterior material 2 and the ratio of alumina to the glass constituting the element body 3.

One chip 6 is formed by the lower layer exterior material 2, the element body 3, and the marker 5 as described above, and the edge of the chip 6 is rounded. Specifically, the edge 2a of the lower packaging material 2 and the edge 5a of the marker 5 are rounded at a desired angle.
The external electrodes 7-1 and 7-2 are formed at both ends of the chip 6. Specifically, the external electrodes 7-1 and 7-2 are made of silver, nickel, copper, tin or the like, and the external electrodes 7-1 are made of the element body 3 as shown in FIGS. The external electrode 7-2 is connected to the outer end portion 42b of the internal electrode 42 exposed from the right end surface of the element body 3, and is connected to the outer end portion 41b of the internal electrode 41 exposed from the left end surface.

Next, a method for manufacturing the inductor 1 will be described.
This manufacturing method includes three steps of a first step to a third step.
In addition, this manufacturing method implement | achieves the manufacturing method based on invention of Claim 1 concretely.
4 is a cross-sectional view showing the first step, FIG. 5 is a cross-sectional view showing the second step, and FIG. 6 is a cross-sectional view showing the third step. 4 and 5, the case where three chip portions are formed on one wafer is shown for easy understanding.

The first step is a step of forming a wafer on which three chips are placed by a photolithography method.
Specifically, as shown in FIG. 4A, first, the paste-like lower-layer exterior material 2 is applied onto a peelable film-like substrate 10 and exposed to the entire surface with ultraviolet rays. Then, as shown in FIG. 4B, a paste-like insulating layer 31 is applied and fully exposed, and a paste-like internal electrode 41 is applied on the insulating layer 31 and exposed and developed. The internal electrode 41 is patterned. Thereafter, as shown in FIG. 4C, after the insulating layer 32, the internal electrode 42, and the insulating layer 33 are laminated, the marker 5 is patterned on the surface of the insulating layer 33.
That is, the three element bodies 3 are formed on the lower-layer exterior material 2, and the marker 5 is formed on the upper surface of each element body 3, thereby forming the wafer 100 as a stacked body on which the three chip portions are mounted.
Here, in the first step, the ratio of alumina to the glass is set so that the hardness of the marker 5 after firing in the second step, which will be described later, is greater than the hardness of the lower sheath material 2 and the hardness of the element body 3. Keep it.
Specifically, in the marker 5, a paste containing cobalt and having an alumina to glass ratio of 5 wt% or more and 45 wt% or less is applied on the insulating layer 33 to form the marker 5 portion. On the other hand, in the element body 3, the insulating layer 31 to 33 is formed by applying a paste in which the ratio of alumina to glass is 0 wt% or more and 45 wt% or less, and the lower covering material 2 also has a ratio of alumina to glass. Is applied to the base material 10 to form the lower-layer exterior material 2 portion. Preferably, in the marker 5, the ratio of alumina to the glass is set to 35% by weight, and in the element body 3 and the lower packaging material 2, the ratio of alumina to the glass is set to 30% by weight or less.

The second step is a step of firing the chips obtained by cutting the wafer.
Specifically, as shown in FIG. 5A, a so-called guillotine cut is performed using a cutter 110 at the boundary between adjacent outer end portions 41 b and outer end portions 42 b on the wafer 100. Then, as shown in FIG. 5 (b), three chips 6 are obtained from one wafer 100 by peeling the base material 10. Thereafter, as shown in FIG. 5C, each chip 6 is fired.

The third step is a step until the inductor 1 is completed.
It is necessary to round the edge of the chip 6 fired in the second step at a desired angle. Further, as shown in FIGS. 5A and 5B, it is necessary to remove the burrs 2 b at the edge of the lower-layer exterior material 2 generated when the wafer 100 is cut. Further, when the chip 6 is baked, the internal electrodes 41 and 42 as shown in FIG. 5C due to differences in thermal expansion coefficient and shrinkage ratio between the insulating layers 31 to 33 and the internal electrodes 41 and 42. The outer end portions 41b and 42b are covered with the portions 3a and 3b of the insulating layers 31 to 33. Therefore, it is necessary to remove the portions 3 a and 3 b of the insulating layers 31 to 33 and expose the outer end portions 41 b and 42 b of the internal electrodes 41 and 42 from the element body 3.
Therefore, as shown in FIG. 6A, in this third step, the chip 6 baked in the second step is polished using the barrel 120. Thereby, the edge of the chip 6 is rounded to a desired angle, the burr 2 b is removed, and the outer end portions 41 b and 42 b of the internal electrodes 41 and 42 are exposed from the element body 3.

However, if the hardness of the marker 5 after firing is substantially the same as the hardness of the lower packaging material 2 and the hardness of the element body 3, the removal of the burr 2b of the chip 6 and the outer end portions 41b and 42b of the internal electrodes 41 and 42 are performed. When exposure is performed reliably, as shown in FIG. 6B, the marker 5 is overpolished and the thickness of the marker 5 is reduced. For this reason, the contrast between the marker 5 and the element body 3 is reduced, making it difficult to recognize the marker 5.
However, in this embodiment, as described above, in the marker 5, the ratio of alumina to glass is set to 35% by weight, and in the element body 3 and the lower-layer exterior material 2, the ratio of alumina to glass is 30% by weight or less. The hardness of the marker 5 is set to be larger than the hardness of the lower-layer exterior material 2 and the hardness of the element body 3.
Accordingly, the removal time of the portions 3a and 3b of the insulating layers 31 to 33 covering the burrs 2b of the chip 6 and the outer ends 41b and 42b of the internal electrodes 41 and 42 shown in FIG. Shorter than. As a result, as shown in FIG. 6C, parts 3a and 3b of the insulating layers 31 to 33 covering the burr 2b of the chip 6 and the outer ends 41b and 42b of the internal electrodes 41 and 42 are removed, and the chip Even after the edge of 6 is polished to a desired angle, the marker 5 having a desired thickness remains on the element body 3. For this reason, since the contrast between the marker 5 and the element body 3 is increased, the marker 5 can be easily recognized.

  Next, after both ends of the chip 6 polished by the barrel 120 are dipped in a silver paste and baked, nickel, copper, tin, etc. are plated from above the silver layer, so that FIG. As shown, external electrodes 7-1 and 7-2 are formed at both ends of the chip 6 to complete the manufacture of the inductor 1.

Next, a usage example of the inductor 1 will be described.
FIG. 7 is a perspective view showing an example of use of the inductor 1.
As shown in FIG. 7, the inductor 1 can be mounted by mounting the external electrodes 7-1 and 7-2 on the lands 201 and 202 on the substrate 200 and connecting them.
At this time, the marker 5 serves as a mark in the mounting direction. As described above, the marker 5 on the surface of the inductor 1 maintains a predetermined thickness and maintains a clear contrast with the element body 3. The mounting direction can be easily recognized.
As described above, since the outer end portions 41b and 42b of the coil body 4 are sufficiently exposed from the element body 3, the coil body 4 and the external electrodes 7-1 and 7-2 are securely connected. ing. Therefore, for example, the current input from the land 201 to the external electrode 7-1 flows into the coil body 4 through the outer end portion 41b, and is output from the external electrode 7-2 to the land 202 through the outer end portion 42b. It becomes.

Next explained is an electronic component manufacturing method according to the second embodiment of the invention.
This manufacturing method specifically realizes the manufacturing method according to the invention of claim 2.
FIG. 8 is a cross-sectional view showing the firing state of the inductor chip to which the electronic component manufacturing method according to the second embodiment of the present invention is applied.
In the first embodiment, the barrel time required for removing the burrs of the chip 6 in the third step and rounding the edge to a desired angle and the outer ends 41b, 42b of the internal electrodes 41, 42 are exposed from the element body 3. From the standpoint that the barrel time required for this is approximately equal, the lower exterior packaging material 2 and the base body 3 are set to have the same hardness.
However, as shown in FIG. 8, the burr 2b of the lower-layer exterior material 2 of the chip 6 baked in the second step is large, and the element 3 covers the outer ends 41b and 42b of the internal electrodes 41 and 42. The portions 3a and 3b may be thin. In such a case, the barrel time required to round the edge 2a of the lower-layer exterior packaging material 2 baked in the second step to a desired angle is required until the outer ends 41b and 42b of the internal electrodes 41 and 42 are exposed. Longer than barrel time.
Therefore, if the hardness of the lower-layer exterior material 2 and the element body 3 are set to be equal, the burr 2b of the lower-layer exterior material 2 is obtained even though the outer ends 41b and 42b of the internal electrodes 41 and 42 are exposed. It takes a long time for removal and rounding, and the throughput deteriorates.

In this embodiment, the barrel time required to round the edge of the lower-layer exterior material 2 of the fired chip 6 to a desired angle is exposed from the various working conditions in the second step, and the outer ends 41b and 42b of the internal electrodes 41 and 42 are exposed. This is a method applied when it is determined that the barrel time required to be longer is set. The hardness of the lower-layer exterior material 2 is set to be smaller than the hardness of the element body 3, and the first to third steps are executed. Is.
Specifically, in the marker 5, a paste containing cobalt and having an alumina to glass ratio of 5 wt% or more and 45 wt% or less is applied on the insulating layer 33. On the other hand, in the element body 3, a paste having an alumina ratio of 3 wt% or more and 45 wt% or less is applied as insulating layers 31 to 33, and in the lower sheath material 2, the alumina ratio of glass is 0 wt% or more. A paste of 40% by weight or less is applied on the substrate 10.
And in the said range, the hardness of the lower-layer exterior material 2 is set smaller than the hardness of the element | base_body 3, and the hardness of the element | base_body 3 is set smaller than the hardness of the marker 5. FIG.
Preferably, in the marker 5, the ratio of alumina to glass is set to 35% by weight. And in the element | base_body 3, the ratio of the alumina with respect to glass is set to 25 weight%, and in the lower layer exterior material 2, the ratio of the alumina with respect to glass is set to 20 weight%.

With this configuration, in the third step, the barrel time required for removal and rounding of the burr 2b of the lower layer exterior material 2 is such that the portions 3a and 3b of the thin element body 3 are polished to the outer ends of the internal electrodes 41 and 42. This is almost equal to the short barrel time required to expose the portions 41b and 42b. As a result, the burr 2b of the lower-layer exterior material 2 can be removed and rounded in a short barrel time with respect to the internal electrodes 41 and 42, and the working time can be shortened and the throughput can be improved.
Since other configurations, operations, and effects are the same as those of the first embodiment, description thereof is omitted.

Next explained is an electronic component manufacturing method according to the third embodiment of the invention.
This manufacturing method specifically realizes the manufacturing method according to the invention of claim 3.
FIG. 9 is a sectional view showing the firing state of the inductor chip to which the electronic component manufacturing method according to the third embodiment of the present invention is applied.
As shown in FIG. 9, the burr 2b of the lower-layer exterior material 2 of the chip 6 fired in the second step is small, but a part 3a of the element body 3 covering the outer ends 41b, 42b of the internal electrodes 41, 42, 3b may be thick. In such a case, the barrel time required to expose the outer ends 41b, 42b of the internal electrodes 41, 42 of the chip 6 fired in the second step is rounded to the desired angle. Longer than the barrel time required.
Therefore, as in the first and second embodiments, if the hardness of the lower-layer exterior material 2 is set smaller than or equal to the hardness of the element body 3, the burrs 2b of the lower-layer exterior material 2 are removed. In spite of being rounded to a desired angle, the outer end portions 41b and 42b of the internal electrodes 41 and 42 are not yet exposed, and the coil body 4 and the external electrodes 7-1 and 7-2 are disconnected. May be incurred. However, if the barrel time is extended until the outer ends 41b, 42b of the internal electrodes 41, 42 are exposed, the edge of the lower-layer exterior material 2 becomes over-polished, and the inductor 1 may roll over during mounting.

In this embodiment, the barrel time required to expose the outer end portions 41b, 42b of the internal electrodes 41, 42 of the fired chip 6 from the various working conditions in the second step is desired for the edge of the lower layer exterior material 2 This method is applied when it is determined that the barrel time required for rounding to an angle is longer. The hardness of the element body 3 is set to be smaller than the hardness of the lower-layer exterior material 2, and the first to third steps are executed. To do.
Specifically, in the marker 5, a paste containing cobalt and having an alumina to glass ratio of 5 wt% or more and 45 wt% or less is applied on the insulating layer 33. On the other hand, in the element body 3, a paste having a ratio of alumina to glass of 3 wt% or more and 45 wt% or less is applied as insulating layers 31 to 33, and in the lower sheathing material 2, the ratio of alumina to glass is 5 wt% or more. A paste of 40% by weight or less is applied on the substrate 10.
Then, within the above range, the hardness of the element body 3 is set smaller than the hardness of the lower-layer exterior material 2, and the hardness of the lower-layer exterior material 2 is set smaller than the hardness of the marker 5.
Preferably, the ratio of alumina to glass in the marker 5 is set to 35% by weight, the ratio of alumina to glass in the element body 3 is set to 25% by weight, and the ratio of alumina to glass in the lower sheathing material 2 is set to 30% by weight. To do.

With this configuration, in the third step, the barrel time required to polish the portions 3a and 3b of the thick element body 3 and expose the outer ends 41b and 42b of the internal electrodes 41 and 42 is reduced. It is approximately equal to the short barrel time required for 2b removal and rounding. As a result, the exposure work of the outer end portions 41b and 42b of the internal electrodes 41 and 42 can be performed simultaneously with the barrel time for removing or rounding the burrs 2b of the lower-layer exterior material 2. For this reason, it is possible to provide a high-quality inductor 1 that is free of disconnection and that does not cause a rollover during mounting, and it is possible to shorten the working time and improve the throughput.
Since other configurations, operations, and effects are the same as those of the first and second embodiments, description thereof is omitted.

Next explained is an electronic component according to the third embodiment of the invention.
FIG. 10 is a sectional view showing an electronic component manufacturing method according to the third embodiment of the present invention, and FIG. 11 is a perspective view showing the main part of the third embodiment.
As shown in FIGS. 10 and 11, the inductor 1 ′ of this embodiment is different from the first to third embodiments in the structure of the lower-layer exterior material.
Specifically, as shown in FIGS. 10 and 11, four small rectangular lower layer exterior materials 2 ′ are arranged below the element body 3.
With this configuration, the lower-layer exterior material 2 ′ is located at a location where the wear is most severe during the barreling in the third step.

Next, a method for manufacturing the inductor 1 ′ will be described.
This manufacturing method specifically realizes the manufacturing method according to the invention of claim 4.
FIG. 12 is a cross-sectional view showing the manufacturing process of the inductor 1 ′.
In the first step of this method, as shown in FIG. 12 (a), a large lower layer exterior material 2 'made of the same material as the lower layer exterior material 2 of the first embodiment is formed on the base material 10 and each It arrange | positions in the position straddling the corner | angular part of a chip | tip.
Thereafter, as shown in FIG. 12 (b), the element body 3 and the marker 5 are laminated on the lower-layer exterior material 2 'using the photolithography method in the same manner as in the first to third embodiments. To do.
Then, in the second step, as shown in FIG. 12C, the boundary between the adjacent outer end 41b and the outer end 42b on the wafer is guillotine cut using the cutter 110, and then the base material By peeling 10, three chips 6 ′ in which the lower-layer exterior material 2 ′ is located at the lower four corners are obtained.
Thereafter, in the same manner as in the first to third embodiments, after firing each chip 6 ', the third step is performed to perform barrel polishing and formation of external electrodes 7-1 and 7-2. Thus, the manufacture of the inductor 1 'is completed.
Since other configurations, operations, and effects are the same as those in the first to third embodiments, description thereof is omitted.

1 is an exploded perspective view of an inductor which is an electronic component according to a first embodiment of the present invention. FIG. 3 is a perspective view showing the inductor through. It is arrow AA sectional drawing of FIG. It is sectional drawing which shows a 1st process. It is sectional drawing which shows a 2nd process. It is sectional drawing which shows a 3rd process. It is a perspective view which shows the usage example of an inductor. It is sectional drawing which shows the baking state of the chip | tip of the inductor to which the electronic component manufacturing method concerning 2nd Example of this invention is applied. It is sectional drawing which shows the baking state of the chip | tip of the inductor which applies the electronic component manufacturing method concerning 3rd Example of this invention. It is sectional drawing which shows the electronic component manufacturing method which concerns on 3rd Example of this invention. It is a perspective view which shows the principal part of 3rd Example. It is sectional drawing which shows the manufacturing process of the inductor of 3rd Example.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1,1 '... Inductor 2, 2' ... Lower layer exterior material, 2a, 5a ... Edge, 2b ... Burr, 3 ... Element body, 3a, 3b ... Part, 4 ... Coil body, 5 ... Marker, 6, 6 '... chip, 7-1, 7-2 ... external electrode, 31-33 ... insulating layer, 41, 42 ... internal electrode, 41a, 42a ... inner end, 41b, 42b ... outer end, 43 ... via hole, 100 ... wafer, 110 ... cutter, 120 ... barrel, 200 ... substrate, 201,202 ... land.

Claims (9)

A first step of placing a lower layer exterior material on a substrate, laminating an insulating layer and internal electrodes on the lower layer exterior material to form an element body, and forming a marker on the upper surface of the element body;
A second step of cutting the laminate composed of the base material, the lower layer exterior material, the element body, and the marker into a plurality of chips, then peeling the base material and firing each chip;
A third step of forming external electrodes on both ends of the chip after polishing each baked chip with a barrel;
The marker of the chip after firing in the second step is made of a main component inorganic material, a hardness adjusting material, and a pigment,
Both the base body and the lower layer exterior material of the chip after firing in the second step are made of a main component inorganic material and a hardness adjusting material,
The electronic component manufacturing method of setting the hardness of these markers, element body and lower layer exterior material in the ratio of the hardness adjusting material to the inorganic material,
The ratio of the hardness adjusting material was set so that the Vickers hardness of the marker (hereinafter, “Vickers hardness” is simply referred to as “hardness”) is greater than the hardness of the lower layer exterior material and the hardness of the element body,
An electronic component manufacturing method characterized by the above. In the electronic component manufacturing method according to claim 1,
The ratio of the hardness adjusting material was set so that the hardness of the lower layer exterior material was smaller than the hardness of the element body,
An electronic component manufacturing method characterized by the above. In the electronic component manufacturing method according to claim 1,
The ratio of the hardness adjusting material was set so that the hardness of the element body was smaller than the hardness of the lower layer exterior material,
An electronic component manufacturing method characterized by the above. In the electronic component manufacturing method according to any one of claims 1 to 3,
The lower layer exterior material was arranged at the lower corner of the element body,
An electronic component manufacturing method characterized by the above. A lower body packaging material, an insulating layer, and an element body in which internal electrodes are laminated on the lower layer outer packaging material, a chip having a marker provided on the upper surface of the element body, and external electrodes provided at both ends of the chip ,
The marker of the chip is made of a main component inorganic material, a hardness adjusting material and a pigment,
Both the element body and the lower layer exterior material are made of a main component inorganic material and a hardness adjusting material,
The hardness of these marker, element body and lower layer exterior material is an electronic component set by the ratio of the hardness adjusting material to the inorganic material,
The hardness of the marker is set larger than the hardness of the lower layer exterior material and the hardness of the element body,
An electronic component characterized by that. The electronic component according to claim 5,
The hardness of the lower layer exterior material is smaller than the hardness of the element body,
An electronic component characterized by that. The electronic component according to claim 5,
The hardness of the element body is smaller than the hardness of the lower layer exterior material,
An electronic component characterized by that. The electronic component according to any one of claims 5 to 7,
The lower layer exterior material is disposed at the lower corner of the element body,
An electronic component characterized by that. The electronic component according to any one of claims 5 to 8,
The inorganic material is glass, the hardness adjusting material is alumina, and the pigment is cobalt.
An electronic component characterized by that.

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