JP2008159155A - Short detection circuit, imaging device using the same, and storage device - Google Patents

Abstract

A short current is detected without increasing the chip area.
An active element, a plurality of element signal lines connected to the active element and arranged in one direction, element signal line selection information is decoded, and a first control line group corresponding to the element signal line is A row selection circuit for arbitrarily selecting the control line, a control signal and a mode setting signal supplied from the first control line, and optionally from a second control line group corresponding to the first control line group A mode setting circuit that selects the second control line and sets the potential level of the second control line, and a third control signal is supplied from the mode setting circuit, and a short current is generated between the adjacent element signal lines. A driver circuit for setting a plurality of element signal lines to different potentials for generation is used to detect a short-circuit current between adjacent element signal lines.
[Selection] Figure 1

Description

It is an invention related to wiring short detection of a semiconductor having a cell array in the row direction and the column direction,
In particular, the present invention relates to a short detection circuit such as an image sensor or a storage device.

  A short circuit in a wiring of a semiconductor circuit having cell arrays in the row direction and the column direction is one of the main causes of malfunctions. At the time of production selection, it is important to exclude a chip (Chip) in which a short circuit between wirings exists. As for the technology relating to short detection, as disclosed in Patent Document 1 (Japanese Patent Laid-Open No. 11-297098) in a semiconductor memory, memory cells are arranged in an XY matrix, and the memory cells are driven in the horizontal direction. Word lines (lines) are arranged in the vertical direction and bit lines (lines) are arranged in the vertical direction.

  A switching transistor and a pad are connected in series to the end of each word line arranged in the horizontal direction, and the word line can be separated from the pad during normal and inspection by controlling on / off of this switching transistor. Has been.

At the time of a short inspection, the switching transistor is turned on (ON) so that the word line and the pad are connected, and the horizontal signal line (word line) or the vertical signal line is divided into several types (for example, even rows and odd rows). A short circuit is detected by electrically connecting to the pad and monitoring the current by applying a different potential to the pad.
Japanese Patent Laid-Open No. 11-297098

However, in the technique disclosed in Patent Document 1, a pad (PAD) must be prepared for each word line (row) for testing, and the area of the pad is compared with other elements, wirings, and the like. Since it is significantly large, the chip size increases. In addition, since how to supply power is determined by the connection of wiring from the pad, there are few variations in how to apply the potential.
As the process is miniaturized, the leakage current when the transistor Tr is turned off increases and the standby current increases, so that the detection sensitivity of a minute current change when the word line is short-circuited decreases.
The criteria for determining whether or not there is a short-circuit between word lines is determined by the absolute value of the standby current, but in the production selection process, the process varies depending on the transistor gate (L) length on the narrow side, and standby When the current increases, even if the product is good, it is judged as a defective product, and the yield is greatly reduced.
In order to solve the above problems, the present invention can set horizontal or vertical control lines to even potentials, odd potentials, and different potentials, and can perform the above settings for each block. Detect shorts between control lines.

  The short detection circuit of the present invention decodes an active element, a plurality of element signal lines to which the active element is connected and arranged in one direction, and element signal line selection information, and a first signal corresponding to the element signal line is decoded. A row selection circuit for arbitrarily selecting a first control line from the control line group, a control signal supplied from the first control line, and a mode setting signal are supplied, and a first selection line corresponding to the first control line group is supplied. A second control line is arbitrarily selected from the two control line groups and a potential level of the second control line is set; a third control signal is supplied from the mode setting circuit; A driver circuit for setting the plurality of element signal lines to different potentials in order to generate a short current between the element signal lines;

  The short detection circuit of the present invention decodes an active element, a plurality of element signal lines to which the active element is connected and arranged in one direction, and element signal line selection information, and a first signal corresponding to the element signal line is decoded. A row selection circuit for arbitrarily selecting the first control line from the control line group, and the first control line group supplied with the first control signal and the word line setting signal supplied from the first control line. A second control line is arbitrarily selected from the second control line group corresponding to the second control line, and a second control signal and a block setting signal output from the second control line are supplied, and the second control line A group is divided into a plurality of blocks, a mode setting circuit that selects at least one of the divided blocks and controls the potential of a control line in the block, and a third control signal is supplied from the mode setting circuit. Short current between adjacent element signal lines And a driver circuit for setting a different potential to each other the potential of the plurality of device signal line for generating.

  An imaging apparatus according to the present invention decodes a pixel that converts an input optical signal into an electrical signal, a plurality of pixel signal lines that are connected to the pixel and arranged in one direction, and pixel signal line selection information. A selection circuit for generating a first control signal for arbitrarily selecting a signal line, and the first control signal and the mode setting signal are supplied to select the pixel signal line and set the potential level of the pixel signal line A plurality of pixel signal lines are set to different potentials in order to generate a short current between the adjacent pixel signal lines. A driver circuit.

  The memory device of the present invention decodes a memory cell, a word line or bit line connected to the memory cell and arranged in one direction, address information of the word line or bit line, and the word line or bit line is decoded. A selection circuit for generating a first control signal to be arbitrarily selected, the first control signal and the mode setting signal are supplied, and the word line or bit line is selected, and the potential level of the word line or bit line is set. A mode setting circuit for generating a second control signal to be set and the second control signal are supplied, and the word line or bit line is different from each other in order to generate a short current between the adjacent word line or bit line. And a driver circuit set to a potential.

  In the present invention, the mode setting circuit arbitrarily selects adjacent element (cell) control lines in the horizontal direction or the vertical direction, or arbitrarily selects adjacent element signal lines in the selected block. Different potentials are applied to the signal lines to detect a leakage current of the driving transistor and a short-circuit current between adjacent element signal lines.

According to the present invention, the standby current at the time of short detection can be suppressed small by selecting the horizontal signal line and the vertical signal line for each block (block) and setting the different power supply, and the standby current increases due to the miniaturization of the process. But it can detect shorts.
Further, by dividing the chip into blocks, the standby current of each block of the chip can be compared, and even if the standby current lot (wafer) variation increases, it becomes easy to detect a short circuit. .

FIG. 1 shows a block configuration of a short detection circuit 100 according to an embodiment of the present invention.
Application examples of the short detection circuit include a semiconductor memory (storage device) and an image sensor (solid-state image sensor). Usually, a row is selected by a horizontal control (signal) line, and a control (signal) line in the column direction is used. Performs operations related to reading / writing data.

The short detection circuit 100 includes a row selection circuit 11, a mode selection (Mode select) circuit 12-N to 12-0, cells C _{00 to} C _NM and word line drivers (CMOS inverter configuration) P _{N and} N _N to It is composed of P ₀ , N ₀ , MOS transistors, and word lines (lines) of row ₀ to row N. (Lines row 0 to row N are also referred to as word lines, and column direction vertical signal lines Column 0 to Columns are also referred to as column lines (signal lines) or signal lines. Word lines are also referred to as solid-state imaging devices other than storage devices) (When including a signal line, it is also called an element signal line.)

The row selection circuit 11 is composed of, for example, a decoder or a shift register, decodes the supplied address data by the decoder, outputs a control signal from the outputs 11-0 to 11-N, and outputs arbitrary word lines row0 to rowN. Select.
Here, the outputs 11-0 to 11-N output from the row selection circuit 11 and corresponding to the word lines in the horizontal direction are also referred to as a first control line group.

The mode setting (select) circuits 12-0 to 12-N are configured by a word line selection circuit WL and a block selection circuit BLK, and select any adjacent word line or arbitrary block. Select adjacent word lines.
Here, the control lines output from the mode setting circuits 12-0 to 12-N are also referred to as a second control line group.

The transistors P _N, N _{N to} P ₀ , N ₀ constituting the word line driver are composed of a P-channel MOS transistor and an N-channel MOS transistor, and a word line composed of row 0 to row N (or horizontal / vertical direction). The element signal line) is arbitrarily selected.

The cells C _{00 to} C _NM are arranged in a matrix of N rows and M columns, and each cell includes a MOS transistor and a capacitor or a MOS transistor in the case of a storage cell. In the cells C _{00 to} C _NM selected by the row 0 to row N (word lines 0 to N) and the column (bit) line, data stored in the capacitor is read via the bit line, and data is also transmitted via the bit line. Is stored in the selected capacity.

  In the case of a MOS type solid-state imaging device, it is composed of a PD (light detection diode), an amplification transistor, a reset (gate) transistor, a reading transistor, and the like. After resetting the FD (floating diffusion) with the reset transistor and amplifying the signal charge generated by the photodetection diode with the amplification transistor, the video signal selected by the horizontal row0 to rowN and the vertical signal line is the signal line. It is output via (vertical control line or signal line).

The outputs 11-0 to 11-N of the row selection circuit 11 are connected to the inputs of the mode setting circuits 12-0 to 12-N, respectively. The output terminal of the mode setting circuit 12-N is connected to both gates of the P _N and N _N MOS transistors of the driver that drives the word line row _N , and the source of the P _N MOS transistor is a reference power source, for example, a power source that supplies the power source voltage V1. The drains of the P _N MOS transistor and the N _N MOS transistor are connected in common and connected to the word line row N. The source of the N _N MOS transistor is connected to a reference power supply, for example, ground (GND; V0).

Word line rowN cell _{C N0, C N1, ···,} are connected to the horizontal selection terminal of the _{C NM.} Also the cell C _N0 vertical signal line is connected to (or bit lines, vertical signal lines, etc.) Colum0, vertical column is selected. Similarly, the cell C _N1 is connected to the vertical signal line column1,..., The cell C _NM is connected to the vertical signal line collumm, and the cell in the column direction is selected by the column selection signal output from the vertical selection circuit. .

The output of the mode setting circuit 12- (N-1) is connected to both gates of the P _(N-1) and N _(N-1) MOS transistors of the driver that drives the word line row _N , and P _(N-1) MOS The source of the transistor is connected to a reference power source such as a power source, and the drains of the P _(N-1) MOS transistor and the N _(N-1) MOS transistor are connected in common and connected to the word line row (N-1). The source of the N _(N-1) MOS transistor is connected to a reference power supply, for example, ground (GND).

The word line row (N-1) is connected to the horizontal selection terminals of the cells C _{(N-1) 0} , C _{(N-1) 1} ,..., C _{(N-1) M.} The cell C _{(N-1) 0} is connected to a vertical signal line (or bit line, vertical signal line, etc.) column0, and a vertical column is selected. Similarly, the cell C _{(N-1) 1} is connected to the vertical signal line column1,..., The cell C _{(N-1) M} is connected to the vertical signal line columnum, and the column selection signal output from the column selection circuit. The cell in the column direction is selected by.
Thereafter, the same connection configuration is repeated up to the mode setting circuit 12-0.

Next, FIG. 2 shows a circuit configuration example of the mode setting circuits 12-N to 12-0.
The output 11-N of the row selection circuit 11 is connected to one input of the NOR circuit 20-N, and the other input is connected to a control line to which a mode setting signal is supplied. The output of the NOR circuit 20-N is connected to the word line rowN.
An output 11- (N-1) of the row selection circuit 11 is connected to an input of a NOT circuit 20- (N-1), and the other input is connected to a control line to which a mode setting signal is supplied. The output of the NOT circuit 20- (N-1) is connected to the word line row (N-1). Similarly, the above-described connection configuration is repeated up to the word line row0.
Here, the mode setting circuit 12-N in FIG. 1 is connected to the NOR circuit 20-N shown in FIG. 2, the mode setting circuit 12- (N-1) is connected to the NOT circuit 20- (N-1),. The mode setting circuit 12-1 corresponds to the NOR circuit 20-1, and the mode setting circuit 12-0 corresponds to the NOT circuit 20-0.

  Next, the operation of the short detection circuit 100 shown in FIG. 1 will be described. The operation of the short detection circuit 100 has two types of normal operation and detection operation.

First, the normal operation will be described.
During normal operation, address data is supplied to the row selection circuit 11 and is decoded by the decoder of the row selection circuit 11 to output a control signal for selecting an arbitrary row. At this time, since the mode setting circuits 12-N to 12-0 are always set in a conductive state, the control signal from the outputs 11-0 to 11-N of the row selection circuit 11 is a word for driving the word lines rowN to row0. The signals are supplied to transistors P _N, N _{N to} P ₀ , N ₀ constituting a line driver (CMOS inverter). During normal operation, the mode setting circuits 12-N to 12-0 set only the selected row to the voltage V1 (generally the power supply voltage), and set the other rows to V0 (generally GND).
Similarly, for the vertical signal line, an arbitrary line is selected from vertical signal lines (signal lines) Column0 to Columnm in the column direction. Then, a cell at a position where the word line in the row direction intersects with the vertical signal line in the column direction is selected, and data is written into the selected cell, or a vertical signal line (signal line; bit line from the cell to the column direction). ) Is read out via. In the case of a memory device, data is written into the memory cell.

Next, the detection operation of the short detection circuit 100 will be described with reference to FIGS.
The mode setting signal is supplied to the mode setting circuits 12-N to 12-0, and the word line (WL) select circuits 20-0 to 20-N constituting the mode setting circuits 12-N to 12-0 operate.
Specifically, the row selection signal supplied from the output 11-N of the row selection circuit 11 is supplied to one input of the NOR circuit 20-N shown in FIG. 2, and is supplied to the other input of the NOR circuit 20-N. Is supplied with a mode setting signal. When the row selection signal supplied from the output 11-N of the row selection circuit 11 is “H” (high) level and the mode setting signal is “H” level, the output of the NOR circuit 20-N is “L” (low). ) Level. The “L” level voltage is supplied to the word line rowN.
The row selection signal supplied from the output 11- (N-1) of the row selection circuit 11 is connected to the NOT circuit 20- (N-1) shown in FIG. 2, and the row selection signal is at "H" (high) level. At this time, the output of the NOR circuit 20-N becomes “L” level.
The same is repeated until the NOT circuit 20-0.

As described above, one of adjacent word lines is at “H” level (high voltage) and the other is at “L” level (low voltage).
Other than the above-described logical combinations, adjacent word lines can be set to different potentials by other combinations of “H” level and “L” level.
Contrary to the above-described example by changing the logic circuits of the mode setting circuits 12-N to 12-0, the word line rowN is set to the “H” level, the word line row (N−1) is set to the “L” level,. The word line row 1 may be set to “L” level and the word line row 0 may be set to “H” level. In this case, it can be realized by adding a NOT circuit in the subsequent stage of each logic circuit in FIG.
As a result, the potential state supplied from the word line rowN to the word line row0 is shown in FIG. The solid line indicates the “H” level voltage, and the dotted line indicates the “L” level voltage. As shown in FIG. 3, the adjacent word lines in the horizontal direction are set to different potentials. Similarly, the vertical signal lines column0 to column in the column direction are set to different potentials between adjacent column lines. be able to.

  In this manner, by supplying different voltages between even word lines (or vertical signal lines) and odd word lines (or vertical signal lines) or vice versa, a short current between wirings can be detected.

Next, short-circuit current detection between word lines (rowN to row0) will be described. FIG. 4 shows a word line driver circuit when different voltages are supplied between the word lines and a configuration diagram showing the connection state when the word lines are short-circuited by equivalent resistance.
As shown in FIG. 4, in order to measure the leakage current of the transistor and the short-circuit current between the wirings, for example, an ammeter is connected between the source and the power supply (terminal) of each of the P ₁ MOS transistor and the P ₀ MOS transistor.

The mode setting circuits 12-N to 12-0 perform the following operations during the short detection operation.
As shown in FIG. 3, for the cells (all pixels correspond to the imager), the word lines in the even columns are set to the ground (GND) V0, and the word lines in the odd columns are set to the power supply voltage V1.
Thus, different potentials of the word lines (horizontal signal lines) can be set by the selection signal without preparing a test pad (PAD).

In the word line driver circuit, when an “L” level voltage is supplied from the output of the mode setting circuit 20-1 to the commonly connected gates of the P ₁ MOS transistor and the N ₁ MOS transistor, the P ₁ MOS transistor becomes conductive. A current flows from the power source to the word line row1 through the drain and source. On the other hand, at this time, since the N ₁ MOS transistor is in an inactive state, no current flows from the drain to the GND through the source. However, a leakage current flows even when this N ₁ MOS transistor is non-conductive. In general, the leakage current tends to increase with the miniaturization of the MOS transistor.

When an “H” level voltage is supplied from the output of the mode setting circuit 20-0 to the commonly connected gates of the P ₀ MOS transistor and the N ₀ MOS transistor, the P ₀ MOS transistor is turned off. On the other hand, at this time, since the N ₀ MOS transistor becomes conductive, a current flows to the ground (V0) through the word line row0, the drain, and the source. However, a leak current is generated even when the P ₁ MOS transistor is non-conductive. That is, a leakage current flows from the power source to the ground (V0) through the drain and source of the P ₁ MOS transistor and further through the N ₁ MOS transistor.

When the word lines row1 and row0 are not in contact with each other, a short current is not generated but a leak current is generated. For example, leak currents are generated between the word line driver P ₁ MOS transistor and the N ₁ MOS transistor, and between the P ₀ MOS transistor and the N ₀ MOS transistor. If the leakage current is now I _standby ,

I _standby = I _leak (N ₀ ) + I _leak (P ₀ ) (1)
Further, depending on the voltage setting, by setting the word line row 1 to “L” level, eg, ground, and the word line row 0 to “H” level, eg, power supply voltage V 1,

I _standby = I _leak (P ₁ ) + I _leak (N ₁ ) (2)
It becomes.
Further, in the non-operating state, the gate is set in a floating state, and the power source voltage V1 is applied to the sources of the P ₁ MOS transistor and the P ₀ MOS transistor to thereby apply the P ₁ MOS transistor, the N ₁ MOS transistor, the P ₀ MOS transistor, and the N ₀ MOS transistor Each leakage current in between is expressed as I _standby .

Next, in addition to these leakage currents, a short current when the word lines row1 and row0 are in contact is described.
A current flows as a short-circuit current from the word line row 1 set to the “H” level voltage (power supply voltage V 1) to the word line row 0 set to the “L” level voltage (ground; V 0). Now, where the short resistance between the word line row1 and row0 and _{R short,} the short current _{I s} is

I _s = (V 1 −V 0) / R _short (3)
It is expressed. This R _short is determined by the contact state of adjacent word lines.
Therefore, the actually measured current I is a value obtained by adding the expression (1) (or the expression (2)) and the expression (3),

I = I _standby + I _s (4)
It becomes.
The same measurement is repeated between the word lines row 2 and row 3, the word lines row 4 and row 5,..., The word lines row (N−1) and row N, and the current is measured.

  FIG. 5 shows a graph of the result of measuring the current between adjacent word lines. The horizontal axis represents the measured current value, and the vertical axis represents the number of measurements. The measurement result is a Gaussian distribution. In general, the current when the word line is short-circuited exists at a position deviating from or away from the Gaussian distribution curve.

When a short circuit occurs between adjacent signal lines in the row (horizontal) direction, the current between the power supply voltage V1 of the power source and the ground V0 is _expressed by the short-circuit current I _short (short circuit ₎ from the standby current I standby as shown in the equation (4). The current increases by the current flowing at the location. If you set the short circuit exists if it exceeds criterion current _{I Stanby} CRI of STBY current _{I Stanby,} can short detection by measuring the standby current _{I Stanby,} can sorting defective.
As shown in FIG. 5, I _spec is set using the criteria current I _standby CRI as a selection criterion, and if it is greater than I _spec, it is determined that a short circuit has occurred between the word lines, and if it is less than I _spec , the word line By discriminating that no short circuit has occurred, it is possible to select non-defective products.

Next, a configuration and operation for detecting a short current between adjacent word lines by dividing cells connected to word lines rowN to row0 into blocks will be described. In order to simplify the explanation, an example is shown in which a cell is divided into four blocks, but the number of divisions is not limited to this. Further, when the number of divisions is increased, the number of decoding lines in the decoding unit of the mode setting circuit may be increased, and a block selection logic circuit may be configured accordingly.
The block described above may be a semiconductor memory device such as a DRAM or a non-volatile memory (including SRAM), and other examples include a CCD (Charge Coupled Device), a CMOS (Complementary Metal Oxide Semiconductor), and the like. It may be a solid-state imaging device.

First, FIG. 6 shows another embodiment relating to the mode setting circuit. The mode setting circuit includes a word line selection circuit WL and a block selection circuit BLK.
The word line selection circuit WL has the same configuration as the circuit shown in FIG. 2 and is an example in which 16 outputs 11-0 to 11-15 of the row selection circuit 11 are configured. Since this configuration and its operation have already been described, a detailed configuration and its operation are omitted here.

  The block selection circuit BLK includes a decoding unit and a block selection logic circuit. First, the decoding unit will be described. When the cell is divided into four blocks, the decode lines (231 to 234) are composed of four lines, the line 231 is the logic circuit of the block A, the line 232 is the logic circuit of the block B, and the line 233 is the logic of the block C. In the circuit, line 234 is connected to the logic circuit of block D, respectively.

Next, the circuit configuration of the block selection circuit BLK will be described.
In the block A, one input of the NOR circuit 240-0 is connected to the output of the NOT circuit 220-0 of the word line selection circuit WL, the other input is connected to the block selection line 231 and the output is the word line row0. Connected to.
One input of the NOR circuit 240-1 is connected to the output of the NOR circuit 220-1 of the word line selection circuit WL, the other input is connected to the block selection line 231 and the output is connected to the word line row1. .
One input of the NOR circuit 240-2 is connected to the NOT circuit 220-2 output of the word line selection circuit WL, the other input is connected to the block selection line 231 and the output is connected to the word line row2.
One input of the NOR circuit 240-3 is connected to the output of the NOR circuit 220-3 of the word line selection circuit WL, the other input is connected to the block selection line 231 and the output is connected to the word line row3. . The same process is repeated for block B, block C, and block D.

Next, the operation of the short detection circuit 100 when the block selection circuit 200 is used will be described with reference to FIG.
The control signal output from the row selection circuit 11 is output to the mode setting circuits 12-0 to 12-15 (12-N). Further, the mode setting signal is supplied to the word line selection circuit WL of the mode setting circuits 12-0 to 12-15 (12-N), and the block setting signal is supplied to the block selection circuit BLK.

At the output of the row selection circuit 11, data of “L” level from the 11-0 line, “H” level from the 11-1 line, “L” level from the 11-2 line, and “H” level from the 11-3 line. The case where it is output will be described. The same applies to other cases.
When the mode setting signal supplied to the word line selection circuit is at “H” level, the NOT circuit 220-0 of the block A is output from the 11-0 line of the row selection circuit 11 regardless of the level of the mode setting signal. The “L” level data is inverted and the “H” level data is output to the block selection circuit BLK.
The “H” level signal output from the 11-1 line of the row selection circuit 11 is supplied to one input of the NOR circuit 220-1, and the “H” level signal of the mode setting signal is supplied to the other input. Supplied. As a result, an “L” level signal is output from the output of the NOR circuit 220-1.
The operation of the NOT circuit 220-2 is the same as that of the NOT circuit 220-0. The “L” level signal on the line 11-2 is inverted and an “H” level signal is output from the output.
In the same manner as the NOR circuit 220-0, the NOR circuit 220-3 is also supplied with the "H" level signal and the mode setting signal "H" level signal from the line 11-3, respectively, and the output is "L". A level signal is output.

The outputs 11-4 to 11-15 of the row selection circuit 11 are also set so that the adjacent rows have different potentials for the “L” level and the “H” level for each line.
There are various combinations of voltage settings, and the present invention is not limited to setting different potentials for each line.

Next, an operation for selecting the blocks A, B, C, and D by the block selection circuit will be described.
A case will be described in which, among the lines 231 to 234 constituting the decoding unit, for example, a block selection signal of “L” level is supplied to the line 231 and “H” level is supplied to the other lines 232 to 234.
At this time, the outputs of the NOR circuits 240-4 to 240-7, 240-8 to 240-11, 240-12 to 240-15 become "L" level by the block setting signal. As a result, the signal levels of the word lines output from the blocks B, C, and D all become “L” level. That is, only the block A is activated, and the other blocks B, C, and D are deactivated.

In the selected block A, the “H” level signal output from the NOT circuit 220-0 and the “L” level signal supplied from the block setting signal are supplied to the input of the NOR circuit 240-0 and output. To "L" level signal is output to the word line row0.
The “L” level signal output from the NOR circuit 220-1 and the “L” level signal of the block setting signal are supplied to the input of the NOR circuit 240-1, and the “H” level signal is derived from the output. It is output to the word line row1.
The “H” level signal output from the NOT circuit 220-2 and the “L” level signal supplied from the block setting signal are supplied to the input of the NOR circuit 240-2, and the “L” level signal is output from the output. Is output to the word line row2.
The “L” level signal output from the NOR circuit 220-3 and the “L” level signal of the block setting signal are supplied to the input of the NOR circuit 240-3, and the “H” level signal is derived from the output, It is output to the word line row3.
In this way, the potential between adjacent word lines can be set to a different potential in the selected block A. The “H” level and the “L” level may be opposite to the above-described settings.

FIG. 7A schematically shows a state in which the block A is activated and a state in which the blocks B, C, and D are inactivated.
Figure 7 (A) shows an example of measuring the standby current _{I Stanby} A block A. A potential setting state for detecting a short circuit from word lines row 0 to row 15 is shown. A broken line indicates an “L” level, specifically a ground (V0, ground) level, and a solid line indicates an “H” level. Specifically, it indicates the power supply voltage (VI) level.
As shown in the figure, the block A has a voltage setting which is repeated between the “L” level and the “H” level for each row (word line). However, the rows of the blocks B to D are all represented by broken lines, and the voltage is at the “L” level.
That is, in the block A, adjacent word lines are set to different potentials, but the word lines in the other blocks B, C, and D are all set to the same potential of “L” level. As a result, in the block A, a short current can be generated between adjacent word lines, while in the other blocks, the word lines are all at the same potential, so even if adjacent word lines are in contact with each other. Short current does not flow.

In the potential setting state shown in FIG. 7A, short detection is performed between adjacent control lines (rows) of the word lines row0 to row15.
As described above with reference to FIG. 1, the short-circuit detection method is performed by, for example, a short current between the word lines row 0 and row 1 and between the word lines row 2 and row _{3 of} the P ₀ , N ₀ MOS transistors to P ₃ , N ₃ MOS transistors. Measured with leakage current added.
At this time, since the word lines row4 to row15 of the block B to the block D are all at the ground (V0) level, there is no potential difference between the wirings, so that no current flows due to a short circuit. However, at this time, the leakage current I _standby of the P ₄ , N _{4 to} P ₁₅ , and N ₁₅ MOS transistors flows.

  Next, the case where only the block B shown in FIG. 7B is selected and the short current between the word lines row4 to row7 of the block B is detected will be described. When the “L” level block setting signal is supplied to the line 232 and the other lines 231, 233, and 234 constituting the decoding unit in FIG. 6 are supplied, the NOR circuits 240-0 to 240-3 and 240 are supplied. The outputs of −8 to 240-11, 240-12 to 24015 all become “L” level. That is, the blocks A, C, and D are set in an inactive state, and only the block A is activated.

  In the outputs 11-4 to 11-7 of the row selection circuit 11, for example, from the output 11-4 to the "L" level, from the output 11-5 to the "H" level, from the output 11-6 to the L "level, from the output 11-7 An H "level signal is output. In this state, when the mode setting signal becomes “H” level, the output of the NOT circuit 220-4 is “H” level regardless of the mode setting signal, the output of the NOR circuit 220-5 is “L” level, and the NOT circuit 220. The output of −6 is “H” level, and the output of the NOR circuit 220-7 is “L” level.

As described above, when the block B in FIG. 7B is selected, the line 231 of the decoding unit of the block selection circuit is at the “H” level, the line 232 is at the “L” level, the line 233 is at the “H” level, the line 234 Is set to "H" level.
Accordingly, the output of the NOR circuit 240-4 is “L” level, the output of the NOR circuit 240-5 is “H” level, the output of the NOR circuit 240-6 is “L” level, and the output of the NOR circuit 240-7 is It becomes “H” level, and the voltages of these levels are supplied to the word lines row 0 to row 15, respectively.
FIG. 7B schematically shows the voltage setting state at this time. In this block B, the leakage current and the short current between the word lines are measured between the word lines row 4 to row 7. In the blocks A, C, and D, the word lines row 0 to row 3 and row 8 to row 15 are all at the same potential, so that no current flows due to a short circuit between adjacent word lines.

Similarly, the block setting signal supplied to the decoding unit of the block selection circuit shown in FIG. 6 is controlled to select block C or block D shown in FIGS. to measure the standby current _{I stanby} and short current _{I short.}

FIG. 8 shows the result when a short circuit is detected. The horizontal axis represents the current _obtained by adding the standby current I standby and the short current I _short , and the vertical axis represents the number of word lines (row 0 to row N) corresponding to the measured current value.
As a typical example, as shown in FIG. 8A, the distribution curve shows a Gaussian distribution around a certain current value. At this time, when the word lines are shorted, since short current I _short is added to the standby current I _Stanby, the measured current value is present in the larger away the current value of the distribution.
In this distribution curve, a standard (SPEC) for determining whether a product is non-defective or defective is provided at a predetermined current value. As a result of measurement, if the measured current of a certain word line or block is smaller than this standard, the product is judged as good and larger than the standard value. And defective products.

The distribution curve described above depends on variations in elements. When the element is miniaturized and, for example, the channel length of the drive transistor (P ₀ , N _{0 to} P _N , N _N MOS transistor) is shortened, the leakage current (I _standby current) increases accordingly. The distribution state at this time is shown in FIG. 8B. Since the leakage current increases, the center value of the distribution curve shifts to the larger current. At this time, it is necessary to appropriately set the reference according to the center value of the distribution curve.
If the SPEC described above is fixed, a part of the distribution curve may exceed the standard, and a non-defective product may be determined as a defective product, which may deteriorate the yield.

FIG. 8 (A), the (B), the case where the ratio of the short current and the standby current _{(I short /} I stanby) is small, a short current _{I short} is would fall within the scope of variation in standby current _{I Stanby,} short detection Becomes difficult. The value of the standby current _{I Stanby} is wafer variation, since the lot variation is large, it is necessary to set the short detectable standby current _{I Stanby} of CRI (the criterion) as appropriate.

In order to improve these, the wiring area (area where pixels or cells are arranged) is divided into 1 to M (M is a positive integer), and the data on short-circuit current between blocks is relatively compared, and the short circuit Identify the block or wiring that was used.
For simplicity, FIG. 9 shows a case where the number of divisions is M = 4 and the blocks are divided from A to D blocks. An arbitrary block of blocks A to D is selected by the block selection circuit. In the selected block A, the word lines in the block are set to “H” level and “L” level voltages, the adjacent word lines are set to different potentials, and adjacent to the leakage current of the word line driver transistor. Measure the short current between the word lines. When the current measurement in the block is completed, the block B is selected, and the leak current and the short current are measured in the same manner. This is measured for blocks C and D.
As shown in FIG. 9, for example, when a short current I _short is detected between adjacent word lines in the block C, it exists at a position away from the current measurement distribution curve in the block.
Further, the maximum value and the average value of the measured currents of the blocks A to D are obtained, and a comparison and determination is made _{based on} the difference between I _standbyMAX and I _standbyMean between the blocks, and the block in which the short current is generated and its word line are detected. For example, as shown in FIG. 9, when the difference between the block C and the other blocks A, B, and D is larger, it can be seen that a short current is generated in the block C.

As described above, a different potential can be set for each of the blocks A to D by the mode setting (mode select) circuit. In this case, the standby current of each block _to measure the _{I stanby A~I stanby} D, it is possible to perform the short-circuit detection.
The advantages of dividing into blocks are the following two.
A first advantage is that when a short circuit occurs in the block _{A, I Stanby} A, because for example, about 1/4 of the standby current _{I Stanby} of all pixels (all the word lines), the standby current of all pixels It is easier to detect a short-circuit current than to measure.
The second advantage is that it becomes easy to detect a short circuit by comparing the standby current of each block of the chip.

For _{example, I stanby A~I stanby} maximum value of D, and the mean value of the two data excluding the minimum value when the _{I stanbyMean,} can be provided criteria for selecting the difference between the maximum value _{I StanbyMAX} and _{I stanbyMean.}
I _StanbyMean, since similarly value even if the process standby current increases varied shifts, than to check for short constant value _{I Stanby} CRI, it is possible to much more efficient short detection.

  The circuit and method for detecting a short current for a word line (horizontal control line) in the row (horizontal) direction have been described so far, but the short detection of a vertical control line in the column (vertical) direction is similar to that in the row direction. Short-circuit detection can be performed by different current setting and standby current monitor by block division.

As described above, when the horizontal control line and the vertical control line are selected for each block (block) and the different power supply is set, the standby current at the time of short detection operation can be suppressed to a small level. But it can detect shorts.
Further, by dividing the chip into blocks, the standby current of each block of the chip can be compared, and it becomes easy to detect a short circuit even when the standby current lot (wafer) increases.

It is a schematic diagram of a block configuration of a short detection circuit. It is a circuit block diagram of a mode setting circuit. It is the figure which showed the electric potential setting state of the horizontal wiring on a chip | tip. It is a block diagram explaining the structure for measuring the leakage current between wiring, and a short circuit current, and its operation | movement. It is a distribution map which shows the result of having measured the short current. It is a figure which shows the circuit structure of a mode setting circuit and a block selection circuit. It is an electric potential setting diagram of wiring in a block when a chip is divided. It is a figure which shows the distribution curve of the measurement result by element dispersion | variation. It is a figure for demonstrating the operation | movement which detects the short circuit current of a block.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 ... Row selection circuit, 12-0 to 12-N ... Mode setting circuit, 100 ... Short detection circuit, 200 ... Block selection circuit, 20-0, 20-N-3, 20-N-1, 220-0, 220-2, 220-4, 220-6, 220-8, 220-20, 220-12, 220-14 ... NOT circuit, 20-1, 20-n-2, 20-N, 220 -1,220-3,220-5,220-7,220-9,220-11,220-13,220-15,240-0~240-15 ... NOR _{circuit, C} 00 _{~C NM ...} cell, _{N 0} ~N N ... N-type MOS _transistors, P 0 ~P _N ... P-type MOS transistor, row0~rowN ... row (word line (line); row line), Colum0~ColumN ... vertical signal line (column line)

Claims (12)

An active element;
A plurality of element signal lines to which the active elements are connected and arranged in one direction;
A row selection circuit that decodes element signal line selection information and arbitrarily selects a first control line from a first control line group corresponding to the element signal line;
A control signal and a mode setting signal supplied from the first control line are supplied, and a second control line is arbitrarily selected from a second control line group corresponding to the first control line group and the second control line is selected. A mode setting circuit for setting the potential level of the two control lines;
A short detection circuit, comprising: a driver circuit which is supplied with a third control signal from the mode setting circuit and sets the plurality of element signal lines at different potentials in order to generate a short current between the adjacent element signal lines. The short detection circuit according to claim 1, wherein the mode setting circuit sets one direction to a different potential at an even number and an odd number in a horizontal direction or a vertical direction. The short detection circuit according to claim 1, wherein the mode setting circuit includes a block selection circuit and is supplied with a block setting signal to divide the element signal line into a plurality of blocks. An active element;
A plurality of element signal lines to which the active elements are connected and arranged in one direction;
A row selection circuit that decodes element signal line selection information and arbitrarily selects a first control line from a first control line group corresponding to the element signal line;
A first control signal and a word line setting signal supplied from the first control line are supplied, and a second control line is arbitrarily selected from a second control line group corresponding to the first control line group. Then, the second control signal and the block setting signal output from the second control line are supplied, the second control line group is divided into a plurality of blocks, and at least one of the divided blocks is A mode setting circuit for selecting and controlling the potential of the control line in the block;
A third control signal supplied from the mode setting circuit, and a driver circuit for setting the potentials of the plurality of element signal lines to different potentials in order to generate a short current between the adjacent element signal lines. circuit. 5. The short detection circuit according to claim 4, wherein the element signal lines in the block are set to even potentials and odd odd potentials in one horizontal direction or vertical direction. The short detection circuit according to claim 4, wherein a difference between a maximum current value and an average value measured in the block is obtained, and a short current is detected from the difference current between the blocks. A pixel that converts an input optical signal into an electrical signal;
A plurality of pixel signal lines in which the pixels are connected and arranged in one direction;
A selection circuit that decodes pixel signal line selection information and generates a first control signal for arbitrarily selecting the pixel signal line;
A mode setting circuit, which is supplied with the first control signal and the mode setting signal, selects the pixel signal line and generates a second control signal for setting the potential level of the pixel signal line;
An image pickup apparatus comprising: a driver circuit that is supplied with the second control signal and sets the plurality of pixel signal lines to different potentials in order to generate a short current between the adjacent pixel signal lines. The mode setting circuit is further supplied with a pixel block setting signal, divides the plurality of pixel signal lines for each block, selects at least one of the divided blocks, and sets the potential of the pixel signal lines in the block. The imaging device according to claim 7 to be controlled. The image pickup apparatus according to claim 7, wherein the element signal lines in the pixel block are set to different potentials at even numbers and odd numbers in one horizontal direction or vertical direction. A memory cell;
A word line or a bit line connected to the memory cells and arranged in one direction;
A selection circuit that decodes address information of the word line or bit line and generates a first control signal for arbitrarily selecting the word line or bit line;
A mode setting circuit that is supplied with the first control signal and a mode setting signal, selects the word line or bit line, and generates a second control signal for setting the potential level of the word line or bit line;
A memory device comprising: a driver circuit that is supplied with the second control signal and sets the word lines or bit lines to different potentials to generate a short current between the adjacent word lines or bit lines. The mode setting circuit is further supplied with a memory cell block setting signal, divides the word line or bit line for each block, selects at least one of the divided blocks, and selects the word line or bit line in the block The memory | storage device of Claim 10. The storage device according to claim 10, wherein word lines or bit lines in the block are set to different potentials evenly and oddly in a horizontal direction or a vertical direction.

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