JP2008158779A - Information processing apparatus, ECC control apparatus, and ECC control method - Google Patents

Abstract

[PROBLEMS] To perform optimum ECC control without reducing the use efficiency and access speed of a buffer memory as much as possible.
An information processing apparatus includes a buffer memory that stores data and an ECC for correcting the data, and a cache memory that takes in the data and ECC transferred from the buffer memory and stores the data and ECC. An ECC processor 28 that corrects data using ECC when data and ECC are transferred from the buffer memory to the cache memory; a processor 12 that performs processing using the data stored in the cache memory; The ECC control device 10 is provided.
[Selection] Figure 1

Description

  The present invention relates to an information processing apparatus, an ECC control apparatus, and an ECC control method that perform ECC processing of data stored in a buffer memory.

  Currently, for example, an information processing apparatus such as an LSI (Large Scale Integration) for controlling a hard disk is provided with a buffer memory which is a DRAM (Dynamic Random Access Memory), and is used for temporarily storing data. . In this information processing apparatus, a defect in the buffer memory may occur, and a part of the buffer memory storage circuit may not function normally. As a general technique for coping with such a failure of the buffer memory, an ECC (Error Correcting Code) function for the buffer memory is provided in the hard disk control LSI.

  The buffer memory of the information processing apparatus mainly stores user data such as file data, and the user data is basically accessed in units of sectors (for example, 512 bytes). Therefore, when error correction of the maximum bit in the sector is performed, it is necessary to add ECC corresponding to the bit. By simultaneously reading the ECC when reading in units of sectors, it is possible to correct errors up to the maximum bit.

  However, in addition to user data, the buffer memory of the information processing apparatus may store system data such as firmware control code and data, and a heat run program executed at the time of inspection before shipping the information processing apparatus. In this case, the buffer memory is accessed (read / written) in short bit units (for example, 64/32/16/8 bit units). In this case, error correction using the sector-unit ECC cannot be performed.

  Considering the case of accessing the buffer memory in units of short bits, if ECC is added in units of 8-bit data, 3-bit ECC is required for 8-bit data, so the amount of ECC data jumps. Increase. Therefore, this method is not practical because the effective memory usable area decreases and the effective memory access speed also decreases.

Note that the conventional document (Patent Document 1) shows an example of an information processing apparatus that has a buffer memory and performs ECC processing.
JP-A-5-88987

  As described above, when ECC is generated in units of sectors in consideration of accessing the buffer memory in units of sectors, the use efficiency and access speed of the buffer memory can be improved, but the buffer memory is accessed in units of short bits. Error correction processing cannot be performed. On the other hand, if ECC is generated in a short bit unit in consideration of accessing the buffer memory in a short bit unit, the amount of ECC data increases, and the use efficiency and access speed of the buffer memory decrease.

  The present invention has been made to solve the above-described problems, and is an information processing apparatus, an ECC control apparatus, and an information processing apparatus capable of performing optimal ECC control without reducing the use efficiency and access speed of the buffer memory as much as possible. An object is to provide an ECC control method.

  In order to achieve the above-described object, an information processing apparatus according to the present invention includes a buffer memory that stores data and an ECC for correcting the data, and takes in the data and ECC transferred from the buffer memory. A cache memory for storing data, an ECC processing unit for correcting data using ECC when data and ECC are transferred from the buffer memory to the cache memory, and processing using data stored in the cache memory And an ECC controller having a processor.

  Further, the ECC control device of the present invention includes a buffer memory that stores data and an ECC for correcting the data, a cache memory that stores the data and ECC transferred from the buffer memory, and stores the data and ECC. An ECC processing unit that corrects data using ECC when the data and ECC are transferred from the buffer memory to the cache memory, and a processor that performs processing using the data stored in the cache memory. Features.

  The ECC control method according to the present invention is an ECC control method in an apparatus including a buffer memory, a cache memory, and a processor, and transfers data and an ECC for correcting the data from the buffer memory to the cache memory. The ECC control method includes an ECC processing step for correcting data using ECC and a data storage step for storing data corrected using ECC in a cache memory.

  According to the present invention, it is possible to provide an information processing apparatus, an ECC control apparatus, and an ECC control method capable of performing optimum ECC control without reducing the use efficiency and access speed of the buffer memory as much as possible.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the description, the same reference numerals are used for the same elements or elements having the same function, and redundant description is omitted.

  FIG. 1 is a block diagram showing an information processing apparatus 1 according to this embodiment. The information processing device 1 controls the host 3 indicating the information processing device 1 itself, a buffer memory 5 that temporarily stores data, a hard disk 7 that is a disk-shaped storage medium using magnetism, and the hard disk 7. A hard disk controller 10. The information processing apparatus 1 is, for example, a computer apparatus having the hard disk 7 as a storage medium or a recording / reproducing apparatus for recording audio / video data obtained by receiving broadcast waves on the hard disk 7.

  The buffer memory 5 is a storage medium used for temporarily storing data processed by the hard disk controller 10, and is configured by a DRAM (Dynamic Random Access Memory). As shown in FIG. 2, the buffer memory 5 has a user data area for storing user data (for example, file data and audio / video data) used by the user, and an ECC (Error Correcting) for correcting user data. Code: ECC area 1 for storing error correction system, system data area for storing system data (for example, firmware control code and data, pre-shipment heat run program, etc.), and system An ECC area 2 for storing ECC for data correction is provided.

  Here, the buffer memory 5 can arbitrarily adjust the storage capacities of the user data area, the ECC area 1, the system data area, and the ECC area 2. For example, when it is necessary to store a lot of user data, the buffer memory 5 increases the storage capacity of the user data area and decreases the storage capacity of other areas. For example, when it is necessary to store a lot of system data, the buffer memory 5 increases the storage capacity of the system data area and decreases the storage capacity of other areas. It should be noted that a plurality of ECCs can be written continuously in the ECC areas 1 and 2 of the buffer memory 5 without inserting an 8-bit empty bit.

  The hard disk controller 10 includes, as main components, a CPU (Central Processing Unit) 12 that is a processor that comprehensively controls the hard disk controller 10, a host control unit 14 that controls the exchange of commands and data with the host 3, A memory control unit 16 that controls the exchange of data and ECC with the buffer memory 5 and a disk control unit 18 that controls the writing and reading of data to and from the hard disk 7 are provided. The hard disk controller 10 corresponds to the ECC control device in the claims.

  The hard disk controller 10 includes a cache memory (SRAM: Static Random Access Memory) 20 and an ECC processing unit 28 between the CPU 12 and the memory control unit 16. Further, the hard disk controller 10 includes another cache memory (SRAM) 30 and another ECC processing unit 38 between the host control unit 14 and the memory control unit 16. The hard disk controller 10 further includes another cache memory (SRAM) 40 and another ECC processing unit 48 between the disk control unit 18 and the memory control unit 16.

  The cache memory 20 is a storage medium used for temporarily storing a part of data stored in the buffer memory 5, ECC, and the like, and is configured by an SRAM (Static Random Access Memory). The cache memory 20 includes a data storage area 22 for storing user data and system data, and an ECC storage area 24 for storing ECC for correcting user data and system data stored in the data storage area 22. Have.

  The cache memory 20 stores data and a part of ECC frequently used by the CPU 12 among the data and ECC stored in the buffer memory 5, and makes the stored data and a part of the ECC available to the CPU 12. provide. The CPU 12 can read or write the system data in the cache memory 20 in variable data units such as 64 bits, 32 bits, 16 bits, and 8 bits. On the other hand, since one line of the cache memory 20 is 256 bits between the buffer memory 5 and the cache memory 20, data and ECC are transferred in a fixed data unit of 256 bits. In addition, in order to perform error correction on 256-bit data, at least 10-bit ECC is required.

  When the data stored in the cache memory 20 is rewritten by the CPU 12, the data stored in the buffer memory 5 is not the latest data (dirty state), so the data stored in the buffer memory 5 needs to be updated. Occurs. Therefore, the latest data is transferred from the cache memory 20 to the buffer memory 5 at an appropriate timing, and the data in the buffer memory 5 is updated. Such a function of the cache memory 20 is called a copy back function or a write back function.

  The cache memory 20 holds a pointer indicating the data stored in the data storage area 22 and the address of the ECC buffer memory 5, and uses this pointer to determine a cache hit or a cache miss hit. That is, when the cache memory 20 receives a pointer designation of data to be read from the CPU 12, if the pointer is held, the data to be read exists in the cache memory 20, and therefore, the cache memory 20 performs a cache hit on the data to be read. judge. On the other hand, if the cache memory 20 does not hold the pointer, the read target data does not exist in the cache memory 20, and therefore, a cache miss hit is determined for the read target data.

  Further, the cache memory 20 has an address conversion unit 26 that converts a pointer to the address in the ECC buffer memory 5 corresponding to the data based on the pointer of the data to be read. 26 is used to determine a cache hit or a cache miss hit. That is, when the cache memory 20 receives a pointer designation of data to be read from the CPU 12, the address is converted into an ECC pointer by the address conversion unit 26, and if the ECC pointer is held, the ECC is stored in the cache memory 20. Therefore, a cache hit is determined for the ECC. On the other hand, if the cache memory 20 does not hold the ECC pointer, the ECC does not exist in the cache memory 20, and therefore a cache miss hit is determined for the ECC. The address conversion unit may use an address conversion function that can calculate an ECC pointer using a data pointer as a variable, or use an address conversion table in which an ECC pointer is associated with a data pointer. But you can.

  In addition, the cache memory 20 has an update determination function for determining whether the data read from the buffer memory 5 and the ECC have been updated. When the data and ECC stored in the cache memory 20 are updated, the data and ECC in the buffer memory 5 are not the latest, so the data and ECC in the cache memory 20 are transferred to the buffer memory 5 and the buffer is stored. It is necessary to update the data and ECC of the memory 5. The state in which the data and ECC in the cache memory 20 are not updated and the data and ECC stored in the buffer memory 5 are the latest is referred to as “clean”. On the other hand, the state in which the data and ECC in the cache memory 20 are updated and the data and ECC stored in the buffer memory 5 are not the latest is referred to as “dirty”.

  The cache memory 20 transfers the data and ECC to the buffer memory 5 after the rewriting process by the CPU 12 is performed a plurality of times. For this reason, redundancy and overhead of data transfer between the cache memory 20 and the buffer memory 5 can be reduced, and transfer efficiency can be improved. In addition, since the buffer memory 5 does not perform the reception process every time the CPU 12 performs the rewrite process, the buffer memory 5 can perform another process.

  The ECC processing unit 28 has a function of generating an ECC for correcting the transferred data when the data is transferred between the cache memory 20 and the buffer memory 5. The ECC processing unit 28 has a function of performing error correction on the transferred data using the ECC when the data is transferred between the cache memory 20 and the buffer memory 5.

  A cache memory (SRAM) 30 and an ECC processing unit 38 provided between the host control unit 14 and the memory control unit 16 perform processing similar to the cache memory 20 and the ECC processing unit 28 described above. That is, when data is transferred from the host 3 to the buffer memory 5, the ECC processing unit 38 generates an ECC for error correction of the transferred data in order to deal with a defect in the buffer memory 5, along with the data. The ECC is stored in the buffer memory 5. Note that data is transferred between the host control unit 14 and the memory control unit 16 in a fixed data unit of 512 bits, and the ECC processing unit 38 performs at least 13-bit ECC correction for error correction of 512-bit data. Generate.

  On the other hand, when data is transferred from the buffer memory 5 to the host 3, the ECC processing unit 38 reads the ECC from the buffer memory 5, and detects and corrects an error caused by a defect in the buffer memory 5 using the ECC. The cache memory 30 is a storage medium having a storage area for at least two sectors (512 bits × 2), and is used as a temporary storage area for ECC generation processing and error correction processing by the ECC processing unit 38. .

  A cache memory (SRAM) 40 and an ECC processing unit 48 provided between the disk control unit 18 and the memory control unit 16 perform processing similar to the cache memory 20 and the ECC processing unit 28 described above. That is, when data is transferred from the hard disk 7 to the buffer memory 5, the ECC processing unit 48 generates an ECC for error correction of the transferred data in order to deal with a defect in the buffer memory 5, and together with the data The ECC is stored in the buffer memory 5. Note that data is transferred between the disk control unit 18 and the memory control unit 16 in a fixed data unit of 512 bits, and the ECC processing unit 48 uses at least 13 bits of ECC to correct errors of 512 bits of data. Generate.

  On the other hand, when data is transferred from the buffer memory 5 to the hard disk 7, the ECC processing unit 48 reads the ECC from the buffer memory 5, and detects and corrects an error caused by a defect in the buffer memory 5 using the ECC. The cache memory 40 is a storage medium having a storage area for at least two sectors (512 bits × 2), and is used as a temporary storage area for ECC generation processing and error correction processing by the ECC processing unit 48. .

  FIG. 3 is a list showing the data storage status of the cache memory 20 for each case. When there is a data read or data write request from the CPU 12, the cache memory 20 performs data hit determination and also performs ECC hit determination for error correction of the data. Further, the cache memory 20 performs hit determination of data and ECC, and the data and ECC stored in the cache memory 20 are the same (clean) as or different from the data and ECC stored in the buffer memory 5. It is determined whether or not (dirty). Then, the cache memory 20 performs processing according to the data storage status.

  The processing of situation 1 to situation 7 described below is processing at the time of data read by the CPU 12.

(Situation 1)
Situation 1 is a case where the data to be read hits in the data storage area of the cache memory 20 and the ECC corresponding to the data hits in the ECC storage area in the data read by the CPU 12. FIG. 4 is a flowchart showing the processing of the hard disk controller 10 in the situation 1. In the situation 1, since the CPU 12 can read the user data or system data stored in the cache memory 20, the CPU 12 reads the user data or system data from the cache memory 20 (S401).

(Situation 2)
Situation 2 is a case in which the data to be read hits in the data storage area of the cache memory 20 in the data read by the CPU 12, but the ECC corresponding to the data hits in the ECC storage area. FIG. 4 also shows processing of the hard disk controller 10 in situation 2. In the situation 2, since the CPU 12 can read the user data or system data stored in the cache memory 20, the CPU 12 reads the user data or system data from the cache memory 20 (S401).

(Situation 3)
Situation 3 is a case where, in the data read by the CPU 12, the data to be read has been miss-hit in the data storage area of the cache memory 20, but the ECC corresponding to the data has been hit in the ECC storage area. This is a case where the data to be replaced in the memory 20 is clean. FIG. 5 is a flowchart showing the processing of the hard disk controller 10 in the situation 3.
Data to be read is transferred from the buffer memory 5 to the cache memory 20 (S501). During this data transfer, the ECC processing unit 28 detects and corrects an error in the transferred data using the ECC in the cache (S502). The CPU 12 reads user data or system data to be read from the cache memory 20 (S502).

(Situation 4)
Situation 4 is a case where, in the data read by the CPU 12, the data to be read has been mis-hit in the data storage area of the cache memory 20, but the ECC corresponding to the data has been hit in the ECC storage area. This is a case where the data to be replaced in the memory 20 is dirty. FIG. 6 is a flowchart showing the processing of the hard disk controller 10 in the situation 4.
Data to be replaced is transferred from the cache memory 20 to the buffer memory 5 (S601). The ECC processing unit 28 generates an ECC for error correction of the transferred data, and writes the generated ECC in the cache memory 20 (S602). Data to be read is transferred from the buffer memory 5 to the cache memory 20 (S603). The ECC processing unit 28 detects and corrects an error in the transferred data using the ECC of the cache memory 20 (S604). The CPU 12 reads user data or system data to be read from the cache memory 20 (S605).

(Situation 5)
Situation 5 is a case where, in the data read by the CPU 12, the read target data has a miss in the data storage area of the cache memory 20, and the ECC corresponding to that data has a miss in the ECC storage area. This is a case where the data and ECC to be replaced in the memory 20 are clean. FIG. 7 is a flowchart showing the processing of the hard disk controller 10 in the situation 5.
Data to be read and its ECC are transferred from the buffer memory 5 to the cache memory 20 (S701). The ECC processing unit 28 detects and corrects an error in the transferred data using the transferred ECC (S702). The CPU 12 reads user data or system data to be read from the cache memory 20 (S703).

(Situation 6)
Situation 6 is a case where, in the data read by the CPU 12, the read target data is mis-hit in the data storage area of the cache memory 20, and the ECC corresponding to the data is miss-hit in the ECC storage area. This is a case where the data to be replaced in the memory 20 is clean and the ECC is dirty. FIG. 8 is a flowchart showing the processing of the hard disk controller 10 in the situation 6.
The ECC to be replaced is transferred from the cache memory 20 to the buffer memory 5 (S801). Data to be read and its ECC are transferred from the buffer memory 5 to the cache memory 20 (S802). The ECC processing unit 28 detects and corrects an error in the transferred data using the transferred ECC (S803). The CPU 12 reads user data or system data to be read from the cache memory 20 (S804).

(Situation 7)
Situation 7 is a case where, in the data read by the CPU 12, the read target data has a miss in the data storage area of the cache memory 20, and the ECC corresponding to that data has a miss in the ECC storage area. This is a case where the data to be replaced in the memory 20 is dirty. FIG. 9 is a flowchart showing the processing of the hard disk controller 10 in the situation 7.
The data to be replaced is transferred from the cache memory 20 to the buffer memory 5 (S901). The ECC processing unit 28 generates an ECC for error correction of the transferred data and transfers it to the buffer memory 5 (S902). Data to be read and its ECC are transferred from the buffer memory 5 to the cache memory 20 (S903). The ECC processing unit 28 detects and corrects an error in the transferred data using the transferred ECC (S904). The CPU 12 reads user data or system data to be read from the cache memory 20 (S905).

  The processing of situation 8 to situation 14 described below is processing at the time of data writing by the CPU 12.

(Situation 8)
Situation 8 is a case where the data to be written hits in the data storage area of the cache memory 20 and the ECC corresponding to the data hits in the ECC storage area in the data write by the CPU 12. FIG. 10 is a flowchart showing the processing of the hard disk controller 10 in the situation 8. In situation 8, the CPU 12 writes the write data to the cache (S1001).

(Situation 9)
Situation 9 is a case in which the data to be written hits in the data storage area of the cache memory 20 in the data write by the CPU 12, but the ECC corresponding to the data hits in the ECC storage area. FIG. 10 also shows processing of the hard disk controller 10 in the situation 9. In situation 9, the CPU 12 writes the write data to the cache (S1001).

(Situation 10)
Situation 10 is a case where, during data write by the CPU 12, the write target data has a miss-hit in the data storage area of the cache memory 20, but the ECC corresponding to that data has hit in the ECC storage area. This is a case where the data to be replaced in the memory 20 is clean. FIG. 11 is a flowchart showing processing of the hard disk controller 10 in the situation 10.
Data to be written is transferred from the buffer memory 5 to the cache memory 20 (S1101). The ECC processing unit 28 detects and corrects an error in the transferred data using the ECC of the cache memory (S1102). Write data from the CPU 12 is written into the cache (S1103).

(Situation 11)
Situation 11 is a case where, during data write by the CPU 12, the write target data has a miss-hit in the data storage area of the cache memory 20, but the ECC corresponding to that data has hit in the ECC storage area. This is a case where the data to be replaced in the memory 20 is dirty. FIG. 12 is a flowchart showing the processing of the hard disk controller 10 in the situation 11.
Data to be replaced is transferred from the cache memory 20 to the buffer memory 5 (S1201). The ECC processing unit 28 generates an ECC for error correction of the transferred data and writes it in the cache memory 20 (S1202). Data to be written is transferred from the buffer memory 5 to the cache memory 20 (S1203). The ECC processing unit 28 detects and corrects an error in the transferred data using the ECC of the cache memory 20 (S1204). Write data from the CPU 12 is written into the cache (S1205).

(Situation 12)
Situation 12 is a case where, during data write by the CPU 12, the write target data has a mishit in the data storage area of the cache memory 20, and the ECC corresponding to the data has a mishit in the ECC storage area. This is a case where the data to be replaced in the memory 20 is clean and the ECC corresponding to the data is clean. FIG. 13 is a flowchart showing the processing of the hard disk controller 10 in the situation 12.
Data to be written and its ECC are transferred from the buffer memory 5 to the cache memory 20 (S1301). The ECC processing unit 28 detects and corrects an error in the transferred data using the transferred ECC (S1302). Write data from the CPU 12 is written to the cache (S1303).

(Situation 13)
Situation 13 is a case where, during data write by the CPU 12, the write target data has a miss in the data storage area of the cache memory 20, and the ECC corresponding to that data has a miss in the ECC storage area. This is a case where the data to be replaced in the memory 20 is clean and the ECC corresponding to the data is dirty. FIG. 14 is a flowchart showing the processing of the hard disk controller 10 in the situation 13.
The ECC to be replaced is transferred from the cache memory 20 to the buffer memory 5 (S1401). Data to be written and its ECC are transferred from the buffer memory 5 to the cache memory 20 (S1402). The ECC processing unit 28 detects and corrects an error in the transferred data using the transferred ECC (S1403). Write data from the CPU 12 is written into the cache (S1404).

(Situation 14)
The situation 14 is a case where, during data write by the CPU 12, the write target data has a miss in the data storage area of the cache memory 20, and the ECC corresponding to that data has a miss in the ECC storage area. This is a case where the data to be replaced in the memory 20 is dirty. FIG. 15 is a flowchart showing the processing of the hard disk controller 10 in the situation 14.
Data to be replaced is transferred from the cache memory 20 to the buffer memory 5 (S1501). The ECC processing unit 28 generates an ECC for error correction of the transferred data and transfers it to the buffer memory 5 (S1502). Data to be written and its ECC are transferred from the buffer memory 5 to the cache memory 20 (S1503). The ECC processing unit 28 detects and corrects an error in the transferred data using the transferred ECC (S1504). Write data from the CPU 12 is written into the cache (S1505).

  According to the hard disk controller 10 of the present embodiment, an ECC is generated in order to correct the user data and system data written in the buffer memory 5, so that bit errors in the user data and system data written in the buffer memory 5 are detected. It can be detected and corrected using ECC. Therefore, even if a defective memory cell exists in the buffer memory 5, the defect of the hard disk controller 10 caused by the defective memory cell of the buffer memory 5 is compensated by correcting the defect of the buffer memory 5 by error correction processing using ECC. The rate can be suppressed.

  Further, according to the hard disk controller 10 of the present embodiment, since the cache memory 20 and the ECC processing unit 28 are provided, optimal ECC control is performed without reducing the usage efficiency and access speed of the buffer memory 5 as much as possible. be able to. That is, since data is transmitted and received between the buffer memory 5 and the cache memory 20 in a fixed data unit of 256 bits, the ECC can be completed with a small capacity of 10 bits corresponding to 256 bits of data. Therefore, the usable area (storage area excluding ECC) of the buffer memory 5 can be increased. On the other hand, the CPU 12 can read or write the system data of the cache memory 20 in variable data units such as 64 bits, 32 bits, 16 bits, and 8 bits, so the CPU 12 reads or writes only necessary data. The access speed from the CPU 12 can be improved.

  In the present embodiment, since data is transferred from the buffer memory 5 to the cache memory 20, the CPU 12 accesses the cache memory 20 for data reading and data writing. Therefore, when data transfer is not performed between the buffer memory 5 and the cache memory 20, the buffer memory 5 can perform other processes.

  The data transfer between the host 3 and the buffer memory 5 and the data transfer between the disk controller 18 and the buffer memory 5 are the same as the data transmission / reception between the hard disk 7 and the buffer memory 5 described above. I can say that. That is, even if a defective memory cell exists in the buffer memory 5, the error rate of the hard disk controller 10 caused by the defective memory cell of the buffer memory 5 can be suppressed by correcting the error of the user data and the system data. it can. Then, the usable area of the buffer memory 5 can be increased.

It is a block diagram which shows the information processing apparatus which concerns on this embodiment. It is a figure which shows the data structure of a buffer memory. It is a list which shows the data storage situation of cache memory classified according to a case. It is a 1st flowchart which shows the process at the time of reading of CPU. It is a 2nd flowchart which shows the process at the time of reading of CPU. It is a 3rd flowchart which shows the process at the time of reading of CPU. It is a 4th flowchart which shows the process at the time of reading of CPU. It is a 5th flowchart which shows the process at the time of reading of CPU. It is a 6th flowchart which shows the process at the time of reading of CPU. It is a 1st flowchart which shows the process at the time of writing of CPU. It is a 2nd flowchart which shows the process at the time of writing of CPU. It is a 3rd flowchart which shows the process at the time of writing of CPU. It is a 4th flowchart which shows the process at the time of writing of CPU. It is a 5th flowchart which shows the process at the time of writing of CPU. It is a 6th flowchart which shows the process at the time of writing of CPU.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Information processing apparatus, 3 ... Host, 5 ... Buffer memory, 7 ... Hard disk, 10 ... Hard disk controller, 12 ... CPU, 14 ... Host control part, 16 ... Memory control part, 18 ... Disk control part, 20 ... Cache memory , 26 ... address conversion unit, 28 ... ECC processing unit, 30 ... cache memory, 38 ... ECC processing unit, 40 ... cache memory, 48 ... ECC processing unit.

Claims (11)

A buffer memory for storing data and ECC for correcting the data;
A cache memory that takes in the data and the ECC transferred from the buffer memory and stores the data and the ECC;
An ECC processing unit that corrects the data using the ECC when the data and the ECC are transferred from the buffer memory to the cache memory;
A processor that performs processing using data stored in the cache memory;
An information processing apparatus comprising an ECC control apparatus having   The information processing apparatus according to claim 1, wherein the ECC processing unit generates an ECC for correcting the data when the data is transferred from the cache memory to the buffer memory. Data transfer between the buffer memory and the cache memory is performed in fixed data units,
The information processing apparatus according to claim 1, wherein data transfer between the cache memory and the processor is performed in variable data units.   The information processing apparatus according to claim 1, wherein the cache memory has a function of determining hit of a data and determining hit of an ECC corresponding to the data.   The information processing apparatus according to claim 4, wherein the cache memory includes an address conversion unit that converts address information of data into ECC address information corresponding to the data.   The cache memory has a function of determining whether the data or the ECC stored in the cache memory is the same as the data or the ECC stored in the buffer memory. Item 4. The information processing apparatus according to Item 1.   When the data is transferred from the outside to the buffer memory, the ECC control device generates an ECC for correcting the transferred data, and transfers the generated ECC to the buffer memory. The information processing apparatus according to claim 1, further comprising a processing unit.   8. The information processing apparatus according to claim 7, wherein when the data is transferred from the buffer memory to the outside, the second ECC processing unit corrects the transferred data using the ECC. .   The information processing apparatus according to claim 1, wherein the ECC control apparatus is a hard disk controller. A buffer memory for storing data and ECC for correcting the data;
A cache memory that takes in the data and the ECC transferred from the buffer memory and stores the data and the ECC;
An ECC processing unit that corrects the data using the ECC when the data and the ECC are transferred from the buffer memory to the cache memory;
A processor that performs processing using data stored in the cache memory;
An ECC control device comprising: An ECC control method in an apparatus including a buffer memory, a cache memory, and a processor,
An ECC processing step of correcting the data using the ECC when transferring the data and ECC for correcting the data from the buffer memory to the cache memory;
A data storing step of storing the data corrected using the ECC in the cache memory;
ECC control method including:

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