JP2008158662A - Memory access trace information acquisition method, memory access trace information acquisition device, memory access trace information acquisition program, and recording medium - Google Patents

Abstract

Trace information necessary for debugging work is efficiently obtained.
By executing a program to be debugged, a memory access address acquisition unit 103 that acquires an access address accessed by a CPU 101, an address storage unit 104 that stores the acquired address, and the latest stored address and the previous address are stored. An offset value calculation unit 105 that calculates an offset value from an address, an offset value storage unit 106 that stores an offset value, and compares the latest offset value with the previous offset value to determine whether or not they match. Offset value comparison unit 107, counter 106a that counts the number of times when two offset values match, base address, offset value, and offset value that serve as an offset reference when the two offset values do not match Memory access address that outputs the number of times Composed of scan information output unit 108.
[Selection] Figure 1

Description

  The present invention relates to a memory access trace information acquisition method and a memory access trace information acquisition method for acquiring, as trace information, data indicating an access status accessed by the CPU by a program operating on a processor having a CPU and a memory. The present invention relates to a device, a memory access trace information acquisition program, and a recording medium.

  In order to be useful for checking the operation of a program in a computer system and debugging work in program development, data indicating how the computer has executed an instruction or memory access is generally acquired as trace information. However, in order to acquire all of the trace information, it is necessary to acquire it efficiently because the amount of data becomes enormous.

Conventionally, as a method for efficiently obtaining trace information, a branch trace method is known in which only a branch instruction of a program is obtained and the instruction is restored after the program is executed. Further, a technique is disclosed in which trace information of instructions is temporarily stored, a pattern of the trace information is detected, and the matched portion is replaced with other information to reduce the data amount (for example, Patent Documents 1 and 2). Furthermore, a technique for reducing the amount of data by counting the number of repetitions of a branch instruction and outputting the branch instruction and the number of repetitions is disclosed (for example, see Patent Document 3).
Japanese Patent No. 3498702 Japanese Patent No. 2702462 JP 05-012061 A

  According to such a conventional technique, although the trace information of the instruction can be efficiently acquired, it is difficult to efficiently acquire the trace information of the data, so that it is difficult to perform the debugging work.

  Further, when comparing the patterns of acquired data, there is no problem if the memory capacity is sufficient. However, if the memory capacity is limited, it is difficult to detect the pattern unless the patterns are stored efficiently.

  The present invention has been made in view of the above circumstances, and can efficiently acquire data indicating the access status to the memory as trace information necessary for debugging work, and effectively use a memory having a limited storage capacity. It is an object of the present invention to provide a memory access trace information acquisition method, a memory access trace information acquisition device, a memory access trace information acquisition program, and a recording medium that enable efficient detection of trace information patterns.

  In order to achieve the above object, a first memory access trace information acquisition method according to the present invention provides data indicating an access situation in which the CPU accesses the memory by a program operating on a processor having the CPU and the memory. For acquiring memory access trace information as a trace information, the step of storing an access address for the memory, and one or more offset values between the access address and the access address immediately before the access address A step of calculating, a determination step of determining whether or not an offset value group indicating a result of calculating one or more offset values is compared with the previous offset value group, and the offset value group Match with the previous offset value group. A counting step of counting a number of times, when said offset value group is determined not to match with the offset value group before one has a method and an output step of outputting the number of times the matching.

  By this method, data indicating the access status to the memory can be efficiently acquired as trace information necessary for debugging work, and the trace information pattern can be efficiently detected by effectively using the memory with limited storage capacity.

  In the second memory access trace information acquisition method of the present invention, in the determination step, the offset value is compared with the previous offset value to determine whether or not they match, and in the counting step When it is determined that the offset value matches the previous offset value, the number of times of matching is counted, and in the output step, the offset value is determined not to match the previous offset value In addition, the access address, the offset value, and the number of times of coincidence are output.

  By this method, it is possible to reduce the amount of trace information to be output by counting the number of times the offset values match, and it is possible to acquire more memory access situations than in the past.

  The third memory access trace information acquisition method according to the present invention includes a step of detecting an event of executing the program of the CPU, and if the event is not detected, the offset value is stored in the first buffer. And when the event is detected in the determination step, the contents of the first buffer are compared with a pattern indicating the offset value group stored in the second buffer, A step of counting the number of times of matching when it is determined in the counting step that the contents of the first buffer match the pattern, and in the output step, When it is determined that the content of one buffer does not match the pattern, the pattern and the number of times of matching are determined. To force the contents of the first buffer is set to a way that reflects the contents of the second buffer.

  By this method, it is possible to omit a range where the offset value is not constant, so that it is possible to reduce the amount of information to be output, and it is possible to acquire more memory access situations than in the past.

  Further, according to the fourth memory access trace information acquisition method of the present invention, each time the event is detected, a step of storing a base address serving as a reference of an offset value and a content of the first buffer in the determination step are as follows. A step of storing the base address in the second buffer when it is determined that the pattern matches the pattern, and the output step determining that the contents of the first buffer do not match the pattern Is a method of outputting the base address group indicating the pattern, the number of times of matching, and one or more base addresses.

  By this method, it is possible to efficiently acquire the data trace information necessary for the debugging work even when the address offset value when the event is acquired is not constant.

  The fifth memory access trace information acquisition method of the present invention includes a step of outputting a label corresponding to the pattern when it is determined in the determination step that the contents of the first buffer do not match the pattern. Comparing the pattern with a pattern that has already been output in the output step and determining whether or not they match, and determining that the pattern does not match a pattern that has already been output in the output step If it is determined that the pattern is a pattern that has already been output in the output step, the label that is the same as the pattern that has already been output. And a step of providing.

  By this method, since the same pattern can be detected only once, the amount of information to be output can be further reduced, and the data trace information necessary for debugging can be acquired efficiently.

  Further, the sixth memory access trace information acquisition method of the present invention compares the contents of the first buffer with the pattern having the maximum number of times of matching, and determines whether or not they match, When it is determined that the content of the first buffer does not match the pattern with the maximum number of matches, the step of outputting a label corresponding to the pattern; and the number of times the content of the first buffer matches A step of increasing the priority of the matched pattern when it is determined that the pattern matches the maximum pattern, and in the output step, if the content of the first buffer does not match the pattern in the determination step If determined, the label corresponding to the pattern and the number of matches are output, and the content of the first buffer is the highest priority. It is a way to reflect the lower contents of the second buffer.

  By this method, it is possible to leave a frequently used pattern, so that it is possible to efficiently acquire the memory access status even when the amount of memory for storing the pattern is small.

  The first memory access trace information acquisition apparatus according to the present invention acquires, as trace information, data indicating an access status accessed by the CPU to the memory by a program operating on a processor having the CPU and the memory. A memory access trace information acquisition device that stores an access address acquisition unit that acquires an access address for the memory of the CPU, an access address storage unit that stores the acquired access address, and the access address storage unit An offset value calculation unit that calculates one or more offset values between an access address and the previous access address; an offset value storage unit that stores an offset value group indicating a result of calculating one or more offset values; Stored in the offset value storage unit When comparing the offset value group with the previous offset value group and determining whether or not they match, and determining that the offset value group matches the previous offset value group And a counter that counts the number of times of matching, and a trace information output unit that outputs the value of the counter when it is determined that the offset value group does not match the previous offset value group. Yes.

  With this configuration, data indicating the access status to the memory can be efficiently acquired as trace information necessary for debugging work, and a trace information pattern can be efficiently detected by effectively using a memory with limited storage capacity. it can.

  In the second memory access trace information acquisition device of the present invention, the offset value comparison unit compares the offset value stored in the offset value storage unit with the previous offset value to determine whether they match. When the counter determines that the offset value matches the previous offset value, the counter counts the number of matches, and the trace information output unit determines that the offset value is the previous offset value. When it is determined that the value does not match the offset value, the access address, the offset value, and the counter value are output.

  With this configuration, it is possible to reduce the amount of trace information to be output by counting the number of times the offset values match, and it is possible to acquire more memory access situations than in the past.

  The third memory access trace information acquisition apparatus of the present invention has an event detection unit that detects an event of executing the program of the CPU, and the offset value storage unit is configured to detect the offset between the detected events. An offset value buffer for storing a value and a pattern buffer for storing a pattern indicating the offset value group, wherein the offset value comparison unit compares the offset value stored in the offset value buffer with the pattern stored in the pattern buffer. And the counter counts the number of times of matching when it is determined that the content of the offset value buffer matches the pattern, and the trace information output unit outputs the offset value. If it is determined that the buffer contents do not match the pattern To, and configured to output the pattern and the value of said counter.

  With this configuration, it is possible to omit a range in which the offset value is not constant, so that it is possible to reduce the amount of information to be output, and it is possible to acquire more memory access situations than in the past.

  A first program of the present invention is a program for causing a computer to execute each step of the memory access trace information acquisition method.

  As a result, the present invention can be realized by computer processing, and data indicating the access status to the memory can be efficiently acquired as trace information necessary for debugging work, and a memory having a limited storage capacity can be used effectively. Thus, the trace information pattern can be efficiently detected.

  The first recording medium of the present invention is a computer-readable recording medium on which the above program is recorded.

  As a result, data indicating the access status to the memory can be efficiently acquired as trace information necessary for debugging, and the trace information pattern can be efficiently detected by effectively using the memory with limited storage capacity. It becomes.

  According to the present invention, data indicating an access status to a memory can be efficiently acquired as trace information necessary for debugging work, and a trace information pattern can be efficiently detected by effectively using a memory having a limited storage capacity. A memory access trace information acquisition method, a memory access trace information acquisition device, a memory access trace information acquisition program, and a recording medium can be provided.

  Hereinafter, a plurality of embodiments of a memory access trace information acquisition method, a memory access trace information acquisition device, a memory access trace information acquisition program, and a recording medium according to the present invention will be described. Note that a memory access trace information acquisition program is recorded on the recording medium.

(First embodiment)
First, the processor according to the first embodiment of the present invention is illustrated. FIG. 1 is a block diagram showing a schematic configuration of a processor according to the present embodiment.

  1, a processor 100 includes a central processing unit (CPU) 101 that controls each unit, a memory 102 that stores a program and data, and a memory access address acquisition unit that acquires an access address accessed by the CPU 101 by executing the program. 103, an address storage unit 104 that stores the acquired address, an offset value calculation unit 105 that calculates an offset value from the latest address and the previous address stored in the address storage unit 104, and the calculated offset value An offset value storage unit 106 that stores the offset value, and an offset value comparison unit 107 that compares the latest offset value stored in the offset storage unit 106 with the previous offset value to determine whether or not they match. The latest offset value and the previous offset in the judgment result When the values match, the counter 106a that counts the number of times of matching, and the base address and offset value that serve as a reference for the offset stored in the address storage unit 104 when the latest offset value does not match the previous one The memory access address information output unit 108 outputs the offset value stored in the storage unit 106 and the count value of the counter 106a.

  The processor 100 functions as a memory access trace information acquisition device by the CPU 101 executing a memory access trace information acquisition program stored in the memory 102, and a memory access trace when executing a target program for which trace information is generated Obtain and output information.

  The target program may be described using C language. A program written in the C language is converted into an assembly language that substantially corresponds to a machine language that can be understood by the processor 100 by a C language compiler. Further, the assembly language is converted into a machine language that can be executed on the processor 100 by an assembler and a linker.

  FIG. 2 shows an example of how a part of the C language source code 10 is converted into the assembly language code 11 by the C language compiler.

  The executable statement surrounded by the broken line of the C language source code 10 shown in FIG. 2A corresponds to the portion surrounded by the broken line of the assembly language code 11 shown in FIG. Here, “PC” in the broken line of the assembly language code 11 indicates a program counter value indicating an instruction address, and “MNEMONIC” indicates a mnemonic corresponding to “PC”.

  FIG. 3 shows an example of memory access trace information when the target program of FIG. 2 is executed. The conventional memory access trace information 20 shown in FIG. 3A is a memory access as shown in FIG. 3B in which information is compressed by calculating a basic address, an offset value, and the number of repetitions of the offset value. Trace information 21 can be converted. Here, “ADRS” represents an address at which a memory access has occurred, “#” represents an offset value with respect to the previous memory access address, and “REPEAT” represents the number of repetitions of the offset value.

  Next, a memory access trace information acquisition processing method for the processor of the present embodiment configured as described above will be described. FIG. 4 is a flowchart for explaining a memory access trace information acquisition processing procedure according to this embodiment.

  In the initialization procedure of step S100, the CPU 101 sets the initial value “1” in the counter 106a and “OFF” in the end flag, and the address storage unit 104 sets the base address and comparison addresses 1 and 2, and the offset storage unit 106. Clears the comparison offset values 1 and 2, respectively.

  First, it is determined whether or not the memory access address acquisition unit 103 has acquired a memory access address (step S101). If it is determined that the memory access address has been acquired, the address storage unit 104 has an empty base address. It is determined whether or not (step S102).

  As a result of the determination in step S102, if it is determined that the base address is empty, the address acquired by the address storage unit 104 is set as the base address and the comparison address 1 (step S103, step S104), Returning to the procedure, it is determined whether or not the next memory access address has been acquired.

  On the other hand, if it is determined in step S101 that the memory access address could not be acquired, the CPU 101 sets the end flag to “ON” (step S120), and skips to step S113 described later.

  If it is determined in step S102 that the base address is not empty, the address acquired by the address storage unit 104 is set to the comparison address 2 (step S105), and the offset value calculation unit 105 compares it with the comparison address 1. An offset value of address 2 is calculated (step S106).

  Next, the address storage unit 104 sets the address of the comparison address 2 to the comparison address 1 (step S107), and the offset value storage unit 106 determines whether or not the comparison offset value 1 is empty (step S108). . As a result, if it is determined that the comparison offset value 1 is empty, the offset value storage unit 106 sets the offset value calculated in the procedure of step S106 to the comparison offset value 1 (step S109), and the procedure of step S101. Return to.

  On the other hand, if it is determined in step S108 that the comparison offset value 1 is not empty, the offset value storage unit 106 sets the offset value calculated in step S106 to the comparison offset value 2 (step S110). The value comparison unit 107 determines whether or not the comparison offset value 1 and the comparison offset value 2 are the same (step S111).

  As a result of the determination in step S111, when it is determined that the comparison offset value 1 and the comparison offset value 2 are the same, the offset value calculation unit 105 increases the value of the counter 106a by “1” (step S112), and step S101. Return to the procedure.

  On the other hand, when it is determined in the procedure of step S111 that the comparison offset value 1 and the comparison offset value 2 are not the same, the memory access address information output unit 108 outputs the base address (step S113), and the offset value comparison unit 107 It is determined whether or not the value of the counter 106a is greater than “1” (step S114). As a result, when it is determined that the counter value is greater than “1”, the memory access address information output unit 108 outputs the comparison offset value 1 and the counter value of the counter 106a, respectively (steps S115 and S116).

  If it is determined in step S114 that the counter value of the counter 106a is “1” or less, the process skips to step S117.

  In step S117, the CPU 101 determines whether or not the end flag is “ON”. If the end flag is determined to be “OFF”, the CPU 101 sets the value of the counter 106a and the comparison offset value 1 to the initial values. At the same time, the memory access address acquired by the address storage unit 104 is set as the base address (step S119), and the procedure returns to step S101 to acquire the next memory access address.

  On the other hand, if it is determined in step S117 that the end flag is “ON”, the memory access trace information acquisition process ends.

  Next, a specific example of the memory access trace information acquisition process in the present embodiment will be described with reference to FIG.

  In FIG. 3A, when the data of the address “0x10” is acquired first, the base address is empty in the procedure of step S102 in the flowchart shown in FIG. 4, so the address “0x10” is the base in the procedure of step S103. The address is set, and the comparison address 1 is set in the procedure of step 104.

  Next, when the data of the address “0x14” is acquired, in the procedure of step S102, it is determined that it is not empty because “0x10” is already set in the base address, and the acquired address “0x14” is determined in step S105. Set to comparison address 2 in the procedure.

  In step S106, the offset value of the address “0x10” stored in the comparison address 1 and the address “0x14” stored in the comparison address 2 is calculated by the offset value calculation unit 105 to obtain “# 0x4”. Then, in order to prepare for the comparison with respect to the next data, the address “0x14” stored in the comparison address 2 is set to the comparison address 1 in the subsequent step S107.

  Next, since the comparison offset value 1 is empty as a result of the determination in step S108, the offset value “# 0x4” calculated in the procedure of step S106 is set to the comparison offset value 1 in the procedure of subsequent step S109. .

  Next, when the data of the address “0x18” is acquired, the processing up to step S108 is executed as described above.

  In step S108, since “# 0x4” is stored in the comparison offset value 1, the procedure proceeds to step S110, and the offset value “# 0x4” of “0x14” and “0x18” is set in the comparison offset value 2. Further, in step S111, it is determined whether or not these two offset values are the same.

  Here, since the offset values stored in the comparison offset value 1 and the comparison offset value 2 are the same “# 0x4”, the counter value in the counter 106a is incremented by “1” and “2” in the procedure of step S112. Change to

  If the same processing is performed from the data of the next address “0x1C” to the data of address “0x2C”, the base address is “0x10”, the comparison address 1 is “0x2C”, the comparison offset value 1 is “# 0x4”, and the counter value Becomes “7”.

  Subsequently, for example, if the data of the address “0x100” is acquired, the processing up to step S108 is performed as described above.

  In step S108, since “# 0x4” is stored in the comparison offset value 1, “0x2C” and “0x100” offset values “# 0xD4” are set in the comparison offset value 2 in the processing procedure of step S110. It is determined whether or not the procedure offset values in step S111 are the same.

  Here, since the offset values stored in the comparison offset value 1 and the comparison offset value 2 are “# 0x4” and “# 0xD4”, respectively, the base address “0x10” is different in the procedure of step S113. And at the next step S114, it is determined whether or not the counter value is larger than “1”.

  At this time, since the counter value of the counter 106a is “7” and is larger than “1”, the offset value “# 0x4” stored in the comparison offset value 1 and the counter value “7” are output, The process of step S117 for determining the state of the end flag is performed.

  In the procedure of step S117, the end flag is the initial value “OFF”. Therefore, in the subsequent procedure of step S118, the counter value “7” of the counter 106a and the offset value “# 0x4” stored in the comparison offset value 1 are used. "Is cleared, the address" 0x100 "acquired in the procedure of step S119 is set as the base address, and the process returns to the procedure of step S101 to repeat the determination of whether or not the memory access address has been acquired.

  If, for example, the next address cannot be acquired in the procedure of step S101, the end flag is set to “ON” in the procedure of step S120, and then the process proceeds to the procedure of step S113 to output the base address “0x100”. To do.

  In the next step S114, since the counter value is the initial value “1”, the process jumps to step S117 to determine the end flag. As a result, since the end flag was set to “ON” in step S120, the memory access trace information acquisition process can be ended and the memory access trace information 21 as shown in FIG. 3B can be acquired. .

  As described above, according to the memory access trace information acquisition method, the memory access trace information acquisition device, the memory access trace information acquisition program, and the recording medium according to the first embodiment of the present invention, the offset values match. By counting the number of times of execution, the amount of trace information to be output can be reduced, and the memory access status required for debugging can be acquired efficiently.

(Second Embodiment)
First, a processor according to the second embodiment of the present invention will be exemplified. FIG. 5 is a block diagram illustrating a schematic configuration of a processor according to the second embodiment.

  In FIG. 5, a processor 200 stores a CPU 201 that controls each unit, a memory 202 that stores programs and data, a memory access address acquisition unit 203 that acquires a memory access address accessed by the CPU 202, and an acquired address. An address storage unit 204, an event detection unit 205 that detects an event, an offset value calculation unit 206 that calculates an offset value from the latest address stored in the address storage unit 204 and the previous address, and a calculated offset An offset value storage unit 207 for storing values, a temporary storage buffer 208 for storing offset values from detected events to events, a pattern buffer 209 for storing patterns of offset values, and an offset stored by the temporary storage buffer 208 A pattern comparison unit 210 that determines whether or not the two match with each other by comparing the offset value stored in the pattern buffer 209 with the pattern value stored in the pattern buffer 209, When the offset value and the pattern of the offset value stored in the pattern buffer 209 match, the counter 209a that counts the number of times of matching and the offset value and pattern stored in the temporary storage buffer 208 by the determination in the pattern comparison unit 210 The memory access address information output unit 211 outputs the offset value stored in the pattern buffer 209 when the pattern of the offset value stored in the buffer 209 does not match.

  The processor 200 functions as a memory access trace information acquisition device by the CPU 201 executing the trace information acquisition program stored in the memory 202, and obtains memory access trace information when executing the target program for which the trace information is generated. Obtain and output. Note that the target program of the present embodiment is the same as the target program of the first embodiment described above, and a description thereof will be omitted.

  FIG. 6 shows an example of how a part of C language source code 12 is converted into assembly language code 13 by a C language compiler.

  The executable statement surrounded by the broken line of the C language source code 12 shown in FIG. 6A corresponds to the portion surrounded by the broken line of the assembly language code 13 shown in FIG. Here, “PC” in the broken line of the assembly language code 13 indicates a program counter value indicating an instruction address, and “MNEMONIC” indicates a mnemonic corresponding to “PC”.

  FIG. 7 shows an example of memory access trace information when the target program shown in FIG. 6 is executed. The conventional memory access trace information 22 shown in FIG. 7A is a memory access as shown in FIG. 7B in which information is compressed by calculating the basic address, offset value, and number of repetitions of the offset value. Trace information 23 can be converted. Here, “LOOP” represents an event that returns to the top of the loop by branching, and “LOOP_BEGIN” and “LOOP_END” represent the start and end of the pattern, respectively.

  Next, a memory access trace information acquisition processing method for the processor of the present embodiment configured as described above will be described. FIG. 8 is a flowchart for explaining the memory access trace information acquisition processing procedure in this embodiment.

  In the initialization procedure of step S200, the CPU 201 sets the initial value “1” in the counter 209a and “OFF” in the end flag, and clears the temporary storage buffer 208 and the pattern buffer 209, respectively.

  First, in step S201, the event detection unit 205 acquires an event, and determines whether the event acquired by the pattern comparison unit 210 matches a specified event (step S202).

  If the event does not match as a result of the determination, it is determined in step S203 whether or not the memory access address acquisition unit 203 has acquired the memory access address. As a result, if it is determined that the memory access address has been acquired, the memory access address acquisition unit 203 determines whether or not the memory access address has been acquired for the first time (step S204).

  If it is determined that the acquired memory access address is the first one, the address storage unit 204 sets the memory access address to the comparison address 1 (step S205), and the memory access address information output unit 211 stores the information. In step S206, the process returns to step S201, and the event detection unit 205 acquires the next event.

  On the other hand, if it is determined that the event acquired in step S202 matches the specified event, the process skips to step S211 described later.

  If it is determined that the memory access address could not be acquired in the procedure of step S203, the CPU 201 sets the end flag to “ON” (step S220) and skips to step S211 described later.

  Furthermore, when it is determined in the procedure of step S204 that the acquired memory access address is the second or later, the address storage unit 204 sets the memory access address to the comparison address 2 (step S207).

  Subsequently, the offset calculation unit 206 calculates the offset value from the memory access addresses set in the comparison address 1 and the comparison address 2, respectively (step S208), and the temporary storage buffer 208 stores the calculation result (step S209). ).

  Then, after the memory storage address set in the comparison address 2 by the address storage unit 204 is set in the comparison address 1 (step S210), the process returns to the procedure of step S201.

  In step S <b> 211, the pattern comparison unit 210 determines whether or not the offset value pattern stored in the temporary storage buffer 208 matches the pattern stored in the pattern buffer 209.

  If the pattern matches, the CPU 201 increments the value of the counter 209a by “1” (step S212), clears the temporary storage buffer 208 (step S219), returns to the procedure of step S201, and detects an event. The next event is acquired by the unit 205.

  On the other hand, if the result of determination in step S211 is that the patterns do not match, the memory access address information output unit 211 outputs the pattern stored in the pattern buffer 209 in step S213, and in step S214, the pattern comparison unit 210 It is determined whether or not the value of the counter 209a is greater than “1”.

  As a result of the determination in step S214, if the counter value is greater than “1”, the memory access address information output unit 211 outputs the counter value (step S215), and the process proceeds to the subsequent step S216. On the other hand, if it is determined in step S214 that the counter value is “1” or less, the procedure skips to step S216.

  In step S216, the CPU 201 determines whether or not the end flag is “ON”. As a result of the determination, if it is determined that it is not “ON”, the CPU 201 sets “1” to the counter 209a to return to the initial value and reflects the contents of the temporary storage buffer 208 in the pattern buffer 209 in the following step S217. Then (step S218), the process proceeds to step S219, and the temporary storage buffer 208 is cleared.

  On the other hand, if it is determined in step S216 that the end flag is “ON”, the memory access address information output unit 211 outputs the contents of the temporary storage buffer 208 (step S221), and the memory access trace information acquisition process is performed. finish.

  In the above memory access trace information acquisition processing procedure, the contents of the pattern buffer 209 are emptied in the initialization procedure step S200. However, the detection frequency is high, or a pattern that is likely to appear first is stored. It may be left.

  In step S201, an event is acquired, but it may be replaced with a specific instruction such as a branch, an event inserted by a user, the head of a loop, or the like.

  Next, a specific example of the memory access trace information acquisition process in the present embodiment will be described with reference to FIG.

  In FIG. 7A, when the data of the address “0x10” is acquired first, it is determined as the first memory access address in the procedure of step S204, and the acquired address “0x10” is set to the comparison address 1 in the procedure of step S205. At the same time, it is output in the procedure of the next step S206.

  Next, when the data of the address “0x30” is acquired, it is determined as the second and subsequent addresses in the procedure of step S204. Therefore, the acquired address “0x30” is set as the comparison address 2 in step S207.

  In step S208, the offset value “# 0x20” of the address “0x10” stored in the comparison address 1 and the address “0x30” stored in the comparison address 2 is calculated by the offset value calculation unit 206. The offset value “# 0x20” is stored in the temporary storage buffer 208 in the procedure. Then, to prepare for comparison with the next data, the address “0x30” stored in the comparison address 2 is set to the comparison address 1 in step S210.

  Next, when the address “0x50” is acquired, the processing up to step S209 is performed as described above, and “# 0x20” and “# 0x20” are stored in the temporary storage buffer 208.

  Next, when the event “LOOP” is acquired, the result of determination in step S202 matches the specified event. Therefore, the process skips to step S211 and matches the content “0x20” stored in the temporary storage buffer 208 with the pattern. Judgment processing of whether to do is performed.

  As a result of the determination in step S211, since the pattern buffer 209 is empty, it does not match the content “0x20” stored in the temporary storage buffer 208, and the process proceeds to the process in step S213 to store the pattern stored in the pattern buffer 209. In this case, since the pattern buffer 209 is empty, nothing is output.

  Next, in step S214 for determining whether or not the value of the counter 209a exceeds “1”, since the counter value is “1”, the process skips to step S216 and determines whether or not the end flag is “ON”. judge. Then, since the end flag remains “OFF” that has been initialized, the value of the counter 209a is cleared in the procedure of step S217, and “# 0x20” stored in the temporary storage buffer 208 in the procedure of step S218. , “# 0x20” is reflected in the pattern buffer 209, and the temporary storage buffer 208 is cleared in the procedure of step S219.

  Next, when the same processing is performed on the data of the addresses “0x14”, “0x34”, “0x54” shown in FIG. 7A, the offset values “# -0x3C”, “# 0x20” are stored in the temporary storage buffer 208. "," # 0x20 "are stored, and" # 0x20 "," # 0x20 "are stored in the pattern buffer 209.

  When the same processing is performed for the next event “LOOP”, the patterns “# 0x20” and “# 0x20” are output in step S213, and the contents “# -0x3C” and “#” of the temporary storage buffer 208 are output in step S218. 0x20 "and" # 0x20 "are reflected in the pattern buffer 209.

  Subsequently, when the same processing is performed on the data of the addresses “0x18”, “0x38”, and “0x58”, the offset values “# -0x3C”, “# 0x20”, “# 0x20” are stored in the temporary storage buffer 208. Is stored, and “# -0x3C”, “# 0x20”, and “# 0x20” are stored in the pattern buffer 209.

  Next, when the process of step S211 is performed for the event “LOOP”, the patterns match, so the counter value is incremented by “1” and changed to “2” in step S212, and the temporary storage buffer in step S219. Clear 208.

  If the same processing is performed from the data of the next address “0x1C” to the event “LOOP” following the address “0x6C”, the patterns stored in the pattern buffer 209 become “# -0x3C” and “# 0x20”. The value of the counter 209a becomes “7”.

  For example, if the next address cannot be acquired, the end flag is set to “ON” in the procedure of step S220, and the process of step S211 is executed.

  At this time, since the temporary storage buffer 208 is empty, it does not match the contents of the pattern buffer 209, and the patterns “# -0x3C”, “# 0x20”, “#” stored in the pattern buffer 209 in step S213. 0x20 "is output, and it is determined in step S214 whether the value of the counter 209a is greater than" 1 ". Then, since the counter value is “7”, this is output in the procedure of step S215, and the process of the next step S216 is performed.

  In step S216, since the end flag is “ON”, the process proceeds to step S221, and the contents of the temporary storage buffer 208 are output. However, since the temporary storage buffer 208 is empty, the memory access trace information acquisition process can be completed without outputting anything, and the memory access trace information 23 as shown in FIG. 7B can be acquired.

  As described above, according to the memory access trace information acquisition method, the memory access trace information acquisition device, and the memory access trace information acquisition program according to the second embodiment of the present invention, the offset value is not constant. By omitting, it is possible to reduce the amount of information to be output and to efficiently acquire the memory access status necessary for debugging work.

(Third embodiment)
The processor according to the third embodiment of the present invention has the same configuration as that of the second embodiment shown in FIG.

  In FIG. 5, the processor 200 according to the present embodiment functions as a memory access trace information acquisition device when the CPU 201 executes a trace information acquisition program stored in the memory 202, and executes a target program that is a target for generating trace information. Acquire and output memory access trace information when Note that the target program of the present embodiment is the same as the target program of the second embodiment described above, and a description thereof will be omitted.

  FIG. 9 is an example of memory access trace information when the target program shown in FIG. 6 is executed. The conventional memory access trace information 24 shown in FIG. 7 (a) is shown in FIGS. 9 (a) and 9 (b) in which the information is compressed by calculating the basic address, offset value, and number of repetitions of the offset value. Such memory access trace information 25 can be converted. Here, “LOOP + ADRS” represents the head address of the loop.

  Next, a memory access trace information acquisition processing method for the processor of this embodiment will be described. The memory access trace information acquisition processing method in the present embodiment is a modification of the memory access trace information acquisition processing method in the second embodiment of the present invention described above. FIG. 10 is a flowchart for explaining the memory access trace information acquisition processing procedure of this embodiment.

  In FIG. 10, the memory access trace information acquisition processing method S2a of this embodiment acquires the address that is the reference for offset for the first time in the memory access trace information acquisition method S2 of the second embodiment shown in FIG. Instead of step S204 for determining whether or not the address storage unit 204 provides the procedure of step S246 for determining whether or not the base address is empty, and instead of the procedure of step S206 for outputting the first acquired address, The procedure of step S241 for setting the address acquired by the address storage unit 204 as the base address is provided.

  Further, instead of the procedure of step S219 for clearing the temporary storage buffer 208, the procedure of step S242 for storing the base address by the pattern buffer 209, the step of clearing the base address by the address storage unit, and the step of clearing the temporary storage buffer 208 by the CPU 201 The procedure of S243 is provided. Further, immediately before the procedure of Step S216 for determining whether or not the end flag is “ON”, Step S244 in which the memory access address information output unit 211 outputs the base address group stored by the pattern buffer 209 is added. Further, in place of step S221 of outputting the contents of the temporary storage buffer 208, the memory access address information output unit 211 outputs the contents of the base address in addition to the offset value stored in the temporary storage buffer 208. S245 is provided. Note that the procedure in step S244 may be replaced with the method described in the first embodiment.

  Next, a specific example of the memory access trace information acquisition process in the present embodiment will be described with reference to FIG.

  In FIG. 7A, when the data of the address “0x10” is first acquired, in step S246 for determining whether or not the base address is empty, since the base address is empty, the acquired address “0x10” is set. The comparison address 1 and the base address are set (steps S205 and S241).

  Next, when the data at the address “0x30” is acquired, “0x10” is set as the base address, so the next procedure after step S246 is step S207, and the acquired address “0x30” is set as the comparison address 2. Is done.

  In the subsequent step S208, the offset value “0x10” stored in the comparison address 1 of the address storage unit 204 and the offset value “# 0x20” of the address “0x30” stored in the comparison address 2 are obtained by the offset value calculation unit 206. Then, “0x20” stored in the comparison address 1 in the procedure of step S209 is stored in the temporary storage buffer 208. Thereafter, in preparation for comparison with the next data, the address “0x30” stored in the comparison address 2 is set to the comparison address 1 (step S210).

  Next, when the data of the address “0x50” is acquired and the processing up to step S209 is performed as described above, “# 0x20” and “# 0x20” are stored in the temporary storage buffer 208.

  Next, when the event “LOOP” is acquired in step S201, the result of determination in step S202 is the same as the specified event, so the process of step S211 is executed.

  In step S211, the contents stored in the temporary storage buffer 208 are compared with the pattern. Since the pattern buffer 209 is empty, the process proceeds to step S213, and the pattern stored in the pattern buffer 209 is output. In this case, since the pattern buffer 209 is empty, nothing is output and the following step S214 is executed.

  In step S214, since the value of the counter is “1” or less, the procedure skipping the procedure of step S244 and outputting the base address group stored in the pattern buffer 209 is executed. In this case, since the pattern buffer 209 is empty, nothing is output and the process proceeds to step S216 for determining the end flag.

  Then, since the end flag is “OFF”, “1” is set to the counter 209a to return to the initial value in step S217, and “# 0x20” and “# 0x20” stored in the temporary storage buffer 208 in step S218. "Is reflected in the pattern buffer 209, the procedure of step S242 for storing the base address by the pattern buffer 209 and the procedure of step S243 for clearing the base address and temporary storage buffer 208 are executed.

  Next, when the same processing is performed on the data of the addresses “0x14”, “0x34”, and “0x54”, the offset values “# 0x20” and “# 0x20” are stored in the temporary storage buffer 208 as “base address”. 0x14 "," # 0x20 "," # 0x20 "are stored in the pattern buffer 209, and the base address group (" 0x10 ") is stored in the pattern buffer 209.

  Subsequently, when the event “LOOP” is acquired and the determination process in step S211 is performed, the content of the temporary storage buffer 208 matches the pattern, so that the value of the counter 209a is increased by “1” to “2” in step S212. In step S242, the base address “0x14” is stored in the pattern buffer 208, and in step S243, the base address and temporary storage buffer 209 are cleared.

  If the same processing is performed from the data of the next address “0x1C” to the event “LOOP” that comes after the address “0x6C”, the contents of the pattern buffer 209 are “# 0x20”, “# 0x20”, and the value of the counter 209a is “ It becomes a state of 8 ”.

  For example, when the next address cannot be acquired, the end flag is set to “ON” in the procedure of step S220, and the process of step S211 is executed. Then, since the temporary storage buffer 208 is empty, the patterns “# 0x20” and “# 0x20” are output in step S213, and the process proceeds to step S214 in which the value of the counter 209a is determined.

  In step S214, since the value of the counter 209a is larger than “1”, the value is output in the next step S215, and the base address group (“0x10,“ 0x14 ”,...) Stored in the pattern buffer 209 in step S244. .., “0x2C”) is output, and the procedure of step S216 for determining the end flag is executed.

  In step S216, since the end flag is “ON”, the process proceeds to step S245, and the base address and the contents of the temporary storage buffer 208 are output. In this case, since the base address and the temporary storage buffer 208 are both empty, the memory access trace information acquisition process is terminated without outputting anything. Thereby, the memory access trace information 24 shown in FIG. 9A can be acquired.

  The memory access trace information 25 shown in FIG. 9B can also be obtained by replacing the procedure of step S244 for outputting the base address group stored by the pattern buffer 209 with the method of the first embodiment shown in FIG. Can be obtained.

  As described above, according to the memory access trace information acquisition method, the memory access trace information acquisition device, the memory access trace information acquisition program, and the recording medium of the third embodiment according to the present invention, an event is acquired. Even when the offset value of the address at this time is not constant, it is possible to efficiently obtain the data trace information necessary for the debugging work.

(Fourth embodiment)
The processor according to the fourth embodiment of the present invention has the same configuration as that of the second embodiment shown in FIG.

  In FIG. 5, the processor 200 according to the present embodiment functions as a memory access trace information acquisition device when the CPU 201 executes a trace information acquisition program stored in the memory 202, and executes a target program that is a target for generating trace information. Acquire and output memory access trace information when

  FIG. 12 shows an example of memory access trace information when the target program described in the C language source code 14 as shown in FIG. 11 is executed. The conventional memory access trace information 26 shown in FIG. 12A is a memory access trace obtained by compressing information as shown in FIG. 12B by calculating the basic address, pattern, and number of pattern repetitions. Information 27 can be converted. Here, “LOOP REPEAT” represents the number of times the same pattern is repeated from “LOOP_BEGIN” to “LOOP_END”.

  Next, a memory access trace information acquisition processing method for the processor of this embodiment will be described. The memory access trace information acquisition processing method in the present embodiment is a modification of the memory access trace information acquisition processing method in the second embodiment of the present invention described above, and FIG. 13 shows the memory access trace of the present embodiment. It is a flowchart for demonstrating an information acquisition process procedure.

  The memory access trace information acquisition processing procedure of this embodiment shown in FIG. 13 adds step S250 between step S211 and step 213 of the flowchart in the memory access trace information acquisition processing of the second embodiment shown in FIG. , Steps S251 to S254 are added between Step S218 and Step S219, respectively.

  Step S250 is a processing procedure in which the memory access address information output unit 211 outputs a label when it is determined in step S211 that the contents of the temporary storage buffer 208 do not match the pattern. Step S251 is temporarily stored in step S218. This is a procedure for determining whether or not the pattern comparison unit 210 has already output the same pattern when the contents of the buffer 208 are reflected in the pattern buffer 209. By adding the procedure of step S250, step S213 of the process of outputting a pattern is configured to output a pattern only when outputting a label for the first time, and does not output a pattern thereafter.

  Step S252 is a procedure in which the CPU 201 obtains the label of the pattern when the same pattern has already been output as a result of the determination in step S251, and step S253 outputs the same pattern in step S251. This is a procedure in which the CPU 201 acquires a new label when it is determined that there is no such label. Further, step S254 is a procedure in which the pattern buffer 209 stores the label acquired by the procedure of step S252 or step S253.

  Next, a specific example of the memory access trace information acquisition process in the present embodiment will be described with reference to the memory access trace information 26 shown in FIG.

  From the data at address “0x10” to the data at address “0x50” in FIG. 12A, the same processing as in the second embodiment is performed, and “# 0x20” and “# 0x20” are stored in the temporary storage buffer 208. Stored.

  Next, when the event “LOOP” is acquired and the pattern comparison unit 210 executes step S211 in which the content stored in the temporary storage buffer 208 is compared with the pattern, the pattern buffer 209 is empty. In step S250, the memory access address information output unit 211 outputs a label (if it is empty, nothing is output), and in step S213, the memory access address information output unit 211 outputs a pattern (if empty). In step S214, the pattern comparison unit 210 determines whether the value of the counter 209a is greater than “1”.

  Then, since the value of the counter 209a is “1” or less, the process skips to step S216 for determining the end flag. At this time, since the end flag is “OFF”, the CPU 201 clears the counter 209a in step S217, and the contents “# 0x20” and “# 0x20” of the temporary storage buffer 208 are reflected in the pattern buffer 209 in step S218. Thereafter, the process of step S251 is performed.

  In step S251 for determining whether or not the same pattern has already been output, since there is no match with the already output pattern, a new label “LOOP1” is acquired in the subsequent step S253, and in step S254, the pattern buffer 209 is acquired. The CPU 201 clears the temporary storage buffer 208 in the procedure of step S219.

  If the same processing is performed from the data of the next address “0x14” to the event “LOOP” that comes after the address “0x6C”, the contents of the pattern buffer 209 become “# -0x3C”, “# 0x20”, “# 0x20”. The value of the counter 209a is “7” and the label is “LOOP2”.

  Next, for example, when the data of the address “0x100” is acquired, the processing up to step S209 is executed as described above.

  When a loop from the data of the address “0x10” occurs again, the same processing as described above is performed up to the data of the address “0x50”, and “# 0xA4”, “# -0xF0”, “ # 0x20 "and" # 0x20 "are stored.

  Next, when the event “LOOP” is acquired and the determination process of step S211 is performed, the contents of the pattern buffer 208 are “LOOP2” and do not match, so the process proceeds to the process of step S250 and the memory access address information is output. The unit 211 outputs a label (nothing is output when it is empty), and further outputs patterns “# -0x3C”, “# 0x20”, “# 0x20” in step S213, and compares the patterns in the procedure of step S214. The unit 210 determines whether or not the value of the counter 209a is greater than “1”.

  Then, since the value of the counter 209a is “7” and larger than “1”, the memory access address information output unit 211 outputs this value in the procedure of step S215, and the CPU 201 determines the end flag in step S216. Perform the process.

  At this time, since the end flag is "OFF", the CPU 201 clears the counter 209a in the procedure of step S217, and the contents "# 0xA4", "# -0xF0", "# -0xF0" of the temporary storage buffer 208 in step S218. After reflecting 0x20 "and" # 0x20 "in the pattern buffer 209, the process of step S251 is executed.

  As a result of the determination process in step S251, there is no pattern that already matches the output pattern, so in the subsequent step S253, the CPU 201 obtains a new label “LOOP3”, and in step S254, the label is stored in the pattern buffer 209. In step S219, the CPU 201 clears the temporary storage buffer 208.

  When the same processing as described above is performed from the data of the next address “0x14” to the data of the address “0x54”, the contents of the temporary storage buffer 208 are “# -0x3C”, “# 0x20”, “# 0x20”, pattern The contents of the buffer 209 become “# 0xA4”, “# -0xF0”, “# 0x20”, “# 0x20”.

  Next, when the event “LOOP” is acquired and the determination process in step S211 is executed, the contents of the pattern buffer 208 are “LOOP3” and do not match. Therefore, the memory access address information output unit 211 performs the procedure in step S250. After the label “LOOP3” is output and the pattern “# 0xA4”, “# -0xF0”, “# 0x20”, “# 0x20” is output by the memory access address information output unit 211 in the subsequent step S213, the determination in step S214 Process.

  In step S214, since the value of the counter 209a is “1” or less, the process skips to step S216 for determining the end flag. Then, since the end flag is “OFF”, the CPU 201 clears the counter 209a in step S217, and the contents “# -0x3C”, “# 0x20”, “# 0x20” of the temporary storage buffer 208 are stored in the pattern buffer in step S218. After reflecting in 209, the process of step S251 is performed.

  In step S251, since there is a pattern that already matches the output pattern, the CPU 201 obtains the label “LOOP2” in the subsequent step S252, stores the label obtained by the pattern buffer 209 in step S254, and the CPU 201 obtains the label in step S219. The temporary storage buffer 208 is cleared.

  The memory access trace information 27 shown in FIG. 12B can be acquired by performing the same processing from the data of the next address “0x1C” to the event “LOOP” that comes after the address “0x6C”.

  As described above, according to the memory access trace information acquisition method, the memory access trace information acquisition device, the memory access trace information acquisition program, and the recording medium of the fourth embodiment according to the present invention, the output has already been performed. Since the pattern can be detected only once, the memory for storing the pattern can be reduced, and many patterns can be matched, making the data trace information necessary for debugging work more efficient. Can get well.

(Fifth embodiment)
The processor of the computer system according to the fifth embodiment of the present invention has the same configuration as that of the second embodiment shown in FIG.

  In FIG. 5, the processor 200 according to the present embodiment functions as a memory access trace information acquisition device when the CPU 201 executes a trace information acquisition program stored in the memory 202, and executes a target program that is a target for generating trace information. Acquire and output memory access trace information when

  In addition, the target program and the memory access trace information in this embodiment are the same as those in the second embodiment shown in FIGS.

  Next, a memory access trace information acquisition processing method for the processor of this embodiment will be described. The memory access trace information acquisition processing method in the present embodiment is a modification of the memory access trace information acquisition processing method in the second embodiment of the present invention described above. FIG. 14 is a flowchart for explaining the memory access trace information acquisition processing procedure of this embodiment.

  The memory access trace information acquisition processing procedure of this embodiment shown in FIG. 14 is provided with step S265 instead of step S211 of the flowchart in the memory access trace information acquisition processing of the second embodiment shown in FIG. Step S260 is added during step S219. Further, step S262 is added between the changed steps S265 and S213, and steps S266, S261, S263, and S264 are provided in place of step S218.

  Step S265 is a procedure in which the pattern comparison unit 210 determines whether the contents of the temporary storage buffer 208 match the pattern with the maximum value of the counter 209a. Step S260 is a step in which the contents of the temporary storage buffer 208 are counted in step S260. This is a procedure in which the CPU 201 increases the priority of the matched pattern when it is determined that the pattern matches the maximum value.

  Step S262 is a procedure in which the memory access address information output unit 211 outputs a label when it is determined in step S265 that the contents of the temporary storage buffer 208 do not match the pattern having the maximum counter value. By adding the procedure of step S262, step S213 for outputting a pattern is configured to output a pattern only when a label is output for the first time, and no pattern is output thereafter.

  Further, step S266 is a procedure in which the pattern comparison unit 210 determines whether or not the content of the temporary storage buffer 208 matches the pattern. In step S261, the content of the temporary storage buffer 208 does not match the pattern in step S263. This is a procedure for reflecting the contents of the temporary storage buffer 208 to the pattern buffer 209 having the lowest priority when it is determined.

  Further, step S263 is a procedure for the CPU 201 to acquire a label, and step S264 is a procedure for storing the acquired label by the pattern buffer 209.

  Next, a specific example of the memory access trace information acquisition process in the present embodiment will be described with reference to the memory access trace information 26 shown in FIG. Here, the pattern buffer 209 can store two patterns, and holds a counter value for each pattern.

  From the data at address “0x10” to the data at address “0x50” in FIG. 12A, the same processing as in the second embodiment is performed, and “# 0x20” and “# 0x20” are stored by the temporary storage buffer 208. Is done.

  Next, when the event “LOOP” is acquired and the process of step S265 is executed, the pattern buffer 209 is empty, so the process proceeds to step S262, and the memory access address information output unit 211 outputs a label (empty). In step S213, the memory access address information output unit 211 outputs a pattern (and outputs nothing when empty), and the pattern comparison unit 210 outputs a counter 209a in step S214. It is determined whether or not the value of is greater than “1”.

  Then, since the value of the counter 209a is “0”, the process skips to step S216 for determining the end flag. At this time, since the end flag is “OFF”, the CPU 201 clears the counter 209a in the procedure of step S217, and executes the process of step S266.

  In step S266, the contents “# 0x20” and “# 0x20” in the temporary storage buffer 208 do not match the pattern, which is reflected by the pattern buffer 1 (step S261), and the CPU 201 acquires the label “LOOP1”. (Step S263), the pattern buffer 209 stores the data (Step S264).

  When the same processing is performed from the data at the next address “0x14” to the data at address “0x54”, “# -0x3C”, “# 0x20”, “# 0x20” are stored by the pattern buffer 209.

  Next, when the event “LOOP” is acquired and the determination process of step S260 is performed, the contents of the pattern buffer 208 are “LOOP1” and do not match. Therefore, in step S262, the memory access address information output unit 211 displays this label. “LOOP1” is output, the memory access address information output unit 211 outputs the patterns “# 0x20” and “# 0x20” in step S213, and the pattern comparison unit 210 outputs the value of the counter 209a from “1” in step S214. Judge whether or not it is large.

  Then, since the value of the counter 209a is “1” or less, the process skips to step S216 and determines the end flag. At this time, since the end flag is “OFF”, the CPU 201 clears the counter 209a in step S217, and the pattern comparison unit 210 performs the contents “# -0x3C” and “# 0x20” of the temporary storage buffer 208 in the procedure of step S266. It is determined whether “# 0x20” matches the pattern.

  As a result of the determination in step S266, the patterns do not match. Therefore, the contents “# -0x3C”, “# 0x20”, “# 0x20” of the temporary storage buffer 208 are reflected in the pattern buffer 209 (step S261). The label “LOOP2” is acquired (step S263) and stored in the pattern buffer 209 (step S264).

  When the same processing as described above is performed from the data at the next address “0x18” to the data at address “0x58”, “# -0x3C”, “# 0x20”, “# 0x20” are stored by the temporary storage buffer 208. The

  Next, when the event “LOOP” is acquired and the determination process of step S265 is performed, the content of the temporary storage buffer 208 matches the pattern, so the CPU 201 increases the value of the counter 209a by “1” to “2”. (Step S212) The priority of the matched pattern buffer 2 is increased (Step S260), and the temporary storage buffer 208 is cleared (Step S219).

  If the same processing is performed from the data at the subsequent address “0x1C” to the event “LOOP” that comes after the address “0x6C”, the pattern buffer 1 is “# 0x20”, “# 0x20”, and the label of the pattern buffer 1 is “LOOP1”. The pattern buffer 2 is “# -0x3C”, “# 0x20”, “# 0x20”, the label of the pattern buffer 2 is “LOOP2”, the value of the counter 209a is “7”, and the priority of the pattern buffer 2 is It becomes high.

  Next, for example, if the data of the address “0x100” is acquired, the processing up to step S209 is performed as described above.

  When a loop occurs again from the data at address “0x10”, the same processing as described above is performed up to the data at address “0x50”, and “# 0xA4”, “# -0xF0”, “#” are stored in temporary storage buffer 208. 0x20 "and" # 0x20 "are stored.

  Next, when the event “LOOP” is acquired and the determination process of step S265 is performed, the contents of the pattern buffer 209 are not matched because the counter value is the maximum “LOOP2”. The information output unit 211 outputs the label “LOOP2”. In step S213, the memory access address information output unit 211 outputs the patterns “# -0x3C” and “# 0x20”. In step S214, the pattern comparison unit 210 outputs the counter 209a. It is determined whether or not the value of is greater than “1”.

  Then, since the value of the counter 209a is larger than “1”, this value is output in the procedure of step S215, and the process of step S216 for determining the end flag is performed. Then, since the end flag is “OFF”, the CPU 201 clears the counter 209a in the procedure of step S217, and performs the process of step S266.

  As a result of the determination in step S266, the content of the temporary storage buffer 208 does not match the pattern, so in step S261, the CPU 201 causes the content of the temporary storage buffer “# 0xA4”, “# -0xF0”, “# 0x20”, “# 0x20”. Is reflected in the pattern buffer 1 having a low priority, then the label “LOOP3” is acquired in the procedure of step S263, the label is stored in the pattern buffer in step S264, and the CPU 201 stores the temporary storage buffer 208 in step S219. clear.

  When the same processing as described above is performed from the data of the next address “0x14” to the data of the address “0x54”, the contents of the temporary storage buffer 208 are “# -0x3C”, “# 0x20”, “# 0x20”, pattern The buffer 1 becomes “# 0xA4”, “# -0xF0”, “# 0x20”, “# 0x20”, and the pattern buffer 2 becomes “# -0x3C”, “# 0x20”, “# 0x20”.

  Next, when the event “LOOP” is acquired and the determination process of step S265 is performed, the pattern buffer matches the label “LOOP2”, so the CPU 201 increments the value of the counter 209a by “1” to “2” (step In S212, the priority of the matched pattern buffer 2 is increased (Step S260), and the temporary storage buffer is cleared (Step S219).

  The memory access trace information 27 shown in FIG. 12B can be acquired by performing the same processing from the data of the next address “0x14” to the event “LOOP” that comes after the address “0x6C”.

  As described above, according to the memory access trace information acquisition method, the memory access trace information acquisition device, the memory access trace information acquisition program, and the recording medium of the fifth embodiment according to the present invention, the priority is By leaving a large pattern, it is possible to increase the frequency of matching the pattern, and it is possible to efficiently acquire data trace information necessary for debugging work.

  In this embodiment, the priority of the matched pattern is increased, but a generally known data replacement algorithm may be used.

  Further, although the initial value of the pattern buffer is set to be empty, a frequently occurring pattern may be stored as the initial value.

  A memory access trace information acquisition method, a memory access trace information acquisition device, a memory access trace information acquisition program, and a recording medium according to the present invention can efficiently acquire data indicating a memory access status as trace information necessary for debugging work. It has the effect of making it possible to efficiently detect a trace information pattern by effectively using a memory having a limited storage capacity, and is useful for a debugger of a system that supports program debugging.

1 is a block diagram showing a schematic configuration of a memory access trace information acquisition apparatus according to a first embodiment of the present invention. (A) The figure which shows a part of C language source code of the debug object program which concerns on the 1st Embodiment of this invention (b) The assembly language code into which the debug object program which concerns on the 1st Embodiment of this invention was converted Figure showing a part of (A) Diagram showing conventional memory access trace information (b) Diagram showing memory access trace information according to the first embodiment of the present invention Flowchart for explaining a memory access trace information acquisition processing procedure according to the first embodiment of the present invention The block diagram which shows schematic structure of the memory access trace information acquisition apparatus which concerns on the 2nd-5th embodiment of this invention. (A) The figure which shows a part of C language source code of the debug object program which concerns on the 2nd Embodiment of this invention (b) The assembly language code into which the debug object program which concerns on the 2nd Embodiment of this invention was converted Figure showing a part of (A) The figure which shows conventional memory access trace information (b) The figure which shows the memory access trace information based on the 2nd Embodiment of this invention The flowchart for demonstrating the acquisition processing procedure of the memory access trace information which concerns on the 2nd Embodiment of this invention. (A) Diagram showing memory access trace information according to the third embodiment of the present invention (b) Diagram showing memory access trace information according to the third embodiment of the present invention Flowchart for explaining a memory access trace information acquisition processing procedure according to the third embodiment of the present invention The figure which shows the source code of the debug object program which concerns on the 4th Embodiment of this invention (A) The figure which shows the conventional memory access trace information (b) The figure which shows the memory access trace information based on the 4th Embodiment of this invention The flowchart for demonstrating the acquisition processing procedure of the memory access trace information which concerns on the 4th Embodiment of this invention. The flowchart for demonstrating the acquisition processing procedure of the memory access trace information which concerns on the 5th Embodiment of this invention

Explanation of symbols

100, 200 processor 101, 201 CPU
102, 202 Memory 103, 203 Memory access address acquisition unit 104, 204 Address storage unit 105, 206 Offset value calculation unit 106, 207 Offset value storage unit 106a, 209a Counter 107 Offset value comparison unit 108, 211 Memory access address information output unit 208 Temporary storage buffer 209 Pattern buffer 210 Pattern comparison unit

Claims (11)

A memory access trace information acquisition method for acquiring, as trace information, data indicating an access status in which the CPU accesses the memory by a program operating on a processor having a CPU and a memory,
Storing an access address for the memory;
Calculating one or more offset values between the access address and the access address immediately before the access address;
A determination step of determining whether or not an offset value group indicating a result of calculating one or more offset values is compared with the previously calculated offset value group; and
When it is determined that the offset value group matches the previously calculated offset value group, a counting step for counting the number of times of matching,
A memory access trace information acquisition method comprising: an output step of outputting the number of times of matching when it is determined that the offset value group does not match the previously calculated offset value group. The memory access trace information acquisition method according to claim 1,
In the determination step, the offset value is compared with the previous offset value to determine whether or not they match.
In the counting step, when it is determined that the offset value matches the previous offset value, the number of times of matching is counted,
A memory access trace information acquisition method for outputting the access address, the offset value, and the number of times of matching when it is determined in the output step that the offset value does not match the previous offset value. The memory access trace information acquisition method according to claim 1,
Detecting an event of executing the program of the CPU;
Storing the offset value in a first buffer if the event is not detected; and
In the determination step, when the event is detected, the contents of the first buffer are compared with a pattern indicating the offset value group stored in the second buffer to determine whether or not they match. ,
In the counting step, when it is determined that the content of the first buffer matches the pattern, the step of counting the number of times of matching,
If it is determined in the output step that the contents of the first buffer do not match the pattern, the pattern and the number of matches are output, and the contents of the first buffer are changed to the contents of the second buffer. To obtain memory access trace information to be reflected The memory access trace information acquisition method according to claim 3, further comprising:
Each time the event is detected, storing a base address that serves as a reference for the offset value;
Storing the base address in the second buffer when the determination step determines that the content of the first buffer matches the pattern; and
If it is determined in the output step that the contents of the first buffer do not match the pattern, the pattern, the number of times of matching, and the base address group indicating one or more base addresses are output. Memory access trace information acquisition method. The memory access trace information acquisition method according to claim 3, further comprising:
When it is determined in the determination step that the contents of the first buffer do not match the pattern,
Outputting a label corresponding to the pattern;
Comparing the pattern with a pattern that has already been output in the output step and determining whether or not they match;
A step of assigning a new label to the pattern when it is determined that the pattern does not match a pattern that has already been output in the output step;
A memory access trace information acquisition method comprising: a step of assigning the same label as the pattern that has already been output when it is determined that the pattern matches a pattern that has already been output in the output step. The memory access trace information acquisition method according to claim 3,
Comparing the contents of the first buffer with the pattern with the largest number of matches and determining whether they match;
Outputting the label corresponding to the pattern when it is determined that the content of the first buffer does not match the pattern having the maximum number of matches;
Increasing the priority of the matched pattern when it is determined that the content of the first buffer matches the pattern with the largest number of matches,
In the output step, when it is determined in the determination step that the content of the first buffer does not match the pattern, the label corresponding to the pattern and the number of times of the match are output, and the content of the first buffer A memory access trace information acquisition method that reflects the contents of the second buffer with the lowest priority. A memory access trace information acquisition device for acquiring, as trace information, data indicating an access status of the CPU accessing the memory by a program operating on a processor having a CPU and a memory,
An access address acquisition unit for acquiring an access address for the memory of the CPU;
An access address storage unit for storing the acquired access address;
An offset value calculation unit that calculates one or more offset values between the access address stored in the access address storage unit and the previous access address;
An offset value storage unit that stores an offset value group indicating a result of calculating one or more of the offset values;
Comparing the offset value group stored in the offset value storage unit with the offset value group calculated before that, and determining whether or not they match,
A counter that counts the number of times of matching when it is determined that the offset value group matches the previously calculated offset value group;
A trace information output unit that outputs the value of the counter when it is determined that the offset value group does not match the previously calculated offset value group;
A memory access trace information acquisition device. The memory access trace information acquisition device according to claim 7,
The offset value comparison unit compares the offset value stored in the offset value storage unit with the previous offset value, and determines whether or not they match.
If the counter determines that the offset value matches the previous offset value, the counter counts the number of matches,
The memory access trace information acquisition device that outputs the access address, the offset value, and the counter value when the trace information output unit determines that the offset value does not match the previous offset value. The memory access trace information acquisition device according to claim 7,
An event detection unit for detecting an event of executing the program of the CPU;
The offset value storage unit includes an offset value buffer that stores the offset value between the detected events and a pattern buffer that stores a pattern indicating the offset value group,
The offset value comparison unit compares the offset value stored in the offset value buffer with the pattern stored in the pattern buffer, and determines whether or not they match.
When the counter determines that the contents of the offset value buffer match the pattern, the counter counts the number of matches,
The trace information output unit is a memory access trace information acquisition device that outputs the pattern and the value of the counter when it is determined that the content of the offset value buffer does not match the pattern.   The program for making a computer perform each step of the memory access trace information acquisition method in any one of Claim 1 thru | or 6.   The computer-readable recording medium which recorded the program of Claim 10.

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