JP2008158312A - Pitch estimator, pitch estimation method, self-correlation computing device, and self-correlation computation method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To detect a pitch period of a signal of discrete value system with less computation amount. <P>SOLUTION: A pitch estimator has a self-correlation computation unit which computes a self-correlation coefficient Corr(n, k) for a time difference k of a signal X(n) of discrete value system; and a maximum value detection means which detects, as a pitch period, a time difference which gives a maximum value from among the absolute values of a plurality of self-correlation coefficients Corr(n, k) which are different in time difference k, from the self-correlation coefficients Corr(n, k). The self-correlation computation device has a binary value encoding means which converts the signal X(n) to one bit signal X<SB>bin</SB>(n), which conforms to a value below an intermediate value in its dynamic range or to the intermediate value or a value over the intermediate value; and a computation means which computes a self-correlation value of the one bit signal X<SB>bin</SB>(n) and outputs it as a self-correlation coefficient Corr(n, k). <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a pitch estimator, a pitch estimation method, an autocorrelation calculator, and an autocorrelation calculation method, and can be applied to, for example, estimation of a pitch period of an audio signal.

[Application of voice pitch detection in packet communication]
In a method in which communication is performed in units of packets such as VoIP (Voice over IP) communication, voice information contained in the lost packet is lost at the time of packet loss, and at that time, call quality deteriorates. Become.

  In order to remedy the deterioration of the call quality due to the packet loss, in Non-Patent Document 1, the speech pitch period is obtained by calculating the autocorrelation of the speech signal of a certain interval received immediately before the packet loss, A past signal corresponding to this period is cut out and reproduced in place of the voice information of the lost packet, thereby relieving the deterioration of the call quality.

[Pitch estimation]
In general, the normalized cross-correlation coefficient Corr (n, k) of two discrete-time signals X (n) and Y (nk) is defined by equation (1).

  Here, the time signals X (n) and Y (n) in the discrete value system are sampled in unit time, and the index n represents the current time. Further, 0 ≦ k <M.

The qualitative meaning of the formula (1) will be described. When the time n is fixed, the similarity of the signal X (n−i), 0 ≦ i <N and Y (n−k−i), 0 ≦ i <N, which is composed of N samples, is calculated. The search range is 0 ≦ k <M. That is, since M normalized cross-correlation coefficients Corr (n, 0), Corr (n, 1),..., Corr (n, M−1) are obtained at the current time n, Corr (n , the absolute value of k) | Corr (n, k ) | when referred to k when the maximum value and _{k max, X (n-i} ), the highest similarity signal to 0 ≦ i <n Is Y (n−k _max −i), where 0 ≦ i <N.

In particular, when X (n) and Y (n) are the same audio signal, equation (1) becomes a normalized autocorrelation coefficient, and k _max corresponds to a pitch period. However, the minimum value of the fluctuation range of k is set to a value larger than 0, for example, a value corresponding to a fraction of a short pitch period of a female voice.

[Amount of calculation]
As mentioned in Non-Patent Document 1, the correlation calculation performed when estimating the pitch period is a dominant term of the calculation amount required for the algorithm.

  Here, first, an amount of calculation required for a general normalized cross-correlation calculation is estimated.

  As a precondition for estimating the amount of calculation when the discrete normalized cross-correlation coefficient Corr (n, k) represented by the equation (1) is calculated M times in the range of 0 ≦ k <M, in the form of a × b + c The product-sum operation that can be expressed can be calculated in one machine cycle (one clock) by hardware.

  First, the numerator of equation (1) requires N product-sum operations. Further, in the pitch search, since the calculation of equation (1) is performed for 0 ≦ k <M, NM product-sum calculations are required.

Next, a calculation amount is obtained for the square root on the left side of the denominator. Since the variable k does not appear in this term, it may be calculated once every time n is updated. If the sum of squares S _X at time n−1 is defined as shown in equation (2), the calculation shown in equation (3) is required when the time is updated from n−1 to n. Let's assume that the amount of calculation in the equation can be calculated α times by converting it to the number of product-sum operations. In Non-Patent Document 1, this calculation is omitted because it does not contribute to k. Similarly, for the square root on the right side of the denominator, the same processing as in equation (3) is required every time k is updated.

  From the above, the amount of calculation required to calculate the expression (1) M times is expressed by the expression (4) when converted by the number of product-sum operations.

NM + αM + α (4)
[Reduction of calculation amount by conventional technology]
According to Non-Patent Document 1, the normalized autocorrelation coefficient for calculating the pitch period employs equation (5) obtained by modifying equation (1).

  Here, N = 160, and 0 ≦ i <160 and 40 ≦ k ≦ 120. Also, the indices i and k are changed by one to reduce the amount of calculation.

Forty-one correlation coefficients Corr (n, k) are obtained by the correlation calculation of equation (5), and k when the absolute value is the maximum is set as a temporary k _max . Next, for k _max ± 1, correlation coefficients Corr (n, k _max −1), Corr (n, k _max ), and Corr (n, k _max +1) are obtained by incrementing one by one for i. K, which is the maximum value among the absolute values of these three correlation coefficients, is regarded as a formal k _max . Therefore, the amount of calculation at this time is as shown in equation (6). By comparing with the equation (4), it can be seen that the amount of calculation is reduced to a fraction.

N / 2 (M / 2-1) + α (M / 2 + 1) + α + 3N + 3α
= N (M / 4 + 7/2) + α (M / 2 + 5) (6)
In Non-Patent Document 1, N = 160 and M = 80. Further, α depends on a numerical format to be used (fixed point or floating point, operation word length) and operation hardware. When the values of N and M are substituted into equation (6), the amount of calculation required for pitch estimation in Non-Patent Document 1 is 3760 + 45α.
TTC JT-G711, Appendix 1 High Quality Low Complexity Algorithm for Packet Loss Compensation for Standard JT-G711

  The sound signal pitch detection using the correlation calculation of equation (5) according to Non-Patent Document 1 is an effective method when there is a need to calculate equation (5) as mathematically as possible and in a short time.

  However, from an application point of view, there is a demand for obtaining a correlation coefficient using a small-scale computing unit in a short time as much as possible, rather than calculating the correlation coefficient mathematically accurately. Many.

  In particular, such a request tends to be strong in a VoIP gateway apparatus installed in a communication network and accommodating a large number of voice channels. The reason is that the packet loss compensation specified in Non-Patent Document 1 is surely effective in a communication network with poor communication quality and a large packet loss rate, and satisfies the cost / performance ratio of the function. On the other hand, in communication networks with good call quality and a small packet loss rate, the packet loss compensation function rarely operates, but it occurs due to a failure of a relay router in the communication network. If the performance is sufficient to enable simultaneous packet loss compensation for all channels at the same time in preparation for a momentary interruption of all the accommodated voice channels, the cost / performance value of the relevant function at this time will be significantly degraded. Will be. Therefore, there is a very strong demand to obtain the correlation coefficient using a small-scale computing unit in a short time as much as possible, rather than calculating the correlation coefficient mathematically accurately. is there.

  In the speech signal pitch estimator using the autocorrelation calculation of equation (5) according to Non-Patent Document 1, the calculation accuracy may become excessive quality, and the calculation amount is reduced to about a fraction of at most. In addition, there is a risk of missing the true voice pitch period because the correlation operation is thinned out and executed to reduce this operation, and multiplication, division, and square root operations are still required, reducing the hardware scale There is a problem that it does not contribute at all.

  The present invention has been made in view of the above points, and to a pitch estimator and an autocorrelation calculator capable of calculating a desired value with a small amount of calculation, and to such a pitch estimator and autocorrelation calculator. It is intended to provide an applicable pitch estimation method and autocorrelation calculation method.

The first aspect of the present invention uses a predetermined section of the discrete value system signal X (n) (the number of samples in this section is N) as a reference signal, and from this, the self-phase relationship with the same signal in the predetermined section N in the past by time k In the autocorrelation computing unit for calculating the number Corr (n, k), (1) a 1-bit signal corresponding to whether the discrete time signal X (n) is less than an intermediate value, an intermediate value, or an intermediate value of the dynamic range Binary encoding means for converting to X _bin (n), and (2) an operation according to the equation (A) based on the 1-bit signal X _bin (n) from the binary encoding means, and the operation result Is calculated as the autocorrelation coefficient Corr (n, k).

  However, a symbol in which + is circled represents an exclusive OR operation.

The second aspect of the present invention uses a predetermined section of the discrete value system signal X (n) (the number of samples in this section is N) as a reference signal, and from this, the self-phase relationship with the same signal in the predetermined section N in the past by time k In the autocorrelation calculation method for calculating the number Corr (n, k), (0) binary encoding means and calculation means are provided. (1) The binary encoding means includes a discrete time signal X (n). Is converted into a 1-bit signal X _bin (n) corresponding to whether the dynamic range is less than the intermediate value, the intermediate value, or the intermediate value, and (2) the arithmetic means outputs one bit from the binary encoding means. Based on the signal X _bin (n), the calculation according to the equation (B) is executed, and the calculation result is output as the autocorrelation coefficient Corr (n, k).

  However, a symbol in which + is circled represents an exclusive OR operation.

  According to a third aspect of the present invention, in a pitch estimator for detecting a pitch period of a discrete value system signal X (n), (1) an autocorrelation coefficient Corr (n, k) and (2) giving the maximum absolute value of the autocorrelation coefficients Corr (n, k) having different time differences k from the autocorrelation calculator. A maximum value detecting means for detecting a time difference as a pitch period, and (1) the first invention according to the present invention is applied as the autocorrelation calculator.

  According to a fourth aspect of the present invention, there is provided a pitch estimation method for detecting a pitch period of a discrete value system signal X (n), comprising: (0) an autocorrelation calculator and maximum value detection means; The calculator calculates an autocorrelation coefficient Corr (n, k) with respect to the time difference k of the discrete value system signal X (n), and (2) the maximum value detecting means outputs the time difference k from the autocorrelation calculator. A time difference giving the maximum absolute value is detected as a pitch period from a plurality of autocorrelation coefficients Corr (n, k) having different values. (1) The autocorrelation calculator The method of the third aspect of the present invention is applied.

  According to the pitch estimator and the pitch estimation method, the autocorrelation calculator and the autocorrelation calculation method of the present invention, a desired value can be calculated with a small amount of calculation.

(A) Main embodiment
Hereinafter, an embodiment in which a pitch estimator, a pitch estimation method, an autocorrelation calculator and an autocorrelation calculation method according to the present invention are applied to pitch estimation of an audio signal will be described with reference to the drawings.

(A-1) Technical idea in the embodiment In this embodiment, when estimating the pitch of the audio signal, the audio signal is encoded into binary values of +1 and −1, thereby reducing the calculation amount and the hardware scale required for the autocorrelation calculation. It is intended to greatly reduce.

[Normalized autocorrelation algorithm for binary signal]
First, a normalized autocorrelation calculation algorithm for signals binarized to ± 1 will be described.

In general, the normalized autocorrelation coefficient Corr (n, k) of the discrete-time signal X (n) is defined by equation (7).

  Here, d ≦ k ≦ d + M. In general, the numerical format of the signal X (n) is a floating point or a fixed point composed of a plurality of bits.

Next, a signal obtained by encoding the signal X (n) into a binary value of ± 1 is expressed as X _sgn (n) and is defined as shown in Equation (8).

Here, when X (n) = 0 immediately after the start of the operation, since X (n−1) and X _sgn (n−1) do not exist yet, the value of X _sgn (n) is +1. Either −1 may be used.

The normalized autocorrelation coefficient Corr _sgn (n, k) of the binarized signal X _sgn (n) can be expressed by equation (9). In the formula (9), d ≦ k ≦ d + M.

As shown in the equation (8), X _sgn (n) is a binary value of ± 1, but it is treated as 1-bit binary data on the actual implementation (product). According to the general definition of bits, the numerical value +1 is made to correspond to the binary number “0”, and the numerical value −1 is made to correspond to the binary number “1”. FIG. 2 shows the binary representation of the binary signal X _sgn (n) as X _bin (n) and shows the correspondence.

Next, the multiplication X _sgn (n−i) X _sgn (n−k−i) in the equation (9) will be considered using the correspondence shown in FIG. There are only four such multiplications, and the correspondence with binary numbers at this time is as shown in FIG. In FIG. 3, a symbol in which + is surrounded by a white circle represents an exclusive OR. In the specification, such a symbol cannot be used. Therefore, in the specification, “∧” is used as an exclusive OR.

As is apparent from FIG. 3, the multiplication of the signal binarized to ± 1 corresponds to an exclusive OR in the binary number. _{Thus, X bin (n-i)} ∧X bin sum of (n-k-i) from i = 0 for up to _{N-1 ΣX bin (n-} i) ∧X bin (n-k-i) is , ΣX _sgn (n−i) X _sgn (n−k−i) (the sum is from i = 0 to N−1), X _sgn (n−i) X _sgn (n−k−i) is −1 Will be expressed. Conversely, the number of X _sgn (n−i) X _sgn (n−k−i) that is 1 is N−ΣX _bin (n−i) ∧X _bin (n−k−i). Therefore, equation (10) is established. Here, when the normalized autocorrelation coefficient Corr _sgn (n, k) is expressed using the binary notation X _bin (n), equation (11) is obtained. In equation (11), 1 / N, which is a normalization process, is a mere constant and is not worth computing in application, so equation (11) is transformed into equation (12).

(A-2) Pitch Estimator of Embodiment FIG. 1 is a block diagram showing the overall configuration of the pitch estimator of the embodiment. The pitch estimator 100 according to the embodiment calculates an autocorrelation coefficient of an input audio signal according to the equation (12) and estimates a pitch period.

  In FIG. 1, the pitch estimator 100 according to the embodiment includes a sign bit extractor 101, shift registers 102 and 103, an exclusive OR gate group 104, an adder 105, a subtractor 106, and a maximum value detector 107.

  Here, a component part including the sign bit extractor 101, the shift registers 102 and 103, the exclusive OR gate group 104, the adder 105, and the subtractor 106 constitutes an autocorrelation calculator.

A discrete time signal X (n) is input to the sign bit extractor 101, and the sign bit extractor 101 is in accordance with the expression (13) according to the positive value, the negative value, and 0 of the input signal X (n). A 1-bit signal X _bin (n) is output. The addition of the upper bar in the equation (13) represents the negation of the assigned bit value, that is, the bit inversion of the assigned bit value. In this specification, bit inversion is represented by adding “/” in front of a sign representing a value to be inverted.

  When the discrete time signal to be processed is a signal having a range of 0 and a positive value, the median of the dynamic range is subtracted from the processing target signal to obtain a positive and negative discrete time signal X ( n) and input to the sign bit extractor 101.

  FIG. 4 shows a specific configuration example of the sign bit extractor 101 when the numerical format of the discrete time signal X (n) is 2's complement.

  In FIG. 4, the sign bit extractor 101 includes a NOR gate 201, a 2-1 selector 202, a NOT gate 203, and a register 204.

  Since the numerical format of the input signal X (n) is 2's complement, the MSB bit is a sign bit. The sign bit is 0 when 0 ≦ X (n) and 1 when X (n) <0. When the input signal X (n) = 0, all the bits of the input signal X (n) are 0.

  All bits of the input signal X (n) are input to the NOR gate 201. The output of the NOR gate 201 is 1 only when X (n) = 0, and 0 otherwise, and this output signal is The signal is supplied to the selection control terminal of the 2-1 selector 202.

The MSB bit, which is the sign bit of the input signal X (n), is input to one input terminal of the 2-1 selector 202, and the output from the sign bit extractor 101 is input to the other input terminal of the 2-1 selector 202. signal _X signal before one unit time of the _{bin (n) X bin (n} -1) and the bit inversion _{/ X} bin (n-1) is input. 2-1 selector 202, in response to the output signal of the NOR gate 201, select when the input signal X (n) is 0 only _{/ X bin (n-1)} , the output of the 2-1 selector 202 _{X bin} ( n), otherwise, the sign bit of the input signal X (n) is selected and appears as X _bin (n) in the output of the selector 202.

The register 204 is a register for storing the output signal Xbin (n) of the 2-1 selector 202, and the stored value is updated in synchronization with the sampling rate of the input signal X (n). Therefore, the output of the register 204 is X _bin (n−1) which is a value one unit time before the output signal X _bin (n).

The output signal X _bin (n−1) from the register 204 is input to the NOT gate 203, and the NOT gate 203 bit-inverts this signal X _bin (n−1) to / X _bin (n−1) as 2- 1 is given to the selector 202.

The configuration example of the code bit extractor 101 shown in FIG. 4 is merely an example for realizing the above-described equation (13). For example, when it is desirable to update the output signal X _bin (n) from the sign bit extractor 101 in synchronization with the sampling rate, the output of the register 204 is used as the output signal Xbin (n) from the sign bit extractor 101. It is also good. Even when the numerical format is not 2's complement, the sign bit extractor may be designed in accordance with the numerical format so as to satisfy the expression (13).

  The two shift registers 102 and 103 and the exclusive OR gate group 104 in FIG. 1 perform the exclusive OR operation shown in the equation (14), which is the element operation of the above equation (12), with respect to i. It is executed in one machine cycle in parallel in the range of ≦ i <N, and in M + 1 machine cycles in the range of d ≦ k ≦ d + M for k.

_{X bin (n-i) ∧X} bin (n-k-i) ... (14)
The shift register 102 forms the element X _bin (n−i) on the left side of the equation (14) as much as necessary for the summation of the equation (12), and the shift register 103 has the right side of the equation (14). Elements X _bin (n−k−i) are formed as much as necessary for the summation of equation (12), and the exclusive OR gate group 104 has N exclusive gates related to the summation of equation (12). A value of logical sum is formed.

  FIG. 5 is a block diagram illustrating a specific configuration example of the shift registers 102 and 103 and the exclusive OR gate group 104.

As will be described below, in the configuration example of FIG. 5, k is changed to d while decrementing with d + M as an initial value, and this should be noted for understanding the operation. Further, in FIG. 5, in order to simplify the notation, in the output from the exclusive OR gate group 104, the place to be described as X _bin (n) is simply described as X (n).

  The shift register 102 shown in FIG. 5 is an N-bit shift register having a serial input parallel output function. The shift register 102 includes a serial input terminal SI, a shift enable input terminal SE, a clock input terminal CK, and a parallel output terminal (a storage unit corresponding to the parallel output terminal is appropriately referred to as a register) Qx (0) to Qx (N -1). In the following description, signals related to the input / output terminals are also described using the same reference numerals as the input / output terminals.

When the shift enable signal SE is active, the bit information of the register Qx (N-2) is shifted to the register Qx (N-1) in synchronization with the clock signal CK synchronized with the sampling rate, and the register Qx (N-1 -3) is shifted to the register Qx (N-2), and similarly, the bit information of the register Qx (0) is shifted to the register Qx (1), and the sign bit extractor 101 shown in FIG. The output signal X _bin (n) is stored in the register Qx (0) via the serial input SI. Accordingly, at time n, the output terminals Qx (0) to Qx (N−1) of the shift register 102 have N bits from the signals X _bin (n) to X _bin (n− (N−1)). Until the next input X _bin (n + 1) is input, while maintaining this output state, these N bits X _bin (n) to X _bin (n− (N−1)) are exclusive. To the logical OR gate group 104.

  The signal at the output terminal Qx (d−1) of the shift register 102 is also supplied to the shift register 103.

  The shift register 103 shown in FIG. 5 is an N + M-bit shift register having a serial input parallel output function, a parallel input loading function, and a rotate shift function (cyclic shift function).

  The shift register 103 holds 1-bit information output from the shift register 102 after being delayed by an arbitrary sampling period, is bit-shifted in time series in the sampling period, and within one sampling period, When 1-bit information that has been rotated by a predetermined number of times and is output from the shift register 102 after being delayed by an arbitrary sampling period is shifted by 1 bit from the previous input. It has a loading function that can.

  The shift register 103 includes a serial input terminal SI, a shift enable input terminal SE, a load enable input terminal LE, a clock input terminal CK, parallel input terminals Dk (0) to Dk (N + M−1), and a parallel output terminal Qk (0 ) To Qk (N + M-1).

  The N bits of the parallel output terminals (registers) Qk (M) to Qk (N + M−1) are connected to the exclusive OR gate group 104, and the serial output terminal SI has a register output Qk ( N + M-1) is input.

  The value of the parallel input terminal Qx (d−1) of the shift register 102 is input to the parallel input terminal Dk (0), and the value of the parallel output terminal Qk (M) of the shift register 103 is input to the parallel input terminal Dk (1). A value is input,..., The value of the parallel output terminal Qk ((2M−3) mod (N + M) of the shift register 103 is input to the parallel input terminal Dk (M−2), and the parallel input terminal Dk (M− 1) is input with the value of the parallel output terminal Qk ((2M−2) mod (N + M) of the shift register 103, and the parallel input terminal Dk (M) is connected with the parallel output terminal Qk ((2M −1 mod (N + M)) is input, and the parallel output terminal Qk ((2M) m of the shift register 103 is connected to the parallel input terminal Dk (M + 1). d (N + M)) is inputted, and the parallel input terminal Dk (N + M-2) is inputted with the value of the parallel output terminal Qk (M-3) of the shift register 103, and the parallel input terminal Dk (N + M). -1) is inputted with the value of the parallel output terminal Qk (M-2) of the shift register 103.

  Here, s mod t represents the remainder of s when t is modulo. For example, 9 mod 8 = 1. When the feedback path from the parallel output terminal to the parallel input terminal of the shift register 103 is expressed in general using this mod, the parallel output terminal Q ((x + M−1) is connected to the parallel input terminal D (x). The value of mod (N + M) is input. However, x ≠ 0. The reason for connecting the shift register 103 as described above will be described later.

  When the load enable signal LE of the shift register 103 is active, the bit information of the parallel input terminals Dk (0) to Dk (N + M−1) is synchronized with the clock signal CK and the parallel output terminals Qk (0) to Qk. (N + M-1). On the other hand, when the shift enable signal SE of the shift register 103 is active, the values of the respective registers Qk (0) to Qk (N + M−2) are respectively synchronized with the clock signal CK. Shifted from (1) to Q (N + M-1). However, the value of the register Qk (N + M−1) at the final stage is rotated to the register Q (0) via the serial input terminal SI. Note that the load enable signal LE and the shift enable signal SE are never active at the same time.

At time n, the load enable signal LE of the shift register 103 is activated, and X _bin (nd), which is the data of the register Qx (d−1) of the shift register 102, is converted into the parallel input terminal Dk of the shift register 103. Load to register Qk (0) via (0). Next, the load enable signal LE of the shift register 103 is made inactive, the shift enable signal SE is made active, and is shifted about M times in synchronization with the clock signal CK. This shift operation must be completed before the next sampled data X _bin (n + 1−d) is input from the output Qx (d−1) of the shift register 102. Therefore, when the frequency of the clock signal CK of the shift register 103 is set to f _ck and the sampling frequency of the signal X _bin (n) is set to f _s , the relationship expressed by the equation (15) must be established. By doing so, it is possible to perform the calculation for each element of the equation (14) in M + 1 machine cycles for 0 ≦ i ≦ N−1 and d + M ≧ k ≧ d within one sampling period.

f _ck ≧ (M + 1) · f _s (15)
Note that when the shift register 103 is shifted by about M bits, the signal X _bin (nd) has moved to the register Qk (M). The bit information needs to be loaded into the register Qk (1) when the next sampled data X _bin (n + 1−d) arrives. This is the reason why the parallel output of the shift register 103 is twisted and connected to its own parallel input as described above.

  By the way, since the N bits from the parallel output terminals Qk (M) to Q (N + M−1) of the shift register 103 are connected to the exclusive OR gate group 104 as described above, when the shift register 103 is loaded. In the equation (12), this corresponds to k = d + M. Next, every time the shift register 103 performs bit shift, k = d + M, d + M−1,. ) The parallel logic operation for 0 ≦ i ≦ N−1 in the equation is executed a total of M + 1 times.

  The exclusive OR gate group 104 shown in FIG. 5 is composed of N exclusive OR gates, and receives N-bit signals output from the two shift registers 102 and 103, respectively. An exclusive OR operation for 0 ≦ i ≦ N−1 is performed in parallel, and N-bit operation result information is supplied to the adder 105 in FIG.

The adder 105 calculates the number of bits whose logical value in the N-bit information output from the exclusive OR gate group 104 is 1 as an unsigned integer, doubles the calculation result, By assigning a sign bit to make a signed integer, the value of the second term on the right side of the above-described equation (12) as shown in equation (16) is calculated. The calculation result by the adder 105 is provided to the subtractor 106.

FIG. 6 is a block diagram illustrating a specific configuration example of the adder 105. In FIG. 6, the adder 105 includes a first stage to an r-th stage unsigned integer adder and an MSB / LSB adding unit. Here, r = F (log ₂ N), the function F (x) is a sailing function, and represents the smallest integer not less than x.

  First, in the first stage, two pairs of N-bit signals are taken, input to an unsigned integer adder, and added. In FIG. 6, N is drawn as an even number, but in the case of an odd number, the remaining 1 bit after pairing is input to the next second stage. This difference in configuration due to odd / even is the same in the second and subsequent stages. Note that the number of unsigned integer adders in the first stage is N / 2 when N is an even number, and (N-1) / 2 when N is an odd number.

  The addition results of the first stage are respectively input to the unsigned integer adder of the second stage, and two pairs of additions are executed as in the first stage. Thereafter, such a process is repeatedly executed up to one r-th unsigned integer adder belonging to the stage.

Since the output of the unsigned integer adder of the r-th stage as the final stage is half of the value shown in the equation (16), and the maximum value of this value is N, this is the number of unsigned integer bits R Is converted to R = G (log ₂ N) +1. Here, G (x) is a floor function and represents the maximum integer that does not exceed x.

  By adding an LSB of “0” to the R-bit output of the r-th stage unsigned integer adder, the R-bit output of the r-th stage unsigned integer adder is doubled, and the r-th stage An MSB consisting of “0” is added to the R bit output of the unsigned integer adder of the stage to convert it to a signed integer.

  Incidentally, it is assumed that the operation of the adder 105 shown in FIG. 6 can be performed in one machine cycle from the first stage to the final stage (rth stage). However, when r increases, the processing delay in the adder 105 increases, and there is a possibility that it cannot be implemented in one machine cycle. In such a case, a register capable of holding the input signal in synchronization with the clock signal may be provided at an appropriate stage interval. In other words, the pipeline operation as described above increases the processing delay, but does not reduce the processing throughput, and allows the expression (12) to be implemented in an M + 1 machine cycle period.

  The subtracter 106 in FIG. 1 subtracts the output of the adder 105 (the second term on the right side of the equation (12)) from N, without needing to give a specific configuration example. ) Expression is completely calculated.

The maximum value detector 107 in FIG. 1 is obtained when the autocorrelation coefficient N · Corr _sgn (n, k) expressed by the equation (12) is changed in a range of d + M ≧ k ≧ d with respect to k. An absolute value is selected from among M + 1 correlation coefficients N · Corr _sgn (n, d), N · Corr _sgn (n, d + 1), ..., N · Corr _sgn (n, d + M) input from the subtractor 106. The index k _max of k when maximizing is calculated (estimated) as the pitch period of the input signal X (n).

The maximum value detector 107 can be realized by software executed by the CPU, for example. FIG. 7 is a flowchart showing the flow of processing when the maximum value detector 107 is realized by software as described above. It should be noted that correlation coefficients N · Corr _sgn (n, d), N · Corr _sgn (n, d + 1), ..., N · Corr _sgn (n, d + M) are sequentially input from the subtractor 106 in the reverse order. The maximum value detector 107 appropriately incorporates a buffer memory that absorbs the difference between the timing and the processing timing of the maximum value detector 107.

  When the pitch estimation process (maximum value detection process) shown in FIG. 7 is started, three types of parameters max, kmax, and k are initialized to 0, d + M, and d + M, respectively (step 301).

Thereafter, when the parameter k is equal to or greater than the value d, it is confirmed that all the correlation coefficient comparison processes have not been completed (step 302), and the correlation coefficient N ··· which is determined by the value of the parameter k at that time. It is determined whether Corr _sgn (n, k) is greater than or equal to the parameter max (step 303). When step 303 is executed for the first time, since k is d + M, the correlation coefficient N · Corr _sgn (n, d + M) is compared with the parameter max.

If the correlation coefficient N · Corr _sgn (n, k) is equal to or greater than the parameter max, the value of the parameter max is replaced with the value of the correlation coefficient N · Corr _sgn (n, k) to be processed at that time, The parameter kmax is replaced with the parameter k at that time (step 304).

When it is determined in step 303 that the correlation coefficient N · Corr _sgn (n, k) is smaller than the parameter max, or when the process in step 304 is completed, the parameter k is decremented by 1 (step 305), the process returns to step 302 described above.

By repeating the processing loop of step 302 to step 305, the correlation coefficient N · Corr _sgn (n, d + M) to the correlation coefficient N · Corr _sgn (n, d) one by one. Corr _sgn (n, k) is compared with the maximum value max at that time. If the maximum value max is exceeded, the maximum value max and the time difference kmax are updated.

When the processing loop from step 302 to step 305 is executed for all of M + 1 correlation coefficients N · Cor _sgn (n, d + M) to N · Corr _sgn (n, d), a negative result is obtained in step 302. The series of processes shown in FIG. The value of the parameter kmax at the end is output as the pitch period of the input signal X (n).

  Even if there are a plurality of M + 1 correlation coefficients that have the same maximum value, step 303 compares them including equal, and even if equal, step 304 updates the parameter kmax. A shorter time difference is detected as a pitch period.

  Note that it would be easy for those skilled in the art to realize the maximum value detector 107 with a hardware configuration and realize the loop processing shown in FIG. 7 with a processing time of one machine cycle for one correlation coefficient. .

(A-3) Effect of Embodiment [Effect 1] Small Computation Amount As described above, the computation amount required to calculate the pitch period according to the prior art described in Non-Patent Document 1 is N (M / 4 + 7/2) + α ( M / 2 + 5) machine cycle. In contrast, in the above embodiment, there are M + 1 machine cycles.

  For example, the values of parameters N and M employed in the prior art described in Non-Patent Document 1 are N = 160 and M = 80, respectively. Substituting this, 3760 + 45α machine cycles in the prior art and 81 machine cycles in the embodiment. α is the number of machine cycles required to calculate equation (3) in the prior art. Here, assuming a conservative value of α = 40, the prior art has 5560 machine cycles (the embodiment has 81 machine cycles since it is not related to α).

  That is, according to the embodiment, the amount of calculation required in the conventional technique is dramatically reduced to about 1/70.

  In addition, in the above-described embodiment, the thinning-out process regarding the parameters N and M, which has been performed in the pitch search in the prior art, is not performed, and the true pitch is not overlooked. If the thinning process is applied to the embodiment as in the conventional technique, the amount of calculation can be reduced to about 1/140 compared to the conventional technique.

[Effect 2] Elimination of Multiplication / Division / Square Root In general, when multiplication, division, and square root operations are compared with an addition operation, both the hardware scale and the processing time are smaller in the addition operation. Since the above embodiment is processed according to equation (12), multiplication, division, and square root calculation are unnecessary, and the hardware scale, processing time, and power consumption can be reduced.

[Effect 3] Performance Comparison The results of performing packet loss compensation standardized in the prior art described in Non-Patent Document 1 using pitch estimation according to the prior art described in Non-Patent Document 1 and pitch estimation according to the embodiment will be described. .

  As an implementation condition, the sound source is male voice 60 seconds, the packet discard rate is 1% to 50%, the sound source is a signal (S), and the difference between the sound source and the waveform reproduced by the packet loss compensation is regarded as noise (N). Measure. A double-precision floating point was used for the calculation of pitch estimation according to the prior art. An implementation result is shown in FIG.

  In the packet loss rate range of 1% to 50%, the difference in the SN ratio is within the number of commas dB. In particular, there is no difference near the packet loss rate of 1%. The packet loss rate is defined in TTC standard JT-Y1541 (ITU-T recommendation Y.1541) “Network target in IP-based service”, 0.1% for class 0 to 4 and unspecified for class 5 It has become. Therefore, in the communication network having the quality of class 0 to 4, even if packet loss compensation using the pitch estimator of the embodiment is used, there is no inferiority.

(B) Other Embodiments In the description of the above-described embodiment, various modified embodiments have been referred to. However, modified embodiments as exemplified below can be cited.

  In the above-described embodiment, the autocorrelation calculator is generally configured by hardware, but may be configured as software (autocorrelation calculation program) executed by the CPU. Similarly, the pitch estimator may be configured as software (pitch estimation program). Even in this case, the same effects as those of the above-described embodiment can be obtained except for the reduction of the hardware scale.

  In the above embodiment, the input signal is an audio signal. However, the type of the signal is not limited to the audio signal, and may be a general discrete value system signal.

The autocorrelation calculator according to the present invention is not limited to the one configured by the set of components as in the above embodiment. In short, the input signal X (n) is converted into the 1-bit signal X _bin (n). It suffices if the configuration can execute the above-described expression (12) later.

In the above embodiment, the input signal X (n) is converted into the 1-bit signal X _bin (n) and then the time difference k for calculating the autocorrelation is considered. It may be converted into a 1-bit signal after performing processing for separating the sequences and giving the time difference k (for example, processing for delaying one). The expression of the claims does not necessarily include such a modification, but the claim covers such a modification.

  Furthermore, in the above embodiment, the autocorrelation calculator is applied to the pitch estimator. However, the application apparatus of the autocorrelation calculator is not limited to this.

It is a block diagram which shows the structure of the pitch estimator 100 of embodiment. It is a chart explaining the correspondence between the binarized signal X _sgn (n) and the binary representation X _bin (n) of the embodiment. It is a _{table | surface} explaining the corresponding | compatible relationship with the binary number expression in multiplication _Xsgn ( _ni ) _Xsgn ( _nki ) of embodiment. It is a block diagram which shows the specific structural example of the code bit extractor 101 in embodiment. 3 is a block diagram illustrating a specific configuration example of shift registers 102 and 103 and an exclusive OR gate group 104 in the embodiment. FIG. It is a block diagram which shows the specific structural example of the adder 105 in embodiment. It is a flowchart which shows the process of the maximum value detector 107 in embodiment. It is explanatory drawing of the effect of the performance surface in embodiment.

Explanation of symbols

  100: pitch estimator, 101: sign bit extractor, 102, 103: shift register, 104: exclusive OR gate group, 105: adder, 106: subtractor, 107: maximum value detector.

Claims (5)

A predetermined interval (the number of samples in this interval is N) of the discrete value system signal X (n) is used as a reference signal, and an autocorrelation coefficient Corr (n, k) with the same signal in the predetermined interval N past by this time k. In the autocorrelation calculator that calculates
Binary encoding means for converting the discrete time signal X (n) into a 1-bit signal X _bin (n) according to whether the dynamic range is less than the intermediate value, intermediate value, or excess intermediate value;
Calculation means for executing an operation according to the equation (A) based on the 1-bit signal X _bin (n) from the binary encoding means and outputting the calculation result as the autocorrelation coefficient Corr (n, k); An autocorrelation calculator comprising:

However, a symbol in which + is circled represents an exclusive OR operation. The computing means is
A first N-bit signal holding unit that holds and outputs the 1-bit signal X _bin (n) from the binary encoding means for at least N bits required on the current side in the equation (A);
A second N-bit signal holding unit that holds and outputs the 1-bit signal X _bin (n) from the binary encoding means for at least N bits required on the past side in the equation (A);
An exclusive OR operation unit that performs an exclusive OR operation on a bit-by-bit basis for a total of 1-bit signals output from the first and second 1-bit signal holding means;
Converting the number of logical “1” bits from the output of the exclusive OR operation of N bits into an integer value, and a summation / doubling unit for doubling the integer value;
The autocorrelation computing unit according to claim 1, further comprising: a subtracting unit that subtracts an integer value from the sum / doubling unit from N. A predetermined interval (the number of samples in this interval is N) of the discrete value system signal X (n) is used as a reference signal, and an autocorrelation coefficient Corr (n, k) with the same signal in the predetermined interval N past by this time k. In the autocorrelation calculation method for calculating
A binary encoding means and an arithmetic means;
The binary encoding means converts the discrete time signal X (n) into a 1-bit signal X _bin (n) according to whether the dynamic range is less than the intermediate value, the intermediate value, or the intermediate value,
The calculation means executes a calculation according to the equation (B) based on the 1-bit signal X _bin (n) from the binary encoding means, and the calculation result is set as the autocorrelation coefficient Corr (n, k). An autocorrelation calculation method characterized by output.

However, a symbol in which + is circled represents an exclusive OR operation. In the pitch estimator for detecting the pitch period of the discrete value system signal X (n),
An autocorrelation calculator that calculates an autocorrelation coefficient Corr (n, k) for the time difference k of the discrete value system signal X (n);
A maximum value detecting means for detecting, as a pitch period, a time difference giving the maximum absolute value from a plurality of autocorrelation coefficients Corr (n, k) having different time differences k from the autocorrelation calculator; And
The pitch estimator according to claim 1 or 2, wherein the autocorrelation calculator is applied. In the pitch estimation method for detecting the pitch period of the discrete value system signal X (n),
An autocorrelation calculator and maximum value detection means;
The autocorrelation calculator calculates an autocorrelation coefficient Corr (n, k) for a time difference k of the discrete value system signal X (n),
The maximum value detecting means detects, as a pitch period, a time difference giving the maximum absolute value from a plurality of autocorrelation coefficients Corr (n, k) having different time differences k from the autocorrelation calculator. ,
4. The pitch estimation method according to claim 3, wherein the autocorrelation calculator applies the method according to claim 3 as an autocorrelation calculation method.

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