JP2008153486A - Semiconductor device and method for manufacturing semiconductor device - Google Patents

Abstract

A semiconductor element in which a dummy electrode is formed so as to prevent an increase in resistance value of a wiring electrode part in a peripheral circuit part, and a method for manufacturing the semiconductor element are provided.
A semiconductor element according to the present invention includes an image pickup unit on which a photoelectric conversion unit is formed on a semiconductor substrate, and a peripheral circuit unit that is formed around the image pickup unit and includes a wiring electrode. 14, a dummy electrode 18 is formed in the peripheral circuit portion 14, and the dummy electrode 18 is formed to have a long dimension at least along the direction in which the wiring electrode 16 is wired.
[Selection] Figure 2

Description

  The present invention relates to a semiconductor element and a method for manufacturing the semiconductor element.

  A solid-state imaging device using a CCD in an imaging region includes a photoelectric conversion unit such as a photodiode and a charge transfer unit including a charge transfer electrode for transferring a signal charge from the photoelectric conversion unit. A plurality of charge transfer electrodes are arranged adjacent to each other on a charge transfer path formed on the semiconductor substrate, and are sequentially driven.

In recent years, demands for higher resolution and higher sensitivity have been increasing in solid-state imaging devices, and the number of imaging pixels has been increasing to more than gigapixels.
When manufacturing a solid-state imaging device, a substrate (silicon substrate) on which the solid-state imaging device is built is mounted by stacking filters and lenses. For this reason, the alignment between the lens and the photoelectric conversion unit is important, and the distance, that is, the distance in the height direction is extremely high in order to increase the positional accuracy in the manufacturing process and the sensitivity (photoelectric conversion efficiency) in use. It is an important issue.

  Further, in such a situation, in order to obtain high resolution without increasing the chip size, it is necessary to reduce the area per unit pixel and achieve high integration. On the other hand, if the area of the photodiode constituting the photoelectric conversion unit is reduced, the sensitivity is lowered, so the area of the photodiode unit must be ensured. Therefore, various studies have been made to reduce the size of the chip while securing the area occupied by the photodiode portion by reducing the wiring area ratio of the charge transfer portion and the peripheral circuit portion and reducing the area ratio of the wiring. Yes.

  In this situation, maintaining the flatness of the interlayer insulating film between the wiring layers is an important technique for high integration by miniaturization of the wiring. Therefore, when the interlayer insulating film is planarized by chemical mechanical polishing (CMP), it is provided around the pixel region 101 of the solid-state image sensor 100 as shown in FIG. There has also been proposed a method of flattening an interlayer insulating film by providing a dummy electrode 104 in the peripheral circuit portion 102 (see, for example, the following patent document). As shown in FIG. 4, generally, the dummy electrode 104 is divided into a plurality of substantially rectangular shapes in a top view so as to be evenly arranged in the peripheral circuit portion 102 in order to ensure flatness. They are arranged in a pattern arranged in a lattice pattern.

JP 2005-209713 A

  FIG. 5 is a schematic cross-sectional view of the peripheral circuit portion of FIG. On the dummy electrode 104 formed in the peripheral circuit portion 102 of the semiconductor substrate 110, a wiring electrode portion 106 is formed of aluminum or the like so as to cover the dummy electrode 104. When the dummy electrode 104 is formed in a lattice shape as described above, the surface of the wiring electrode portion 106 is curved due to the influence of the unevenness on the upper surface of the dummy electrode 104 so that it slightly meanders in a sectional view. Will be formed. Then, since the wiring length of the wiring electrode portion 106 is substantially increased, the resistance value of the wiring electrode portion 106 is increased, and there is room for improvement in that the electrical characteristics of the solid-state imaging device are deteriorated. there were.

  The present invention has been made in view of the above circumstances, and an object thereof is to manufacture a semiconductor element and a semiconductor element in which a dummy electrode is formed so as to prevent an increase in the resistance value of the wiring electrode part of the peripheral circuit part. It is to provide a method.

The above object of the present invention is achieved by the following configurations.
(1) A semiconductor element comprising a semiconductor substrate and a wiring electrode formed on the semiconductor substrate, comprising a dummy electrode having a long dimension along a direction in which the wiring electrode is wired. A featured semiconductor element.
(2) A semiconductor element having an imaging unit in which a photoelectric conversion unit is formed on the semiconductor substrate, and a peripheral circuit unit that is formed around the imaging unit and in which the wiring electrode is formed. The dummy electrode is formed in a circuit portion, and the dummy electrode is formed to have a long dimension at least along a direction in which the wiring electrode is wired. Semiconductor element.
(3) The semiconductor element according to (1) or (2), wherein a total area of the upper surfaces of the dummy electrodes is larger than a total area of the bottom surfaces of the wiring electrodes formed on the dummy electrodes. .
(4) The semiconductor element according to any one of (1) to (3), wherein the dummy electrode is formed of the same material as the conductive film formed in the imaging unit.
(5) The semiconductor element according to (4), wherein the conductive film is a charge transfer electrode for transferring a signal charge generated in the photoelectric conversion unit.
(6) A method of manufacturing a semiconductor device comprising a semiconductor substrate and a wiring electrode formed on the semiconductor substrate, the step of forming a wiring electrode on the semiconductor substrate, and forming a dummy electrode on the semiconductor substrate. Patterning the wiring electrode using a mask pattern including a pattern for forming the dummy electrode so as to have a long dimension at least along a direction in which the wiring electrode is wired. A method for manufacturing a semiconductor device, characterized by:
(7) A method for manufacturing a semiconductor device, comprising: an imaging unit in which a photoelectric conversion unit is formed on the semiconductor substrate; and a peripheral circuit unit that is formed around the imaging unit and in which the wiring electrode is formed. Using a mask pattern including a step of forming a conductive film on the imaging unit, a pattern of the conductive film formed on the imaging unit, and a pattern for forming the dummy electrode on the peripheral circuit unit, The step of patterning the conductive film, and the dummy electrode is formed so as to have a long dimension at least along a direction in which the wiring electrode is wired. A method for manufacturing a semiconductor device.
(8) The semiconductor element according to (6) or (7), wherein a total area of the upper surfaces of the dummy electrodes is larger than a total area of the bottom surfaces of the wiring electrodes formed on the dummy electrodes. Manufacturing method.
(9) The semiconductor according to any one of (6) to (8), wherein the conductive film is a charge transfer electrode for transferring a signal charge generated in the photoelectric conversion unit. Device manufacturing method.

  According to the present invention, since the dummy electrode is formed so as to have a long dimension along the direction in which the wiring electrode is wired, the surface of the wiring electrode is affected by the unevenness of the lattice pattern of the dummy electrode as in the prior art. The bending does not occur, and the wiring length of the wiring electrode can be prevented from becoming substantially long.

  It is preferable that the sum of the areas of the upper surfaces of the dummy electrodes be larger than the sum of the areas of the bottom surfaces of the wiring electrodes formed on the dummy electrodes. In this way, since the dummy electrode formed below the region where the wiring electrode is to be formed is continuously formed without interruption, it is possible to reliably avoid the provision of irregularities that cause the wiring electrode to bend. The entire wiring electrode can be formed flat.

  ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method of the semiconductor element which formed the dummy electrode so that the resistance value of the wiring electrode part of a peripheral circuit part can be prevented, and a semiconductor element manufacturing method can be provided.

Hereinafter, embodiments according to the present invention will be described in detail with reference to the drawings.
FIG. 1 is a schematic plan view illustrating the configuration of the semiconductor element of this embodiment. In the present embodiment, a configuration of a solid-state image sensor as a semiconductor element will be described as an example.
The semiconductor element 10 includes a semiconductor substrate 11 made of silicon or the like, and an imaging unit 12 is formed at the center of the imaging surface of the semiconductor substrate 11.

  The imaging unit 12 is formed with a photoelectric conversion unit such as a photodiode (not shown). In the case of a solid-state imaging device, a charge transfer electrode for transferring signal charges generated in the photoelectric conversion unit, a light shielding film for preventing incident light from directly entering the charge transfer electrode, an antireflection film, A lens layer for condensing incident light is formed on the photoelectric conversion unit.

  A peripheral circuit unit 14 is formed around the imaging unit 12 on the imaging surface.

  FIG. 2 is a partially enlarged view of the semiconductor element of FIG. A wiring electrode 16 made of aluminum or the like is formed on the peripheral circuit portion 14. The wiring electrode 16 is formed by extending a conductive film in a substantially strip shape in a predetermined direction. In the present embodiment, the plurality of wiring electrodes 16 are arranged in parallel with each other so as to surround the periphery of the imaging unit 12.

  In the imaging unit 12 of the semiconductor element 10, a conductive film is formed on the semiconductor substrate 11, and this conductive film is patterned with a mask pattern so as to have a predetermined pattern. At this time, in order to form another insulating film or other film flatly on the conductive film, a flattening process is performed by CMP. For example, when the conductive film of the imaging unit 12 is flattened, a dummy electrode 18 that is not electrically connected to the peripheral circuit unit 14 is formed in order to prevent the conductive film from being excessively polished. The overpolishing of the conductive film 12 of the imaging unit 12 is suppressed.

  In the present embodiment, the dummy electrode 18 has a long dimension along the direction in which the wiring electrode 16 formed in the upper part is wired, as shown by the hatched portion in FIG. It is formed to have a law.

  Specifically, in FIG. 2, the wiring electrode 16 on the upper side with respect to the imaging unit 12 is extended and wired in the left-right direction in FIG. 2, and the dummy electrode 18 is long in the left-right direction in the drawing. A plurality of strips are formed so as to have a law. Further, the wiring electrode 16 on the right side with respect to the imaging unit 12 is extended and wired in the vertical direction in the figure, and the dummy electrode 18 is approximately so as to have a long dimension in the vertical direction in the figure. A plurality of strips are formed.

  As described above, the dummy electrode 18 is not formed in a substantially rectangular shape in the form of a lattice as in the prior art, but is formed as an integral member having a long dimension along the wiring direction of the wiring electrode. Yes. In the present embodiment, the dummy electrodes 18 are formed in a plurality of strips according to the shape of the plurality of wiring electrodes 16. However, the dummy electrodes 18 are formed in a planar shape so as to have a predetermined area so as to form the plurality of wiring electrodes 16. May be. At this time, as long as the dummy electrode 18 has a long dimension at least along the direction in which the wiring electrode 16 is wired, the dummy electrode 18 may be appropriately deformed.

  The semiconductor element 10 is formed so that the dummy electrode 18 has a long dimension along the direction in which the wiring electrode 16 is wired. Therefore, when the semiconductor element 10 is formed with a lattice pattern of the dummy electrode 18 as in the prior art, the influence of unevenness is exerted. Therefore, the surface of the wiring electrode 16 is not curved, and the wiring length of the wiring electrode 16 can be prevented from becoming substantially long. For this reason, the semiconductor element 10 can prevent the resistance of the wiring electrode 16 from increasing, and the electrical characteristics do not deteriorate.

  Next, the procedure of the semiconductor device manufacturing method will be described. FIG. 3 is a schematic cross-sectional view of a semiconductor element for explaining the procedure of the method for manufacturing the semiconductor element. In the procedure of the following manufacturing method, the configuration of the solid-state imaging device shown in FIGS. 1 and 2 will be described as an example.

  First, a photodiode, a transfer channel, and the like are formed in the imaging unit 12 of the semiconductor substrate 11 by ion implantation. Thereafter, as shown in FIG. 3A, a gate insulating film 2 having a so-called ONO film structure in which an oxide film 2a, a nitride film 2b, and an oxide film 2c are sequentially deposited on the imaging surface of the semiconductor substrate 11 is formed. . On the gate insulating film 2, a conductive film 3 made of polysilicon or the like, an interelectrode insulating film 4, and a nitride 5 are formed and patterned with a predetermined mask pattern by a photolithography process. At this time, the conductive film 3 of the imaging unit 12 is formed in a predetermined pattern to be a first charge transfer electrode, and the conductive film 3 of the peripheral circuit unit 14 is formed in a predetermined pattern so that the dummy electrode 18 is formed. It becomes. As the mask pattern, a pattern including a pattern of the first charge transfer electrode of the imaging unit 12 and a pattern for forming the pattern of the dummy electrode 18 is used.

  As shown in FIG. 3B, after patterning the conductive film 3, an interlayer insulating film 6 is formed so as to cover the imaging unit 12 and the peripheral circuit unit 14. Thereafter, as shown in FIG. 3C, a conductive film 7 such as polysilicon is formed on the interlayer insulating film 6. Then, as shown in FIG. 3D, after the conductive film 7 is formed, CMP is performed. At this time, the nitride 5 formed in the imaging unit 12 and the peripheral circuit unit 14 is used as a polishing stopper so that an appropriate polishing amount is obtained. Thus, the conductive film 7 is polished, and the conductive film 7 left in the imaging unit 12 is caused to function as a second charge transfer electrode. In the present embodiment, a solid-state imaging device having a single-layer electrode structure has been described as an example. However, a two-layer electrode structure in which the first charge transfer electrode and the second charge transfer electrode partially overlap two layers may be used.

  When the second charge transfer electrode is formed, the area above the dummy electrode 18 is formed to be large and flat, so that when the wiring electrode is formed on the dummy electrode 18, the wiring electrode is flattened without being bent. Can be formed. Here, it is preferable that the total area of the upper surfaces of the dummy electrodes 18 is larger than the total area of the bottom surfaces of the wiring electrodes 16 formed on the dummy electrodes 18. In this way, since the dummy electrode 18 formed below the region where the wiring electrode 16 is formed is continuously formed without interruption, it is ensured that the unevenness that causes the wiring electrode 16 to be curved is provided. This can be avoided, and the entire wiring electrode 16 can be formed flat.

  If the dummy electrode 18 is formed in an excessively large area, the dummy electrode 18 of the peripheral circuit unit 14 becomes dense with respect to the region where the electrode on the imaging unit 12 side is formed, so that the polishing amount of the imaging unit 12 is reduced. May end up. Therefore, if the dummy electrode 18 is formed only at least under the region where the wiring electrode 16 is formed, it is possible to suppress adverse effects on the planarization.

In addition, this invention is not limited to embodiment mentioned above, A suitable deformation | transformation, improvement, etc. are possible.
For example, in the above-described embodiment, the configuration of a semiconductor element such as a solid-state imaging element has been described as an example. However, the present invention can also be applied to the configuration of a semiconductor element such as a logic circuit element.
The logic circuit element includes a semiconductor substrate and wiring electrodes formed in a predetermined pattern on the semiconductor substrate. And it can be set as the structure which formed the dummy electrode which has a elongate dimension along the direction where a wiring electrode is wired. Here, the pattern of the wiring electrode is not particularly limited. If the wiring electrode pattern extends along a certain direction, the long dimension of the dummy electrode can be defined based on the extending direction.
As a procedure of such a method of manufacturing a logic circuit element, a process of forming a wiring electrode on a semiconductor substrate and a process of patterning the wiring electrode using a mask pattern including a pattern for forming a dummy electrode on the semiconductor substrate And have. And when forming a dummy electrode, it forms so that it may have a long dimension at least along the direction where a wiring electrode is wired.

  Since the logic circuit element having such a configuration is formed so that the dummy electrode has a long dimension along the direction in which the wiring electrode is wired, it can be made less susceptible to the unevenness of the dummy electrode pattern. Thus, the surface of the wiring electrode is not curved, and the wiring length of the wiring electrode can be prevented from becoming substantially long.

1 is a schematic plan view of a semiconductor element according to the present invention. FIG. 2 is a partially enlarged view of the semiconductor element of FIG. 1. It is a figure explaining the procedure of the manufacturing method of a semiconductor element. It is a schematic plan view of a solid-state image sensor. It is a schematic sectional drawing of the peripheral circuit part of the solid-state image sensor of FIG.

Explanation of symbols

3, 7 Conductive film 10 Semiconductor element 11 Semiconductor substrate 12 Imaging unit 14 Peripheral circuit unit 16 Wiring electrode 18 Dummy electrode

Claims (9)

  A semiconductor element including a semiconductor substrate and a wiring electrode formed on the semiconductor substrate, wherein the semiconductor element includes a dummy electrode having a long dimension along a wiring direction of the wiring electrode. Semiconductor element. An imaging unit in which a photoelectric conversion unit is formed on the semiconductor substrate;
A semiconductor element having a peripheral circuit part formed around the imaging part and on which the wiring electrode is formed,
The dummy electrode is formed in the peripheral circuit portion, and the dummy electrode is formed to have a long dimension at least along a direction in which the wiring electrode is wired. Semiconductor element.   3. The semiconductor device according to claim 1, wherein the total area of the upper surfaces of the dummy electrodes is larger than the total area of the bottom surfaces of the wiring electrodes formed on the dummy electrodes.   4. The semiconductor element according to claim 1, wherein the dummy electrode is made of the same material as the conductive film formed in the imaging unit. 5.   The semiconductor element according to claim 4, wherein the conductive film is a charge transfer electrode for transferring a signal charge generated in the photoelectric conversion unit. A method for manufacturing a semiconductor element comprising a semiconductor substrate and a wiring electrode formed on the semiconductor substrate,
Forming a wiring electrode on the semiconductor substrate;
Patterning the wiring electrode using a mask pattern including a pattern for forming a dummy electrode on the semiconductor substrate,
The method of manufacturing a semiconductor device, wherein the dummy electrode is formed to have a long dimension along at least a direction in which the wiring electrode is wired. An imaging unit in which a photoelectric conversion unit is formed on the semiconductor substrate;
A method of manufacturing a semiconductor element having a peripheral circuit portion formed around the imaging portion and having the wiring electrode formed thereon,
Forming a conductive film on the imaging unit;
Patterning the conductive film using a pattern of the conductive film formed on the imaging unit and a mask pattern including a pattern for forming the dummy electrode on the peripheral circuit unit,
The method of manufacturing a semiconductor element according to claim 6, wherein the dummy electrode is formed to have a long dimension at least along a direction in which the wiring electrode is wired.   8. The method of manufacturing a semiconductor element according to claim 6, wherein a total area of the upper surfaces of the dummy electrodes is larger than a total area of the bottom surfaces of the wiring electrodes formed on the dummy electrodes.   9. The method of manufacturing a semiconductor element according to claim 6, wherein the conductive film is a charge transfer electrode for transferring a signal charge generated in the photoelectric conversion unit.

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