JP2008152862A - Disk reproducing apparatus, PLL circuit, and clock synchronization method - Google Patents

Abstract

The pull-in time of a PLL is shortened by a method different from the conventional one.
A PLL circuit 30 includes a voltage control transmission circuit 32 that outputs a clock signal corresponding to a control voltage, a square operation circuit 36 that squares an input wave to generate a squared input wave, and a clock signal. A timing signal generation circuit 38 that generates a timing signal that changes at a timing that becomes the reference phase, and a difference that is obtained by subtracting the reference value from the squared input wave at the timing at which the timing signal changes is obtained as an input wave and a clock signal. A phase comparison circuit 40 that outputs the phase difference signal of the signal, and a control voltage that reduces the phase difference between the input wave and the clock signal is generated based on the phase difference signal output by the phase comparison circuit, and the control voltage is voltage-controlled. And a loop compensation circuit 42 that supplies the oscillation circuit.
[Selection] Figure 2

Description

  The present invention relates to a disk playback device, a PLL circuit, and a clock synchronization method.

A conventional document (Patent Document 1) discloses a timing phase control device that controls a timing phase for sampling a received signal. In this timing phase control device, a square value obtained by squaring a received signal is calculated, and a phase shift is calculated at a timing when the square value becomes a maximum, thereby speeding up the timing phase.
Japanese Patent Publication No. 63-62932

  As shown in the above document, techniques for reducing the phase pull-in time have been studied, but there is still a demand for shortening the phase pull-in time.

  The present invention has been made to solve the above-described problems, and provides a disk reproducing apparatus, a PLL circuit, and a clock synchronization method capable of reducing the PLL pull-in time by a method different from the conventional technique. Objective.

  In order to achieve the above-described object, the disc reproducing apparatus of the present invention is a PLL circuit that generates a clock signal that is phase-synchronized with a phase-modulated input wave having a constant period, and outputs a clock signal corresponding to a control voltage. A voltage-controlled oscillator circuit that squares an input wave to generate a squared input wave, a timing signal generation circuit that generates a timing signal that changes at a timing at which the clock signal becomes a reference phase, and a timing The phase comparison circuit that outputs the difference obtained by subtracting the reference value from the squared input wave at the timing when the signal changes as the phase difference signal between the input wave and the clock signal, and the phase difference output by the phase comparison circuit Based on the signal, a control voltage for reducing the phase difference between the input wave and the clock signal is generated, and the control voltage is supplied to the voltage controlled oscillation circuit. And loop compensation circuit, characterized by comprising a PLL circuit having a.

  The PLL circuit of the present invention is a PLL circuit that generates a clock signal that is phase-synchronized with a phase-modulated input wave having a constant period, and a voltage-controlled oscillation circuit that outputs a clock signal according to a control voltage; A square calculation circuit that squares a wave to generate a squared input wave, a timing signal generation circuit that generates a timing signal that changes at a timing at which the clock signal becomes the reference phase, and a square at a timing at which the timing signal changes A phase comparison circuit that outputs a difference obtained by subtracting the reference value from the input wave as a phase difference signal of the input wave and the clock signal, and the input wave and the phase difference signal output by the phase comparison circuit A loop compensation circuit that generates a control voltage for reducing the phase difference of the clock signal and supplies the control voltage to the voltage controlled oscillation circuit. The features.

  The clock synchronization method of the present invention is a clock synchronization method for synchronizing the phase of a clock signal of a voltage controlled oscillation circuit that outputs a clock signal according to a control voltage with a phase-modulated input wave having a constant period, A square calculation step that squares an input wave and generates a squared input wave, a timing signal generation step that generates a timing signal that changes at a timing at which the clock signal becomes a reference phase, and a timing at which the timing signal changes, A phase comparison step using the difference obtained by subtracting the reference value from the squared input wave as the phase difference signal of the input wave and the clock signal, and reducing the phase difference of the input wave and the clock signal based on the phase difference signal Generating a control voltage to be supplied and supplying the control voltage to the voltage controlled oscillation circuit.

  According to the present invention, it is possible to provide a disk reproducing device, a PLL circuit, and a clock synchronization method capable of reducing the PLL pull-in time.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the description, the same reference numerals are used for the same elements or elements having the same function, and redundant description is omitted.

  FIG. 1 is a block diagram showing a disc playback apparatus 1 according to an embodiment of the present invention. The disc reproducing apparatus 1 is configured to be detachable from an optical disc D that is a disc-shaped storage medium, and has a function of writing data to the optical disc D and a function of reading data from the optical disc D.

  Here, the optical disk D means HD-DVD (High Definition Digital Versatile Disc), DVD-RAM (DVD Random Access Memory), DVD-R (DVD Recordable), DVD-RW (DVD ReWritable), CD (Compact Disc). It is a disk-shaped storage medium used in standards such as.

  The disk reproducing apparatus 1 includes an optical head PUH, a preamplifier 10, an RF circuit 12, a data processing unit 14, a control unit 20, a motor drive control unit 22, a light spot position control unit 24, and an optical head position control. A unit 26, a motor M, a feed mechanism R, and a wobble PLL (Phase Locked Loop) circuit 30 are provided.

  When writing data to the optical disc D, the data processing unit 14 adds an error detection code (EDC), an error correction code (ECC), and the like to the recording data, and then determines the recording data in advance, such as a run length limit code. The data is converted into modulation data according to a rule, and a recording pulse signal having a pulse width corresponding to the obtained modulation data is generated and output. The optical head PUH takes in the recording pulse signal and irradiates the optical disc D with an appropriate laser beam corresponding to the recording data. Data is recorded on the optical disc D by irradiating the optical disc D with an appropriate laser beam from the optical head PUH.

  At the time of reading data from the optical disk D, data is reproduced from the optical disk D by irradiating the optical disk D with an appropriate laser beam from the optical head PUH. The optical head PUH emits a laser beam of appropriate power and detects reflected light from the optical disc D, thereby outputting two types of signals, a sum signal S1 including data information and a difference signal S2 including address information. . In other words, the optical head PUH is a reproduction signal generation unit that reads out data recorded on the optical disc D and generates a reproduction signal.

  The sum signal S1 and the difference signal S2 will be described. On the recording track of the optical disc D, a wobble groove slightly wobbling in the radial direction is formed. This reflected light is detected by the sensor of the optical head PUH. The optical sensor is divided into two in the radial direction. The sum signal S1 is a signal obtained by adding the detection value of the outer peripheral side optical sensor and the detection value of the inner peripheral side optical sensor, and has a signal level corresponding to the track width in the beam spot. It is a signal according to the state. On the other hand, the difference signal S2 is a signal obtained by subtracting the detection value of the inner-side photosensor from the detection value of the outer-side photosensor, and is a wobble signal corresponding to the wobbling of the track.

  The sum signal S 1 from the optical head PUH is amplified by the preamplifier 10 and then input to the data processing unit 14 via the RF circuit 12. The data processing unit 14 performs demodulation processing, error correction processing, and the like on the data read from the optical disc D, reproduces the original data, and outputs the reproduced data to an external device.

  The controller 20 outputs a command signal to each of the motor drive controller 22, the light spot position controller 24, and the optical head position controller 26 during data recording or data reproduction. The motor drive control unit 22 controls the spindle motor M to rotate the optical disc D stably. The light spot position control unit 24 performs light spot position control such as focusing and tracking, and copes with the eccentricity and surface vibration of the optical disk D accompanying the rotation of the optical disk D. The optical head position control unit 26 controls the feed mechanism R to move the optical head PUH to the vicinity of the track to be recorded or reproduced.

  The wobble PLL circuit 30 takes in the wobble signal S2, which is a difference signal from the optical head PUH, generates a wobble clock signal corresponding to the wobble signal S2, and sends the wobble clock signal WPLL to the data processing unit 14, the control unit 20, and the like. Output. Even when data is not recorded on the optical disk D, the address of the optical disk D can be determined by the wobble clock signal. The data processing unit 14 and the control unit 20 count the wobble clock signal to determine the address of the optical disc D and use it for control.

  Next, the wobble PLL circuit 30 will be described in more detail with reference to FIG. FIG. 2 is a block diagram showing a circuit configuration of the wobble PLL circuit 30. As shown in FIG.

  The wobble PLL circuit 30 is a circuit for generating a wobble clock signal that is phase-synchronized with a phase-modulated wobble signal having a constant period (hereinafter referred to as a wobble input wave). The wobble PLL circuit 30 includes an analog-to-digital (A / D) conversion circuit 34, a square operation circuit 36, a phase comparison circuit 40, a loop compensation circuit 42, and a voltage controlled oscillator (VCO). ) 32 and a timing signal generation circuit 38.

  The VCO 32 is a circuit that outputs a clock signal having a fixed period, and is configured to be able to adjust its oscillation frequency and phase in accordance with a control voltage supplied from the outside. The VCO 32 takes in a control voltage from the loop compensation circuit 42 and outputs a wobble clock signal WPLL whose oscillation frequency and phase are adjusted according to the control voltage. The VCO 32 can generate a clock signal having a frequency different from that of the wobble clock signal WPLL. The timing signal generating circuit 38 is supplied with a clock signal having a frequency eight times that of the wobble clock signal WPLL. The D conversion circuit 34 is supplied with a clock signal with a higher magnification frequency.

  The A / D conversion circuit 34 is a circuit capable of converting an analog signal into a digital signal in accordance with a clock signal from the VCO 32, and converts a wobble input wave of an analog signal input from the outside into a wobble input wave of a digital signal. To do. FIG. 3A is an example of a wobble input wave of a digital signal. Since the clock signal input from the VCO 32 to the A / D conversion circuit 34 has a high frequency, the wobble input wave of the analog signal is almost directly converted into the wobble input wave of the digital signal. In FIG. 3A, the wobble input wave is phase-modulated, and the phase is inverted halfway.

  The square calculation circuit 36 takes the digital signal wobble input wave from the A / D conversion circuit 34, calculates the square of the wobble input wave, and outputs the squared wobble input wave to the phase comparison circuit 40. In the following description, the squared wobble input wave is referred to as a wobble square wave. FIG. 3B is an example of a wobble square wave. Since the wobble square wave is a waveform obtained by squaring the wobble input wave, the waveform disturbance due to phase modulation is eliminated, and the waveform is suitable for signal processing in the subsequent stage.

  The timing signal generation circuit 38 is a circuit that supplies a phase comparison timing signal to the phase comparison circuit 40. The timing signal generation circuit 38 takes in a clock signal having a frequency eight times that of the wobble clock signal (hereinafter referred to as an eight times clock signal) from the VCO 32. Then, the timing signal generation circuit 38 generates a phase comparison timing signal as shown in FIG. 4 based on the 8-times clock signal. 4A shows a wobble clock signal, FIG. 4B shows an 8 × clock signal, and FIG. 4C shows a phase comparison timing signal.

  The timing signal generation circuit 38 changes the phase comparison timing signal from OFF to ON at the timing when the 8 times clock signal changes from OFF to ON, counting from the timing when the wobble clock signal changes from OFF to ON. Thus, the phase comparison timing signal is changed from on to off at the timing when the 8-times clock signal is changed from off to on for the fourth time. Further, the timing signal generation circuit 38 changes the phase comparison timing signal from OFF to ON at the timing when the 8 times clock signal changes from OFF to ON, counting from the timing when the wobble clock signal changes from OFF to ON. The phase comparison timing signal is changed from on to off at the timing when the 8 times clock signal is changed from off to on for the eighth time.

  In other words, the phase comparison timing signal changes from off to on when the wobble clock signal has a phase of 45 °, and then changes from on to off when the wobble clock signal has a phase of 135 °. The phase comparison timing signal changes from off to on when the wobble clock signal has a phase of 225 °, and then changes from on to off when the wobble clock signal has a phase of 315 °. Since the wobble clock signal and the wobble input wave are substantially in phase, the phase comparison timing signal changes from off to on when the wobble input wave has a phase of 45 °, and the wobble input wave has a phase of 225 °. When it becomes, it changes from off to on.

  As can be understood from the description below, the phase comparison timing signal generated by the timing signal generation circuit 38 is a reference phase in which the phases of the wobble clock signal and the wobble input wave are set in advance (45 ° in this embodiment, Any signal may be used as long as the signal is a timing at which the wobble input wave becomes a reference value set in advance (in this embodiment, an intermediate value of the wobble input wave). Here, the reference phase and the reference value correspond to each other.

  Note that the phase comparison timing signal is a clock signal having a frequency twice that of the wobble clock signal, and approximates the frequency to the wobble square wave. Therefore, the phase comparison timing signal can be easily timed with respect to the wobble square wave, and the processing in the phase comparison circuit 40 is easy.

  The phase comparison circuit 40 is a circuit that outputs a phase difference signal indicating a phase difference between the wobble clock signal and the wobble input wave. The phase comparison circuit 40 takes in the wobble square wave and, for example, calculates the average value of the wobble square wave or calculates the center value of the maximum value and the minimum value of the wobble square wave. Is calculated (see FIG. 5). Then, the phase comparison circuit 40 subtracts the intermediate value from the wobble square wave generated by the square calculation circuit 36 at the timing when the phase comparison timing signal from the timing signal generation circuit 38 changes from off to on, thereby obtaining the wobble square. Calculate the difference between the wave and the intermediate value.

  As described above, the phase comparison timing signal is a signal that changes from off to on when the wobble input wave has a phase of 45 ° and 225 °. Since the wobble square wave has an intermediate value when the wobble input wave has 45 ° and 225 ° phases (reference phases), the difference between the wobble square wave and the intermediate value is the phase synchronization of the wobble clock signal with respect to the wobble input wave. If it is removed, it should be zero. However, if the phase of the wobble clock signal is delayed with respect to the wobble input wave, the positive value has a magnitude corresponding to the amount of phase shift, and the phase advance of the wobble clock signal occurs with respect to the wobble input wave. If it is, it becomes a negative value corresponding to the amount of phase shift.

  Then, the phase comparison circuit 40 supplies the difference between the wobble square wave and the intermediate value to the loop compensation circuit 42 as a phase difference signal indicating the phase difference between the wobble clock signal and the wobble input wave. The reference value subtracted from the wobble square wave is preferably an intermediate value of the wobble square wave from the viewpoint of simplifying the process, but other than the maximum value and the minimum value of the wobble square wave, It may be a value. Accordingly, if the reference phase is 45 ° or 225 °, it is preferable that the phase comparison timing signal can be easily generated from the 8-fold clock signal, but other phases may be used.

  The loop compensation circuit 42 takes in the phase difference signal output from the phase comparison circuit 40 and generates a VCO control voltage for adjusting the oscillation frequency and phase of the wobble clock signal based on the phase difference signal. Here, the VCO control voltage is a control value for adjusting the phase of the wobble clock signal so as to reduce the phase difference between the wobble input wave and the wobble clock signal. The loop compensation circuit 42 supplies the VCO control voltage to the VCO 32. The VCO 32 adjusts the oscillation frequency according to the VCO control voltage to reduce the phase difference between the wobble input wave and the wobble clock signal.

  With reference to FIG. 5, the situation where the phase of the wobble clock signal of the VCO 32 is delayed with respect to the phase of the wobble input wave will be described. In FIG. 5, at the timing when the phase comparison timing signal changes from OFF to ON, the difference obtained by subtracting the intermediate value from the wobble square wave becomes a positive value corresponding to the phase delay of the wobble clock signal. Therefore, the phase comparison circuit 40 outputs this positive value to the loop compensation circuit 42 as a phase difference signal. The loop compensation circuit 42 generates a VCO control voltage that raises the oscillation frequency of the VCO 32, advances the phase of the wobble clock signal in the direction of the arrow A1, and brings the phase of the wobble clock signal closer to the phase of the wobble input wave.

  With reference to FIG. 6, the situation where the phase of the wobble clock signal of VCO 32 is advanced with respect to the phase of the wobble input wave will be described. In FIG. 6, at the timing when the phase comparison timing signal changes from OFF to ON, the difference obtained by subtracting the intermediate value from the wobble square wave becomes a negative value corresponding to the phase advance of the wobble clock signal. Therefore, the phase comparison circuit 40 outputs this negative value to the loop compensation circuit 42 as a phase difference signal. The loop compensation circuit 42 generates a VCO control voltage that lowers the oscillation frequency of the VCO 32, delays the phase of the wobble clock signal in the direction of the arrow A2, and brings the phase of the wobble clock signal closer to the phase of the wobble input wave.

  With reference to FIG. 7, a situation where the phase of the wobble clock signal of the VCO 32 is synchronized with the phase of the wobble input wave will be described. As described above, when the phase of the wobble clock signal of the VCO 32 is delayed with respect to the phase of the wobble input wave, the phase of the wobble clock signal is advanced by advancing the phase of the wobble clock signal. Synchronize with. In addition, when the phase of the wobble clock signal of the VCO 32 is advanced with respect to the phase of the wobble input wave, the phase of the wobble clock signal is synchronized with the phase of the wobble input wave by delaying the phase of the wobble clock signal.

  According to the wobble PLL circuit 30 of the present embodiment, the wobble clock signal of the VCO 32 can be synchronized with the wobble input wave. In particular, according to the wobble PLL circuit 30 of this embodiment, since the process of synchronizing the wobble clock signal with the wobble input wave is simple, the wobble PLL circuit 30 can be shifted to the phase locked state at an early stage. A reduction in the synchronization pull-in time of the circuit 30 is realized. In addition, since the circuit configuration of the wobble PLL circuit 30 of this embodiment is simplified as compared with the prior art, the wobble clock signal can be accurately synchronized with the wobble input wave.

  That is, since the phase difference between the wobble clock signal and the wobble input wave is obtained using the wobble square wave obtained by squaring the wobble input wave, the wobble PLL circuit 30 can be shifted to the phase locked state relatively early. it can. That is, the wobble square wave is not affected by the phase modulation and is a monotonous waveform without any disturbance, so that the phase comparison between the wobble clock signal and the wobble input wave can be performed in a stable state. Therefore, the wobble PLL circuit 30 can be shifted to the phase locked state relatively early, and the synchronization pull-in time of the wobble PLL circuit 30 can be shortened.

  Further, as described above, by calculating the difference obtained by subtracting the reference value from the stable wobble square wave, the phase difference between the wobble clock signal and the wobble input wave can be easily calculated. The pull-in time of the wobble PLL circuit 30 can be shortened by shifting to the phase locked state at an early stage. Further, in the wobble PLL circuit 30, the circuit for calculating the phase difference between the wobble clock signal and the wobble input wave has a simple circuit configuration in which only the reference value is subtracted from the wobble square wave. It is possible to save power than the wobble PLL circuit.

It is a block diagram which shows the circuit structure of the disc reproducing | regenerating apparatus of this embodiment. It is a block diagram which shows the circuit structure of the wobble PLL circuit of this embodiment. It is a time chart which shows a wobble input wave and a wobble square wave. It is a time chart which shows a wobble clock signal, an 8 times clock signal, and a phase comparison timing signal. It is a time chart which shows the condition where the phase of the wobble clock signal of VCO is behind. It is a time chart which shows the condition where the phase of the wobble clock signal of VCO has advanced. It is a time chart which shows the condition where the phase of the wobble clock signal of VCO is synchronizing.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Disc reproducing apparatus, 10 ... Preamplifier, 12 ... RF circuit, 14 ... Data processing part, 20 ... Control part, 22 ... Motor drive control part, 24 ... Light spot position control part, 26 ... Optical head position control part, 30 ... Wobble PLL circuit, 32 ... VCO, 34 ... A / D conversion circuit, 36 ... square calculation circuit, 38 ... timing signal generation circuit, 40 ... phase comparison circuit, 42 ... loop compensation circuit, D ... optical disc, M ... spindle motor , PUH: optical head, R: feed mechanism.

Claims (7)

A PLL circuit that generates a clock signal that is phase-synchronized with a phase-modulated input wave having a constant period,
A voltage control transmission circuit that outputs a clock signal according to the control voltage;
A square arithmetic circuit that squares the input wave to generate a squared input wave;
A timing signal generation circuit that generates a timing signal that changes at a timing at which the clock signal becomes a reference phase;
A phase comparison circuit that outputs a difference obtained by subtracting a reference value from the squared input wave at a timing when the timing signal changes, as a phase difference signal between the input wave and the clock signal;
A loop compensation circuit that generates a control voltage for reducing a phase difference between the input wave and the clock signal based on the phase difference signal output by the phase comparison circuit, and supplies the control voltage to the voltage controlled oscillation circuit; ,
A disk reproducing apparatus comprising a PLL circuit having   2. The disc reproducing apparatus according to claim 1, wherein the reference value is an intermediate value of the squared input wave.   The timing signal generation circuit generates a timing signal that changes at a timing at which the clock signal becomes the reference phase by using a clock signal having a frequency that is a multiple of the clock signal. The disc reproducing apparatus described.   2. The disk reproducing apparatus according to claim 1, wherein the timing signal generation circuit generates a timing signal having a frequency twice as high as the clock signal as the timing signal.   5. The disk reproducing apparatus according to claim 1, wherein the input wave is a wobble input wave in which a wobble groove formed on a disk-shaped storage medium is detected. A PLL circuit that generates a clock signal that is phase-synchronized with a phase-modulated input wave having a constant period,
A voltage control transmission circuit that outputs a clock signal according to the control voltage;
A square arithmetic circuit that squares the input wave to generate a squared input wave;
A timing signal generation circuit that generates a timing signal that changes at a timing at which the clock signal becomes a reference phase;
A phase comparison circuit that outputs a difference obtained by subtracting a reference value from the squared input wave at a timing when the timing signal changes, as a phase difference signal between the input wave and the clock signal;
A loop compensation circuit that generates a control voltage for reducing a phase difference between the input wave and the clock signal based on the phase difference signal output by the phase comparison circuit, and supplies the control voltage to the voltage controlled oscillation circuit; ,
A PLL circuit comprising: A clock synchronization method for synchronizing the clock signal of a voltage controlled oscillation circuit that outputs a clock signal corresponding to a control voltage with a phase-modulated input wave having a constant period,
Squaring the input wave to generate a squared input wave;
A timing signal generation step of generating a timing signal that changes at a timing at which the clock signal becomes a reference phase;
A phase comparison step in which a difference obtained by subtracting a reference value from the squared input wave at a timing at which the timing signal changes is a phase difference signal between the input wave and the clock signal;
A loop compensation step for generating a control voltage for reducing the phase difference between the input wave and the clock signal based on the phase difference signal and supplying the control voltage to the voltage controlled oscillation circuit;
Including clock synchronization method.

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