JP2008148008A - Substrate control circuit, semiconductor integrated circuit and substrate control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a substrate control circuit wherein a starting time to an operating state is shortened and a stable operation is attained. <P>SOLUTION: In the substrate control circuit, power supply unit lines L1, L2 are connected to one-side ends of transfer gates TF2, TF3 and signal lines L3, L4 are connected to other ends of the transfer gates TF2, TF3. On/off-operations of the transfer gates TF2, TF3 are controlled by an active signal ACT. A transfer gate TF1 is interposed between a node N1 which is a drain of a PMOS transistor QP1 and a node N2 which is a drain of an NMOS transistor QN1. On/off-operations of the transfer gate TF1 are controlled by a wake-up signal WUP. The signal lines L3, L4 are electrically connected to the nodes N1, N2. The wake-up signal WUP becomes "H" only in a predetermined period when it transits from a sleep state to an active state. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a substrate control circuit for controlling a substrate potential which is a potential of a body region of a MOS transistor in a CMOS type semiconductor circuit or the like, a semiconductor integrated circuit including the substrate control circuit, and a substrate control method.

  The term “MOS” has been used in the past for metal / oxide / semiconductor laminated structures, and is taken from the acronym Metal-Oxide-Semiconductor. However, in particular, in a field effect transistor having a MOS structure (hereinafter, simply referred to as “MOS transistor”), materials for a gate insulating film and a gate electrode have been improved from the viewpoint of recent integration and improvement of a manufacturing process.

  For example, in a MOS transistor, polycrystalline silicon has been adopted instead of metal as a material of a gate electrode mainly from the viewpoint of forming a source / drain in a self-aligned manner. From the viewpoint of improving electrical characteristics, a material having a high dielectric constant is adopted as a material for the gate insulating film, but the material is not necessarily limited to an oxide.

  Therefore, the term “MOS” is not necessarily limited to the metal / oxide / semiconductor stacked structure, and is not presumed in this specification. That is, in view of technical common sense, here, “MOS” has not only an abbreviation derived from the word source but also a broad meaning including a laminated structure of a conductor / insulator / semiconductor.

  It is well known that the MOS transistor has a threshold voltage Vth that increases due to a back bias effect on the substrate (body region), the drain current Id decreases, and the circuit delay increases. If forward bias control is performed by using this as a reverse hand, the circuit delay is also reduced. By actively controlling the substrate potential (body potential) using such a substrate effect, it is possible to achieve both low power consumption and high-speed operation. The shorter the state transition time from the sleep state to the active state, the finer state switching is possible, and the controllability is improved. However, in general, in order to shorten the state transition time, it is necessary to increase the current driving force of the power supply unit, and this driving force increase causes an increase in operating current or an increase in area penalty. was there.

  As a method for dynamically controlling a substrate potential without adding a bias power supply, a substrate (body) potential control method using a CRABC (Charge Reccling Actively Body-bias Conrolled) method is disclosed in Non-Patent Document 1, for example. Has been. In the CRABC method, the N-well region (body region) of the PMOS transistor fixed at the power supply level VDD and the P-well region (body region) of the NMOS transistor fixed at the ground level GND during sleep (standby state). Are short-circuited at the time of transition from the sleep state to the active state, and are each made to transition toward the (VDD / 2) potential by charge sharing.

  If attention is paid to the PMOS transistor side, the forward bias corresponding to the potential dropped from the power supply level VDD is applied to the substrate (body region) of the PMOS transistor, and if attention is paid to the NMOS transistor side, the NMOS transistor substrate is lifted from the ground level GND. The forward bias corresponding to the minute amount is applied.

  In an actual device, these values depend on the division ratio between the parasitic capacitance connected to the PMOS substrate (N well region) and the parasitic capacitance connected to the NMOS substrate (P well region), or the characteristics of the switch transistor for short circuit. Therefore, the potential to be focused on depends on the manufacturing conditions or individual differences of the devices depending on the manufacturing conditions of the device. Furthermore, it also changes during operation due to the influence of leakage current and the like.

Masayuki Kitamura, Masaaki Iijima, Kenji Hamada, Masahiro Numa, Hiromi Notani, Akira Tada, Shigeto Maekawa, "Acceleration Method of SOI-CMOS by Charge-Reusing Dynamic Body Potential Control," IEICE Tech. no. 476, ICD2005-198, pp. 37-42, December 2005 (Figure 2).

  As described above, the substrate potential control by the above-mentioned CRABC method is very excellent in terms of starting from the sleep state, and although the area overhead is small, the substrate potential during active operation is not uniquely determined, so the operation is stable. There was a problem of lack of sex.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to obtain a substrate control circuit that shortens the start-up time during the operation state and achieves stable operation.

  According to an embodiment of the present invention, the substrate control circuit includes a switch cell group that receives the first and second drive voltages.

  The switch cell group includes a first node for applying a first body potential and a second body potential for applying a second body potential in a wake-up period, which is a predetermined period during which the controlled object shifts from a standby state to an operating state. Short-circuit with the node. The first and second drive voltages are supplied to the first and second nodes in the operation state after the wake-up period has elapsed.

  According to the substrate control circuit of the above embodiment, the wake-up period is provided prior to the operation state of the control target circuit, and the first and second nodes are electrically connected by electrically connecting the first and second nodes. Immediately leads to an intermediate potential.

  Then, after the first and second body potentials approach the first and second driving voltages, which are target values, respectively, the wake-up period ends, and the first and second driving voltages are used to determine the first and second driving voltages. By setting the body potential, it is possible to shorten the start-up time during the operation state and to achieve stable operation of the first and second body potentials.

<Embodiment 1>
1 is a circuit diagram showing a configuration of a substrate control circuit according to Embodiment 1 of the present invention. As shown in the figure, it is composed of two power supply units 1 and 2 (first and second voltage supply circuits) and a switch cell group SWG.

  When the power supply unit drive signal PON is “L” (“0”), the power supply unit 1 puts the power supply unit line L1 into a high impedance state, and when the power supply unit drive signal PON is “H” (1), it becomes active. A drive voltage Vbp (first drive voltage) is supplied from L1.

  Similarly, the power supply unit 2 puts the power supply unit line L2 in a high impedance state when the power supply unit drive signal PON is “L”, and becomes active when the power supply unit drive signal PON is “H”. Vbn (second drive voltage) is supplied.

  The control signal generation circuit 3 generates a standby signal STB, a wake-up signal WUP, an active signal ACT, and a power supply unit drive signal PON at a timing described in detail later.

  The switch cell group SWG includes a wakeup switch unit WUPSW and an active switch unit ACTSW.

  The active switch unit ACTSW is composed of transfer gates TF2 and TF3 (fourth and fifth switching means). A power supply unit line L1 (first voltage supply line) is connected to one end of the transfer gate TF2, a signal line L3 is connected to the other end, and a power supply unit line L2 (second voltage supply line) is connected to one end of the transfer gate TF3. Are connected, and the signal line L4 is connected to the other end. Each of the NMOS gates of the transfer gates TF2 and TF3 receives an active signal ACT, and each of the PMOS gates receives an inverted active signal bar ACT.

  The wakeup switch unit WUPSW includes a PMOS transistor QP1 (first switching means), an NMOS transistor QN1 (second switching means), and a transfer gate TF1 (third switching means). The source of the PMOS transistor QP1 is connected to the power supply (VDD), the inverted standby signal bar STB is received at the gate, and the node N1 (first node) as the drain is connected to one end of the transfer gate TF1. The source of the NMOS transistor QN1 is grounded (GND), the gate receives a standby signal STB, and the drain node N2 (second node) is connected to the other end of the transfer gate TF1.

  Transfer gate TF1 receives wakeup signal WUP at the NMOS gate and inverted wakeup signal bar WUP at the PMOS gate.

  The node N1 is connected to the other end of the transfer gate TF2 of the active switch unit ACTSW through the signal line L3, and the node N2 is connected to the other end of the transfer gate TF3 of the active switch unit ACTSW through the signal line L4. . The nodes N1 and N2 are connected to the P body potential line LP and the N body potential line LN (first and second body potential lines), and the potential obtained from the P body potential line LP is the body potential BVP (first potential). As the body potential BVN (second body potential) is output to the outside. The body potential BVP and the body potential BVN are used for setting the potentials of the body regions of the PMOS transistor and the NMOS transistor to be controlled (not shown in FIG. 1).

  FIG. 2 is a timing chart showing the operation of the substrate control circuit according to the first embodiment shown in FIG. Hereinafter, a substrate control method by the substrate control circuit of the first embodiment will be described with reference to FIG.

  First, in the sleep period T1, which is a period during which the control target is in a standby state, the standby signal STB is set to “H” (the inverted standby signal bar STB is “L”), and the wakeup signal WUP is set to “L” (the inverted wakeup signal bar). WUP is set to “H”), the active signal ACT is set to “L” (the inverted active signal bar ACT is set to “H”), and the power supply unit drive signal PON is set to “L”.

  Accordingly, in the switch cell group SWG, the PMOS transistor QP1 and the NMOS transistor QN1 are turned on, and the transfer gates TF1 to TF3 are turned off. On the other hand, the power supply unit lines L1 and L2 of the power supply units 1 and 2 are both set to a high impedance state.

  As a result, in the sleep period T1, the body potential BVP is set to the power supply voltage VDD, and the body potential BVN is set to the ground level (GND).

  In general, in the CMOS transistor in the control target circuit that receives the body potential BVP and the body potential BVN, the source of the PMOS transistor is set to the power supply voltage VDD, and the source of the NMOS transistor is grounded.

  For this reason, by making the PN junction between the source region and the body region of the PMOS transistor and the NMOS transistor in the general control target circuit zero bias (reducing the forward bias degree), the PMOS transistor and Since the threshold voltage Vth of each NMOS transistor is set high, the circuit to be controlled can effectively suppress the leakage current in the sleep period T1.

  After the elapse of the sleep period T1, the wakeup period T2 is started. The wake-up period T2 is a period inserted only for a predetermined period when transitioning from the sleep state to the active state (operating state), and is assumed to reach the target values (driving voltage Vbp and driving voltage Vbn) ± 0.1V. Is set.

  In the wakeup period T2, the standby signal STB is changed to “L”, the wakeup signal WUP is changed to “H”, and the active signal ACT is maintained at “L”. Further, the power supply unit drive signal PON is maintained at “L” from the disclosure of the wake-up period T2 to the elapse of the first period T21.

  Accordingly, in the switch cell group SWG, the PMOS transistor QP1 and the NMOS transistor QN1 are turned off, the transfer gate TF1 is turned on, the transfer gates TF2 and TF3 are turned off, and the power supply unit lines L1 and L2 of the power supply units 1 and 2 Are both set to a high impedance state.

  With the above setting, the node N1 and the node N2 are electrically connected (short-circuited) via the transfer gate TF1, and the nodes N1 and N2 are in a floating state.

  As a result, the charges charged in the wiring and the body region of the PMOS transistor in the control target circuit are transferred to the NMOS transistor side in the control target circuit via the P body potential line LP, the transfer gate TF1, and the N body potential line LN. The body potential BVP and the body potential BVN quickly transition toward the intermediate potential (Vbp, Vbn) between VDD and GND.

  Thus, by providing the wake-up period T2 prior to the active period T3, it is possible to shorten the activation time during the operation state.

  Considering an ideal transistor, the transition proceeds until the body potential BVP and the body potential BVN become the same potential. However, in an actual device, there is a parasitic component of the capacitance, and the transfer becomes smaller as the potential difference between the body potential BVP and the body potential BVN becomes smaller. Since the driving force of the gate TF1 becomes small, the body potential BVP starts to saturate when it falls to some extent. Similarly, the body potential BVN begins to saturate when it rises to some extent.

  On the other hand, the power supply unit drive signal PON rises to “H” at time t12 when the first period T21 in the wake-up period T2 ends and the second period T22 starts. As a result, the power supply units 1 and 2 are in an operating state, the power supply unit 1 generates the drive voltage Vbn from the power supply unit line L1, and the power supply unit 2 generates the drive voltage Vbn from the power supply unit line L2.

  On the other hand, also in the second period T22 of the wakeup period T2, the transfer gates TF2 and TF3 maintain the off state, so that the drive voltage Vbp and the drive voltage Vbn stay only charging the power supply unit lines L1 and L2, and the drive voltage Vbp. The drive voltage Vbn is not transmitted to the signal lines L3 and L4.

  After the wake-up period T2 elapses, the active period T3 is started. In the active period T3, even if the standby signal STB maintains “L”, the wakeup signal WUP is changed to “L” and the active signal ACT is changed to “H”. Further, the power supply unit drive signal PON is maintained at “H”.

  Accordingly, in the switch cell group SWG, the PMOS transistor QP1 and the NMOS transistor QN1 are kept off, the transfer gate TF1 is turned off, the transfer gate TF3 is turned on, and the power supply unit lines L1, L1 of the power supply units 1 and 2 are turned on. A drive voltage Vbp and a drive voltage Vbn are supplied from L2.

  With the above settings, the drive voltage Vbp from the power supply unit 1 is supplied to the P body potential line LP via the signal line L3, and the drive voltage Vbn from the power supply unit 2 is supplied to the N body potential line LN via the signal line L4. Is done. As a result, the body potential BVP and the body potential BVN reach the drive voltage Vbp and the drive voltage Vbn. Thereafter, the body potential BVP is stabilized at the drive voltage Vbp, and the body potential BVN is stabilized at the drive voltage Vbn.

  Thus, during the active period T3 after the body potential BVP and the body potential BVN approach the target values of the driving voltage Vbp and the driving voltage Vbn during the wakeup period T2, the driving voltages Vbp and Since the body potential BVP and the body potential BVN are driven by the drive voltage Vbn, it is not necessary to increase the drive current capacity required for the power supply units 1 and 2 so much.

  As described above, the substrate control circuit of the first embodiment uses the capacitive coupling between the capacitance associated with the P body potential line LP and the capacitance associated with the N body potential line LN during the wakeup period T2. In addition, it is possible to restart from sleep and to supply stable body potential BVP and body potential BVN using the small-capacity power supply units 1 and 2. In other words, compared to the CRABC method, there is an advantage that the stability at the time of operation can be secured, and compared to the power supply method, there is an effect that the desired performance can be achieved by using the power units 1 and 2 having a low capacity / low area. .

  Further, prior to the active period T3, the power supply units 1 and 2 are already driven (active) in the second period T22 of the wakeup period T2, so that the power supply unit line L1 and the power supply unit line in the second period T22. L2 can be charged in advance with the driving voltage Vbp and the driving voltage Vbn, respectively.

  Therefore, simultaneously with the start of the active period T3, the charges charged in the power supply unit line L1 and the power supply unit L2 are transmitted to the P body potential line LP and the N body potential line LN via the signal lines L3 and L4. The potential BVP and the body potential BVN can quickly reach the drive voltage Vbp and the drive voltage Vbn after the start of the active period T3. In consideration of this precharging effect, the drive current capacity of the power supply units 1 and 2 can be further reduced.

<Embodiment 2>
FIG. 3 is a timing chart showing a substrate control method by the substrate control circuit according to the second embodiment. The configuration of the substrate control circuit of the second embodiment is the same as that of the first embodiment shown in FIG. 1, and only the generation timing of the active signal ACT and the power supply unit drive signal PON from the control signal generating circuit 3 is different. Hereinafter, a substrate control method by the substrate control circuit according to the second embodiment will be described with reference to FIG.

  First, in the sleep period T1, the standby signal STB is set to “H”, the wakeup signal WUP is set to “L”, the active signal ACT is set to “L”, and the power supply unit drive signal PON is set to “L”. A similar operation is performed.

  Next, in the wakeup period T2, the standby signal STB is changed to “L”, the wakeup signal WUP is changed to “H”, the active signal ACT is changed to “H”, and the power supply unit drive signal PON is changed to “H”. Change to H ".

  Accordingly, in the switch cell group SWG, the PMOS transistor QP1 and the NMOS transistor QN1 are turned off, the transfer gates TF1 to TF3 are turned on, the power supply units 1 and 2 are activated, and the power supply unit 1 is connected to the power supply unit line L1. The drive voltage Vbn is generated, and the power supply unit 2 generates the drive voltage Vbn from the power supply unit line L2.

  With the above setting, the node N1 and the node N2 are electrically connected (short-circuited) via the transfer gate TF1, and the nodes N1 and N2 are connected to the power supply units 1 and 2 via the signal line L3 and the signal line L4. A drive voltage Vbp and a drive voltage Vbn are applied.

  As a result, the charges charged in the wiring and the body region of the PMOS transistor in the control target circuit are transferred to the NMOS transistor side in the control target circuit via the P body potential line LP, the transfer gate TF1, and the N body potential line LN. The body potential BVP and the body potential BVN transition toward the intermediate potential between VDD and GND.

  Furthermore, the body potential BVP is more strongly shifted toward the drive voltage Vbp due to the influence of the drive voltage Vbp supplied from the power supply unit 1, and the body potential BVP is affected by the drive voltage Vbn supplied from the power supply unit 2 to The potential BVN makes a stronger transition toward the drive voltage Vbn.

  Therefore, in the wakeup period T2, when compared with the operation of the first embodiment, the body potential BVP of the second embodiment approaches the drive voltage Vbp, and the body potential BVN approaches the drive voltage Vbn.

  In the active period T3, the standby signal STB is maintained at “L”, the wakeup signal WUP is changed to “L”, and the active signal ACT is maintained at “H”. Further, the power supply unit drive signal PON is maintained at “H”.

  Therefore, in the active period T3, as in the case of the first embodiment, the body potential BVP and the body potential BVN reach the drive voltage Vbp and the drive voltage Vbn, and then the body potential BVP is stabilized at the drive voltage Vbp. BVN is stabilized at the drive voltage Vbn.

  As described above, the substrate control circuit according to the second embodiment sets the wakeup signal WUP to “H” during the wakeup period T2, and also sets the active signal ACT and the power supply unit drive signal PON to “H”. Yes.

  That is, in the wake-up period T2, the first body potential setting operation by turning on the transfer gate TF1 and short-circuiting between the nodes N1 and N2, and turning on the transfer gates TF2 and TF3 to the nodes N1 and N2. The second body potential setting operation by supplying the drive voltage Vbp and drive voltage Vbn from the power supply units 1 and 2 is also performed.

  As a result, the substrate control circuit according to the second embodiment that performs the first and second body potential setting operations has the following effects compared to the first embodiment that performs only the first body potential setting operation.

  When the length of the wake-up period T2 is set to be the same between the first embodiment and the second embodiment, the second embodiment is configured to set the body potential BVP and the body potential BVN to the target values (driving) during the wake-up period T2. The voltage Vbp and the drive voltage Vbn) can be brought close to each other.

  Further, when the target set potential in the wake-up period T2 is set to the same condition as in the first embodiment, the effect of the second embodiment can shorten the length of the wake-up period T2 compared to the first embodiment. Play.

<Embodiment 3>
(First layout configuration)
FIG. 4 is an explanatory diagram showing a first layout configuration of the semiconductor integrated circuit according to the third embodiment of the present invention. As shown in the figure, the semiconductor integrated circuit according to the third embodiment includes the substrate control circuit and the control target circuit according to the first or second embodiment. For convenience of explanation, illustration of the control signal generation circuit 3 is omitted.

  As shown in the figure, under the control of one unit substrate control circuit (power supply units 1 and 2 and switch cell group SWG (control signal generation circuit not shown)), a matrix (12 × 5 (rows r1 to r5)) The substrate potential of each of the plurality of circuit blocks CB (control target circuit) arranged in () is controlled. Each circuit block CB means a logic circuit such as an AND gate or a flip-flop having at least one MOS transistor, for example. In order to clarify the configuration of one unit of the circuit block CB, only the upper right one of the plurality of circuit blocks CB is illustrated by lattice-shaped hatching, and the other portions are illustrated by hatching. It should be noted that the same hatching is also performed in the drawings of the layout configuration shown below.

  As shown in the figure, the P body potential line LP and the N body potential line LN are wired to all circuit blocks CB. Also, a VDD wiring LV that supplies the power supply voltage VDD and a GND wiring LG that is set to the GND level are wired for each of the columns r1 to r5.

  FIG. 5 is a cross-sectional view taken along the line AA of FIG. The structure shown in FIG. 5 is a cross-sectional structure of the circuit block CB4 and the circuit block CB5 adjacent to each other between the columns r4 and r5.

  As shown in the figure, an N well region 12 is selectively formed in the central portion of the upper layer portion of the P well region 11 formed in the upper layer portion of the semiconductor substrate 10.

A P ⁺ diffusion region 13 and N ⁺ diffusion regions 14 and 15 are selectively formed in the upper layer portion of the P well region 11 of the circuit block CB4, and a gate is formed on the surface of the P well region 11 between the N ⁺ diffusion regions 14 and 15. Gate electrode 31 is formed through an oxide film (not shown).

The N ⁺ diffusion regions 14 and 15 and the gate electrode 31 constitute an NMOS transistor Q42, and the P ⁺ diffusion region 13 functions as a body contact region for setting the body potential of the NMOS transistor Q42.

Similarly, P ⁺ diffusion region 23, N ⁺ diffusion regions 24 and 25 are selectively formed in an upper layer portion of the P-well region 11 of the circuit block CB5, N ⁺ between the diffusion regions 24 and 25 of the P-well region 11 A gate electrode 34 is formed on the surface via a gate oxide film (not shown).

The N ⁺ diffusion regions 24 and 25 and the gate electrode 34 constitute an NMOS transistor Q52, and the P ⁺ diffusion region 23 functions as a body contact region for setting the body potential of the NMOS transistor Q52.

On the other hand, N ⁺ diffusion region 18 is formed at the center of the upper layer in N well region 12 (on the boundary between circuit blocks CB4 and CB5). Then, P ⁺ diffusion regions 16 and 17 are selectively formed in the upper layer portion of the N well region 12 on the circuit block CB4 side across the N ⁺ diffusion region 18, and are formed in the upper layer portion of the N well region 12 on the circuit block CB5 side. P ⁺ diffusion regions 26 and 27 are selectively formed.

Then, a gate electrode 32 is formed on the surface of the N well region 12 between the P ⁺ diffusion regions 16 and 17 via a gate oxide film (not shown). The PMOS is formed by the P ⁺ diffusion regions 16 and 17 and the gate electrode 32. Transistor Q41 is configured.

Similarly, the gate electrode 33 is formed via a gate oxide film (not shown) on the surface of the N-well region 12 between the P ⁺ diffusion regions 26 and 27, P ⁺ diffusion regions 26, 27 and the gate electrode 33 As a result, a PMOS transistor Q51 is formed.

The N ⁺ diffusion region 18 is shared by the PMOS transistors Q41 and Q51, and functions as a body contact region for setting the body potential of the PMOS transistors Q41 and Q51.

Further, a wiring 41 (corresponding to the N body potential line LN) is formed on the P ⁺ diffusion region 13, and a wiring 42 (corresponding to the GND wiring LG) is formed on the N ⁺ diffusion region 14. N ⁺ diffusion region 15 and P ⁺ diffusion region 16 are electrically connected by wiring 43.

Wiring 44 (corresponding to VDD wiring LV) is formed on P ⁺ diffusion region 17, wiring 45 (corresponding to P body potential line LP) is formed on N ⁺ diffusion region 18, and wiring is formed on P ⁺ diffusion region 27. 46 (corresponding to VDD wiring LV) is formed. The P ⁺ diffusion region 26 and the N ⁺ diffusion region 25 are electrically connected by a wiring 47.

Further, a wiring 48 (corresponding to the GND wiring LG) is formed on the N ⁺ diffusion region 24, and a wiring 49 (corresponding to the N body potential line LN) is formed on the P ⁺ diffusion region 23.

  A body potential BVN is applied to the wirings 41 and 49, a ground level is applied to the wirings 42 and 48, a power supply voltage VDD is applied to the wirings 44 and 46, and a body potential BVP is applied to the wiring 45. The

  As described above, the circuit block CB4 (CB5) includes the CMOS-structured PMOS transistor Q41 (Q51) and the NMOS transistor Q42 (Q52), and the same MOS transistor type (PMOS transistor) centering on the boundary between the columns r4 and r5. A P body potential line LP is formed between the PMOS transistors Q41 and Q51 that are formed symmetrically and are adjacent to each other across the boundaries of the columns r4 and r5.

  Thus, the first layout configuration of the third embodiment has a relationship in which the PMOS transistors are adjacent (first adjacent circuit relationship) between the circuit blocks CB in the columns r4 and r5, and the body potential line LP is shared. Wired as possible. Similarly, in the columns r2 and r3, PMOS transistors are formed adjacent to each other, and the P body potential line LP is sharable.

  On the other hand, the adjacent MOS types are NMOS transistors between the columns r1, r2, and r3, r4, and the N body potential line LN is sharable. In other words, the NMOS transistors are adjacent to each other between the columns r1, r2 and r3, r4 (second adjacent circuit relationship).

  As described above, in the first layout configuration of the third embodiment, the switch cell group SWG is concentratedly arranged at one place, so that the layout can be easily performed.

  In addition, in the first layout configuration, the P body potential line LP or the body potential line LN is sharable between the circuit blocks CB having a relationship in which PMOS transistors or NMOS transistors are adjacently arranged in the column direction. ing. Therefore, the number of P body potential lines LP and N body potential lines LN to be branched can be suppressed to three for the circuit block groups in the columns r1 to r5, and the degree of integration can be improved.

(Second layout configuration)
FIG. 6 is an explanatory diagram showing a second layout configuration of the semiconductor integrated circuit according to the third embodiment of the present invention.

  As shown in the figure, in the second layout configuration, similarly to the first layout configuration, one unit of substrate control circuit (power supply units 1 and 2 and switch cell group SWG (including control signal generation circuit 3 not shown)). ), The substrate potentials of the plurality of circuit blocks CB arranged in a matrix (12 × 5 (columns r1 to r5)) are controlled.

  As shown in the figure, the P body potential line LP and the N body potential line LN are wired to all circuit blocks CB. Further, the VDD wiring LV that supplies the power supply voltage VDD in units of columns r1 to r5 and the GND wiring LG that is set to the GND level are wired in common.

  The circuit block CB in the second layout configuration has a relationship in which the PMOS transistors are adjacently arranged between the columns r2, r3 and r4, r5, as in the first layout configuration.

  However, in the second layout configuration, the body potential line LP is branched corresponding to the columns r2 and r3, and the body potential line LP is branched corresponding to the columns r4 and r5. Instead, the VDD wiring LV is sharable between the columns r2 and r3 and the columns r4 and r5.

  Further, NMOS transistors are arranged adjacent to each other between the columns r1 and r2 and the columns r3 and r4, as in the first layout configuration.

  However, in the second layout configuration, N body potential lines LN are branched and wired corresponding to columns r1 and r2, and body potential lines LN are branched and wired corresponding to columns r3 and r4, respectively. Instead, the VDD wiring LV is sharable between the columns r2 and r3 and the columns r4 and r5.

  As described above, in the second layout configuration according to the third embodiment, the switch cell group SWG is concentrated in one place as in the first layout configuration, so that the layout can be easily performed.

  In addition, in the second layout configuration, the VDD wiring LV or the GND wiring LG is shared between the circuit blocks CB arranged adjacent to each other in the column direction. The number of branch lines of the wiring LV and the GND wiring LG can be suppressed to three.

  Further, the P body potential line LP is branched and wired corresponding to the column in which the PMOS transistor is formed adjacently, and the N body potential line LN is branched and wired corresponding to the column in which the NMOS transistor is formed adjacently. The wiring length required for the potential line LP and the N body potential line LN can be shortened.

<Embodiment 4>
(First layout configuration)
FIG. 7 is an explanatory diagram showing a first layout configuration of the semiconductor integrated circuit according to the fourth embodiment of the present invention. As shown in the figure, the semiconductor integrated circuit according to the fourth embodiment is configured to include the substrate control circuit and the control target circuit according to the first or second embodiment.

  As shown in the figure, a substrate control circuit comprising one unit of power supply units 1 and 2 (including a control signal generation circuit 3 not shown) and three units of switch cell groups SWG1 to SWG3 (a predetermined number of switch cell groups). Under the control, the substrate potential of each of the plurality of circuit blocks CB arranged in a matrix (12 × 5 (columns r1 to r5)) is controlled.

  As shown in the figure, the power supply unit line L1 from the power supply unit 1 is commonly connected to the switch cell groups SWG1 to SWG3, and the power supply unit line L2 from the power supply unit 2 is commonly connected to the switch cell groups SWG1 to SWG3. The The internal structure of each of switch cell groups SWG1 to SWG3 is the same as that of the first embodiment shown in FIG. 1, and P body potential lines LP and N body potential lines LN in FIG. The first body potential lines) and N body potential lines LN1 to LN3 (a predetermined number of second body potential lines).

  That is, the switch cell groups SWG1 to SWG3 each include a PMOS transistor QP1, an NMOS transistor QN1, transfer gates TF1 to TF3, and nodes N1 and N2. However, a standby signal STB, a wakeup signal WUP, and an active signal ACT output from a control signal generation circuit 3 (not shown) are commonly applied to the switch cell groups SWG1 to SWG3.

  As shown in the figure, a VDD wiring LV for supplying the power supply voltage VDD and a GND wiring LG set to the GND level are wired for each of the columns r1 to r5.

  The first layout configuration of the fourth embodiment has a relationship in which PMOS transistors are formed adjacent to each other between the columns r2 and r3 and between the columns r4 and r5, similarly to the first layout configuration of the third embodiment. The NMOS transistors are adjacently formed between the columns r1 and r2 and between the columns r3 and r4.

  The body potential lines LP2 and LP3 are sharable between the columns r2 and r3 and between the columns r4 and r5, and the N body potential lines LN1 and LN2 are sharable between the columns r1 and r2 and between the columns r3 and r4. Wired.

  As described above, in the first layout configuration according to the fourth embodiment, the switch cell groups SWG1 to SWG3 are distributed and arranged in two circuit blocks CB at a ratio of one, so that the transfer of each of the switch cell groups SWG1 to SWG3 is performed. The drive current of the gates TF1 to TF3 can be dispersed. For this reason, the drive capability required for the transfer gates TF to TF3 can be reduced.

  In addition, in the first layout configuration, any one of the P body potential lines LP1 to LP3 and the N body potential lines LN1 to LN3 is sharable between the circuit blocks CB arranged adjacent to each other in the column direction. Can do. Therefore, each of the switch cell groups SWG1 to SWG3 can be formed without branching the pair of P body potential lines LP1 to LP3 and N body potential lines LN1 to LN3 between different columns, thereby improving the degree of integration. Can do.

  Further, due to the distributed arrangement of the switch cell groups SWG1 to SWG3, the wiring length of the power supply unit line L1 and the power supply unit line L2 becomes longer than that of the layout configuration of the third embodiment, and the wiring capacity increases. However, in the substrate control circuit of the first embodiment, since the drive voltage Vbp and the drive voltage Vbn are charged to the power supply unit lines L1 and L2 during the second period T22 of the wakeup period T2, the power supply unit lines L1 and L2 There is an advantage that the increase in the wiring capacity of the above leads to an improvement in driving force during the active period T3, and there are not many negative aspects.

(Second layout configuration)
FIG. 8 is an explanatory diagram showing a second layout configuration of the semiconductor integrated circuit according to the fourth embodiment of the present invention.

  As shown in the figure, in the second layout configuration, similarly to the first layout configuration, one unit of power supply units 1 and 2 and three units of switch cell groups SWG1 to SWG3 constitute a substrate control circuit. Under the control of the substrate control circuit, substrate potentials of a plurality of circuit blocks CB arranged in a matrix (12 × 5 (columns r1 to r5)) are controlled.

  As shown in the figure, similarly to the first layout configuration, the power supply unit lines L1 and L2 from the power supply units 1 and 2 are commonly connected to the switch cell groups SWG1 to SWG3. The internal configuration of each of the switch cell groups SWG1 to SWG3 is the same as that of the first embodiment shown in FIG.

  The P body potential line LP1 from the switch cell group SWG1 is wired corresponding to the circuit block CB in the column r1, and the N body potential line LN1 is branched corresponding to the circuit block CB in the columns r1 and r2. . The P body potential line LP2 from the switch cell group SWG2 is branched and wired corresponding to the circuit blocks CB of the columns r2 and r3, and the N body potential line LN2 corresponds to the circuit blocks CB of the columns r3 and r4. Branch wiring. Switch body group SWG3 to P body potential line LP3 are branched and wired corresponding to circuit blocks CB in columns r4 and r5, and N body potential line LN3 is wired to correspond to circuit block CB in column r5.

  Further, the VDD wiring LV that supplies the power supply voltage VDD in units of columns r1 to r5 and the GND wiring LG that is set to the GND level are wired in common.

  In the circuit block CB in the second layout configuration of the fourth embodiment, a PMOS transistor is adjacently disposed between the columns r2, r3 and r4, r5, as in the second layout configuration of the third embodiment, and the VDD wiring LV Wiring is shared.

  Further, between the columns r1 and r2 and the columns r3 and r4, as in the second layout configuration of the third embodiment, NMOS transistors are arranged adjacent to each other and share the GND wiring LG.

  As described above, in the second layout configuration of the fourth embodiment, the drive capability required for the transfer gates TF to TF3 can be reduced as in the first layout configuration.

  In addition, in the second layout configuration, the VDD wiring LV or the GND wiring LG is shared between the circuit blocks CB arranged adjacent to each other in the column direction. Since the number of wirings LV and GND wiring LG can be reduced to three each, the degree of integration can be improved.

  One of the P body potential lines LP1 to LP3 is branched corresponding to the column in which the PMOS transistor is adjacently formed, and one of the N body potential lines LN1 to LN3 is associated with the column in which the NMOS transistor is adjacently formed. Branching wiring, the wiring length required for the P body potential lines LP1 to LP3 and the N body potential lines LN1 to LN3 can be shortened.

(Third layout configuration)
FIG. 9 is an explanatory diagram showing a third layout configuration of the semiconductor integrated circuit according to the fourth embodiment of the present invention.

  As shown in the figure, the third layout configuration includes one unit of power supply units 1 and 2 (including a control signal generation circuit 3 not shown) and an active switch unit ACTSW and three units of wakeup switch units WUPSW1 to WUPSW3 ( A substrate control circuit is constituted by a predetermined number of wake-up switch units). Under the control of the substrate control circuit, substrate potentials of a plurality of circuit blocks CB arranged in a matrix (12 × 5 (columns r1 to r5)) are controlled.

  As shown in the figure, the power supply unit line L1 from the power supply unit 1 is connected to the active switch unit ACTSW, and the power supply unit line L2 from the power supply unit 2 is connected to the active switch unit ACTSW.

  Signal lines L3 and L4 from the active switch unit ACTSW are commonly connected to the wakeup switch units WUPSW1 to WUPSW3. The configuration of the combination circuit of the active switch unit ACTSW and the wakeup switch unit WUPSWi (i = 1 to 3) is the same as that of the first embodiment shown in FIG.

  Note that a standby signal STB and a wakeup signal WUP from a control signal generation circuit 3 (not shown) are commonly applied to the wakeup switch units WUPSW1 to WUPSW3.

  As described above, in the first and second layout configurations, the entire switch cell group SWG is dispersedly arranged in three, whereas in the third layout configuration, the active switch unit ACTSW is located in one place in the switch cell group SWG. The difference is that three wakeup switch units WUPSW are distributed in a centralized manner.

  The internal configuration of each of wakeup switch units WUPSW1 to WUPSW3 is the same as that of wakeup switch unit WUPSW of the first embodiment shown in FIG. 1, and P body potential line LP and N body potential line LN in FIG. This corresponds to the lines LP1 to LP3 and the N body potential lines LN1 to LN3. That is, each of the wakeup switch units WUPSW1 to WUPSW3 includes a PMOS transistor QP1, an NMOS transistor QN1, a transfer gate TF1, a node N1, and a node N2.

  The P body potential line LP1 from the wakeup switch unit WUPSW1 is wired corresponding to the circuit block CB in the column r1, and the N body potential line LN1 is branched corresponding to the circuit block CB in the columns r1 and r2. The Further, the P body potential line LP2 from the wakeup switch section WUPSW2 is branched and wired corresponding to the circuit blocks CB in the columns r2 and r3, and the N body potential line LN2 corresponds to the circuit blocks CB in the columns r3 and r4. Branch wiring. The wake-up switch unit WUPSW3 to the P body potential line LP3 are branched and wired corresponding to the circuit blocks CB in the columns r4 and r5, and LN3 is wired to the circuit block CB in the column r5.

  Further, the VDD wiring LV that supplies the power supply voltage VDD in units of columns r1 to r5 and the GND wiring LG that is set to the GND level are wired in common.

  In the circuit block CB in the third layout configuration of the fourth embodiment, a PMOS transistor is adjacently disposed between the columns r2, r3 and r4, r5, as in the second layout configuration of the third embodiment, and the VDD wiring LV Wiring is shared.

  Similarly to the second layout configuration of the third embodiment, NMOS transistors are adjacently arranged between the columns r1 and r2 and the columns r3 and r4, and the GND wiring LG is sharable.

  As described above, in the third layout configuration of the fourth embodiment, the wakeup switch units WUPSW1 to WUPSW3 are distributed and arranged at a ratio of one to two circuit blocks CB. Therefore, the wakeup switch units WUPSW1 to WUPSW3 The drive current of the transfer gate TF1 can be distributed. For this reason, it is possible to reduce the drive capability required for the transfer gate TF1.

  Further, the degree of integration can be improved in the third layout configuration compared to the first and second layout configurations by limiting the symmetry to be distributed not only to the entire switch cell group SWG but only to the wakeup switch unit WUPSW. .

  In addition, in the third layout configuration, as in the first and second layout configurations, by sharing the VDD wiring LV or the GND wiring LG between the circuit blocks CB arranged adjacent to each other in the column direction, With respect to the circuit block groups r1 to r5, the number of VDD wirings LV and GND wirings LG can be suppressed to three and the degree of integration can be improved.

<Embodiment 5>
(First layout configuration)
FIG. 10 is an explanatory diagram showing a first layout configuration of the semiconductor integrated circuit according to the fifth embodiment of the present invention.

  As shown in the figure, the first layout configuration includes one unit of power supply units 1 and 2 (including a control signal generation circuit 3 not shown) and nine units of switch cell groups SWG11 to SWG13, SWG21 to SWG23, and SWG31. A substrate control circuit is configured by SWG 33 (hereinafter, sometimes simply abbreviated as “9 units of SWG”; a predetermined number of switch cell groups). Under the control of the substrate control circuit, the substrate potentials of the plurality of circuit blocks CB each composed of groups g1 to g3 arranged in a matrix (3 × 5 (columns r1 to r5)) are controlled.

  The switch cell groups SWG11, SWG21, and SWG31 are provided corresponding to the group g1, the switch cell groups SWG12, SWG22, and SWG32 are provided corresponding to the group g2, and the switch cell groups SWG13, SWG23, and SWG33 are included in the group g3. Correspondingly provided.

  As shown in the figure, the power supply unit line L1 from the power supply unit 1 is commonly connected to 9 units of SWG, and the power supply unit line L2 from the power supply unit 2 is commonly connected to 9 units of SWG. The internal configuration of each of the switch cell groups SWG11 to SWG13, SWG21 to SWG23, SWG31 to SWG33 is the same as that of the first embodiment shown in FIG. Further, the P body potential line LP and the N body potential line LN in FIG. 1 are replaced with the P body potential lines LP11 to LP13, LP21 to LP23, LP31 to LP33 (a predetermined number of first body potential lines) and N body potential lines LN11 to LN11. This corresponds to LN13, LN21 to LN23, and LN31 to LN33 (a predetermined number of second body potential lines).

  That is, each of the 9 units of SWG includes a PMOS transistor QP1, an NMOS transistor QN1, transfer gates TF1 to TF3, and nodes N1 and N2. Note that a standby signal STB, a wake-up signal WUP, and an active signal ACT are commonly given to nine units of SWG from a control signal generation circuit 3 (not shown).

  The switch cell groups SWG11, SWG21, and SWG31 are grouped as g1, the switch cell groups SWG12, SWG22, and SWG32 are grouped as g2, and the switch cell groups SWG13, SWG23, and SWG33 are grouped as g3. .

  Corresponding to the groups g1 to g3, a plurality of circuit blocks CB are also distributed and arranged in groups g1 to g3. In this manner, 9 units of SWGs and a plurality of circuit blocks CB are distributed in groups of three classification numbers.

  Further, the switch body groups SWG11 to SWG13 to P body potential lines LP11 to LP13 are wired to the circuit block CB in the column r1 in the groups g1 to g3, and the N body potential lines LN11 to LN13 are connected to the columns r1 and r2 in the groups g1 to g3. It is wired so that it can be shared between circuit blocks CB. The P body potential lines LP21 to LP23 from the switch cell groups SWG21 to SWG23 are sharable between the circuit blocks CB in the columns r2 and r3 in the groups g1 to g3, and the N body potential lines LN21 to LN23 are grouped to the groups g1 to g3. Wiring is shared between the circuit blocks CB in columns r3 and r4 in g3. P body potential lines LP31 to LP33 are wired so that they can be shared among circuit blocks CB in columns r4 and r5 in groups g1 to g3, and N body potential lines LN31 to LN33 are wired to circuit blocks CB in column r5 in groups g1 to g3. The

  Although not shown in FIG. 10, the VDD wiring LV that supplies the power supply voltage VDD in units of the columns r1 to r5 of the groups g1 to g3 and the GND wiring LG that is set to the GND level are wired in common. The

  As described above, the circuit blocks CB of the groups g1 to g3 in the first layout configuration of the fifth embodiment are similar to the first layout configuration of the third embodiment between the columns r2 and r3 and the columns r4 and r5. , PMOS transistors are arranged adjacent to each other. Therefore, the circuit blocks CB of the groups g1 to g3 can be wired so that the P body potential lines LP21 to LP23 and the P body potential lines LP31 to LP33 can be shared between the columns r2 and r3 and the columns r4 and r5.

  In each of the circuit blocks CB of the groups g1 to g3, NMOS transistors are adjacently arranged between the columns r1 and r2 and the columns r3 and r4 as in the first layout configuration of the third embodiment. Therefore, the N body potential lines LN1 to LN3 and the N body potential lines LN21 to LN23 can be shared between the columns r1 and r2 and the columns r3 and r4.

  Thus, in the first layout configuration of the fifth embodiment, 9 units of SWG are distributed to groups g1 to g3 for each of the three switch cell groups SWG, and two columns in groups g1 to g3 are further distributed. One is arranged in the circuit block CB. Therefore, the drive currents of the transfer gates TF1 to TF3 of the switch cell groups SWG11 to SWG13, SWG21 to SWG23, and SWG31 to SWG33 can be dispersed. As a result, the drive capability required for the transfer gates TF1 to TF3 can be reduced.

  Further, 9 units of SWG and a plurality of circuit blocks CB are distributed and arranged in three groups g1 to g3. Therefore, the RC path charged / discharged by the transfer gate TF1 can be shortened by shortening the wiring distance from the PMOS transistor QP1 (NMOS transistor QN1) to the body (NMOS transistor body) of the PMOS transistor to be controlled. The change time constant of the body potential of each MOS transistor can be made uniform.

  In addition, in the first layout configuration, the P body potential lines LP1i to LP3i and the N body are arranged between the circuit blocks CB arranged adjacent to each other in the column direction for each group gi (i = 1 to 3). Any one of the potential lines LN1i to LN3i is wired so as to be shared. Therefore, each of the switch cell groups SWG1i to SWG3i can be formed without branching the pair of P body potential lines LP1i to LP3i and N body potential lines LN1i to LN3i between different columns, thereby improving the degree of integration. Can do.

(Second layout configuration)
FIG. 11 is an explanatory diagram showing a second layout configuration of the semiconductor integrated circuit according to the fifth embodiment of the present invention.

  As shown in the figure, the second layout configuration includes one unit of power supply units 1 and 2 (including the control signal generation circuit 3), an active switch unit ACTSW, and nine units of wakeup switch units WUPSW11 to WUPSW13, WUPSW21 to The substrate control circuit is configured by the WUPSW 23 and the WUPSW 31 to WUPSW 33 (hereinafter sometimes simply referred to as “9 units of WUPSW”). Under the control of the substrate control circuit, the substrate potentials of the plurality of circuit blocks CB each composed of groups g1 to g3 arranged in a matrix (3 × 5 (columns r1 to r5)) are controlled.

  The wakeup switch units WUPSW11, WUPSW21 and WUPSW31 are provided corresponding to the group g1, the wakeup switch units WUPSW12, WUPSW22 and the switch cell group SWG32 are provided corresponding to the group g2, and the wakeup switch units WUPSW13, WUPWS23. And WUPSW 33 are provided corresponding to the group g3.

  As shown in the figure, the power supply unit line L1 from the power supply unit 1 and the power supply unit line L2 from the power supply unit 2 are connected to the active switch unit ACTSW. The signal line L3 and the signal line L4 of the active switch unit ACTSW are commonly connected to 9 units of WUPSW. The configuration of the combination circuit of the active switch unit ACTSW and the wakeup switch unit WUPSWij (i, j = 1 to 3) is the same as that of the first embodiment shown in FIG.

  That is, each 9-unit WUPSW has a PMOS transistor QP1, an NMOS transistor QN1, a transfer gate TF1, a node N1, and a node N2. Note that a standby signal STB and a wakeup signal WUP generated by a control signal generation circuit 3 (not shown) are commonly applied to 9 units of WUPSW.

  The P body potential line LP and the N body potential line LN in FIG. 1 correspond to the P body potential lines LP11 to LP13, LP21 to LP23, LP31 to LP33, and the N body potential lines LN11 to LN13, LN21 to LN23, LN31 to LN33.

  The P body potential lines LP11 to LP13 from the wakeup switch sections WUPSW11 to WUPSW13 are wired to the circuit block CB of the column r1 in the groups g1 to g3, and the N body potential lines LN11 to LN13 are the circuit blocks CB of the columns r1 and r2. Wiring is shared between them.

  Further, P body potential lines LP21 to LP23 from wakeup switch sections WUPSW21 to WUPSW23 are wired so as to be sharable between circuit blocks CB of columns r2 and r3 in groups g1 to g3. N body potential lines LN21 to LN23 are wired so that they can be shared among circuit blocks CB of columns r3 and r4 in groups g1 to g3. P body potential lines LP31 to LP33 are wired so that they can be shared between circuit blocks CB of columns r4 and r5 in groups g1 to g3. N body potential lines LN31 to LN33 are wired to circuit block CB in column r5 in groups g1 to g3.

  Although not shown in FIG. 11, the VDD wiring LV that supplies the power supply voltage VDD in units of the columns r1 to r5 of the groups g1 to g3 and the GND wiring LG that is set to the GND level are wired in common. The

  In each of the circuit blocks CB of the groups g1 to g3 in the second layout configuration of the fifth embodiment, the PMOS transistors are arranged between the columns r2 and r3 and the columns r4 and r5 as in the first layout configuration of the third embodiment. The P body potential lines LP21 to LP23 and the P body potential lines LP31 to LP33 are arranged adjacent to each other so as to be shared.

  Further, in each of the circuit blocks CB of the groups g1 to g3, NMOS transistors are arranged adjacently between the columns r1 and r2 and the columns r3 and r4 as in the first layout configuration of the third embodiment, and the N body potential line LN11. ˜LN13 and N body potential lines LN21˜LN23 are sharable.

  As described above, in the second layout configuration of the fifth embodiment, 9 units of WUPSW are distributed to each of the groups g1 to g3 for each of the three wakeup switch units WUPSWWG, and further, two columns in each of the groups g1 to g3 are arranged. One is arranged in the circuit block CB. For this reason, the drive current of the transfer gate TF1 of each of 9 units of WUPSW can be dispersed, and the drive capability required for the transfer gate TF1 can be reduced.

  Furthermore, by disposing 9 units of WUPSW in a distributed manner, the RC path charged / discharged by the transfer gate TF1 can be shortened, as in the first layout configuration, and the change time constant of the body potential between the MOS transistors to be body controlled Can be made uniform.

  In addition, since the distribution symmetry is limited not to the entire switch cell group SWG but only to the wakeup switch unit WUPSW, the second layout configuration can improve the degree of integration compared to the first layout configuration.

  In the second layout configuration, as in the first layout configuration, the P body potential is set between the circuit blocks CB arranged adjacent to each other in the column direction in each group gi (i = 1 to 3). Any one of the lines LP1i to LP3i and the N body potential lines LN1i to LN3i is wired so as to be shared. Therefore, the pair of P body potential lines LP1i to LP3i and N body potential lines LN1i to LN3i can be formed without branching between different columns, and the degree of integration can be improved.

It is a circuit diagram which shows the structure of the board | substrate control circuit which is Embodiment 1 of this invention. FIG. 3 is a timing diagram illustrating an operation of the substrate control circuit according to the first embodiment. FIG. 10 is a timing diagram illustrating an operation of the substrate control circuit according to the second embodiment. It is explanatory drawing which shows the 1st layout structure of the semiconductor integrated circuit which is Embodiment 3 of this invention. It is sectional drawing which shows the AA cross section of FIG. It is explanatory drawing which shows the 2nd layout structure of the semiconductor integrated circuit which is Embodiment 3 of this invention. It is explanatory drawing which shows the 1st layout structure of the semiconductor integrated circuit which is Embodiment 4 of this invention. It is explanatory drawing which shows the 2nd layout structure of the semiconductor integrated circuit which is Embodiment 4 of this invention. It is explanatory drawing which shows the 3rd layout structure of the semiconductor integrated circuit which is Embodiment 4 of this invention. It is explanatory drawing which shows the 1st layout structure of the semiconductor integrated circuit which is Embodiment 5 of this invention. It is explanatory drawing which shows the 2nd layout structure of the semiconductor integrated circuit which is Embodiment 5 of this invention.

Explanation of symbols

  1, 2 power supply units, 3 control signal generation circuit, ACTSW active switch section, CB circuit block, L1, L2 power supply unit lines, LN, LN1 to LN3, LN11 to LN13, LN21 to LN23, LN31 to LN33 N body potential lines, LP, LP1 to LP3, LP11 to LP13, LP21 to LP23, LP31 to LP33 P body potential lines, SWG, SWG1 to SWG3, SWG11 to SWG13, SWG21 to SWG23, SWG31 to SWG33 switch cell group, TF1 to TF3 transfer gate, WUPSW , WUPSW1-WUPSW3 Wake-up switch part.

Claims (15)

A substrate control circuit for supplying first and second body potentials for potential setting of body regions of PMOS and NMOS transistors to be controlled,
The substrate control circuit is
A first voltage supply circuit for supplying a first drive voltage in an active state;
A second voltage supply circuit for supplying a second drive voltage lower than the first drive voltage in an active state;
A switch cell group connected to the outputs of the first and second voltage supply circuits and receiving the first and second drive voltages when the first and second voltage supply circuits are in an active state,
The switch cell group includes:
A first switching unit having one end supplied with a first power supply voltage higher than the first drive voltage and the other end connected to a first node;
A second power supply voltage having one end supplied with a second power supply voltage lower than the second drive voltage and the other end connected to a second node, and obtained from the first and second nodes. The potential becomes the first and second body potentials,
Third switching means interposed between the first and second nodes;
A fourth switching means having one end connected to the output of the first voltage supply circuit and the other end connected to the first node;
A fifth switching means having one end connected to the output of the second voltage supply circuit and the other end connected to the second node;
The substrate control circuit is
When the control object is in a standby state, the first and second switching means are set to an on state, the third to fifth switching means are set to an off state, and the first and second power supply voltages are set to the first state. And performing a first control operation with a second body potential,
In the wake-up period, which is a predetermined period during which the control target shifts from the standby state to the operating state, the second switching unit sets the first and second switching units to the off state and the third switching unit to the second state. Execute the control action of
In the operation state of the controlled object after the lapse of the way-up period, the first and second voltage supply circuits are activated, the fourth and fifth switching means are turned on, and the first to third The switching means is set in an off state, and the first and second drive voltages are set as the first and second body potentials.
Board control circuit. The substrate control circuit according to claim 1,
The outputs of the first and second voltage supply circuits and one ends of the fourth and fifth switching means are connected via first and second voltage supply lines,
The substrate control circuit is
The fourth and fifth switching means are set in an off state during the wakeup period, and the first and second voltage supply circuits are set in an active state at least by the end of the wakeup period.
Board control circuit. The substrate control circuit according to claim 1,
The substrate control circuit is
During the wakeup period, the fourth and fifth switching means are set in an on state, and the first and second voltage supply circuits are set in an active state.
Board control circuit. The substrate control circuit according to any one of claims 1 to 3,
A plurality of control target circuits each having at least one MOS transistor to be controlled;
The plurality of control target circuits receive the first and second body potentials in common;
Semiconductor integrated circuit. A semiconductor integrated circuit according to claim 4, wherein
A first body potential line and a second body potential line connected to the first and second nodes of the substrate control circuit and wired corresponding to the plurality of control target circuits;
The plurality of control target circuits have a first adjacent circuit relationship having a PMOS transistor adjacent or a second adjacent circuit relationship having an NMOS transistor adjacent between circuits adjacent in a predetermined direction,
The first body potential line is sharable between the control target circuits having the first adjacent circuit relationship,
The second body potential line is sharable between the control target circuits having the second adjacent circuit relationship,
Semiconductor integrated circuit. A semiconductor integrated circuit according to claim 4, wherein
A first body potential line and a second body potential line connected to the first and second nodes of the substrate control circuit and wired corresponding to the plurality of control target circuits;
The plurality of control target circuits have a first adjacent circuit relationship having a PMOS transistor adjacent or a second adjacent circuit relationship having an NMOS transistor adjacent between circuits adjacent in a predetermined direction,
The first body potential line is branched corresponding to the control target circuit having the first adjacent circuit relationship,
The second body potential line is branched corresponding to the control target circuit having the second adjacent circuit relationship;
Semiconductor integrated circuit. A semiconductor integrated circuit comprising the substrate control circuit according to any one of claims 1 to 3,
Each of the switch cell groups in the substrate control circuit includes the first and second nodes and the first to fifth switching, and the first and second voltage supply circuits provide first and second switching circuits. Including a predetermined number of switch cell groups that commonly receive the drive voltage of
The semiconductor integrated circuit is:
A plurality of control target circuits each having at least one MOS transistor that is a body potential control target;
A predetermined number of first and second body potential lines connected to the first and second nodes of the predetermined number of switch cell groups SWG and wired corresponding to the plurality of control target circuits; ,
The plurality of control target circuits receive the first and second body potentials via the predetermined number of first and second body potential lines;
Semiconductor integrated circuit. A semiconductor integrated circuit according to claim 7, wherein
The predetermined number of switch cell groups constitutes a predetermined number of groups, and is distributed and arranged in units of the predetermined number of classifications,
The plurality of control target circuits are distributed and arranged in units of the predetermined classification number corresponding to the predetermined classification number group in the predetermined number of switch cell groups,
The plurality of control target circuits, for each group unit of the predetermined classification number, out of the predetermined number of first and second body lines via the first and second body lines in a corresponding group. Receiving first and second body potentials;
Semiconductor integrated circuit. A semiconductor integrated circuit comprising the substrate control circuit according to any one of claims 1 to 3,
The switch cell group in the substrate control circuit includes a wake-up switch unit including the first and second nodes and the first to third switching units, and an active switch unit including the fourth and fifth switching units. Including
Each of the wake-up switch units has the first and second nodes and the first to third switching, and each of the first and second nodes is the fourth and fifth switching means. A predetermined number of wake-up switch units connected in common with the other end of
The semiconductor integrated circuit is:
A plurality of control target circuits each having at least one MOS transistor that is a body potential control target;
A predetermined number of first and second body potential lines connected to the first and second nodes of the predetermined number of wake-up switch sections and wired corresponding to the plurality of control target circuits; ,
The plurality of control target circuits receive the first and second body potentials via the predetermined number of first and second body potential lines;
Semiconductor integrated circuit. A semiconductor integrated circuit according to claim 9, wherein
The predetermined number of wake-up switch units constitute a predetermined number of groups, and are distributed in units of the predetermined number of groups,
The plurality of control target circuits are distributed and arranged in units of the predetermined number of groups corresponding to the predetermined number of groups in the predetermined number of wakeup switch units,
The plurality of control target circuits, for each group unit of the predetermined classification number, out of the predetermined number of first and second body lines via the first and second body lines in a corresponding group. Receiving first and second body potentials;
Semiconductor integrated circuit. A semiconductor integrated circuit according to any one of claims 7 to 10,
The plurality of control target circuits have a first adjacent circuit relationship having a PMOS transistor adjacent or a second adjacent circuit relationship having an NMOS transistor adjacent between circuits adjacent in a predetermined direction,
Any of the predetermined number of first body potential lines is sharable between the control target circuits having the first adjacent circuit relationship,
Any of the predetermined number of the second body potential lines is sharable between the control target circuits having the second adjacent circuit relationship,
Semiconductor integrated circuit. A semiconductor integrated circuit according to any one of claims 7 to 10, wherein
The plurality of control target circuits have a first adjacent circuit relationship having a PMOS transistor adjacent or a second adjacent circuit relationship having an NMOS transistor adjacent between circuits adjacent in a predetermined direction,
One of the predetermined number of first body potential lines is branched corresponding to the control target circuit having the first adjacent circuit relationship,
One of the predetermined number of second body potential lines is branched and wired corresponding to the control target circuit having the second adjacent circuit relationship.
Semiconductor integrated circuit. A substrate control method using a substrate control circuit for supplying first and second body potentials for setting potentials of body regions of a PMOS transistor and an NMOS transistor to be controlled from first and second nodes,
(a) supplying first and second power supply voltages to the first and second nodes when the control target is in a standby state;
(b) short-circuiting between the first and second nodes in a wake-up period, which is a predetermined period in which the controlled object transitions from the standby state to the operating state;
(c) supplying the first and second drive voltages to the first and second nodes in the operation state of the control target after the lapse of the way-up period,
The potential height is set in the order of the first power supply voltage, the first drive voltage, the second drive voltage, and the second power supply voltage.
Substrate control method. The substrate control method according to claim 13, comprising:
The step (b) further includes setting the first and second nodes in a floating state during the wake-up period.
Substrate control method. The substrate control method according to claim 13, comprising:
The step (b) further includes supplying the first and second drive voltages to the first and second nodes during the wake-up period.
Substrate control method.

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