JP2008148082A - Solid-state imaging apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging apparatus which can correct vertical stripe-like noise and horizontal shading, without requiring interception means of an image pickup device. <P>SOLUTION: A solid-state imaging apparatus has a photodiode 101, a floating diffusion range 106 for receiving a signal of the photodiode 101, a pixel portion having unit pixels two-dimensionally arranged, with a transfer transistor 103 for transferring the signal to the floating diffusion range and an amplification transistor 102; a column signal line 12 commonly connected to a column direction pixel; a noise suppression portion 30 suppressing a noise of a pixel signal outputted to the column signal line; a vertical scanning portion 21 driving and controlling a pixel; a horizontal scanning portion 22 outputting a signal, after a noise suppression to a horizontal signal line 19, and a mode setting control circuit 23 having an imaging signal read mode reading an imaging signal, and a correction signal read mode acquiring a correction signal for suppressing stripe-like noise or the like due to a noise suppression portion, and performing drive control including transfer transistor ON in the imaging signal read mode, and performing driving control, only for transistor OFF in the correction signal read mode. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device that outputs a video output signal such as a digital camera, and more particularly to a solid-state imaging device capable of correcting vertical stripe noise and horizontal shading.

  Solid-state imaging devices such as CCD image sensors and MOS image sensors are devices that convert light into electrical signals, and are widely used in digital cameras and the like. FIG. 11 is a circuit configuration diagram showing a configuration example of a conventional MOS image sensor. The MOS type image sensor according to this configuration example includes a photodiode PD1 that is a photoelectric conversion unit, an amplification transistor M1 that amplifies a detection signal of the photodiode PD1, a reset transistor M2 that resets the detection signal of the photodiode PD1, and each row. The unit pixel 2011 is commonly connected to the unit pixel 2011 including the row selection transistor M3 for selection and the pixel power supply VDD, the vertical scanning unit 2012 that drives the unit pixel, and the unit pixels 2011 arranged in the column direction. Are connected to the column signal line 2013 for outputting a signal from the bias transistor M5 for supplying a constant current to the column signal line 2013, the bias current adjusting voltage line VBIAS for determining the current value of the bias transistor, and the column signal line 2013. Clamp capacitor C11, hold capacitor C12 for holding the voltage change of the column signal line 2013, and clamp A sample-and-hold transistor M12 for connecting the quantity C11 and the hold capacitor C12, a clamp transistor C11 for clamping the clamp capacitor C11 and the hold capacitor C12 to a predetermined voltage, and one for selecting a signal from the hold capacitor C12 of each column. A column selection transistor M13 having a terminal connected to the hold capacitor C12, a horizontal signal line 2015 to which the other terminal of the column selection transistor M13 is connected, an output amplifier 2016, and a horizontal scanning unit 2014 for driving the column selection transistor M13. Has been. The clamp capacitor C11, the hold capacitor C12, the clamp transistor M11, and the sample hold transistor M12 form a noise suppression unit 2017.

  In the image sensor configured as described above, it is possible to suppress the variation of the amplification transistor M1 of the unit pixel by the noise suppression unit 2017 that performs correlated double sampling provided for each column. However, the noise suppression unit 2017 If there is variation in itself, there is a problem that due to the variation, vertical streak noise and horizontal shading are superimposed on the obtained pixel signal.

  Therefore, conventionally, the following method is used to correct the vertical stripe noise and the horizontal shading. 12 and 13 are diagrams showing a schematic configuration of an image sensor capable of correcting vertical streak noise and horizontal shading disclosed in, for example, Japanese Patent Application Laid-Open No. 2000-261730, and a solid-state imaging device equipped with the image sensor. It is a block block diagram which shows the structure of these. FIG. 12 shows a simplified configuration of the MOS image sensor shown in FIG. 11, and the same reference numerals are given to the same components as those of the image sensor shown in FIG. In the entire pixel area 2001a of the pixel portion constituted by a plurality of unit pixels arranged in a matrix, an OB area 2001c whose surface is covered with a light shielding film and an effective pixel area 2001b used for actual imaging are provided. The upper side of the OB area 2001c is a vertical OB area 2001d.

  The solid-state imaging device shown in FIG. 13 includes an image sensor 3010, an A / D converter 3020 that converts a signal from the image sensor 3010 into a digital signal, and an image sensor from a digital signal output from the A / D converter 3020. A signal for 3010 vertical OB areas 2001d is extracted and added and averaged in the column direction, a vertical OB area addition averaging section 3030, a line memory 3040 for holding signals from the vertical OB area addition averaging section 3030, and A / D conversion A subtraction unit 3050 that subtracts a signal (correction data) held in the line memory 3040 from an imaging signal output from the unit 3020, and an image processing unit 3060 that performs image processing on the signal from the subtraction unit 3050 and outputs an image signal It is configured.

  In the solid-state imaging device configured as described above, when the imaging signal is acquired, a signal obtained by adding and averaging the signals of the vertical OB area 2001d in the column direction is used as correction data for vertical stripe noise and horizontal shading. The vertical streak noise and the horizontal shading are corrected by subtracting the correction data held in the line memory 3040 from the image pickup signal during normal image pickup. Here, the reason why the averaging of the signals in the vertical OB region is performed in the column direction is to make the signals less susceptible to random noise components.

Further, as disclosed in Japanese Patent Application Laid-Open No. 10-313428, a state in which light is not incident on the image sensor is created, and correction data obtained by averaging in the column direction is obtained from the output in that state, whereby vertical stripe noise and A method for correcting the shading in the horizontal direction is also known.
JP 2000-261730 A JP 10-313428 A

  However, in the method disclosed in the above Japanese Patent Laid-Open No. 2000-261730, the correction data is acquired by the vertical OB region 2001d covered with the light shielding film, so that an actual imaging signal is acquired. There is a difference in pixel characteristics from the effective pixel region 2001b. Further, in the method disclosed in Japanese Patent Laid-Open No. 10-313428, a light shielding unit is necessary to obtain correction data in the effective pixel region.

  As described above, conventionally, when acquiring vertical stripe noise and correction data for shading correction in the horizontal direction, it has been a problem to obtain a signal equivalent to the light shielding state without using the light shielding means. The present invention has been made to solve the above problems in a solid-state imaging device, and provides a solid-state imaging device capable of correcting vertical stripe noise and horizontal shading without requiring a light-shielding means of a solid-state imaging device. With the goal.

  In order to solve the above problems, the invention according to claim 1 is directed to photoelectric conversion means, amplification means for amplifying a signal supplied to the input section, reset means for resetting the input section of the amplification means, and the photoelectric conversion means. A plurality of pixels having transfer means for transferring the imaging signal generated by the conversion means to the input section of the amplification means, the output section of the amplification means for each pixel arranged two-dimensionally and arranged in each column Are connected to a common signal line provided for each column, a column processing circuit for suppressing noise of a signal from the pixel output to the common signal line, an amplifying unit for the pixel, and a reset unit And a vertical scanning circuit that controls the transfer means in units of rows, a horizontal scanning circuit that controls output of signals after noise suppression from the column processing circuit to horizontal signal lines in units of columns, and the imaging signal Horizontal signal line A first reading mode for reading and a second reading mode for acquiring correction data for suppressing noise caused by the column processing circuit can be set. Here, the transfer means includes the first reading mode and the second reading mode. A solid-state imaging device including a mode setting control circuit configured to perform drive control including ON in the first read mode and drive control only in the second read mode; and a memory holding the correction data; A solid-state imaging device is configured including correction means for correcting the imaging signal read in the first readout mode based on correction data held in a memory.

  According to a second aspect of the present invention, in the solid-state imaging device according to the first aspect, at least one of the memory and the correcting unit is formed on the same semiconductor chip as the solid-state imaging element. It is.

  According to a third aspect of the present invention, in the solid-state imaging device according to the first or second aspect, the mode setting control circuit sets the second readout mode at an arbitrary timing, and the memory is acquired at the arbitrary timing. Further, the correction data is stored.

  According to the first aspect of the present invention, in the second readout mode, the pixel transfer unit is driven and controlled only by being OFF, and the transfer of the imaging signal to the amplification unit is cut off. In this case, it is possible to obtain correction data for suppressing noise caused by the column processing circuit in a state equivalent to the state where light is shielded by the light shielding unit with a simple configuration without separately providing the light shielding unit. An imaging device can be realized. According to the second aspect of the present invention, since at least one of the memory and the correction unit is configured on the same semiconductor chip as the solid-state imaging device, the external memory and the external correction unit are not required, and the solid-state imaging device It is possible to reduce the size. According to the invention of claim 3, it is possible to change the correction signal held in the memory at an arbitrary timing.

  Next, the best mode for carrying out the present invention will be described.

(Example 1)
First, Embodiment 1 of the solid-state imaging device according to the present invention will be described. FIG. 1 is a circuit configuration diagram illustrating a configuration of one pixel of a solid-state imaging device and a portion corresponding thereto in the solid-state imaging device according to the first embodiment. The solid-state imaging device according to this embodiment includes a photodiode 101 that is a photoelectric conversion unit, a floating diffusion region 106 that receives a signal corresponding to the electric charge accumulated in the photodiode 101, and an amplifier that reads and amplifies the signal. An amplifying transistor 102, a transfer transistor 103 which is means for transferring the electric charge accumulated in the photodiode 101 to the floating diffusion region 106, and a reset transistor 104 for resetting the floating diffusion region 106 which is an input part of the amplifying transistor 102 A unit pixel 11 including a row selection transistor 105 for selecting each row and a pixel power supply VDD. In FIG. 1, reference numeral 107 denotes a stray capacitance formed by the floating diffusion region 106, and a plurality of the unit pixels 11 are arranged in a matrix.

  The solid-state imaging device is commonly connected to the unit pixels 11 arranged in the column direction, and outputs a signal of the unit pixel 11 and a bias transistor 13 for supplying a constant current to the column signal line 12. And a bias current adjustment voltage line VBIAS that determines the current value of the bias transistor 13, a clamp capacitor 14 connected to the column signal line 12, and a hold capacitor 15 that holds the voltage change of the column signal line 12. A unit pixel 11 that performs correlated double sampling and a sample and hold transistor 16 that connects the clamp capacitor 14 and the hold capacitor 15 and a clamp transistor 17 that clamps the clamp capacitor 14 and the hold capacitor 15 to a predetermined voltage. The noise suppressor 30 that suppresses the noise of the signal from the signal and the hold capacitor 15 for reading the signal from the hold capacitor 15 of the noise suppressor 30 of each column The connected column selection transistor 18, the horizontal signal line 19 to which the other terminal of the column selection transistor 18 is connected, the output amplifier 20, the vertical scanning circuit 21, the horizontal scanning circuit 22, and the imaging signal readout mode described below And a mode setting control circuit 23 that controls driving by switching between the correction signal reading mode and the correction signal reading mode. The mode setting control circuit 23 further includes a mode setting unit 23a for setting a mode and a control unit 23b for performing control according to the set mode.

  Next, the image data acquisition operation in the imaging signal readout mode of the solid-state imaging device according to the first embodiment shown in FIG. 1 will be described based on the timing chart of the imaging signal readout mode shown in FIG. ΦROW, φRST, and φTR in FIG. 2 are a row selection pulse for pixel driving, a reset control pulse, and a transfer pulse signal, which are output from the vertical scanning circuit 21.

  First, in the horizontal blanking period, when the row selection pulse φROW = H, the row selection transistor 105 is turned on, and the signal voltage of the floating diffusion region 106 is output to the column signal line 12. Next, with the clamp control pulse φCL = H and the sample hold control pulse φSH = H, the sample hold transistor 16 and the clamp transistor 17 are turned on, and one terminal of the clamp capacitor 14 and the hold capacitor 15 are fixed to the reference potential VREF. To do. The clamp control pulse φCL and the sample hold control pulse φSH are output from the control unit 23b.

  Next, the reset transistor 104 is turned on with the reset control pulse φRST = H, and the voltage of the floating diffusion region 106 is reset. Thereafter, the reset control pulse φRST = L and the reset transistor 104 is turned off. Then, by setting the clamp control pulse φCL = L and turning off the clamp transistor 17, the level of the floating diffusion region 106 after the reset is clamped to the clamp capacitor 14. Thereafter, the transfer pulse φTR = H is set to turn on the transfer transistor 103, and the charges accumulated in the photodiode 101 are transferred to the floating diffusion region 106. At this time, an imaging signal level corresponding to the charge amount appears on the column signal line 12 and is accumulated in the hold capacitor 15 via the clamp capacitor 14 and the sample hold transistor 16.

  Then, the signal component of the photodiode 101 is held in the hold capacitor 15 by setting the sample and hold transistor 16 to the OFF state by setting the sample and hold control pulse φSH = L. Thereafter, in the horizontal video period, the column selection pulse output from the horizontal scanning circuit 22 is set to “H” to turn on the column selection transistor 18, whereby the signal component held in the hold capacitor 15 is output to the horizontal signal line 19. The output amplifier 20 outputs a pixel signal in which noise is suppressed. By repeating this operation for each row, an image signal for one screen can be obtained.

  Next, the correction signal acquisition operation of the solid-state imaging device shown in FIG. 1 will be described based on the timing chart in the correction signal readout mode shown in FIG. A row selection pulse φROW, a reset control pulse φRST, and a transfer pulse φTR in FIG. 3 are signals for driving pixels, and are output from the vertical scanning circuit 21.

  First, in the horizontal blanking period, when the row selection pulse φROW = H, the row selection transistor 105 is turned on, and the signal voltage of the floating diffusion region 106 is output to the column signal line 12. At this time, the clamp control pulse φCL = H and the sample hold control pulse φSH = H are set, the sample hold transistor 16 and the clamp transistor 17 are turned on, and one terminal of the clamp capacitor 14 and the hold capacitor 15 are fixed to the reference potential VREF. To do.

  Next, the reset transistor 104 is turned on with the reset control pulse φRST = H, and the voltage of the floating diffusion region 106 is reset. Thereafter, the reset control pulse φRST = L and the reset transistor 104 is turned off. Then, by setting the clamp control pulse φCL = L and turning off the clamp transistor 17, the level of the floating diffusion region 106 after the reset is clamped to the clamp capacitor 14. Thereafter, the sample hold transistor 16 is turned off by setting the sample hold control pulse φSH = L, so that the signal level is held in the hold capacitor 15. In this case, it is assumed that charges due to light are accumulated in the photodiode 101. However, since the transfer operation is not performed, the level of the floating diffusion region 106 does not change. Therefore, the signal level is the same as when the pixel area is shielded from light.

  Thereafter, during the horizontal video period, the signal component held in the hold capacitor 15 is output to the horizontal signal line 19 by the column selection pulse output from the horizontal scanning circuit 22, and the signal from which the noise is suppressed is output from the output amplifier 20. Is output. By repeating this operation for each row, a signal equivalent to the light-shielded state can be obtained without putting the pixel region in the light-shielded state, so that it is possible to suppress noise caused by the noise suppressor 30 for each column. It can be used as a correction signal.

(Example 2)
Next, Example 2 will be described. FIG. 4 is a circuit configuration diagram illustrating a configuration of one pixel of the solid-state imaging device and a portion corresponding thereto in the solid-state imaging device according to the second embodiment. The configuration of the solid-state imaging device according to the second embodiment is a configuration in which the noise suppression unit that performs correlated double sampling in the solid-state imaging device according to the first embodiment is changed from a clamp type to a differential type.

  As illustrated in FIG. 4, the solid-state imaging device according to the second embodiment includes a photodiode 501 that is a photoelectric conversion unit, a floating diffusion region 506 that receives a signal corresponding to a charge accumulated in the photodiode 501, and a floating diffusion. A stray capacitance 507 formed by the region, an amplifying transistor 502 for amplifying and reading out the signal, a transfer transistor 503 as means for transferring the charge accumulated in the photodiode 501 to the floating diffusion region 506, an amplifying transistor The unit pixel 51 includes a reset transistor 504 for resetting the floating diffusion region 506, which is an input unit of 502, a row selection transistor 505 for selecting each row, and a pixel power supply VDD, and is arranged in the column direction. A column signal line 52 for outputting a signal of the unit pixel 51 and a bias transistor for supplying a constant current to the column signal line 52. 53, a bias current adjustment voltage line VBIAS that determines the current value of the bias transistor, a first selection transistor 54 that operates according to a selection pulse φS, a second selection transistor 55 that operates according to a selection pulse φR, and a column signal A first capacitor 56 that holds a photodiode signal output to the line 52, a second capacitor 57 that also holds a photodiode signal output to the column signal line 52, and a first capacitor 56 A first horizontal signal line 58 for outputting the generated signal, a second horizontal signal line 59 for outputting a signal held in the second capacitor 57, a first capacitor 56, and a first horizontal signal line 58. The first column selection transistor 60 for connecting the second capacitor 57, the second column selection transistor 61 for connecting the second capacitor 57 and the second horizontal signal line 59, and the horizontal signal line reset voltage operated by the column reset pulse. To the first horizontal signal line 58 A first horizontal signal line reset transistor 62 to be connected; a second horizontal signal line reset transistor 63 that operates by a column reset pulse to connect a horizontal signal line reset voltage to the second horizontal signal line 59; Mode setting control for switching and controlling the differential output amplifier 64 connected to the two horizontal signal lines 58 and 59, the vertical scanning circuit 65, the horizontal scanning circuit 66, and the imaging signal readout mode and the correction signal readout mode. The circuit 67 is provided. The mode setting control circuit 67 further includes a mode setting unit 67a for setting a mode and a control unit 67b for performing control according to the set mode.

  Next, the image data acquisition operation in the imaging signal readout mode of the solid-state imaging device according to the second embodiment shown in FIG. 4 will be described based on the timing chart of the imaging signal readout mode shown in FIG. A row selection pulse φROW, a reset control pulse φRST, and a transfer pulse φTR in FIG. 5 are signals for driving a pixel, and are output from the vertical scanning circuit 65.

  First, in the horizontal blanking period, when the row selection pulse φROW = H, the row selection transistor 505 is turned on, and the signal voltage of the floating diffusion region 506 is output to the column signal line 52. Next, the reset transistor 504 is turned on with the reset control pulse φRST = H, and the floating diffusion region 506 is reset. After that, the reset transistor 504 is turned off with the reset control pulse φRST = L. Then, the second selection transistor 55 is turned on with the second selection pulse φR = H, and the reset potential of the floating diffusion region 506 is held in the second capacitor 57. Thereafter, the second selection pulse 55 is turned off with the second selection pulse φR = L.

  Next, the transfer transistor 503 is turned on with the transfer pulse φTR = H, and the charge accumulated in the photodiode 501 is transferred to the floating diffusion region 506. Next, after the transfer transistor 503 is turned off with the transfer pulse φTR = L, the first select transistor 54 is turned on with the first selection pulse φS = H, whereby the potential of the floating diffusion region 506 is changed to the first capacitance 56. Retained. Thereafter, the first selection pulse φS = L and the first selection transistor 54 is turned off. The second and first selection pulses φR, φS and the column reset pulse are output from the control unit 67b.

  Thereafter, in the horizontal video period, the column selection pulse output from the horizontal scanning circuit 66 is set to “H”, and the second column selection transistor 61 and the first column selection transistor 60 are turned on, whereby the second The signals held in the capacitor 57 and the first capacitor 56 are respectively output to the second horizontal signal line 59 and the first horizontal signal line 58, input to the differential output amplifier 64, and included in the photoelectric conversion signal. A pixel signal in which noise is suppressed is output. Note that the first and second horizontal signal lines 58 and 59 are reset by the horizontal signal line reset voltage before the column selection pulse is set to “H”.

  Next, the correction signal acquisition operation of the solid-state imaging device according to the second embodiment shown in FIG. 4 will be described based on the timing chart of the correction signal readout mode shown in FIG. A row selection pulse φROW, a reset control pulse φRST, and a transfer pulse φTR in FIG. 6 are signals for driving pixels, and are output from the vertical scanning circuit 65.

  First, in the horizontal blanking period, the row selection pulse φROW = H is set to turn on the row selection transistor 505, and then the reset control pulse φRST = H is set to turn on the reset transistor 504 to reset the floating diffusion region 506. After that, the reset transistor 504 is turned off with the reset control pulse φRST = L.

  Then, the second selection transistor 55 is turned on with the second selection pulse φR = H, and the reset potential of the floating diffusion region 506 is held in the second capacitor 57. Thereafter, the second selection pulse 55 is turned off with the second selection pulse φR = L. Thereafter, the first selection transistor 54 is turned on by setting the first selection pulse φS = H, and the potential of the floating diffusion region 506 is held in the first capacitor 56. At this time, even if charge due to light is accumulated in the photodiode 501, since the transfer operation is not performed, the level of the floating diffusion region 506 does not change, and the signal level is almost the same as when the pixel region is shielded from light. Yes. Thereafter, the first selection pulse φS = L and the first selection transistor 54 is turned off.

  Thereafter, in the horizontal video period, the column selection pulse output from the horizontal scanning circuit 66 is set to “H”, and the second column selection transistor 61 and the first column selection transistor 60 are turned on, whereby the second The signals held in the capacitor 57 and the first capacitor 56 are read out to the second horizontal signal line 59 and the first horizontal signal line 58, respectively, and input to the differential amplifier 64 to be connected to the second capacitor 57. A differential signal of the first capacitor 56 is output, and a signal in which noise is suppressed is obtained. Since this difference signal does not depend on the amount of incident light, it becomes a signal equivalent to the light shielding state. Thus, even when a differential type noise suppression unit is used, a correction signal can be acquired without shading the pixel region.

(Example 3)
Next, Example 3 will be described. FIG. 7 is a circuit configuration diagram illustrating a configuration of one pixel of a solid-state imaging device and a portion corresponding thereto in the solid-state imaging device according to the third embodiment. In the configuration of the solid-state imaging device according to the third embodiment, the second transfer transistor 708 and the memory region 709 that holds a signal corresponding to the photocharge are added to the configuration of the unit pixel of the solid-state imaging device according to the first embodiment. The other configuration is the same as that of the first embodiment except that the configuration is different. In FIG. 7, reference numeral 710 denotes a stray capacitance formed in the memory area.

  Next, the operation of the solid-state imaging device having the configuration shown in FIG. 7 will be described. In the pixel portion, first, the floating diffusion region 706 and the memory region 709 are collectively reset by setting the reset control pulse φRST = H and the first transfer pulse φTR1 = H at the same time for all pixels, and the second time at the same time for all pixels after an arbitrary time. The transfer pulse φTR2 = H is set, and the charges accumulated in the photodiode 701 of each pixel are collectively transferred to the memory region 709. At this time, the time from batch reset to batch transfer is the charge accumulation time of the photodiode 701. Subsequent pixel signal readout can be performed in the same operation by regarding the memory region 709 as the photodiode 101 of the first embodiment shown in FIG.

  As described above, when the memory area is provided in the unit pixel, the charge accumulation period of all the pixels can be made the same, and the operation of the imaging signal readout mode and the correction signal readout mode can be performed as in the first embodiment. In the correction signal reading mode, a signal equivalent to the light shielding state can be obtained without shading the pixel region, so that it can be used as a correction signal.

  In the third embodiment, the noise suppression unit is a clamp type. Needless to say, a differential type as shown in the second embodiment may be used. In the first to third embodiments, only the noise suppression unit that performs correlated double sampling is shown as the column processing circuit, but a circuit that performs amplification for each column or a circuit that performs A / D conversion may be added. Needless to say, it is good.

Example 4
Next, a configuration example of a solid-state imaging device equipped with the solid-state imaging device shown in the first to third embodiments will be described as a fourth embodiment. FIG. 8A shows a simplified diagram of the solid-state imaging device 1010, and FIG. 8B shows a block configuration diagram of the solid-state imaging device. The solid-state imaging device shown in FIG. 8A includes a pixel portion composed of a plurality of unit pixels arranged in a matrix, and the entire pixel region 1001a of the pixel portion is covered with a light shielding film. A covered OB area 1001c and an effective pixel area 1001b used for actual imaging are provided. The upper side of the OB area 1001c is a vertical OB area 1001d, and a part of the effective pixel area 1001b is a selected pixel area 1001e. Here, the selected pixel region 1001e is a pixel region that is selected in the correction signal readout mode, and includes an arbitrary plurality of row regions including effective pixels, and is an optimal region for acquiring correction data by the mode setting control unit 1018. Is set to.

  The solid-state imaging device includes a vertical scanning unit 1013 that drives the pixel unit, a noise suppression unit 1017 provided for each column, a column selection transistor M13, and a horizontal scanning unit 1014 that drives the column selection transistor M13. , A horizontal signal line 1015, an output amplifier 1016, and a mode setting control unit 1018 that performs drive control by switching between an imaging signal readout mode and a correction signal readout mode.

  As shown in FIG. 8B, the solid-state imaging device includes a solid-state imaging device 1010 having the above configuration, an A / D conversion unit 1020 that converts a signal from the solid-state imaging device 1010 into a digital signal, and a correction signal readout mode. Selected pixel vertical addition averaging unit 1030 for averaging the signals from the A / D conversion unit 1020 in the column direction, line memory 1040 for holding signals from the selected pixel vertical addition averaging unit 1030, and A in the imaging signal readout mode A subtracting unit 1050 that subtracts a signal (correction data) held in the line memory 1040 from an imaging signal output from the / D conversion unit 1020, and an image processing unit that performs image processing on the signal from the subtracting unit 1050 and outputs an image signal It consists of 1060. When an A / D conversion circuit is mounted on the solid-state imaging device, the A / D conversion unit 1020 is not necessary.

  Next, the operation of the solid-state imaging device configured as described above will be described. FIG. 9 is a flowchart showing an operation in the correction signal readout mode for correcting vertical stripe noise and horizontal shading. Hereinafter, the operation in the correction signal readout mode will be described with reference to this flowchart. First, when a correction data acquisition command is issued from the mode setting control unit 1018, the vertical scanning unit 1013 is controlled to select an arbitrary plurality of row regions, the selected pixel region 1001e is scanned, and the selected pixel region 1001e is scanned. The correction signal of each pixel is read out to the horizontal signal line 1015 by the horizontal scanning unit 1014 and output from the output amplifier 1016.

  At this time, the correction signal of each pixel in the selected pixel region 1001e can be acquired by the method described in the first to third embodiments. When the vertical scanning unit 1013 finishes scanning the selected pixel region 1001e, the vertical scanning unit 1013 ends the scanning, and the solid-state image sensor 1010 outputs a correction signal for only the selected pixel region 1001e. In the A / D converter 1020, the correction signal of the selected pixel region 1001e is converted into a digital signal. Then, the corrected average signal of the selected pixel area 1001e added and averaged in the column direction by the selected pixel vertical addition averaging unit 1030 is held in the line memory 1040 as correction data.

  FIG. 10 is a flowchart showing an operation in the imaging signal readout mode for correcting vertical stripe noise and horizontal shading. Hereinafter, the operation in the imaging signal readout mode will be described with reference to this flowchart. From the solid-state imaging device 1010, imaging signals of all the pixel regions 1001a are output for each row by the method described in the first to third embodiments. This imaging signal is converted into a digital signal by the A / D conversion unit 1020. The correction data held in the line memory 1040 is subtracted from the digital signal by the subtracting unit 1050, and a signal in which vertical stripe noise and horizontal shading are corrected is input to the image processing unit 1060. The above processing is performed for the imaging signals in each row. Then, the image processing unit 1060 performs image processing on the corrected imaging signal and outputs an image signal.

  As described above, in the solid-state imaging device shown in the present embodiment, an imaging signal in which vertical stripe noise and horizontal shading are corrected can be obtained without putting the solid-state imaging device in a light-shielding state. Note that the number of rows of the selected pixel region 1001e in the effective pixel region 1001b of the pixel portion can be arbitrarily set between 1 and the number of rows of the effective pixel region. For example, as the number of rows increases, random noise can be reduced. Accordingly, the correction data acquisition time can be shortened as the number of rows is reduced, and may be set as appropriate.

  In addition, acquisition of correction data is performed as appropriate according to the stability of the system and the characteristics of the solid-state imaging device, and if correction data is changed, changes in vertical stripes and horizontal shading due to temperature changes, etc. It is possible to make corrections corresponding to. Furthermore, if the correction data is acquired at the time of every imaging, it is possible to always correct the optimum vertical stripes and horizontal shading. If at least one of the components other than the solid-state imaging device of the solid-state imaging device shown in FIG. 8B is configured on the same semiconductor chip as the solid-state imaging device, the solid-state imaging device can be reduced in size. Is possible.

It is a circuit block diagram which shows the structure of 1 pixel of the solid-state image sensor in Example 1 of the solid-state imaging device which concerns on this invention, and the part corresponding to it. 3 is a timing chart for explaining an operation in an imaging signal readout mode in the embodiment 1 shown in FIG. 3 is a timing chart for explaining an operation in a correction signal reading mode in the embodiment 1 shown in FIG. It is a circuit block diagram which shows the structure of 1 pixel of the solid-state image sensor in Example 2 of this invention, and the part corresponding to it. 6 is a timing chart for explaining an operation in an imaging signal readout mode in the second embodiment shown in FIG. 4. 6 is a timing chart for explaining an operation in a correction signal read mode in the embodiment 2 shown in FIG. 4. It is a circuit block diagram which shows the structure of 1 pixel of the solid-state image sensor in Example 3 of this invention, and the part corresponding to it. It is a block diagram which shows the structure of the solid-state image sensor in the structural example of the solid-state imaging device concerning this invention, and the whole structure. It is a flowchart for demonstrating operation | movement at the time of the correction signal read-out mode in the solid-state imaging device shown in FIG. It is a flowchart for demonstrating operation | movement at the time of the imaging signal read-out mode in the solid-state imaging device shown in FIG. It is a circuit block diagram which shows the structural example of the conventional MOS type image sensor. FIG. 12 is a diagram schematically showing the MOS image sensor shown in FIG. FIG. 13 is a block diagram showing a configuration of a solid-state imaging device on which the MOS type image sensor shown in FIG. 12 is mounted.

Explanation of symbols

11, 51, 71 unit pixel
12, 52, 72 signal lines
13, 53, 73 Bias transistor
14, 74 Clamp capacity
15 75 Hold capacity
16,76 Sample hold transistor
17, 77 Clamp transistor
18, 78 column select transistor
19, 79 Horizontal signal line
20, 80 output amplifier
21, 65, 81 Vertical scanning circuit
22, 66, 82 Horizontal scanning circuit
23, 67, 83 Mode setting control circuit
23a, 67a, 83a Mode setting section
23b, 67b, 83b Control unit
30, 90 Noise suppressor
54 First selection transistor
55 Second selection transistor
56 First capacity
57 Second capacity
58 First horizontal signal line
59 Second horizontal signal line
60 First column select transistor
61 Second column select transistor
62 First horizontal signal line reset transistor
63 Second horizontal signal line reset transistor
64 differential output amplifier
101,501,701 Photodiode
102,502,702 amplification transistor
103,503 Transfer transistor
104,504,704 Reset transistor
105,505,705 Row selection transistor
106,506,706 Floating diffusion region
107,507,707 stray capacitance
703 first transfer transistor
708 Second transfer transistor
709 memory area
710 stray capacitance
1001a All pixel area
1001b Effective pixel area
1001c OB area
1001d Vertical OB area
1001e Selected pixel area
1010 Solid-state image sensor
1013 Vertical scanning section
1014 Horizontal scanning section
1015 Horizontal signal line
1016 Output amplifier
1017 Noise suppressor
1018 Mode setting controller
1020 A / D converter
1030 Selected pixel vertical addition average part
1040 line memory
1050 Subtraction unit
1060 Image processing unit

Claims (3)

Photoelectric conversion means, amplification means for amplifying a signal supplied to the input section, reset means for resetting the input section of the amplification means, and an imaging signal generated by the photoelectric conversion means to the input section of the amplification means A plurality of pixels having transfer means for transferring, a pixel portion connected in a two-dimensional manner, and an output portion of the amplifying means of each pixel arranged in each column connected to a common signal line provided for each column; A column processing circuit for suppressing noise of a signal from the pixel output to the common signal line, a vertical scanning circuit for controlling the pixel amplifying unit, the reset unit, and the transfer unit in units of rows, A horizontal scanning circuit that controls the output of a signal after noise suppression from the column processing circuit to the horizontal signal line in units of columns, a first readout mode for reading the imaging signal to the horizontal signal line, and the column processing circuit A second read mode for acquiring correction data for suppressing the noise caused by the noise can be set, wherein the transfer means is a drive control including ON in the first read mode, A solid-state imaging device comprising a mode setting control circuit for driving control only for OFF in the readout mode of 2;
A memory for holding the correction data;
A solid-state imaging apparatus comprising: correction means for correcting the imaging signal read in the first readout mode based on correction data held in the memory.   The solid-state imaging device according to claim 1, wherein at least one of the memory and the correction unit is formed on the same semiconductor chip as the solid-state imaging element.   3. The solid state according to claim 1, wherein the mode setting control circuit sets the second reading mode at an arbitrary timing, and the memory stores the correction data acquired at the arbitrary timing. Imaging device.

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