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JP2008147495A - Connecting terminal, substrate for mounting semiconductor chip using same, semiconductor package, its manufacturing method, wiring board, and its manufacturing method - Google Patents

Connecting terminal, substrate for mounting semiconductor chip using same, semiconductor package, its manufacturing method, wiring board, and its manufacturing method Download PDF

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JP2008147495A
JP2008147495A JP2006334384A JP2006334384A JP2008147495A JP 2008147495 A JP2008147495 A JP 2008147495A JP 2006334384 A JP2006334384 A JP 2006334384A JP 2006334384 A JP2006334384 A JP 2006334384A JP 2008147495 A JP2008147495 A JP 2008147495A
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plating film
electroless
solder
wiring board
thickness
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JP4798451B2 (en
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Yoshinori Ejiri
芳則 江尻
Shuichi Hatakeyama
修一 畠山
Kiyoshi Hasegawa
清 長谷川
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Resonac Corp
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Hitachi Chemical Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a connecting terminal which exhibits a high reliability of connection after heat treatment even when the thickness of its electroless nickel plating film is 0.8 μm or less and to provide a substrate for mounting a semiconductor chip using the connecting terminal, a semiconductor package and its manufacturing method as well as a wiring board and its manufacturing method. <P>SOLUTION: The connecting terminal is formed by forming the electroless nickel plating film which has a thickness of ≥0.2 μm and includes phosphorus of 0.5-3 wt.%, an electroless paladium plating film, an immersion gold film and further an electroless gold plating film in sequence on the surface of wiring conductor and welding solder on them. The substrate for mounting a semiconductor chip is formed by using the connecting terminal. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、接続端子、接続端子を用いた半導体チップ搭載用基板、半導体パッケージとその製造方法及び配線板とその製造方法に関する。   The present invention relates to a connection terminal, a semiconductor chip mounting substrate using the connection terminal, a semiconductor package, a manufacturing method thereof, a wiring board, and a manufacturing method thereof.

近年の情報化社会の発展は目覚しく、民生機器ではパソコン、携帯電話等の小型化、軽量化、高性能化、高機能化が進められ、産業用機器としては無線基地局、光通信装置、サーバ、ルータ等のネットワーク関連機器など、大型、小型を問わず、同じように機能の向上が求められている。   The development of the information society in recent years has been remarkable, and consumer devices have been reduced in size, weight, performance, and functionality, such as personal computers and mobile phones. Industrial equipment includes wireless base stations, optical communication devices, and servers. In addition, there is a demand for improvement in function in the same way, regardless of whether it is large or small, such as routers and other network-related devices.

また、情報伝達量の増加に伴い、年々扱う信号の高周波化が進む傾向にあり、高速処理及び高速伝送技術の開発が進められている。実装関係についてみると、CPU、DSPや各種のメモリなどのLSIの高速化、高機能化と共に、新たな高密度実装技術としてシステムオンチップ(SoC)、システムインパッケージ(SiP)などの開発が盛んに行われている。   In addition, with the increase in the amount of information transmitted, the frequency of signals handled tends to increase year by year, and high-speed processing and high-speed transmission technology are being developed. With regard to mounting relations, the development of system-on-chip (SoC), system-in-package (SiP), etc., as new high-density mounting technologies, as well as higher-speed and higher-performance LSIs such as CPUs, DSPs, and various types of memory are actively developed. Has been done.

このため、半導体チップ搭載基板やマザーボードも、高周波化、高密度配線化、高機能化に対応するために、ビルドアップ方式の多層配線基板が使用されるようになってきた。
電子機器メーカ各社は、製品の小型・薄型・軽量化を実現するために競って高密度実装に取り組み、パッケージの多ピン狭ピッチ化の急速な技術進歩がなされ、プリント配線板への実装は従来のQFP(Quad Flat Package)からエリア表面実装のBGA(Ball Grid Array)/CSP(Chip Size Package)実装へと進化した。
For this reason, build-up type multilayer wiring boards have come to be used for semiconductor chip mounting boards and motherboards in order to cope with high frequency, high density wiring, and high functionality.
Electronic device manufacturers have been competing in high-density packaging to achieve smaller, thinner, and lighter products, and rapid technological progress has been made in narrowing the multi-pin pitch of packages. From QFP (Quad Flat Package) to BGA (Ball Grid Array) / CSP (Chip Size Package) mounting on the surface.

ところで、半導体チップと半導体実装基板との接続方法は金ワイヤボンディングが一般的であり、配線板側の端子には金ワイヤの接着層である金めっきが必要である。通常、銅配線上にニッケルめっきを施した後、金めっきが行われる。   By the way, the connection method between the semiconductor chip and the semiconductor mounting substrate is generally gold wire bonding, and the terminal on the wiring board side requires gold plating as an adhesive layer of the gold wire. Usually, gold plating is performed after nickel plating on copper wiring.

従来、銅配線上に金属めっき皮膜を形成する方法としては電気めっきが適用されていたが、近年、半導体チップの高速化、高集積化に伴い基板の配線が微細化し、めっき電力供給用の引き出し線の形成が困難となっている。そのため、引き出し線が不用である無電解めっき方法に対する必要性が強まっている。   Conventionally, electroplating has been applied as a method for forming a metal plating film on copper wiring. However, in recent years, the wiring on a substrate has become finer as the speed and integration of semiconductor chips has increased, leading to the supply of plating power. Line formation is difficult. Therefore, there is an increasing need for an electroless plating method that does not require lead wires.

BGAにはんだボールが接続した端子構造は、導体端子上にニッケルめっき皮膜、金めっき皮膜が順次形成されており、その上にはんだボールが接続されている。一般的に最も多く使用されている無電解ニッケルめっき皮膜は、リンの含有率が7%前後の中リンタイプと呼ばれるめっき皮膜である。   In the terminal structure in which a solder ball is connected to the BGA, a nickel plating film and a gold plating film are sequentially formed on the conductor terminal, and the solder ball is connected thereon. The electroless nickel plating film that is most commonly used is a plating film called a medium phosphorus type having a phosphorus content of around 7%.

中リンタイプの無電解ニッケルめっき皮膜を用い、その上に置換金めっきにより金めっき皮膜を形成し、はんだとめっき界面との良好な接続強度が得られることが広く知られている(例えば、非特許文献1参照)。
トップテクノフォーカス、第34号、P48(奥野製薬工業株式会社)発行
It is widely known that a medium phosphorous type electroless nickel plating film is used, and a gold plating film is formed thereon by displacement gold plating, and a good connection strength between the solder and the plating interface can be obtained (for example, non- Patent Document 1).
Top Techno Focus, No. 34, P48 (Okuno Pharmaceutical Co., Ltd.) issued

また、はんだとめっき界面とのさらなる接続強度向上のため、無電解ニッケルめっき皮膜と置換金めっき皮膜との間に無電解パラジウムめっき皮膜を形成する技術が知られている(例えば、非特許文献2参照)。
第41回セミナーテクスト、「実装技術を支える最新めっき技術」、P52(社団法人 エレクトロニクス実装学会)発行
Also, a technique for forming an electroless palladium plating film between an electroless nickel plating film and a displacement gold plating film is known for further improving the connection strength between the solder and the plating interface (for example, Non-Patent Document 2). reference).
41st Seminar Text, “Latest Plating Technology to Support Packaging Technology”, P52 (Electronic Packaging Society of Japan) published

ところで、非特許文献1に記載の、中リンタイプの無電解ニッケルめっき皮膜を用い、その上に置換金めっきにより金めっき皮膜を形成し、はんだボールを接続させても、中リンタイプの無電解ニッケルめっき皮膜の厚さが0.8μm未満の場合、はんだボールの接続後の熱処理によって、接続信頼性が著しく低下する課題があることが明らかとなった。   By the way, even if a medium phosphorus type electroless nickel plating film described in Non-Patent Document 1 is used, a gold plating film is formed thereon by displacement gold plating, and solder balls are connected, the medium phosphorus type electroless When the thickness of the nickel plating film is less than 0.8 μm, it has been clarified that there is a problem that the connection reliability is significantly lowered by the heat treatment after the connection of the solder balls.

また、非特許文献2に記載の、中リンタイプの無電解ニッケルめっき皮膜と置換金めっき皮膜との間に無電解パラジウムめっき皮膜を形成し、はんだボールを接続させても、中リンタイプの無電解ニッケルめっき皮膜の厚みが0.8μm未満の場合、はんだボールの接続後の熱処理によって、接続信頼性が著しく低下し、課題の解決に至らないことが明らかとなった。   In addition, even if an electroless palladium plating film described in Non-Patent Document 2 is formed between the electroless nickel plating film and the displacement gold plating film and the solder balls are connected, the medium phosphorus type When the thickness of the electrolytic nickel plating film is less than 0.8 μm, it has been clarified that the heat treatment after the connection of the solder balls significantly reduces the connection reliability and does not solve the problem.

本発明は、無電解ニッケルめっき皮膜の厚さが0.8μm以下であっても、熱処理後の接続信頼性に優れた接続端子、その接続端子を用いた半導体チップ搭載用基板、半導体パッケージとその製造方法及び配線板とその製造方法を提供することを目的とするものである。   The present invention provides a connection terminal excellent in connection reliability after heat treatment, a semiconductor chip mounting substrate using the connection terminal, a semiconductor package, and a semiconductor package, even if the thickness of the electroless nickel plating film is 0.8 μm or less. An object of the present invention is to provide a manufacturing method, a wiring board, and a manufacturing method thereof.

本発明者らは、上記目的を達成すべく鋭意検討した結果、配線導体の表面に0.5〜3重量%のリンを含有した、低リンタイプと呼ばれる無電解ニッケルめっき皮膜を形成し、その上に無電解パラジウムめっき皮膜、置換金めっき皮膜、さらに無電解金めっき被膜を順に形成することで、はんだ接合後に熱処理を行っても、接続信頼性が優れることを見出し、本発明の完成するに至った。   As a result of intensive studies to achieve the above object, the inventors of the present invention formed an electroless nickel plating film called a low phosphorus type containing 0.5 to 3% by weight of phosphorus on the surface of the wiring conductor. By forming an electroless palladium plating film, a displacement gold plating film, and an electroless gold plating film in this order, it was found that even when heat treatment was performed after soldering, connection reliability was excellent, and the present invention was completed. .

本発明は、次の事項に関する。
(1)配線導体の表面に、厚さが0.2μm以上で、0.5〜3重量%のリンを含有した無電解ニッケルめっき皮膜、無電解パラジウムめっき皮膜、置換金めっき皮膜、さらに無電解金めっき皮膜が順に形成され、その上にはんだが溶着された接続端子。
(2)無電解パラジウムめっき皮膜が、90重量%以上の純度のパラジウムである請求項1記載の接続端子。
The present invention relates to the following matters.
(1) Electroless nickel plating film, electroless palladium plating film, substitutional gold plating film, and electroless electrolysis with a thickness of 0.2 μm or more and containing 0.5 to 3% by weight of phosphorus on the surface of the wiring conductor A connection terminal in which a gold plating film is formed in order and solder is deposited on it.
(2) The connection terminal according to claim 1, wherein the electroless palladium plating film is palladium having a purity of 90% by weight or more.

(3)ワイヤボンディング用端子とはんだ接続用の接続端子を備えた半導体チップ搭載用基板において、前記ワイヤボンディング用端子の端子間又は引き回し配線間(Y)が30μm以下で、かつ端子高さ(Z)が端子間又は引き回し配線間(Y)の5分の2以上であり、前記ワイヤボンディング用端子と前記はんだ接続用の接続端子表面に、請求項1記載の厚さが0.2μm以上で、0.5〜3重量%のリンを含有した無電解ニッケルめっき皮膜、無電解パラジウムめっき皮膜、置換金めっき皮膜、さらに無電解金めっき皮膜が順に形成された半導体チップ搭載用基板。 (3) In a semiconductor chip mounting board provided with wire bonding terminals and solder connection terminals, the wire bonding terminals have a terminal height (Z) of 30 μm or less and between the lead wires (Y). ) Is more than two-fifths between the terminals or between the routing wires (Y), and the thickness of the wire bonding terminal and the connection terminal for solder connection is 0.2 μm or more, A semiconductor chip mounting substrate on which an electroless nickel plating film, an electroless palladium plating film, a displacement gold plating film, and further an electroless gold plating film containing 0.5 to 3% by weight of phosphorus are sequentially formed.

(4)配線導体の表面に厚さが0.2μm以上で、0.5〜3重量%のリンを含有した無電解ニッケルめっき皮膜、無電解パラジウムめっき皮膜、置換金めっき皮膜、さらに無電解金めっき皮膜が順に形成され、その上にはんだが溶着された接続端子、該配線導体を支持する半導体チップ搭載用基板、半導体チップ、該半導体チップ及び該配線導体を接続する接続導体とからなる半導体パッケージ。
(5)無電解パラジウムめっき皮膜が、90重量%以上の純度のパラジウムである請求項4記載の半導体パッケージ。
(4) Electroless nickel plating film, electroless palladium plating film, substitutional gold plating film, and electroless gold with a thickness of 0.2 μm or more on the surface of the wiring conductor and containing 0.5 to 3% by weight of phosphorus A semiconductor package comprising a connection terminal on which a plating film is formed in order and solder is deposited thereon, a semiconductor chip mounting substrate for supporting the wiring conductor, a semiconductor chip, and a connection conductor for connecting the semiconductor chip and the wiring conductor .
(5) The semiconductor package according to claim 4, wherein the electroless palladium plating film is palladium having a purity of 90% by weight or more.

(6)半導体チップ搭載用基板の表面に配線導体を形成した後、該配線導体の表面に厚さが0.2μm以上で、0.5〜3重量%のリンを含有した無電解ニッケルめっき皮膜、無電解パラジウムめっき皮膜、置換金めっき皮膜、さらに無電解金めっき皮膜を順に形成し、その上にはんだを溶着して接続端子を形成し、該接続端子のはんだの上に半導体チップを搭載した後、半導体チップと配線導体を接続する接続導体を形成することを特徴とする半導体パッケージの製造方法。 (6) After forming a wiring conductor on the surface of the semiconductor chip mounting substrate, an electroless nickel plating film having a thickness of 0.2 μm or more and containing 0.5 to 3% by weight of phosphorus on the surface of the wiring conductor Then, an electroless palladium plating film, a displacement gold plating film, and an electroless gold plating film are formed in this order, solder is deposited thereon to form a connection terminal, and a semiconductor chip is mounted on the solder of the connection terminal And forming a connection conductor connecting the semiconductor chip and the wiring conductor.

(7)折り曲げ部と接続端子部を併せてもつ配線板において、前記折り曲げ部と接続端子部に配線導体が形成されており、前記折り曲げ部と接続端子部の表面に厚さが0.2μm以上、0.8μm以下で、0.5〜3重量%のリンを含有した無電解ニッケルめっき皮膜、無電解パラジウムめっき皮膜、置換金めっき皮膜、さらに無電解金めっき皮膜が順に形成された配線板。 (7) In a wiring board having both a bent portion and a connecting terminal portion, a wiring conductor is formed on the bent portion and the connecting terminal portion, and a thickness of 0.2 μm or more is formed on the surface of the bent portion and the connecting terminal portion. A wiring board in which an electroless nickel plating film, an electroless palladium plating film, a displacement gold plating film, and further an electroless gold plating film containing 0.5 to 3% by weight of phosphorus at 0.8 μm or less are formed in this order.

(8)折り曲げ部と接続端子部を併せてもつ配線板の表面に配線導体を形成した後と、該配線導体の表面に厚さが0.2μm以上、0.8μm以下で、0.5〜3重量%のリンを含有した無電解ニッケルめっき皮膜、無電解パラジウムめっき皮膜、置換金めっき皮膜、さらに無電解金めっき皮膜を順に形成し、接続端子部の配線導体にはんだを溶着して接続端子を形成することを特徴とする配線板の製造方法。 (8) After the wiring conductor is formed on the surface of the wiring board having both the bent portion and the connecting terminal portion, the thickness of the wiring conductor surface is 0.2 μm or more and 0.8 μm or less, and 0.5 to An electroless nickel plating film containing 3% by weight of phosphorus, an electroless palladium plating film, a displacement gold plating film, and an electroless gold plating film are formed in this order, and solder is welded to the wiring conductor of the connection terminal part. A method of manufacturing a wiring board, comprising: forming a wiring board.

本発明によれば、無電解ニッケルめっき皮膜の厚みが0.8μm以下であっても、熱処理後の接続信頼性に優れた接続端子、その接続端子を用いた半導体チップ搭載用基板、半導体パッケージとその製造方法及び配線板とその製造方法を提供することができる。   According to the present invention, even when the thickness of the electroless nickel plating film is 0.8 μm or less, the connection terminal having excellent connection reliability after the heat treatment, the semiconductor chip mounting substrate using the connection terminal, the semiconductor package, and The manufacturing method, the wiring board, and the manufacturing method thereof can be provided.

本発明において、はんだが溶着された接続端子構造は、配線導体の端子上に、厚さが0.2μm以上で、0.5〜3重量%のリンを含有した無電解ニッケルめっき皮膜、無電解パラジウムめっき皮膜、置換金めっき皮膜、さらに無電解金めっき皮膜が順に形成されており、その上にはんだが接続されている構造であることを特徴とする。   In the present invention, the connection terminal structure in which solder is welded has an electroless nickel plating film containing 0.5 to 3% by weight of phosphorus on the terminal of the wiring conductor and having a thickness of 0.2 μm or more. A palladium plating film, a displacement gold plating film, and an electroless gold plating film are formed in this order, and a solder is connected to the palladium plating film.

配線導体としては、銅、銀、金、パラジウム、タングステン、モリブデン、アルミニウム、これら各々の合金等からなる群から選ばれる少なくとも1種類以上のものを材料として用いることができる。これらの中でも、工業上、価格上の点で銅がより好ましい。
リンの濃度を0.5〜3重量%含有した無電解ニッケルめっき皮膜は、必要に応じて鉛が含有される。
As the wiring conductor, at least one or more selected from the group consisting of copper, silver, gold, palladium, tungsten, molybdenum, aluminum, alloys of these, and the like can be used as a material. Among these, copper is more preferable in terms of industry and price.
The electroless nickel plating film containing 0.5 to 3% by weight of phosphorus contains lead as necessary.

無電解ニッケルめっき皮膜中のリンの濃度は0.5〜3重量%が好ましく、1〜2重量%の範囲であることがより好ましい。0.5 重量%未満であると、ニッケルがはんだに溶解しやすくなるため、Ni−Cu−Sn合金が形成されやすくなり、熱処理を行った後に接続信頼性が低下する。3重量%を超えると、0.8μm未満の膜厚で、熱処理を行ったときに無電解ニッケルめっき皮膜と配線導体の間にボイドが発生し、接続信頼性が著しく低下する問題がある。   The concentration of phosphorus in the electroless nickel plating film is preferably 0.5 to 3% by weight, more preferably 1 to 2% by weight. When it is less than 0.5% by weight, nickel is easily dissolved in the solder, so that a Ni—Cu—Sn alloy is easily formed, and the connection reliability is lowered after heat treatment. If it exceeds 3% by weight, a void is generated between the electroless nickel plating film and the wiring conductor when heat treatment is performed with a film thickness of less than 0.8 μm, and there is a problem that connection reliability is remarkably lowered.

リンの濃度を0.5〜3重量%含んだ無電解ニッケルめっき皮膜の膜厚は、0.2μm以上、好ましくは0.2〜10μm、より好ましくは0.5〜5μmの範囲とされ、0.2μm未満では、Ni−Cu−Sn合金が形成されやすくなり、熱処理を行った後に接続信頼性が低下する。上限は10μmを超えると、効果がそれ以上に向上せず、経済的でないので好ましくない。   The film thickness of the electroless nickel plating film containing 0.5 to 3% by weight of phosphorus is 0.2 μm or more, preferably 0.2 to 10 μm, more preferably 0.5 to 5 μm. If the thickness is less than 2 μm, a Ni—Cu—Sn alloy is easily formed, and the connection reliability decreases after heat treatment. If the upper limit exceeds 10 μm, the effect is not improved further and it is not economical, which is not preferable.

無電解ニッケルめっきの構造は層状の析出形態であることが好ましい。層状の析出形態とは、得られる無電解ニッケルめっき皮膜をエッチングしたときに、めっきの成長方向に対して水平に区分されるような析出線があるもののことである。   The structure of electroless nickel plating is preferably a layered precipitation form. The layered precipitation form means that there is a precipitation line that is divided horizontally with respect to the growth direction of the plating when the obtained electroless nickel plating film is etched.

無電解パラジウムめっきは、めっき液中のパラジウムイオンを還元剤の働きによってニッケル表面にパラジウムを析出させたものであり、還元剤に蟻酸化合物を使用すると無電解パラジウムめっき皮膜の純度が99重量%以上になるので、接続の信頼性が高く好ましく、また還元剤に燐含有化合物、ホウ素含有化合物を使用するとめっき皮膜がパラジウム−燐、パラジウム−ホウ素合金になり、パラジウムの純度が90重量%以上になるが、はんだボール接続信頼性は問題ない。   Electroless palladium plating is a plating solution in which palladium ions are deposited on the nickel surface by the action of a reducing agent. When a formic acid compound is used as the reducing agent, the purity of the electroless palladium plating film is 99% by weight or more. Therefore, connection reliability is high and preferable, and when a phosphorus-containing compound or boron-containing compound is used as the reducing agent, the plating film becomes palladium-phosphorus or palladium-boron alloy, and the purity of palladium becomes 90% by weight or more. However, there is no problem with the solder ball connection reliability.

このパラジウムの純度は、90重量%以上の純度のパラジウムが好ましい。
この無電解パラジウムめっき皮膜の膜厚は、0.02μm〜1.0μmの範囲が好ましく、0.03μm〜0.5μmの範囲がより好ましく、0.05μm〜0.2μmの範囲であることが特に好ましい。1.0μmを超えると、効果がそれ以上に向上せず、経済的でないので好ましくない。0.02μm未満であると、はんだ接続信頼性が低下する傾向がある。
The purity of this palladium is preferably 90% by weight or more.
The film thickness of the electroless palladium plating film is preferably in the range of 0.02 μm to 1.0 μm, more preferably in the range of 0.03 μm to 0.5 μm, and particularly preferably in the range of 0.05 μm to 0.2 μm. preferable. If it exceeds 1.0 μm, the effect is not improved further and it is not economical, which is not preferable. If it is less than 0.02 μm, the solder connection reliability tends to decrease.

無電解金めっきのうち、置換型無電解金めっきは、下地のニッケルと溶液中の金イオンとの置換反応によってニッケル表面に金皮膜を形成するものであり、めっき液には、シアン化合物を含むものと含まないものがあるが、いずれのめっき液でも使用できる。さらに必要に応じ還元型の無電解金めっき皮膜を形成してもよい。   Among electroless gold platings, substitutional electroless gold plating forms a gold film on the nickel surface by a substitution reaction between the underlying nickel and gold ions in the solution, and the plating solution contains a cyanide compound. Some of them are not included, but any plating solution can be used. Further, if necessary, a reduced electroless gold plating film may be formed.

この無電解金めっき皮膜は、99重量%以上の純度の金であることが好ましく、99重量%未満であれば、接続の信頼性が低下する場合もある。
さらに、この無電解金めっき皮膜の純度は、99.5重量%以上であることがより好ましい。
The electroless gold plating film is preferably gold having a purity of 99% by weight or more. If the electroless gold plating film is less than 99% by weight, connection reliability may be lowered.
Furthermore, the purity of the electroless gold plating film is more preferably 99.5% by weight or more.

金めっき皮膜の膜厚は、0.005μm〜3μmの範囲が好ましく、0.005μm〜1μmの範囲がより好ましく、0.005μm〜0.5μmの範囲であることが特に好ましい。0.005μm未満では、ワイヤボンディングの成功率が低下する傾向があり、3μmを超えると、効果がそれ以上に向上せず、経済的でないので好ましくない。   The thickness of the gold plating film is preferably in the range of 0.005 μm to 3 μm, more preferably in the range of 0.005 μm to 1 μm, and particularly preferably in the range of 0.005 μm to 0.5 μm. If it is less than 0.005 μm, the success rate of wire bonding tends to decrease, and if it exceeds 3 μm, the effect is not further improved and it is not economical, which is not preferable.

接続端子の下地である基材の種類は、セラミック、半導体、樹脂基板等で、この樹脂基板には、フェノール、エポキシ、ポリイミド等のものが使用でき、さらに剛性の強い板状の基材、柔軟なフレキシブルな基材のいずれも用いることができる。例えば、フレキシブルな基材の場合、折り曲げ性が要求され、ニッケルめっきの薄膜化が最も効果的な手法である。   The base material of the connection terminal is ceramic, semiconductor, resin substrate, etc. This resin substrate can be phenol, epoxy, polyimide, etc., more rigid plate-like substrate, flexible Any flexible substrate can be used. For example, in the case of a flexible substrate, bendability is required, and nickel plating thinning is the most effective technique.

配線導体の表面に0.5〜3重量%のリンを含有した、低リンタイプと呼ばれる無電解ニッケルめっき皮膜を0.8μm以下で形成し、その上に無電解パラジウムめっき皮膜、置換金めっき皮膜、さらに無電解金めっき皮膜を順に形成することで、屈曲部では屈曲性に優れ、かつはんだ接合部では接続信頼性に優れた基板を得ることが可能である。   An electroless nickel plating film called 0.5 μm or less containing 0.5 to 3% by weight of phosphorus on the surface of the wiring conductor is formed at 0.8 μm or less, and an electroless palladium plating film or a displacement gold plating film is formed thereon. Further, by forming the electroless gold plating film in order, it is possible to obtain a substrate having excellent flexibility at the bent portion and excellent connection reliability at the solder joint portion.

はんだが溶着された接続端子を有する半導体チップ搭載用基板には、CSP、BGA、MCM、配線板及び半導体チップの他、はんだバンプを有するCSP、BGA、MCM、配線板及び半導体チップがある。   In addition to CSP, BGA, MCM, a wiring board and a semiconductor chip, there are CSP, BGA, MCM, a wiring board and a semiconductor chip having solder bumps as a semiconductor chip mounting substrate having a connection terminal to which solder is welded.

はんだには、はんだボール用はんだ、表面実装用電子部品や配線板用のはんだ、半導体チップ上のはんだ、はんだバンプ用はんだ等であればどのようなものでも使用することができ、その形状も、球状、半球状、立方体状、直方体状、突起状等のはんだを使用することができる。   Any solder can be used as long as it is solder for solder balls, solder for surface mount electronic components and wiring boards, solder on semiconductor chips, solder for solder bumps, etc. A solder having a spherical shape, a hemispherical shape, a cubic shape, a rectangular parallelepiped shape, a protruding shape, or the like can be used.

また、60%錫と40%鉛の共晶はんだ、鉛を含まない錫、さらに銀、銅、亜鉛、ビスマス等の一元素以上を含む錫合金でも使用できる。例えば、Sn−3.0Ag−0.5Cuを用いることができる。   Further, eutectic solder of 60% tin and 40% lead, tin containing no lead, and tin alloy containing one or more elements such as silver, copper, zinc, bismuth and the like can also be used. For example, Sn-3.0Ag-0.5Cu can be used.

以下、図面を引用して本発明を実施例により詳細に説明するが、本発明はこれらに制限するものではない。
図1及び2は、本発明の実施例の工程を説明するために参照する完成したプリント配線板の一例を示す概略図であり、このうち図1は、金ワイヤボンディング用接続端子側から見た場合の半導体チップ搭載用基板の一例を示す模式図で、図2は、配線導体であるはんだ接続端子側から見た場合の半導体チップ搭載用基板の一例を示す模式図である。
EXAMPLES Hereinafter, although an Example demonstrates this invention in detail with reference to drawings, this invention is not restrict | limited to these.
1 and 2 are schematic views showing an example of a completed printed wiring board referred to for explaining the steps of the embodiment of the present invention. Of these, FIG. 1 is viewed from the gold wire bonding connection terminal side. FIG. 2 is a schematic diagram showing an example of a semiconductor chip mounting substrate when viewed from the side of a solder connection terminal that is a wiring conductor.

図1に示される半導体チップ搭載用基板6は、基板上に、金ワイヤボンディング用接続端子1と金ワイヤボンディング用接続端子1が露出する開口部2を有するように設けられたソルダーレジスト3とを備えて構成されている。   A semiconductor chip mounting substrate 6 shown in FIG. 1 includes a gold wire bonding connection terminal 1 and a solder resist 3 provided so as to have an opening 2 through which the gold wire bonding connection terminal 1 is exposed. It is prepared for.

図2に示される半導体チップ搭載用基板6は、基板上にはんだ接続端子4とはんだ接続端子が露出する開口部2を有するように設けられたソルダーレジスト3とを備えて構成されている。   The semiconductor chip mounting substrate 6 shown in FIG. 2 includes a solder connection terminal 4 and a solder resist 3 provided on the substrate so as to have an opening 2 through which the solder connection terminal is exposed.

この半導体チップ搭載用基板6の金ワイヤボンディング用接続端子1及びはんだ接続端子4に対して無電解ニッケルめっき、無電解パラジウムめっき、置換金めっき、さらに無電解金めっきを行った。はんだ接続信頼性については開口部2を有するように設けられたはんだ接続端子4にはんだボールをリフリー炉で接続させて評価した。 Electroless nickel plating, electroless palladium plating, displacement gold plating, and electroless gold plating were performed on the gold wire bonding connection terminal 1 and the solder connection terminal 4 of the semiconductor chip mounting substrate 6. The solder connection reliability was evaluated by connecting a solder ball to a solder connection terminal 4 provided with an opening 2 in a Refree furnace.

図3及び4は、本発明の実施例の工程を説明するために参照する完成したフレキシブルプリント配線板の一例を示す概略図であり、このうち図3は、はんだ接続端子4と導体配線であるリード線5が形成され、さらに無電解めっきにより0.5〜3重量%のリンを含有した無電解ニッケルめっき皮膜、無電解パラジウムめっき皮膜、置換金めっき皮膜、さらに無電解金めっき皮膜が形成されたフレキシブルプリント配線板の一例を示す模式図である。また図4は、さらにカバーレイフィルムが形成されたフレキシブルプリント配線板の模式図である。   3 and 4 are schematic views showing an example of a completed flexible printed wiring board referred to for explaining the steps of the embodiment of the present invention. Of these, FIG. 3 shows the solder connection terminal 4 and the conductor wiring. Lead wire 5 is formed, and electroless nickel plating film, electroless palladium plating film, displacement gold plating film, and electroless gold plating film containing 0.5 to 3% by weight of phosphorus are further formed by electroless plating. It is a schematic diagram which shows an example of a flexible printed wiring board. FIG. 4 is a schematic view of a flexible printed wiring board on which a coverlay film is further formed.

屈曲性については、図3に示すはんだ接続端子4と導体配線であるリード線5が形成されたフレキシブルプリント配線板に無電解めっきを行い、めっきした面を外側にしてJIS Z2248の金属材料曲げ試験により巻き付け試験を行い、めっきした皮膜のクラックの発生の有無により評価した。はんだ接続信頼性については開口部2を有するように設けられたはんだ接続端子4にはんだボールをリフリー炉で接続させて評価した。   For flexibility, electroless plating is applied to the flexible printed wiring board on which the solder connection terminal 4 and the lead wire 5 which is the conductor wiring shown in FIG. 3 are formed, and the metal material bending test of JIS Z2248 with the plated surface facing outside. A winding test was conducted, and evaluation was performed based on whether or not cracks occurred in the plated film. The solder connection reliability was evaluated by connecting a solder ball to a solder connection terminal 4 provided with an opening 2 in a Refree furnace.

実施例1
(工程a)(配線形成)
基材厚さ0.3mm、銅箔厚さ1μmのガラス布−エポキシ樹脂基板を使用し、所望の位置にドリル穴あけを行った後に無電解銅めっきを行い、両面の導通を取り、エッチングレジストを形成し、不要な銅を塩化第二鉄エッチング液を用いてエッチングし、片面に金ワイヤボンディング用端子を、他の片面にはんだ接続端子のある銅配線パターンを形成した。
Example 1
(Process a) (Wiring formation)
Using a glass cloth-epoxy resin substrate with a base material thickness of 0.3 mm and a copper foil thickness of 1 μm, drilling holes at the desired position, then electroless copper plating, taking both sides of conduction, etching resist Then, unnecessary copper was etched using a ferric chloride etchant to form a copper wiring pattern having a gold wire bonding terminal on one side and a solder connection terminal on the other side.

形成された金ワイヤボンディング用端子は、端子幅:50μm、端子長さ:200μm、端子間スペース:20μm、端子の導体厚み:15μmであった。
また、はんだ接続端子12は直径800μmで、導体厚さは15μmであった。
The formed gold wire bonding terminal had a terminal width of 50 μm, a terminal length of 200 μm, a space between terminals of 20 μm, and a terminal conductor thickness of 15 μm.
The solder connection terminal 12 had a diameter of 800 μm and a conductor thickness of 15 μm.

(工程b)(ソルダーレジスト形成)
次に、図1に示すように、金ワイヤボンディング用接続端子1が露出するように開口部2のあるソルダーレジスト3を以下の手順で形成した。同様に、はんだ接続端子側においても、図2に示すように直径650μmの開口部2を有するようにソルダーレジスト3を以下の手順で形成した。
(Process b) (Solder resist formation)
Next, as shown in FIG. 1, a solder resist 3 having an opening 2 was formed by the following procedure so that the gold wire bonding connection terminal 1 was exposed. Similarly, on the solder connection terminal side, as shown in FIG. 2, a solder resist 3 was formed by the following procedure so as to have an opening 2 having a diameter of 650 μm.

即ち、感光性のソルダーレジスト「PSR−4000 AUS5」〔太陽インキ製造(株)製、商品名〕をロールコータで塗布し、硬化後の厚さが40μmとなるようにした。次いで、露光・現像をすることにより所望の場所に開口部2を有するソルダーレジスト3を形成した。   That is, a photosensitive solder resist “PSR-4000 AUS5” (trade name, manufactured by Taiyo Ink Manufacturing Co., Ltd.) was applied with a roll coater so that the thickness after curing was 40 μm. Subsequently, the solder resist 3 which has the opening part 2 in the desired place was formed by exposing and developing.

(工程c)(前処理1)
上記の絶縁樹脂層が設けられた配線板を、30g/Lの水酸化カリウム溶液に50℃で3分間浸漬し、1分間湯洗した後、5分間水洗した。
(Process c) (Pretreatment 1)
The wiring board provided with the insulating resin layer was immersed in a 30 g / L potassium hydroxide solution at 50 ° C. for 3 minutes, washed with hot water for 1 minute, and then washed with water for 5 minutes.

(工程d)(前処理2)
次に、配線板を、脱脂液「Z−200」〔(株)ワールドメタル製、商品名〕に50℃で3分間浸漬し、2分間水洗した。
(Process d) (Pretreatment 2)
Next, the wiring board was immersed in a degreasing solution “Z-200” (trade name, manufactured by World Metal Co., Ltd.) at 50 ° C. for 3 minutes and washed with water for 2 minutes.

(工程e)(前処理3)
次に、脂肪族チオール化合物であるメルカプト酢酸の濃度が0.02g/Lとなるように調整した、5mL/Lエタノール水溶液に、配線板を25℃で3分間浸漬し、50℃で1分間湯洗した後、1分間水洗した。
(Process e) (Pretreatment 3)
Next, the wiring board is immersed in a 5 mL / L aqueous ethanol solution adjusted to have a concentration of mercaptoacetic acid, which is an aliphatic thiol compound, of 0.02 g / L for 3 minutes at 25 ° C., and then heated at 50 ° C. for 1 minute. After washing, it was washed with water for 1 minute.

(工程f)(前処理4)
次に、配線板を、100g/Lの過硫酸アンモニウム溶液に1分間浸漬し、2分間水洗した。続いて、配線板を10%の硫酸に1分間浸漬し、2分間水洗した。
(Process f) (Pretreatment 4)
Next, the wiring board was immersed in a 100 g / L ammonium persulfate solution for 1 minute and washed with water for 2 minutes. Subsequently, the wiring board was immersed in 10% sulfuric acid for 1 minute and washed with water for 2 minutes.

(工程g)(置換パラジウムめっき処理)
次に、配線板を、めっき活性化処理液である「SA−100」〔日立化成工業(株)製、商品名〕に25℃で5分間浸漬し、2分間水洗した。
(Step g) (Substituted palladium plating treatment)
Next, the wiring board was immersed in “SA-100” (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a plating activation treatment solution, at 25 ° C. for 5 minutes and washed with water for 2 minutes.

(工程h)(無電解ニッケルめっき処理)
次に、配線板を、無電解ニッケルめっき液であるトップ二コロンLPH〔奥野製薬工業(株)製、商品名〕に85℃で40秒間浸漬することにより、接続端子上に1.5重量%のリンを含有した無電解ニッケルめっき皮膜を0.3μmの厚さで形成した。次いで、これを1分間水洗した。
(Process h) (Electroless nickel plating treatment)
Next, the wiring board is immersed in Top Nicolon LPH (trade name, manufactured by Okuno Seiyaku Kogyo Co., Ltd.), which is an electroless nickel plating solution, at 85 ° C. for 40 seconds, thereby 1.5% by weight on the connection terminal. An electroless nickel plating film containing 3 μm of phosphorus was formed to a thickness of 0.3 μm. This was then washed with water for 1 minute.

(工程i)(無電解パラジウムめっき処理)
次に、無電解パラジウムめっき液であるAPP〔石原薬品工業(株)製、商品名〕に、50℃で5分間浸漬し、2分間水洗し、0.15μmの厚さのパラジウムめっき皮膜を形成した。
(Process i) (Electroless palladium plating treatment)
Next, it is immersed in APP (product name, manufactured by Ishihara Pharmaceutical Co., Ltd.), which is an electroless palladium plating solution, at 50 ° C. for 5 minutes and washed with water for 2 minutes to form a palladium plating film having a thickness of 0.15 μm. did.

(工程j)(置換金めっき)
次いで、置換金めっき液であるHGS−100日立化成工業(株)製、商品名〕に、85℃で10分間浸漬し、2分間水洗した。
(Process j) (Substitution gold plating)
Then, it was immersed in HGS-100 Hitachi Chemical Co., Ltd. product name, which is a displacement gold plating solution, at 85 ° C. for 10 minutes and washed with water for 2 minutes.

(工程k)(無電解金めっき処理)
次に、無電解金めっき液であるHGS−2000〔日立化成工業(株)製、商品名〕に、65℃で10分間浸漬し、5分間水洗し、0.1μmの厚さの金めっき皮膜を形成した。
(Process k) (Electroless gold plating treatment)
Next, it is immersed in HGS-2000 (trade name, manufactured by Hitachi Chemical Co., Ltd.) which is an electroless gold plating solution at 65 ° C. for 10 minutes, washed with water for 5 minutes, and a gold plating film having a thickness of 0.1 μm. Formed.

上記で得られた配線板について、下記の基準により接続端子の接続信頼性を評価した。
100箇所のはんだ接続端子に、直径0.76mmのSn−3.0Ag−0.5Cuはんだボールをリフリー炉で接続させ、150℃で1000時間放置後、耐衝撃性ハイスピードボンドテスター4000HS(デイジ社製 商品名)を用いて、20mm/秒の条件ではんだボールのシェア(剪断)試験を施し、それぞれの配線板について下記の基準によりはんだ接続強度について評価した。その結果を表1に示す。
About the wiring board obtained above, the connection reliability of the connection terminal was evaluated according to the following criteria.
Sn-3.0Ag-0.5Cu solder balls with a diameter of 0.76 mm were connected to 100 solder connection terminals in a Refree furnace, left at 150 ° C. for 1000 hours, and then impact-resistant high-speed bond tester 4000HS (Digi Corporation) Using a product name), a shear (shear) test of the solder balls was performed under the condition of 20 mm / second, and the solder connection strength was evaluated according to the following criteria for each wiring board. The results are shown in Table 1.

<はんだ接続信頼性>
A:100箇所の接続端子のすべてにおいてはんだボール内での剪断による破壊である。
B:はんだボール内での剪断による破壊以外のモードによる破壊が1箇所以上5個所以内ある。
C:はんだボール内での剪断による破壊以外のモードによる破壊が6箇所以上29個所以内ある。
D:はんだボール内での剪断による破壊以外のモードによる破壊が30個所以上ある。
<Solder connection reliability>
A: Breakage due to shearing in the solder balls in all 100 connection terminals.
B: There are 1 or more and 5 or less breaks in a mode other than shear breakage in a solder ball.
C: There are 6 or more and 29 or less breaks in modes other than shear breakage in the solder balls.
D: There are 30 or more breaks due to modes other than shear breakage in the solder balls.

実施例2
実施例1に示す、工程h(無電解ニッケルめっき工程)において、無電解ニッケルめっきの処理時間を1分40秒間に変更し、0.7μmの厚さの無電解ニッケルめっき皮膜を形成したと以外は、実施例1と同様の工程を経て配線板を得た。その後この配線板につい実施例1と同様の方法で接続信頼性を評価した。その結果を表1に示す。
Example 2
In step h (electroless nickel plating step) shown in Example 1, except that the electroless nickel plating treatment time was changed to 1 minute and 40 seconds to form an electroless nickel plating film having a thickness of 0.7 μm. Obtained the wiring board through the process similar to Example 1. FIG. Thereafter, connection reliability of this wiring board was evaluated in the same manner as in Example 1. The results are shown in Table 1.

(実施例3)
実施例1に示す、工程h(無電解ニッケルめっき工程)において、無電解ニッケルめっきの処理時間を3分30秒間に変更し、1.5μmの厚さの無電解ニッケルめっき皮膜を形成した以外は、実施例1と同様の工程を経て配線板を得た。その後この配線板につい実施例1と同様の方法で接続信頼性を評価した。その結果を表1に示す。
(Example 3)
In step h (electroless nickel plating step) shown in Example 1, the electroless nickel plating treatment time was changed to 3 minutes 30 seconds, and an electroless nickel plating film having a thickness of 1.5 μm was formed. A wiring board was obtained through the same steps as in Example 1. Thereafter, connection reliability of this wiring board was evaluated in the same manner as in Example 1. The results are shown in Table 1.

Figure 2008147495
Figure 2008147495

実施例4
(工程a)(配線形成)
基材厚さ0.3mm、銅箔厚さ1μmのガラス布−エポキシ樹脂基板を使用し、所望の位置にドリル穴あけを行った後に無電解銅めっきを行い、両面の導通を取り、エッチングレジストを形成し、不要な銅を塩化第二鉄エッチング液を用いてエッチングし、片面に金ワイヤボンディング用端子を、他の片面にはんだ接続端子のある銅配線パターンを形成した。
Example 4
(Process a) (Wiring formation)
Using a glass cloth-epoxy resin substrate with a base material thickness of 0.3 mm and a copper foil thickness of 1 μm, drilling holes at the desired position, then electroless copper plating, taking both sides of conduction, etching resist Then, unnecessary copper was etched using a ferric chloride etchant to form a copper wiring pattern having a gold wire bonding terminal on one side and a solder connection terminal on the other side.

形成されたワイヤボンディング用端子1は、端子幅:50μm、端子長さ:200μm端子間スペース:20μm、端子の導体厚み:15μmであった。
また、はんだ接続端子12は直径800μmで、導体厚さは15μmであった。
The formed wire bonding terminal 1 had a terminal width: 50 μm, a terminal length: 200 μm, a space between terminals: 20 μm, and a terminal conductor thickness: 15 μm.
The solder connection terminal 12 had a diameter of 800 μm and a conductor thickness of 15 μm.

(工程c)(前処理1)
上記の絶縁樹脂層が設けられた配線板を、30g/Lの水酸化カリウム溶液に50℃で3分間浸漬し、1分間湯洗した後、5分間水洗した。
(Process c) (Pretreatment 1)
The wiring board provided with the insulating resin layer was immersed in a 30 g / L potassium hydroxide solution at 50 ° C. for 3 minutes, washed with hot water for 1 minute, and then washed with water for 5 minutes.

(工程d)(前処理2)
次に、配線板を、脱脂液「Z−200」〔(株)ワールドメタル製、商品名〕に50℃で3分間浸漬し、2分間水洗した。
(Process d) (Pretreatment 2)
Next, the wiring board was immersed in a degreasing solution “Z-200” (trade name, manufactured by World Metal Co., Ltd.) at 50 ° C. for 3 minutes and washed with water for 2 minutes.

(工程e)(前処理3)
次に、脂肪族チオール化合物であるメルカプト酢酸の濃度が0.02g/Lとなるように調整した、5mL/Lエタノール水溶液に、配線板を25℃で3分間浸漬し、50℃で1分間湯洗した後、1分間水洗した。
(Process e) (Pretreatment 3)
Next, the wiring board is immersed in a 5 mL / L aqueous ethanol solution adjusted to have a concentration of mercaptoacetic acid, which is an aliphatic thiol compound, of 0.02 g / L for 3 minutes at 25 ° C., and then heated at 50 ° C. for 1 minute. After washing, it was washed with water for 1 minute.

(工程f)(前処理4)
次に、配線板を、100g/Lの過硫酸アンモニウム溶液に1分間浸漬し、2分間水洗した。続いて、配線板を10%の硫酸に1分間浸漬し、2分間水洗した。
(Process f) (Pretreatment 4)
Next, the wiring board was immersed in a 100 g / L ammonium persulfate solution for 1 minute and washed with water for 2 minutes. Subsequently, the wiring board was immersed in 10% sulfuric acid for 1 minute and washed with water for 2 minutes.

(工程g)(置換パラジウムめっき処理)
次に、配線板を、めっき活性化処理液である「SA−100」〔日立化成工業(株)製、商品名〕に25℃で5分間浸漬し、2分間水洗した。
(Step g) (Substituted palladium plating treatment)
Next, the wiring board was immersed in “SA-100” (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a plating activation treatment solution, at 25 ° C. for 5 minutes and washed with water for 2 minutes.

(工程h)(無電解ニッケルめっき処理)
次に、配線板を、無電解ニッケルめっき液であるトップ二コロンLPH〔奥野製薬工業(株)製、商品名〕に85℃で40秒間浸漬することにより、接続端子上に1.5重量%のリンを含有した無電解ニッケルめっき皮膜を0.3μmの厚さで形成した。次いで、これを1分間水洗した。
(Process h) (Electroless nickel plating treatment)
Next, the wiring board is immersed in Top Nicolon LPH (trade name, manufactured by Okuno Seiyaku Kogyo Co., Ltd.), which is an electroless nickel plating solution, at 85 ° C. for 40 seconds, thereby 1.5% by weight on the connection terminal. An electroless nickel plating film containing 3 μm of phosphorus was formed to a thickness of 0.3 μm. This was then washed with water for 1 minute.

(工程i)(無電解パラジウムめっき処理)
次に、無電解パラジウムめっき液であるAPP石原薬品工業(株)製、商品名〕に、50℃で5分間浸漬し、2分間水洗した。
(Process i) (Electroless palladium plating treatment)
Next, it was immersed in APP Ishihara Pharmaceutical Co., Ltd., which is an electroless palladium plating solution, for 5 minutes at 50 ° C. and washed with water for 2 minutes.

(工程j)(置換金めっき)
次いで、置換金めっき液であるHGS−100日立化成工業(株)製、商品名〕に、85℃で10分間浸漬し、2分間水洗した。
(Process j) (Substitution gold plating)
Then, it was immersed in HGS-100 Hitachi Chemical Co., Ltd. product name, which is a displacement gold plating solution, at 85 ° C. for 10 minutes and washed with water for 2 minutes.

(工程k)(無電解金めっき処理)
次に、無電解金めっき液であるHGP−2000〔日立化成工業(株)製、商品名〕に、65℃で10分間浸漬し、5分間水洗した。
(Process k) (Electroless gold plating treatment)
Next, it was immersed for 10 minutes at 65 ° C. in HGP-2000 [trade name, manufactured by Hitachi Chemical Co., Ltd.] which is an electroless gold plating solution, and washed with water for 5 minutes.

(工程l)(カバーレイフィルム形成)
次に、図4に示すように、はんだ接続端子4が露出するように直径650μmの開口部2のあるカバーレイフィルム8を以下の手順で形成した。即ち、感光性のカバーレイフィルムで塗布し、硬化後の厚みが40μmとなるようにした。次いで、露光・現像をすることにより所望の場所に開口部2を有するカバーレイフィルム8を形成した。
(Process l) (Coverlay film formation)
Next, as shown in FIG. 4, a coverlay film 8 having an opening 2 having a diameter of 650 μm was formed by the following procedure so that the solder connection terminals 4 were exposed. That is, it was applied with a photosensitive coverlay film so that the thickness after curing was 40 μm. Next, a coverlay film 8 having an opening 2 at a desired location was formed by exposure and development.

工程kのめっき工程の後に得られたフレキシブル配線板を用いて、屈曲性を評価した。屈曲性については、めっきした面を外側に、JIS Z2248の金属材料曲げ試験により巻き付け試験を行い、リード線部を曲げることによって、めっきした皮膜にクラックが発生するのかどうかを評価した。   Flexibility was evaluated using the flexible wiring board obtained after the plating step of step k. Regarding the flexibility, a winding test was performed by a metal material bending test of JIS Z2248 with the plated surface outside, and it was evaluated whether or not a crack was generated in the plated film by bending the lead wire portion.

<屈曲性>
A:50箇所の導体配線のすべてにおいてクラック発生無し。
B:50箇所の導体配線のうち、クラックの発生が1箇所以上5個所以内ある。
C:50箇所の導体配線のうち、クラックの発生が6箇所以上20個所以内ある。
D:50箇所の導体配線のうち、クラックの発生が21箇所以上ある。
<Flexibility>
A: No cracks occurred in all 50 conductor wirings.
B: Of the 50 conductor wirings, 1 to 5 cracks are generated.
C: There are 6 or more and 20 or less cracks in the 50 conductor wirings.
D: There are 21 or more occurrences of cracks in 50 conductor wirings.

また、上記で得られた配線板について、実施例1と同様の方法で接続端子の接続信頼性を評価した。その結果を表2に示す。   Moreover, the connection reliability of the connection terminal was evaluated by the same method as Example 1 about the wiring board obtained above. The results are shown in Table 2.

実施例5
実施例4に示す工程h(無電解ニッケルめっき工程)において、無電解ニッケルめっきの処理時間を1分40秒間に変更し、0.7μmの厚さの無電解ニッケルめっき皮膜を形成した以外は、実施例4と同様の工程を経て配線板を得た。その後この配線板につい実施例4と同様の方法で屈曲性及び実施例1と同様の方法で接続信頼性を評価した。その結果を表2に示す。
Example 5
In the process h (electroless nickel plating process) shown in Example 4, the electroless nickel plating treatment time was changed to 1 minute and 40 seconds, and an electroless nickel plating film having a thickness of 0.7 μm was formed. A wiring board was obtained through the same steps as in Example 4. Thereafter, the flexibility of the wiring board was evaluated in the same manner as in Example 4 and the connection reliability was evaluated in the same manner as in Example 1. The results are shown in Table 2.

Figure 2008147495
Figure 2008147495

比較例1
実施例1に示す、工程h(無電解ニッケルめっき工程)において、無電解ニッケルめっきの処理時間を15秒間に変更し、0.1μmの厚さの無電解ニッケルめっき皮膜を形成したと以外は、実施例1と同様の工程を経て配線板を得た。その後この配線板につい実施例1と同様の方法で接続信頼性を評価した。その結果を表3に示す。
Comparative Example 1
In step h (electroless nickel plating step) shown in Example 1, the treatment time of electroless nickel plating was changed to 15 seconds, and an electroless nickel plating film having a thickness of 0.1 μm was formed. A wiring board was obtained through the same steps as in Example 1. Thereafter, connection reliability of this wiring board was evaluated in the same manner as in Example 1. The results are shown in Table 3.

比較例2
実施例1の工程h(無電解ニッケルめっき工程)において、無電解ニッケルめっき液をICP二コロンU〔奥野製薬工業(株)製、商品名〕に85℃で3分間浸漬することにより、接続端子上に7重量%のリンを含有した無電解ニッケルめっき皮膜を0.7μmの厚さで形成したこと以外は、実施例1と同様の工程を経て配線板を得た。その後この配線板につい実施例1と同様の方法で接続信頼性を評価した。その結果を表3に示す。
Comparative Example 2
In the process h (electroless nickel plating process) of Example 1, the electroless nickel plating solution was immersed in ICP Nicol U (trade name, manufactured by Okuno Pharmaceutical Co., Ltd.) for 3 minutes at 85 ° C. A wiring board was obtained through the same steps as in Example 1 except that an electroless nickel plating film containing 7% by weight of phosphorus was formed to a thickness of 0.7 μm. Thereafter, connection reliability of this wiring board was evaluated in the same manner as in Example 1. The results are shown in Table 3.

比較例3
実施例1の工程h(無電解ニッケルめっき工程)において、無電解ニッケルめっき液をトップ二コロンNAC〔奥野製薬工業(株)製、商品名〕に85℃で4分間浸漬することにより、接続端子上に11.5重量%のリンを含有した無電解ニッケルめっき皮膜を0.7μmの厚さで形成した以外は、実施例1と同様の工程を経て配線板を得た。その後この配線板につい実施例1と同様の方法で接続信頼性を評価した。その結果を表3に示す。
Comparative Example 3
In the step h (electroless nickel plating step) of Example 1, the electroless nickel plating solution is immersed in Top Nicol NAC (trade name, manufactured by Okuno Pharmaceutical Co., Ltd.) at 85 ° C. for 4 minutes, thereby connecting terminals. A wiring board was obtained through the same steps as in Example 1 except that an electroless nickel plating film containing 11.5% by weight of phosphorus was formed thereon with a thickness of 0.7 μm. Thereafter, connection reliability of this wiring board was evaluated in the same manner as in Example 1. The results are shown in Table 3.

比較例4
実施例1の工程h(無電解ニッケルめっき工程)において、無電解ニッケルめっき液を下記の無電解ニッケルめっき液に変更し、85℃で11分間浸漬することにより、接続端子上にほぼ100%の純度のニッケルの無電解ニッケルめっき皮膜を0.7μmの厚さで形成したこと以外は、実施例1と同様の工程を経て配線板を得た。その後この配線板につい実施例1と同様の方法で接続信頼性を評価した。その結果を表3に示す。
Comparative Example 4
In step h (electroless nickel plating step) of Example 1, the electroless nickel plating solution is changed to the following electroless nickel plating solution and immersed at 85 ° C. for 11 minutes, so that almost 100% is formed on the connection terminals. A wiring board was obtained through the same steps as in Example 1 except that an electroless nickel plating film of pure nickel was formed with a thickness of 0.7 μm. Thereafter, connection reliability of this wiring board was evaluated in the same manner as in Example 1. The results are shown in Table 3.

(無電解ニッケルめっき液)
塩化ニッケル 0.05M
ヒドラジン一水和物 0.4M
グリシン 0.3M
ホウ酸 0.5M
チオ硫酸Na5水和物 1ppm
鉛イオン 0.3ppm
pH 12.0
(Electroless nickel plating solution)
Nickel chloride 0.05M
Hydrazine monohydrate 0.4M
Glycine 0.3M
Boric acid 0.5M
Thiosulfate Na pentahydrate 1ppm
Lead ion 0.3ppm
pH 12.0

Figure 2008147495
Figure 2008147495

比較例5
実施例4の工程h(無電解ニッケルめっき工程)において、無電解ニッケルめっき液をICP二コロンU〔奥野製薬工業(株)製、商品名〕に85℃で3分間浸漬することにより、接続端子上に7重量%のリンを含有した無電解ニッケルめっき皮膜を0.7μmの厚さで形成した以外は、実施例4と同様の工程を経て配線板を得た。その後この配線板につい実施例4と同様の方法で屈曲性及び実施例1と同様の方法で接続信頼性を評価した。その結果を表4に示す。
Comparative Example 5
In the step h (electroless nickel plating step) of Example 4, the electroless nickel plating solution was immersed in ICP Nicol U (trade name, manufactured by Okuno Pharmaceutical Co., Ltd.) for 3 minutes at 85 ° C. A wiring board was obtained through the same steps as in Example 4 except that an electroless nickel plating film containing 7% by weight of phosphorus was formed to a thickness of 0.7 μm. Thereafter, the flexibility of the wiring board was evaluated in the same manner as in Example 4 and the connection reliability was evaluated in the same manner as in Example 1. The results are shown in Table 4.

比較例6
実施例4の工程h(無電解ニッケルめっき工程)において、無電解ニッケルめっき液をICP二コロンU〔奥野製薬工業(株)製、商品名〕に85℃で6分20秒間浸漬処理することにより、接続端子上に7重量%のリンを含有した無電解ニッケルめっき皮膜を1.5μmの厚さで形成した以外は、実施例4と同様の工程を経て配線板を得た。その後この配線板につい実施例4と同様の方法で屈曲性及び実施例1と同様の方法で接続信頼性を評価した。その結果を表4に示す。
Comparative Example 6
In the process h (electroless nickel plating process) of Example 4, the electroless nickel plating solution was immersed in ICP Nicol U (trade name, manufactured by Okuno Pharmaceutical Co., Ltd.) at 85 ° C. for 6 minutes and 20 seconds. A wiring board was obtained through the same steps as in Example 4 except that an electroless nickel plating film containing 7% by weight of phosphorus was formed on the connection terminals in a thickness of 1.5 μm. Thereafter, the flexibility of the wiring board was evaluated in the same manner as in Example 4 and the connection reliability was evaluated in the same manner as in Example 1. The results are shown in Table 4.

比較例7
実施例4の工程h(無電解ニッケルめっき工程)において、無電解ニッケルめっき液をトップ二コロンNAC〔奥野製薬工業(株)製、商品名〕に85℃で4分間浸漬することにより、接続端子上に11.5重量%のリンを含有した無電解ニッケルめっき皮膜を0.7μmの厚さで形成した以外は、実施例4と同様の工程を経て配線板を得た。その後この配線板につい実施例4と同様の方法で屈曲性及び実施例1と同様の方法で接続信頼性を評価した。その結果を表4に示す。
Comparative Example 7
In the step h (electroless nickel plating step) of Example 4, the electroless nickel plating solution was immersed in Top Nicol NAC (trade name, manufactured by Okuno Seiyaku Kogyo Co., Ltd.) at 85 ° C. for 4 minutes. A wiring board was obtained through the same steps as in Example 4 except that an electroless nickel plating film containing 11.5% by weight of phosphorus was formed thereon with a thickness of 0.7 μm. Thereafter, the flexibility of the wiring board was evaluated in the same manner as in Example 4 and the connection reliability was evaluated in the same manner as in Example 1. The results are shown in Table 4.

比較例8
実施例4の工程h(無電解ニッケルめっき工程)において、無電解ニッケルめっき液をトップ二コロンNAC〔奥野製薬工業(株)製、商品名〕に85℃で8分30秒間浸漬することにより、接続端子上に11.5重量%のリンを含有した無電解ニッケルめっき皮膜を1.5μmの厚さで形成した以外は、実施例4と同様の工程を経て配線板を得た。その後この配線板につい実施例4と同様の方法で屈曲性及び実施例1と同様の方法で接続信頼性を評価した。その結果を表4に示す。
Comparative Example 8
In step h (electroless nickel plating step) of Example 4, the electroless nickel plating solution was immersed in Top Nicol NAC (trade name, manufactured by Okuno Pharmaceutical Co., Ltd.) at 85 ° C. for 8 minutes and 30 seconds, A wiring board was obtained through the same steps as in Example 4 except that an electroless nickel plating film containing 11.5% by weight of phosphorus was formed on the connection terminal in a thickness of 1.5 μm. Thereafter, the flexibility of the wiring board was evaluated in the same manner as in Example 4 and the connection reliability was evaluated in the same manner as in Example 1. The results are shown in Table 4.

Figure 2008147495
Figure 2008147495

表1〜4に示されるように、実施例1〜3の配線板は、厚さが0.2μm以上で、0.5〜3重量%のリンを含有した無電解ニッケルめっき皮膜、無電解パラジウムめっき皮膜、置換金めっき皮膜、さらに無電解金めっき被膜を順に形成することで、はんだの接続信頼性に優れた接続端子を有する半導体チップ搭載基板を提供できることが明らかである。   As shown in Tables 1 to 4, the wiring boards of Examples 1 to 3 have a thickness of 0.2 μm or more and an electroless nickel plating film containing 0.5 to 3% by weight of phosphorus and electroless palladium. It is apparent that a semiconductor chip mounting substrate having a connection terminal with excellent solder connection reliability can be provided by sequentially forming a plating film, a displacement gold plating film, and an electroless gold plating film.

また、実施例4及び5の配線板は、厚さが0.2μm以上で、0.5〜3重量%のリンを含有した無電解ニッケルめっき皮膜、無電解パラジウムめっき皮膜、置換金めっき皮膜、さらに無電解金めっき被膜を順に形成することで、屈曲性とはんだの接続信頼性に優れた接続端子を有するフレキシブルプリント配線板を提供できることが明らかである。   In addition, the wiring boards of Examples 4 and 5 have an electroless nickel plating film, an electroless palladium plating film, a displacement gold plating film having a thickness of 0.2 μm or more and containing 0.5 to 3% by weight of phosphorus, Furthermore, it is clear that a flexible printed wiring board having a connection terminal excellent in flexibility and solder connection reliability can be provided by sequentially forming an electroless gold plating film.

これに対し、比較例1〜4の配線板は、はんだの接続信頼性に劣り、また比較例5〜8の配線板は、屈曲性及びはんだの接続信頼性のいずれかに劣ることが明らかである。   On the other hand, the wiring boards of Comparative Examples 1 to 4 are inferior in solder connection reliability, and the wiring boards of Comparative Examples 5 to 8 are clearly inferior in either flexibility or solder connection reliability. is there.

金ワイヤボンディング用接続端子側から見た場合の半導体チップ搭載用基板の一例を示す模式図である。It is a schematic diagram which shows an example of the board | substrate for semiconductor chip mounting when it sees from the connecting terminal side for gold | metal | money wire bonding. はんだ接続端子側から見た場合の半導体チップ搭載用基板の一例を示す模式図である。It is a schematic diagram which shows an example of the board | substrate for semiconductor chip mounting when it sees from the solder connection terminal side. 無電解めっき後のフレキシブルプリント配線板の一例を示す模式図である。It is a schematic diagram which shows an example of the flexible printed wiring board after electroless plating. 無電解めっきを行い、さらにカバーレイフィルムを形成した後のフレキシブルプリント配線板の一例を示す模式図である。It is a schematic diagram which shows an example of the flexible printed wiring board after performing electroless plating and also forming a coverlay film.

符号の説明Explanation of symbols

1 金ワイヤボンディング用接続端子
2 開口部
3 ソルダーレジスト
4 はんだ接続端子
5 リード線
6 半導体チップ搭載用基板
7 ポリイミド樹脂
8 カバーレイフィルム
9 フレキシブルプリント配線板
DESCRIPTION OF SYMBOLS 1 Connection terminal 2 for gold wire bonding 3 Opening part 3 Solder resist 4 Solder connection terminal 5 Lead wire 6 Semiconductor chip mounting board 7 Polyimide resin 8 Coverlay film 9 Flexible printed wiring board

Claims (8)

配線導体の表面に、厚さが0.2μm以上で、0.5〜3重量%のリンを含有した無電解ニッケルめっき皮膜、無電解パラジウムめっき皮膜、置換金めっき皮膜、さらに無電解金めっき皮膜が順に形成され、その上にはんだが溶着された接続端子。   Electroless nickel plating film, electroless palladium plating film, displacement gold plating film, and electroless gold plating film having a thickness of 0.2 μm or more and containing 0.5 to 3% by weight of phosphorus on the surface of the wiring conductor Are connected terminals in which solder is welded. 無電解パラジウムめっき皮膜が、90重量%以上の純度のパラジウムである請求項1記載の接続端子。   The connection terminal according to claim 1, wherein the electroless palladium plating film is palladium having a purity of 90% by weight or more. ワイヤボンディング用端子とはんだ接続用の接続端子を備えた半導体チップ搭載用基板において、前記ワイヤボンディング用端子の端子間又は引き回し配線間(Y)が30μm以下で、かつ端子高さ(Z)が端子間又は引き回し配線間(Y)の5分の2以上であり、前記ワイヤボンディング用端子と前記はんだ接続用の接続端子表面に、請求項1記載の厚さが0.2μm以上で、0.5〜3重量%のリンを含有した無電解ニッケルめっき皮膜、無電解パラジウムめっき皮膜、置換金めっき皮膜、さらに無電解金めっき皮膜が順に形成された半導体チップ搭載用基板。   In a semiconductor chip mounting board provided with wire bonding terminals and solder connection terminals, the wire bonding terminals have a terminal height (Z) of 30 μm or less and a terminal height (Z) of the terminals. The thickness according to claim 1 is 0.2 μm or more on the surface of the wire bonding terminal and the connection terminal for solder connection, and is 0.5 / 5 or more of the space between the wiring lines or between the wiring lines (Y). A substrate for mounting a semiconductor chip, on which an electroless nickel plating film, an electroless palladium plating film, a displacement gold plating film, and an electroless gold plating film containing 3% by weight of phosphorus are sequentially formed. 配線導体の表面に厚さが0.2μm以上で、0.5〜3重量%のリンを含有した無電解ニッケルめっき皮膜、無電解パラジウムめっき皮膜、置換金めっき皮膜、さらに無電解金めっき皮膜が順に形成され、その上にはんだが溶着された接続端子、該配線導体を支持する半導体チップ搭載用基板、半導体チップ、該半導体チップ及び該配線導体を接続する接続導体とからなる半導体パッケージ。   Electroless nickel plating film, electroless palladium plating film, displacement gold plating film, and electroless gold plating film having a thickness of 0.2 μm or more on the surface of the wiring conductor and containing 0.5 to 3% by weight of phosphorus. A semiconductor package comprising a connection terminal formed in order and solder welded thereon, a semiconductor chip mounting substrate for supporting the wiring conductor, a semiconductor chip, and a connection conductor for connecting the semiconductor chip and the wiring conductor. 無電解パラジウムめっき皮膜が、90重量%以上の純度のパラジウムである請求項4記載の半導体パッケージ。   The semiconductor package according to claim 4, wherein the electroless palladium plating film is palladium having a purity of 90% by weight or more. 半導体チップ搭載用基板の表面に配線導体を形成した後、該配線導体の表面に厚さが0.2μm以上で、0.5〜3重量%のリンを含有した無電解ニッケルめっき皮膜、無電解パラジウムめっき皮膜、置換金めっき皮膜、さらに無電解金めっき皮膜を順に形成し、その上にはんだを溶着して接続端子を形成し、該接続端子のはんだの上に半導体チップを搭載した後、半導体チップと配線導体を接続する接続導体を形成することを特徴とする半導体パッケージの製造方法。   After forming a wiring conductor on the surface of the semiconductor chip mounting substrate, the surface of the wiring conductor has a thickness of 0.2 μm or more and contains an electroless nickel plating film containing 0.5 to 3 wt% phosphorus, electroless A palladium plating film, a displacement gold plating film, and an electroless gold plating film are formed in this order, solder is deposited thereon to form a connection terminal, and a semiconductor chip is mounted on the solder of the connection terminal. A method of manufacturing a semiconductor package, comprising forming a connection conductor for connecting a chip and a wiring conductor. 折り曲げ部と接続端子部を併せてもつ配線板において、前記折り曲げ部と接続端子部に配線導体が形成されており、前記折り曲げ部と接続端子部の表面に厚さが0.2μm以上、0.8μm以下で、0.5〜3重量%のリンを含有した無電解ニッケルめっき皮膜、無電解パラジウムめっき皮膜、置換金めっき皮膜、さらに無電解金めっき皮膜が順に形成された配線板。   In a wiring board having both a bent portion and a connecting terminal portion, wiring conductors are formed on the bent portion and the connecting terminal portion, and a thickness of 0.2 μm or more on the surface of the bent portion and the connecting terminal portion. A wiring board in which an electroless nickel plating film, an electroless palladium plating film, a displacement gold plating film, and an electroless gold plating film containing 0.5 to 3% by weight of phosphorus in an order of 8 μm or less are formed in this order. 折り曲げ部と接続端子部を併せてもつ配線板の表面に配線導体を形成した後と、該配線導体の表面に厚さが0.2μm以上、0.8μm以下で、0.5〜3重量%のリンを含有した無電解ニッケルめっき皮膜、無電解パラジウムめっき皮膜、置換金めっき皮膜、さらに無電解金めっき皮膜を順に形成し、接続端子部の配線導体にはんだを溶着して接続端子を形成することを特徴とする配線板の製造方法。   After the wiring conductor is formed on the surface of the wiring board having both the bent portion and the connection terminal portion, the thickness of the wiring conductor is 0.2 μm or more and 0.8 μm or less and 0.5 to 3% by weight. An electroless nickel plating film, an electroless palladium plating film, a displacement gold plating film, and an electroless gold plating film containing phosphorus in this order are formed in this order, and solder is welded to the wiring conductor of the connection terminal portion to form a connection terminal. A method for manufacturing a wiring board.
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013012740A (en) * 2011-06-28 2013-01-17 Samsung Electro-Mechanics Co Ltd Electroless surface treatment plated layers of printed circuit board and method for preparing the same
JP2015137418A (en) * 2014-01-24 2015-07-30 株式会社クオルテック Wiring board and method for manufacturing wiring board
WO2020115279A1 (en) * 2018-12-07 2020-06-11 Atotech Deutschland Gmbh Electroless nickel or cobalt plating solution

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Publication number Priority date Publication date Assignee Title
JPH09306945A (en) * 1996-05-16 1997-11-28 Shinko Electric Ind Co Ltd Semiconductor device package and semiconductor device
JP2002118134A (en) * 2000-10-11 2002-04-19 Hitachi Chem Co Ltd Connection terminal and semiconductor package using the same as well as manufacturing method thereof
JP2004300570A (en) * 2003-03-18 2004-10-28 Ngk Spark Plug Co Ltd Wiring board

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09306945A (en) * 1996-05-16 1997-11-28 Shinko Electric Ind Co Ltd Semiconductor device package and semiconductor device
JP2002118134A (en) * 2000-10-11 2002-04-19 Hitachi Chem Co Ltd Connection terminal and semiconductor package using the same as well as manufacturing method thereof
JP2004300570A (en) * 2003-03-18 2004-10-28 Ngk Spark Plug Co Ltd Wiring board

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013012740A (en) * 2011-06-28 2013-01-17 Samsung Electro-Mechanics Co Ltd Electroless surface treatment plated layers of printed circuit board and method for preparing the same
JP2015137418A (en) * 2014-01-24 2015-07-30 株式会社クオルテック Wiring board and method for manufacturing wiring board
WO2020115279A1 (en) * 2018-12-07 2020-06-11 Atotech Deutschland Gmbh Electroless nickel or cobalt plating solution

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